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a9e61410 AD |
1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
24 | #include "drmP.h" | |
25 | #include "radeon.h" | |
01467a9b | 26 | #include "radeon_asic.h" |
a9e61410 AD |
27 | #include "sid.h" |
28 | #include "r600_dpm.h" | |
29 | #include "si_dpm.h" | |
30 | #include "atom.h" | |
31 | #include <linux/math64.h> | |
bf0936e1 | 32 | #include <linux/seq_file.h> |
a9e61410 AD |
33 | |
34 | #define MC_CG_ARB_FREQ_F0 0x0a | |
35 | #define MC_CG_ARB_FREQ_F1 0x0b | |
36 | #define MC_CG_ARB_FREQ_F2 0x0c | |
37 | #define MC_CG_ARB_FREQ_F3 0x0d | |
38 | ||
39 | #define SMC_RAM_END 0x20000 | |
40 | ||
a9e61410 AD |
41 | #define SCLK_MIN_DEEPSLEEP_FREQ 1350 |
42 | ||
43 | static const struct si_cac_config_reg cac_weights_tahiti[] = | |
44 | { | |
45 | { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, | |
46 | { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
47 | { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, | |
48 | { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, | |
49 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
50 | { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
51 | { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
52 | { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
53 | { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
54 | { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, | |
55 | { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
56 | { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, | |
57 | { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, | |
58 | { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, | |
59 | { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, | |
60 | { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
61 | { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
62 | { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, | |
63 | { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
64 | { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, | |
65 | { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, | |
66 | { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, | |
67 | { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
68 | { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
69 | { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
70 | { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
71 | { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
72 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
73 | { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
74 | { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
75 | { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, | |
76 | { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
77 | { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
78 | { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
79 | { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, | |
80 | { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
81 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
82 | { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
83 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
84 | { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, | |
85 | { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
86 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
87 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
88 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
89 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
90 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
91 | { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
92 | { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
93 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
94 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
95 | { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
96 | { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
97 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
98 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
99 | { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
100 | { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
101 | { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
102 | { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
103 | { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
104 | { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, | |
105 | { 0xFFFFFFFF } | |
106 | }; | |
107 | ||
108 | static const struct si_cac_config_reg lcac_tahiti[] = | |
109 | { | |
110 | { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
111 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
112 | { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
113 | { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
114 | { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
115 | { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
116 | { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
117 | { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
118 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
119 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
120 | { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
121 | { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
122 | { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
123 | { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
124 | { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
125 | { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
126 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
127 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
128 | { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
129 | { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
130 | { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
131 | { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
132 | { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
133 | { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
134 | { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
135 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
136 | { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
137 | { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
138 | { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
139 | { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
140 | { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
141 | { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
142 | { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
143 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
144 | { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
145 | { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
146 | { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
147 | { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
148 | { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
149 | { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
150 | { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
151 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
152 | { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
153 | { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
154 | { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
155 | { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
156 | { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
157 | { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
158 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
159 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
160 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
161 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
162 | { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
163 | { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
164 | { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
165 | { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
166 | { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
167 | { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
168 | { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
169 | { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
170 | { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
171 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
172 | { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
173 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
174 | { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
175 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
176 | { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
177 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
178 | { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
179 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
180 | { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
181 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
182 | { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
183 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
184 | { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
185 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
186 | { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
187 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
188 | { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
189 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
190 | { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
191 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
192 | { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
193 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
194 | { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
195 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
196 | { 0xFFFFFFFF } | |
197 | ||
198 | }; | |
199 | ||
200 | static const struct si_cac_config_reg cac_override_tahiti[] = | |
201 | { | |
202 | { 0xFFFFFFFF } | |
203 | }; | |
204 | ||
205 | static const struct si_powertune_data powertune_data_tahiti = | |
206 | { | |
207 | ((1 << 16) | 27027), | |
208 | 6, | |
209 | 0, | |
210 | 4, | |
211 | 95, | |
212 | { | |
213 | 0UL, | |
214 | 0UL, | |
215 | 4521550UL, | |
216 | 309631529UL, | |
217 | -1270850L, | |
218 | 4513710L, | |
219 | 40 | |
220 | }, | |
221 | 595000000UL, | |
222 | 12, | |
223 | { | |
224 | 0, | |
225 | 0, | |
226 | 0, | |
227 | 0, | |
228 | 0, | |
229 | 0, | |
230 | 0, | |
231 | 0 | |
232 | }, | |
233 | true | |
234 | }; | |
235 | ||
236 | static const struct si_dte_data dte_data_tahiti = | |
237 | { | |
238 | { 1159409, 0, 0, 0, 0 }, | |
239 | { 777, 0, 0, 0, 0 }, | |
240 | 2, | |
241 | 54000, | |
242 | 127000, | |
243 | 25, | |
244 | 2, | |
245 | 10, | |
246 | 13, | |
247 | { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, | |
248 | { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, | |
249 | { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, | |
250 | 85, | |
251 | false | |
252 | }; | |
253 | ||
254 | static const struct si_dte_data dte_data_tahiti_le = | |
255 | { | |
256 | { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, | |
257 | { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, | |
258 | 0x5, | |
259 | 0xAFC8, | |
260 | 0x64, | |
261 | 0x32, | |
262 | 1, | |
263 | 0, | |
264 | 0x10, | |
265 | { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, | |
266 | { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, | |
267 | { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, | |
268 | 85, | |
269 | true | |
270 | }; | |
271 | ||
272 | static const struct si_dte_data dte_data_tahiti_pro = | |
273 | { | |
274 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
275 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
276 | 5, | |
277 | 45000, | |
278 | 100, | |
279 | 0xA, | |
280 | 1, | |
281 | 0, | |
282 | 0x10, | |
283 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
284 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
285 | { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
286 | 90, | |
287 | true | |
288 | }; | |
289 | ||
290 | static const struct si_dte_data dte_data_new_zealand = | |
291 | { | |
292 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, | |
293 | { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, | |
294 | 0x5, | |
295 | 0xAFC8, | |
296 | 0x69, | |
297 | 0x32, | |
298 | 1, | |
299 | 0, | |
300 | 0x10, | |
301 | { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, | |
302 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
303 | { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, | |
304 | 85, | |
305 | true | |
306 | }; | |
307 | ||
308 | static const struct si_dte_data dte_data_aruba_pro = | |
309 | { | |
310 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
311 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
312 | 5, | |
313 | 45000, | |
314 | 100, | |
315 | 0xA, | |
316 | 1, | |
317 | 0, | |
318 | 0x10, | |
319 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
320 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
321 | { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
322 | 90, | |
323 | true | |
324 | }; | |
325 | ||
326 | static const struct si_dte_data dte_data_malta = | |
327 | { | |
328 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
329 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
330 | 5, | |
331 | 45000, | |
332 | 100, | |
333 | 0xA, | |
334 | 1, | |
335 | 0, | |
336 | 0x10, | |
337 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
338 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
339 | { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
340 | 90, | |
341 | true | |
342 | }; | |
343 | ||
344 | struct si_cac_config_reg cac_weights_pitcairn[] = | |
345 | { | |
346 | { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, | |
347 | { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
348 | { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
349 | { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, | |
350 | { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, | |
351 | { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, | |
352 | { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
353 | { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, | |
354 | { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
355 | { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, | |
356 | { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, | |
357 | { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, | |
358 | { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, | |
359 | { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, | |
360 | { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
361 | { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
362 | { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
363 | { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, | |
364 | { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, | |
365 | { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, | |
366 | { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, | |
367 | { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, | |
368 | { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, | |
369 | { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
370 | { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
371 | { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, | |
372 | { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, | |
373 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
374 | { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
375 | { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
376 | { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, | |
377 | { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
378 | { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, | |
379 | { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
380 | { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, | |
381 | { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, | |
382 | { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, | |
383 | { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
384 | { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, | |
385 | { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
386 | { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
387 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
388 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
389 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
390 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
391 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
392 | { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
393 | { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
394 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
395 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
396 | { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
397 | { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
398 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
399 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
400 | { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
401 | { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
402 | { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
403 | { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
404 | { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
405 | { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, | |
406 | { 0xFFFFFFFF } | |
407 | }; | |
408 | ||
409 | static const struct si_cac_config_reg lcac_pitcairn[] = | |
410 | { | |
411 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
412 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
413 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
414 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
415 | { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
416 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
417 | { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
418 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
419 | { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
420 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
421 | { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
422 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
423 | { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
424 | { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
425 | { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
426 | { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
427 | { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
428 | { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
429 | { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
430 | { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
431 | { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
432 | { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
433 | { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
434 | { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
435 | { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
436 | { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
437 | { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
438 | { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
439 | { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
440 | { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
441 | { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
442 | { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
443 | { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
444 | { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
445 | { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
446 | { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
447 | { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
448 | { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
449 | { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
450 | { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
451 | { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
452 | { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
453 | { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
454 | { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
455 | { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
456 | { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
457 | { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
458 | { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
459 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
460 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
461 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
462 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
463 | { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
464 | { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
465 | { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
466 | { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
467 | { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
468 | { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
469 | { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
470 | { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
471 | { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
472 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
473 | { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
474 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
475 | { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
476 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
477 | { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
478 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
479 | { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
480 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
481 | { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
482 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
483 | { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
484 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
485 | { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
486 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
487 | { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
488 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
489 | { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
490 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
491 | { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
492 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
493 | { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
494 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
495 | { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
496 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
497 | { 0xFFFFFFFF } | |
498 | }; | |
499 | ||
500 | static const struct si_cac_config_reg cac_override_pitcairn[] = | |
501 | { | |
3cf8bb1a | 502 | { 0xFFFFFFFF } |
a9e61410 AD |
503 | }; |
504 | ||
505 | static const struct si_powertune_data powertune_data_pitcairn = | |
506 | { | |
507 | ((1 << 16) | 27027), | |
508 | 5, | |
509 | 0, | |
510 | 6, | |
511 | 100, | |
512 | { | |
513 | 51600000UL, | |
514 | 1800000UL, | |
515 | 7194395UL, | |
516 | 309631529UL, | |
517 | -1270850L, | |
518 | 4513710L, | |
519 | 100 | |
520 | }, | |
521 | 117830498UL, | |
522 | 12, | |
523 | { | |
524 | 0, | |
525 | 0, | |
526 | 0, | |
527 | 0, | |
528 | 0, | |
529 | 0, | |
530 | 0, | |
531 | 0 | |
532 | }, | |
533 | true | |
534 | }; | |
535 | ||
536 | static const struct si_dte_data dte_data_pitcairn = | |
537 | { | |
538 | { 0, 0, 0, 0, 0 }, | |
539 | { 0, 0, 0, 0, 0 }, | |
540 | 0, | |
541 | 0, | |
542 | 0, | |
543 | 0, | |
544 | 0, | |
545 | 0, | |
546 | 0, | |
547 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
548 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
549 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
550 | 0, | |
551 | false | |
552 | }; | |
553 | ||
554 | static const struct si_dte_data dte_data_curacao_xt = | |
555 | { | |
556 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
557 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
558 | 5, | |
559 | 45000, | |
560 | 100, | |
561 | 0xA, | |
562 | 1, | |
563 | 0, | |
564 | 0x10, | |
565 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
566 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
567 | { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
568 | 90, | |
569 | true | |
570 | }; | |
571 | ||
572 | static const struct si_dte_data dte_data_curacao_pro = | |
573 | { | |
574 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
575 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
576 | 5, | |
577 | 45000, | |
578 | 100, | |
579 | 0xA, | |
580 | 1, | |
581 | 0, | |
582 | 0x10, | |
583 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
584 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
585 | { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
586 | 90, | |
587 | true | |
588 | }; | |
589 | ||
590 | static const struct si_dte_data dte_data_neptune_xt = | |
591 | { | |
592 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
593 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
594 | 5, | |
595 | 45000, | |
596 | 100, | |
597 | 0xA, | |
598 | 1, | |
599 | 0, | |
600 | 0x10, | |
601 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
602 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
603 | { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
604 | 90, | |
605 | true | |
606 | }; | |
607 | ||
608 | static const struct si_cac_config_reg cac_weights_chelsea_pro[] = | |
609 | { | |
610 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, | |
611 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
612 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, | |
613 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, | |
614 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
615 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
616 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
617 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
618 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, | |
619 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, | |
620 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, | |
621 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, | |
622 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, | |
623 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
624 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, | |
625 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, | |
626 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, | |
627 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, | |
628 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, | |
629 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, | |
630 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, | |
631 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, | |
632 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, | |
633 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
634 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
635 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
636 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
637 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
638 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
639 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
640 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
641 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
642 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, | |
643 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
644 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
645 | { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, | |
646 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
647 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
648 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
649 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
650 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, | |
651 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
652 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
653 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
654 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
655 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
656 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
657 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
658 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
659 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
660 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
661 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
662 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
663 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
664 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
665 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
666 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
667 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
668 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
669 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, | |
670 | { 0xFFFFFFFF } | |
671 | }; | |
672 | ||
673 | static const struct si_cac_config_reg cac_weights_chelsea_xt[] = | |
674 | { | |
675 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, | |
676 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
677 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, | |
678 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, | |
679 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
680 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
681 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
682 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
683 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, | |
684 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, | |
685 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, | |
686 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, | |
687 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, | |
688 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
689 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, | |
690 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, | |
691 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, | |
692 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, | |
693 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, | |
694 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, | |
695 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, | |
696 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, | |
697 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, | |
698 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
699 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
700 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
701 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
702 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
703 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
704 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
705 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
706 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
707 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, | |
708 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
709 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
710 | { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, | |
711 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
712 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
713 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
714 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
715 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, | |
716 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
717 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
718 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
719 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
720 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
721 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
722 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
723 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
724 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
725 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
726 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
727 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
728 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
729 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
730 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
731 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
732 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
733 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
734 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, | |
735 | { 0xFFFFFFFF } | |
736 | }; | |
737 | ||
738 | static const struct si_cac_config_reg cac_weights_heathrow[] = | |
739 | { | |
740 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, | |
741 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
742 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, | |
743 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, | |
744 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
745 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
746 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
747 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
748 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, | |
749 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, | |
750 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, | |
751 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, | |
752 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, | |
753 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
754 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, | |
755 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, | |
756 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, | |
757 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, | |
758 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, | |
759 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, | |
760 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, | |
761 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, | |
762 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, | |
763 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
764 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
765 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
766 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
767 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
768 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
769 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
770 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
771 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
772 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, | |
773 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
774 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
775 | { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, | |
776 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
777 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
778 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
779 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
780 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, | |
781 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
782 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
783 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
784 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
785 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
786 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
787 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
788 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
789 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
790 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
791 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
792 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
793 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
794 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
795 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
796 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
797 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
798 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
799 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, | |
800 | { 0xFFFFFFFF } | |
801 | }; | |
802 | ||
803 | static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = | |
804 | { | |
805 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, | |
806 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
807 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, | |
808 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, | |
809 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
810 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
811 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
812 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
813 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, | |
814 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, | |
815 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, | |
816 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, | |
817 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, | |
818 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
819 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, | |
820 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, | |
821 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, | |
822 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, | |
823 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, | |
824 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, | |
825 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, | |
826 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, | |
827 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, | |
828 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
829 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
830 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
831 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
832 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
833 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
834 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
835 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
836 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
837 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, | |
838 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
839 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
840 | { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, | |
841 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
842 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
843 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
844 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
845 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, | |
846 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
847 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
848 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
849 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
850 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
851 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
852 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
853 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
854 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
855 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
856 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
857 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
858 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
859 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
860 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
861 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
862 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
863 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
864 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, | |
865 | { 0xFFFFFFFF } | |
866 | }; | |
867 | ||
868 | static const struct si_cac_config_reg cac_weights_cape_verde[] = | |
869 | { | |
870 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, | |
871 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
872 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, | |
873 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, | |
874 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
875 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
876 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
877 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
878 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, | |
879 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, | |
880 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, | |
881 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, | |
882 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, | |
883 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
884 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, | |
885 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, | |
886 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, | |
887 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, | |
888 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, | |
889 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, | |
890 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, | |
891 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, | |
892 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, | |
893 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
894 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
895 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
896 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
897 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
898 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
899 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
900 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
901 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
902 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, | |
903 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
904 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
905 | { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, | |
906 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
907 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
908 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
909 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
910 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, | |
911 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
912 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
913 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
914 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
915 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
916 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
917 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
918 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
919 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
920 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
921 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
922 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
923 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
924 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
925 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
926 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
927 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
928 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
929 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, | |
930 | { 0xFFFFFFFF } | |
931 | }; | |
932 | ||
933 | static const struct si_cac_config_reg lcac_cape_verde[] = | |
934 | { | |
935 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
936 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
937 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
938 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
939 | { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
940 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
941 | { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
942 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
943 | { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
944 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
945 | { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
946 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
947 | { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
948 | { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
949 | { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
950 | { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
951 | { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
952 | { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
953 | { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
954 | { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
955 | { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
956 | { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
957 | { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
958 | { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
959 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
960 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
961 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
962 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
963 | { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
964 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
965 | { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
966 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
967 | { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
968 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
969 | { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
970 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
971 | { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
972 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
973 | { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
974 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
975 | { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
976 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
977 | { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
978 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
979 | { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
980 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
981 | { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
982 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
983 | { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
984 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
985 | { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
986 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
987 | { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
988 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
989 | { 0xFFFFFFFF } | |
990 | }; | |
991 | ||
992 | static const struct si_cac_config_reg cac_override_cape_verde[] = | |
993 | { | |
3cf8bb1a | 994 | { 0xFFFFFFFF } |
a9e61410 AD |
995 | }; |
996 | ||
997 | static const struct si_powertune_data powertune_data_cape_verde = | |
998 | { | |
999 | ((1 << 16) | 0x6993), | |
1000 | 5, | |
1001 | 0, | |
1002 | 7, | |
1003 | 105, | |
1004 | { | |
1005 | 0UL, | |
1006 | 0UL, | |
1007 | 7194395UL, | |
1008 | 309631529UL, | |
1009 | -1270850L, | |
1010 | 4513710L, | |
1011 | 100 | |
1012 | }, | |
1013 | 117830498UL, | |
1014 | 12, | |
1015 | { | |
1016 | 0, | |
1017 | 0, | |
1018 | 0, | |
1019 | 0, | |
1020 | 0, | |
1021 | 0, | |
1022 | 0, | |
1023 | 0 | |
1024 | }, | |
1025 | true | |
1026 | }; | |
1027 | ||
1028 | static const struct si_dte_data dte_data_cape_verde = | |
1029 | { | |
1030 | { 0, 0, 0, 0, 0 }, | |
1031 | { 0, 0, 0, 0, 0 }, | |
1032 | 0, | |
1033 | 0, | |
1034 | 0, | |
1035 | 0, | |
1036 | 0, | |
1037 | 0, | |
1038 | 0, | |
1039 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
1040 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
1041 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
1042 | 0, | |
1043 | false | |
1044 | }; | |
1045 | ||
1046 | static const struct si_dte_data dte_data_venus_xtx = | |
1047 | { | |
1048 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
1049 | { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, | |
1050 | 5, | |
1051 | 55000, | |
1052 | 0x69, | |
1053 | 0xA, | |
1054 | 1, | |
1055 | 0, | |
1056 | 0x3, | |
1057 | { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1058 | { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1059 | { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1060 | 90, | |
1061 | true | |
1062 | }; | |
1063 | ||
1064 | static const struct si_dte_data dte_data_venus_xt = | |
1065 | { | |
1066 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
1067 | { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, | |
1068 | 5, | |
1069 | 55000, | |
1070 | 0x69, | |
1071 | 0xA, | |
1072 | 1, | |
1073 | 0, | |
1074 | 0x3, | |
1075 | { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1076 | { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1077 | { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1078 | 90, | |
1079 | true | |
1080 | }; | |
1081 | ||
1082 | static const struct si_dte_data dte_data_venus_pro = | |
1083 | { | |
1084 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
1085 | { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, | |
1086 | 5, | |
1087 | 55000, | |
1088 | 0x69, | |
1089 | 0xA, | |
1090 | 1, | |
1091 | 0, | |
1092 | 0x3, | |
1093 | { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1094 | { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1095 | { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1096 | 90, | |
1097 | true | |
1098 | }; | |
1099 | ||
1100 | struct si_cac_config_reg cac_weights_oland[] = | |
1101 | { | |
1102 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, | |
1103 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
1104 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, | |
1105 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, | |
1106 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1107 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
1108 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
1109 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
1110 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, | |
1111 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, | |
1112 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, | |
1113 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, | |
1114 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, | |
1115 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
1116 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, | |
1117 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, | |
1118 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, | |
1119 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, | |
1120 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, | |
1121 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, | |
1122 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, | |
1123 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, | |
1124 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, | |
1125 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
1126 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
1127 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1128 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
1129 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1130 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1131 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1132 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1133 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
1134 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, | |
1135 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
1136 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
1137 | { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, | |
1138 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1139 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1140 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1141 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
1142 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, | |
1143 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1144 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1145 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1146 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1147 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1148 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1149 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1150 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1151 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1152 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1153 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1154 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1155 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1156 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1157 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1158 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1159 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1160 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1161 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, | |
1162 | { 0xFFFFFFFF } | |
1163 | }; | |
1164 | ||
1165 | static const struct si_cac_config_reg cac_weights_mars_pro[] = | |
1166 | { | |
1167 | { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, | |
1168 | { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1169 | { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, | |
1170 | { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, | |
1171 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1172 | { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1173 | { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1174 | { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1175 | { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, | |
1176 | { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, | |
1177 | { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, | |
1178 | { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, | |
1179 | { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, | |
1180 | { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, | |
1181 | { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, | |
1182 | { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, | |
1183 | { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, | |
1184 | { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1185 | { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, | |
1186 | { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, | |
1187 | { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, | |
1188 | { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, | |
1189 | { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, | |
1190 | { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1191 | { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1192 | { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, | |
1193 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
1194 | { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1195 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1196 | { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
1197 | { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
1198 | { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1199 | { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1200 | { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1201 | { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1202 | { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1203 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1204 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1205 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1206 | { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, | |
1207 | { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, | |
1208 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1209 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1210 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1211 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1212 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1213 | { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, | |
1214 | { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1215 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1216 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1217 | { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, | |
1218 | { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, | |
1219 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1220 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1221 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1222 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1223 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1224 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1225 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1226 | { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, | |
1227 | { 0xFFFFFFFF } | |
1228 | }; | |
1229 | ||
1230 | static const struct si_cac_config_reg cac_weights_mars_xt[] = | |
1231 | { | |
1232 | { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, | |
1233 | { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1234 | { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, | |
1235 | { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, | |
1236 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1237 | { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1238 | { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1239 | { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1240 | { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, | |
1241 | { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, | |
1242 | { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, | |
1243 | { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, | |
1244 | { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, | |
1245 | { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, | |
1246 | { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, | |
1247 | { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, | |
1248 | { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, | |
1249 | { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1250 | { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, | |
1251 | { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, | |
1252 | { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, | |
1253 | { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, | |
1254 | { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, | |
1255 | { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1256 | { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1257 | { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, | |
1258 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
1259 | { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1260 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1261 | { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
1262 | { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
1263 | { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1264 | { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1265 | { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1266 | { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1267 | { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, | |
1268 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1269 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1270 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1271 | { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, | |
1272 | { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, | |
1273 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1274 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1275 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1276 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1277 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1278 | { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, | |
1279 | { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1280 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1281 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1282 | { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, | |
1283 | { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, | |
1284 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1285 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1286 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1287 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1288 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1289 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1290 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1291 | { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, | |
1292 | { 0xFFFFFFFF } | |
1293 | }; | |
1294 | ||
1295 | static const struct si_cac_config_reg cac_weights_oland_pro[] = | |
1296 | { | |
1297 | { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, | |
1298 | { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1299 | { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, | |
1300 | { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, | |
1301 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1302 | { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1303 | { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1304 | { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1305 | { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, | |
1306 | { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, | |
1307 | { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, | |
1308 | { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, | |
1309 | { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, | |
1310 | { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, | |
1311 | { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, | |
1312 | { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, | |
1313 | { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, | |
1314 | { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1315 | { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, | |
1316 | { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, | |
1317 | { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, | |
1318 | { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, | |
1319 | { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, | |
1320 | { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1321 | { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1322 | { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, | |
1323 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
1324 | { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1325 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1326 | { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
1327 | { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
1328 | { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1329 | { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1330 | { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1331 | { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1332 | { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, | |
1333 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1334 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1335 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1336 | { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, | |
1337 | { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, | |
1338 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1339 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1340 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1341 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1342 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1343 | { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, | |
1344 | { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1345 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1346 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1347 | { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, | |
1348 | { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, | |
1349 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1350 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1351 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1352 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1353 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1354 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1355 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1356 | { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, | |
1357 | { 0xFFFFFFFF } | |
1358 | }; | |
1359 | ||
1360 | static const struct si_cac_config_reg cac_weights_oland_xt[] = | |
1361 | { | |
1362 | { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, | |
1363 | { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1364 | { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, | |
1365 | { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, | |
1366 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1367 | { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1368 | { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1369 | { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1370 | { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, | |
1371 | { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, | |
1372 | { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, | |
1373 | { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, | |
1374 | { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, | |
1375 | { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, | |
1376 | { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, | |
1377 | { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, | |
1378 | { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, | |
1379 | { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1380 | { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, | |
1381 | { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, | |
1382 | { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, | |
1383 | { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, | |
1384 | { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, | |
1385 | { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1386 | { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1387 | { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, | |
1388 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
1389 | { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1390 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1391 | { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
1392 | { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
1393 | { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1394 | { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1395 | { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1396 | { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1397 | { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, | |
1398 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1399 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1400 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1401 | { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, | |
1402 | { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, | |
1403 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1404 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1405 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1406 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1407 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1408 | { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, | |
1409 | { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1410 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1411 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1412 | { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, | |
1413 | { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, | |
1414 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1415 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1416 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1417 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1418 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1419 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1420 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1421 | { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, | |
1422 | { 0xFFFFFFFF } | |
1423 | }; | |
1424 | ||
1425 | static const struct si_cac_config_reg lcac_oland[] = | |
1426 | { | |
1427 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1428 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1429 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1430 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1431 | { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1432 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1433 | { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1434 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1435 | { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1436 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1437 | { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
1438 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1439 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1440 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1441 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1442 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1443 | { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1444 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1445 | { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1446 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1447 | { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1448 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1449 | { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1450 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1451 | { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1452 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1453 | { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1454 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1455 | { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1456 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1457 | { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1458 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1459 | { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1460 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1461 | { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1462 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1463 | { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1464 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1465 | { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1466 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1467 | { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1468 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1469 | { 0xFFFFFFFF } | |
1470 | }; | |
1471 | ||
1472 | static const struct si_cac_config_reg lcac_mars_pro[] = | |
1473 | { | |
1474 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1475 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1476 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1477 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1478 | { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1479 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1480 | { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1481 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1482 | { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1483 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1484 | { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1485 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1486 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1487 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1488 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1489 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1490 | { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1491 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1492 | { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1493 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1494 | { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1495 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1496 | { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1497 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1498 | { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1499 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1500 | { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1501 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1502 | { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1503 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1504 | { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1505 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1506 | { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1507 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1508 | { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1509 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1510 | { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1511 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1512 | { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1513 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1514 | { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1515 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1516 | { 0xFFFFFFFF } | |
1517 | }; | |
1518 | ||
1519 | static const struct si_cac_config_reg cac_override_oland[] = | |
1520 | { | |
1521 | { 0xFFFFFFFF } | |
1522 | }; | |
1523 | ||
1524 | static const struct si_powertune_data powertune_data_oland = | |
1525 | { | |
1526 | ((1 << 16) | 0x6993), | |
1527 | 5, | |
1528 | 0, | |
1529 | 7, | |
1530 | 105, | |
1531 | { | |
1532 | 0UL, | |
1533 | 0UL, | |
1534 | 7194395UL, | |
1535 | 309631529UL, | |
1536 | -1270850L, | |
1537 | 4513710L, | |
1538 | 100 | |
1539 | }, | |
1540 | 117830498UL, | |
1541 | 12, | |
1542 | { | |
1543 | 0, | |
1544 | 0, | |
1545 | 0, | |
1546 | 0, | |
1547 | 0, | |
1548 | 0, | |
1549 | 0, | |
1550 | 0 | |
1551 | }, | |
1552 | true | |
1553 | }; | |
1554 | ||
1555 | static const struct si_powertune_data powertune_data_mars_pro = | |
1556 | { | |
1557 | ((1 << 16) | 0x6993), | |
1558 | 5, | |
1559 | 0, | |
1560 | 7, | |
1561 | 105, | |
1562 | { | |
1563 | 0UL, | |
1564 | 0UL, | |
1565 | 7194395UL, | |
1566 | 309631529UL, | |
1567 | -1270850L, | |
1568 | 4513710L, | |
1569 | 100 | |
1570 | }, | |
1571 | 117830498UL, | |
1572 | 12, | |
1573 | { | |
1574 | 0, | |
1575 | 0, | |
1576 | 0, | |
1577 | 0, | |
1578 | 0, | |
1579 | 0, | |
1580 | 0, | |
1581 | 0 | |
1582 | }, | |
1583 | true | |
1584 | }; | |
1585 | ||
1586 | static const struct si_dte_data dte_data_oland = | |
1587 | { | |
1588 | { 0, 0, 0, 0, 0 }, | |
1589 | { 0, 0, 0, 0, 0 }, | |
1590 | 0, | |
1591 | 0, | |
1592 | 0, | |
1593 | 0, | |
1594 | 0, | |
1595 | 0, | |
1596 | 0, | |
1597 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
1598 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
1599 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
1600 | 0, | |
1601 | false | |
1602 | }; | |
1603 | ||
1604 | static const struct si_dte_data dte_data_mars_pro = | |
1605 | { | |
1606 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
1607 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1608 | 5, | |
1609 | 55000, | |
1610 | 105, | |
1611 | 0xA, | |
1612 | 1, | |
1613 | 0, | |
1614 | 0x10, | |
1615 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
1616 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
1617 | { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1618 | 90, | |
1619 | true | |
1620 | }; | |
1621 | ||
1622 | static const struct si_dte_data dte_data_sun_xt = | |
1623 | { | |
1624 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
1625 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1626 | 5, | |
1627 | 55000, | |
1628 | 105, | |
1629 | 0xA, | |
1630 | 1, | |
1631 | 0, | |
1632 | 0x10, | |
1633 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
1634 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
1635 | { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1636 | 90, | |
1637 | true | |
1638 | }; | |
1639 | ||
1640 | ||
1641 | static const struct si_cac_config_reg cac_weights_hainan[] = | |
1642 | { | |
1643 | { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, | |
1644 | { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, | |
1645 | { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, | |
1646 | { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, | |
1647 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1648 | { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, | |
1649 | { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1650 | { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1651 | { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1652 | { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, | |
1653 | { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, | |
1654 | { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, | |
1655 | { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, | |
1656 | { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1657 | { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, | |
1658 | { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1659 | { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1660 | { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, | |
1661 | { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, | |
1662 | { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, | |
1663 | { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, | |
1664 | { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, | |
1665 | { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, | |
1666 | { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, | |
1667 | { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1668 | { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, | |
1669 | { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, | |
1670 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1671 | { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1672 | { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1673 | { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, | |
1674 | { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1675 | { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1676 | { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1677 | { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, | |
1678 | { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, | |
1679 | { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, | |
1680 | { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1681 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1682 | { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, | |
1683 | { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1684 | { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, | |
1685 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1686 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1687 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1688 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1689 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1690 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1691 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1692 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1693 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1694 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1695 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1696 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1697 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1698 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1699 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1700 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1701 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1702 | { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, | |
1703 | { 0xFFFFFFFF } | |
1704 | }; | |
1705 | ||
1706 | static const struct si_powertune_data powertune_data_hainan = | |
1707 | { | |
1708 | ((1 << 16) | 0x6993), | |
1709 | 5, | |
1710 | 0, | |
1711 | 9, | |
1712 | 105, | |
1713 | { | |
1714 | 0UL, | |
1715 | 0UL, | |
1716 | 7194395UL, | |
1717 | 309631529UL, | |
1718 | -1270850L, | |
1719 | 4513710L, | |
1720 | 100 | |
1721 | }, | |
1722 | 117830498UL, | |
1723 | 12, | |
1724 | { | |
1725 | 0, | |
1726 | 0, | |
1727 | 0, | |
1728 | 0, | |
1729 | 0, | |
1730 | 0, | |
1731 | 0, | |
1732 | 0 | |
1733 | }, | |
1734 | true | |
1735 | }; | |
1736 | ||
1737 | struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); | |
1738 | struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); | |
1739 | struct ni_power_info *ni_get_pi(struct radeon_device *rdev); | |
1740 | struct ni_ps *ni_get_ps(struct radeon_ps *rps); | |
1741 | ||
6c7bccea | 1742 | extern int si_mc_load_microcode(struct radeon_device *rdev); |
84bcd469 | 1743 | extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); |
6c7bccea | 1744 | |
a9e61410 AD |
1745 | static int si_populate_voltage_value(struct radeon_device *rdev, |
1746 | const struct atom_voltage_table *table, | |
1747 | u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); | |
1748 | static int si_get_std_voltage_value(struct radeon_device *rdev, | |
1749 | SISLANDS_SMC_VOLTAGE_VALUE *voltage, | |
1750 | u16 *std_voltage); | |
1751 | static int si_write_smc_soft_register(struct radeon_device *rdev, | |
1752 | u16 reg_offset, u32 value); | |
1753 | static int si_convert_power_level_to_smc(struct radeon_device *rdev, | |
1754 | struct rv7xx_pl *pl, | |
1755 | SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); | |
1756 | static int si_calculate_sclk_params(struct radeon_device *rdev, | |
1757 | u32 engine_clock, | |
1758 | SISLANDS_SMC_SCLK_VALUE *sclk); | |
1759 | ||
5e8150a6 AD |
1760 | static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); |
1761 | static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); | |
1762 | ||
a9e61410 AD |
1763 | static struct si_power_info *si_get_pi(struct radeon_device *rdev) |
1764 | { | |
3cf8bb1a | 1765 | struct si_power_info *pi = rdev->pm.dpm.priv; |
a9e61410 | 1766 | |
3cf8bb1a | 1767 | return pi; |
a9e61410 AD |
1768 | } |
1769 | ||
1770 | static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, | |
1771 | u16 v, s32 t, u32 ileakage, u32 *leakage) | |
1772 | { | |
1773 | s64 kt, kv, leakage_w, i_leakage, vddc; | |
1774 | s64 temperature, t_slope, t_intercept, av, bv, t_ref; | |
31f731af | 1775 | s64 tmp; |
a9e61410 | 1776 | |
adfb8e51 | 1777 | i_leakage = div64_s64(drm_int2fixp(ileakage), 100); |
a9e61410 AD |
1778 | vddc = div64_s64(drm_int2fixp(v), 1000); |
1779 | temperature = div64_s64(drm_int2fixp(t), 1000); | |
1780 | ||
1781 | t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); | |
1782 | t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); | |
1783 | av = div64_s64(drm_int2fixp(coeff->av), 100000000); | |
1784 | bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); | |
1785 | t_ref = drm_int2fixp(coeff->t_ref); | |
1786 | ||
31f731af AD |
1787 | tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; |
1788 | kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); | |
1789 | kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); | |
a9e61410 AD |
1790 | kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); |
1791 | ||
1792 | leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); | |
1793 | ||
1794 | *leakage = drm_fixp2int(leakage_w * 1000); | |
1795 | } | |
1796 | ||
1797 | static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, | |
1798 | const struct ni_leakage_coeffients *coeff, | |
1799 | u16 v, | |
1800 | s32 t, | |
1801 | u32 i_leakage, | |
1802 | u32 *leakage) | |
1803 | { | |
1804 | si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); | |
1805 | } | |
1806 | ||
1807 | static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, | |
1808 | const u32 fixed_kt, u16 v, | |
1809 | u32 ileakage, u32 *leakage) | |
1810 | { | |
1811 | s64 kt, kv, leakage_w, i_leakage, vddc; | |
1812 | ||
1813 | i_leakage = div64_s64(drm_int2fixp(ileakage), 100); | |
1814 | vddc = div64_s64(drm_int2fixp(v), 1000); | |
1815 | ||
1816 | kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); | |
1817 | kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), | |
1818 | drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); | |
1819 | ||
1820 | leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); | |
1821 | ||
1822 | *leakage = drm_fixp2int(leakage_w * 1000); | |
1823 | } | |
1824 | ||
1825 | static void si_calculate_leakage_for_v(struct radeon_device *rdev, | |
1826 | const struct ni_leakage_coeffients *coeff, | |
1827 | const u32 fixed_kt, | |
1828 | u16 v, | |
1829 | u32 i_leakage, | |
1830 | u32 *leakage) | |
1831 | { | |
1832 | si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); | |
1833 | } | |
1834 | ||
1835 | ||
1836 | static void si_update_dte_from_pl2(struct radeon_device *rdev, | |
1837 | struct si_dte_data *dte_data) | |
1838 | { | |
1839 | u32 p_limit1 = rdev->pm.dpm.tdp_limit; | |
1840 | u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; | |
1841 | u32 k = dte_data->k; | |
1842 | u32 t_max = dte_data->max_t; | |
1843 | u32 t_split[5] = { 10, 15, 20, 25, 30 }; | |
1844 | u32 t_0 = dte_data->t0; | |
1845 | u32 i; | |
1846 | ||
1847 | if (p_limit2 != 0 && p_limit2 <= p_limit1) { | |
1848 | dte_data->tdep_count = 3; | |
1849 | ||
1850 | for (i = 0; i < k; i++) { | |
1851 | dte_data->r[i] = | |
1852 | (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / | |
1853 | (p_limit2 * (u32)100); | |
1854 | } | |
1855 | ||
1856 | dte_data->tdep_r[1] = dte_data->r[4] * 2; | |
1857 | ||
1858 | for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { | |
1859 | dte_data->tdep_r[i] = dte_data->r[4]; | |
1860 | } | |
1861 | } else { | |
1862 | DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); | |
1863 | } | |
1864 | } | |
1865 | ||
1866 | static void si_initialize_powertune_defaults(struct radeon_device *rdev) | |
1867 | { | |
1868 | struct ni_power_info *ni_pi = ni_get_pi(rdev); | |
1869 | struct si_power_info *si_pi = si_get_pi(rdev); | |
1870 | bool update_dte_from_pl2 = false; | |
1871 | ||
1872 | if (rdev->family == CHIP_TAHITI) { | |
1873 | si_pi->cac_weights = cac_weights_tahiti; | |
1874 | si_pi->lcac_config = lcac_tahiti; | |
1875 | si_pi->cac_override = cac_override_tahiti; | |
1876 | si_pi->powertune_data = &powertune_data_tahiti; | |
1877 | si_pi->dte_data = dte_data_tahiti; | |
1878 | ||
1879 | switch (rdev->pdev->device) { | |
1880 | case 0x6798: | |
1881 | si_pi->dte_data.enable_dte_by_default = true; | |
1882 | break; | |
1883 | case 0x6799: | |
1884 | si_pi->dte_data = dte_data_new_zealand; | |
1885 | break; | |
1886 | case 0x6790: | |
1887 | case 0x6791: | |
1888 | case 0x6792: | |
1889 | case 0x679E: | |
1890 | si_pi->dte_data = dte_data_aruba_pro; | |
1891 | update_dte_from_pl2 = true; | |
1892 | break; | |
1893 | case 0x679B: | |
1894 | si_pi->dte_data = dte_data_malta; | |
1895 | update_dte_from_pl2 = true; | |
1896 | break; | |
1897 | case 0x679A: | |
1898 | si_pi->dte_data = dte_data_tahiti_pro; | |
1899 | update_dte_from_pl2 = true; | |
1900 | break; | |
1901 | default: | |
1902 | if (si_pi->dte_data.enable_dte_by_default == true) | |
1903 | DRM_ERROR("DTE is not enabled!\n"); | |
1904 | break; | |
1905 | } | |
1906 | } else if (rdev->family == CHIP_PITCAIRN) { | |
1907 | switch (rdev->pdev->device) { | |
1908 | case 0x6810: | |
1909 | case 0x6818: | |
1910 | si_pi->cac_weights = cac_weights_pitcairn; | |
1911 | si_pi->lcac_config = lcac_pitcairn; | |
1912 | si_pi->cac_override = cac_override_pitcairn; | |
1913 | si_pi->powertune_data = &powertune_data_pitcairn; | |
1914 | si_pi->dte_data = dte_data_curacao_xt; | |
1915 | update_dte_from_pl2 = true; | |
1916 | break; | |
1917 | case 0x6819: | |
1918 | case 0x6811: | |
1919 | si_pi->cac_weights = cac_weights_pitcairn; | |
1920 | si_pi->lcac_config = lcac_pitcairn; | |
1921 | si_pi->cac_override = cac_override_pitcairn; | |
1922 | si_pi->powertune_data = &powertune_data_pitcairn; | |
1923 | si_pi->dte_data = dte_data_curacao_pro; | |
1924 | update_dte_from_pl2 = true; | |
1925 | break; | |
1926 | case 0x6800: | |
1927 | case 0x6806: | |
1928 | si_pi->cac_weights = cac_weights_pitcairn; | |
1929 | si_pi->lcac_config = lcac_pitcairn; | |
1930 | si_pi->cac_override = cac_override_pitcairn; | |
1931 | si_pi->powertune_data = &powertune_data_pitcairn; | |
1932 | si_pi->dte_data = dte_data_neptune_xt; | |
1933 | update_dte_from_pl2 = true; | |
1934 | break; | |
1935 | default: | |
1936 | si_pi->cac_weights = cac_weights_pitcairn; | |
1937 | si_pi->lcac_config = lcac_pitcairn; | |
1938 | si_pi->cac_override = cac_override_pitcairn; | |
1939 | si_pi->powertune_data = &powertune_data_pitcairn; | |
1940 | si_pi->dte_data = dte_data_pitcairn; | |
d05f7e70 | 1941 | break; |
a9e61410 AD |
1942 | } |
1943 | } else if (rdev->family == CHIP_VERDE) { | |
1944 | si_pi->lcac_config = lcac_cape_verde; | |
1945 | si_pi->cac_override = cac_override_cape_verde; | |
1946 | si_pi->powertune_data = &powertune_data_cape_verde; | |
1947 | ||
1948 | switch (rdev->pdev->device) { | |
1949 | case 0x683B: | |
1950 | case 0x683F: | |
1951 | case 0x6829: | |
46348dc2 | 1952 | case 0x6835: |
a9e61410 AD |
1953 | si_pi->cac_weights = cac_weights_cape_verde_pro; |
1954 | si_pi->dte_data = dte_data_cape_verde; | |
1955 | break; | |
8a309113 AD |
1956 | case 0x682C: |
1957 | si_pi->cac_weights = cac_weights_cape_verde_pro; | |
1958 | si_pi->dte_data = dte_data_sun_xt; | |
1959 | break; | |
a9e61410 AD |
1960 | case 0x6825: |
1961 | case 0x6827: | |
1962 | si_pi->cac_weights = cac_weights_heathrow; | |
1963 | si_pi->dte_data = dte_data_cape_verde; | |
1964 | break; | |
1965 | case 0x6824: | |
1966 | case 0x682D: | |
1967 | si_pi->cac_weights = cac_weights_chelsea_xt; | |
1968 | si_pi->dte_data = dte_data_cape_verde; | |
1969 | break; | |
1970 | case 0x682F: | |
1971 | si_pi->cac_weights = cac_weights_chelsea_pro; | |
1972 | si_pi->dte_data = dte_data_cape_verde; | |
1973 | break; | |
1974 | case 0x6820: | |
1975 | si_pi->cac_weights = cac_weights_heathrow; | |
1976 | si_pi->dte_data = dte_data_venus_xtx; | |
1977 | break; | |
1978 | case 0x6821: | |
1979 | si_pi->cac_weights = cac_weights_heathrow; | |
1980 | si_pi->dte_data = dte_data_venus_xt; | |
1981 | break; | |
1982 | case 0x6823: | |
a9e61410 | 1983 | case 0x682B: |
8a309113 AD |
1984 | case 0x6822: |
1985 | case 0x682A: | |
a9e61410 AD |
1986 | si_pi->cac_weights = cac_weights_chelsea_pro; |
1987 | si_pi->dte_data = dte_data_venus_pro; | |
1988 | break; | |
1989 | default: | |
1990 | si_pi->cac_weights = cac_weights_cape_verde; | |
1991 | si_pi->dte_data = dte_data_cape_verde; | |
1992 | break; | |
1993 | } | |
1994 | } else if (rdev->family == CHIP_OLAND) { | |
1995 | switch (rdev->pdev->device) { | |
1996 | case 0x6601: | |
1997 | case 0x6621: | |
1998 | case 0x6603: | |
8a309113 | 1999 | case 0x6605: |
a9e61410 AD |
2000 | si_pi->cac_weights = cac_weights_mars_pro; |
2001 | si_pi->lcac_config = lcac_mars_pro; | |
2002 | si_pi->cac_override = cac_override_oland; | |
2003 | si_pi->powertune_data = &powertune_data_mars_pro; | |
2004 | si_pi->dte_data = dte_data_mars_pro; | |
2005 | update_dte_from_pl2 = true; | |
2006 | break; | |
2007 | case 0x6600: | |
2008 | case 0x6606: | |
2009 | case 0x6620: | |
8a309113 | 2010 | case 0x6604: |
a9e61410 AD |
2011 | si_pi->cac_weights = cac_weights_mars_xt; |
2012 | si_pi->lcac_config = lcac_mars_pro; | |
2013 | si_pi->cac_override = cac_override_oland; | |
2014 | si_pi->powertune_data = &powertune_data_mars_pro; | |
2015 | si_pi->dte_data = dte_data_mars_pro; | |
2016 | update_dte_from_pl2 = true; | |
2017 | break; | |
2018 | case 0x6611: | |
8a309113 AD |
2019 | case 0x6613: |
2020 | case 0x6608: | |
a9e61410 AD |
2021 | si_pi->cac_weights = cac_weights_oland_pro; |
2022 | si_pi->lcac_config = lcac_mars_pro; | |
2023 | si_pi->cac_override = cac_override_oland; | |
2024 | si_pi->powertune_data = &powertune_data_mars_pro; | |
2025 | si_pi->dte_data = dte_data_mars_pro; | |
2026 | update_dte_from_pl2 = true; | |
2027 | break; | |
2028 | case 0x6610: | |
2029 | si_pi->cac_weights = cac_weights_oland_xt; | |
2030 | si_pi->lcac_config = lcac_mars_pro; | |
2031 | si_pi->cac_override = cac_override_oland; | |
2032 | si_pi->powertune_data = &powertune_data_mars_pro; | |
2033 | si_pi->dte_data = dte_data_mars_pro; | |
2034 | update_dte_from_pl2 = true; | |
2035 | break; | |
2036 | default: | |
2037 | si_pi->cac_weights = cac_weights_oland; | |
2038 | si_pi->lcac_config = lcac_oland; | |
2039 | si_pi->cac_override = cac_override_oland; | |
2040 | si_pi->powertune_data = &powertune_data_oland; | |
2041 | si_pi->dte_data = dte_data_oland; | |
2042 | break; | |
2043 | } | |
2044 | } else if (rdev->family == CHIP_HAINAN) { | |
2045 | si_pi->cac_weights = cac_weights_hainan; | |
2046 | si_pi->lcac_config = lcac_oland; | |
2047 | si_pi->cac_override = cac_override_oland; | |
2048 | si_pi->powertune_data = &powertune_data_hainan; | |
2049 | si_pi->dte_data = dte_data_sun_xt; | |
2050 | update_dte_from_pl2 = true; | |
2051 | } else { | |
2052 | DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); | |
2053 | return; | |
2054 | } | |
2055 | ||
2056 | ni_pi->enable_power_containment = false; | |
2057 | ni_pi->enable_cac = false; | |
2058 | ni_pi->enable_sq_ramping = false; | |
2059 | si_pi->enable_dte = false; | |
2060 | ||
5a344dda | 2061 | if (si_pi->powertune_data->enable_powertune_by_default) { |
a9e61410 AD |
2062 | ni_pi->enable_power_containment= true; |
2063 | ni_pi->enable_cac = true; | |
2064 | if (si_pi->dte_data.enable_dte_by_default) { | |
2065 | si_pi->enable_dte = true; | |
2066 | if (update_dte_from_pl2) | |
2067 | si_update_dte_from_pl2(rdev, &si_pi->dte_data); | |
2068 | ||
2069 | } | |
2070 | ni_pi->enable_sq_ramping = true; | |
2071 | } | |
2072 | ||
2073 | ni_pi->driver_calculate_cac_leakage = true; | |
2074 | ni_pi->cac_configuration_required = true; | |
2075 | ||
2076 | if (ni_pi->cac_configuration_required) { | |
2077 | ni_pi->support_cac_long_term_average = true; | |
2078 | si_pi->dyn_powertune_data.l2_lta_window_size = | |
2079 | si_pi->powertune_data->l2_lta_window_size_default; | |
2080 | si_pi->dyn_powertune_data.lts_truncate = | |
2081 | si_pi->powertune_data->lts_truncate_default; | |
2082 | } else { | |
2083 | ni_pi->support_cac_long_term_average = false; | |
2084 | si_pi->dyn_powertune_data.l2_lta_window_size = 0; | |
2085 | si_pi->dyn_powertune_data.lts_truncate = 0; | |
2086 | } | |
2087 | ||
2088 | si_pi->dyn_powertune_data.disable_uvd_powertune = false; | |
2089 | } | |
2090 | ||
2091 | static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) | |
2092 | { | |
2093 | return 1; | |
2094 | } | |
2095 | ||
2096 | static u32 si_calculate_cac_wintime(struct radeon_device *rdev) | |
2097 | { | |
2098 | u32 xclk; | |
2099 | u32 wintime; | |
2100 | u32 cac_window; | |
2101 | u32 cac_window_size; | |
2102 | ||
2103 | xclk = radeon_get_xclk(rdev); | |
2104 | ||
2105 | if (xclk == 0) | |
2106 | return 0; | |
2107 | ||
2108 | cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; | |
2109 | cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); | |
2110 | ||
2111 | wintime = (cac_window_size * 100) / xclk; | |
2112 | ||
2113 | return wintime; | |
2114 | } | |
2115 | ||
2116 | static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) | |
2117 | { | |
2118 | return power_in_watts; | |
2119 | } | |
2120 | ||
2121 | static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, | |
2122 | bool adjust_polarity, | |
2123 | u32 tdp_adjustment, | |
2124 | u32 *tdp_limit, | |
2125 | u32 *near_tdp_limit) | |
2126 | { | |
2127 | u32 adjustment_delta, max_tdp_limit; | |
2128 | ||
2129 | if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) | |
2130 | return -EINVAL; | |
2131 | ||
2132 | max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; | |
2133 | ||
2134 | if (adjust_polarity) { | |
2135 | *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; | |
2136 | *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); | |
2137 | } else { | |
2138 | *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; | |
2139 | adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; | |
2140 | if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) | |
2141 | *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; | |
2142 | else | |
2143 | *near_tdp_limit = 0; | |
2144 | } | |
2145 | ||
2146 | if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) | |
2147 | return -EINVAL; | |
2148 | if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) | |
2149 | return -EINVAL; | |
2150 | ||
2151 | return 0; | |
2152 | } | |
2153 | ||
2154 | static int si_populate_smc_tdp_limits(struct radeon_device *rdev, | |
2155 | struct radeon_ps *radeon_state) | |
2156 | { | |
2157 | struct ni_power_info *ni_pi = ni_get_pi(rdev); | |
2158 | struct si_power_info *si_pi = si_get_pi(rdev); | |
2159 | ||
2160 | if (ni_pi->enable_power_containment) { | |
2161 | SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; | |
2162 | PP_SIslands_PAPMParameters *papm_parm; | |
2163 | struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; | |
2164 | u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); | |
2165 | u32 tdp_limit; | |
2166 | u32 near_tdp_limit; | |
2167 | int ret; | |
2168 | ||
2169 | if (scaling_factor == 0) | |
2170 | return -EINVAL; | |
2171 | ||
2172 | memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); | |
2173 | ||
2174 | ret = si_calculate_adjusted_tdp_limits(rdev, | |
2175 | false, /* ??? */ | |
2176 | rdev->pm.dpm.tdp_adjustment, | |
2177 | &tdp_limit, | |
2178 | &near_tdp_limit); | |
2179 | if (ret) | |
2180 | return ret; | |
2181 | ||
2182 | smc_table->dpm2Params.TDPLimit = | |
2183 | cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); | |
2184 | smc_table->dpm2Params.NearTDPLimit = | |
2185 | cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); | |
2186 | smc_table->dpm2Params.SafePowerLimit = | |
2187 | cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); | |
2188 | ||
2189 | ret = si_copy_bytes_to_smc(rdev, | |
2190 | (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + | |
2191 | offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), | |
2192 | (u8 *)(&(smc_table->dpm2Params.TDPLimit)), | |
2193 | sizeof(u32) * 3, | |
2194 | si_pi->sram_end); | |
2195 | if (ret) | |
2196 | return ret; | |
2197 | ||
2198 | if (si_pi->enable_ppm) { | |
2199 | papm_parm = &si_pi->papm_parm; | |
2200 | memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); | |
2201 | papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); | |
2202 | papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); | |
2203 | papm_parm->dGPU_T_Warning = cpu_to_be32(95); | |
2204 | papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); | |
2205 | papm_parm->PlatformPowerLimit = 0xffffffff; | |
2206 | papm_parm->NearTDPLimitPAPM = 0xffffffff; | |
2207 | ||
2208 | ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, | |
2209 | (u8 *)papm_parm, | |
2210 | sizeof(PP_SIslands_PAPMParameters), | |
2211 | si_pi->sram_end); | |
2212 | if (ret) | |
2213 | return ret; | |
2214 | } | |
2215 | } | |
2216 | return 0; | |
2217 | } | |
2218 | ||
2219 | static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, | |
2220 | struct radeon_ps *radeon_state) | |
2221 | { | |
2222 | struct ni_power_info *ni_pi = ni_get_pi(rdev); | |
2223 | struct si_power_info *si_pi = si_get_pi(rdev); | |
2224 | ||
2225 | if (ni_pi->enable_power_containment) { | |
2226 | SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; | |
2227 | u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); | |
2228 | int ret; | |
2229 | ||
2230 | memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); | |
2231 | ||
2232 | smc_table->dpm2Params.NearTDPLimit = | |
2233 | cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); | |
2234 | smc_table->dpm2Params.SafePowerLimit = | |
2235 | cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); | |
2236 | ||
2237 | ret = si_copy_bytes_to_smc(rdev, | |
2238 | (si_pi->state_table_start + | |
2239 | offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + | |
2240 | offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), | |
2241 | (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), | |
2242 | sizeof(u32) * 2, | |
2243 | si_pi->sram_end); | |
2244 | if (ret) | |
2245 | return ret; | |
2246 | } | |
2247 | ||
2248 | return 0; | |
2249 | } | |
2250 | ||
2251 | static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, | |
2252 | const u16 prev_std_vddc, | |
2253 | const u16 curr_std_vddc) | |
2254 | { | |
2255 | u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; | |
2256 | u64 prev_vddc = (u64)prev_std_vddc; | |
2257 | u64 curr_vddc = (u64)curr_std_vddc; | |
2258 | u64 pwr_efficiency_ratio, n, d; | |
2259 | ||
2260 | if ((prev_vddc == 0) || (curr_vddc == 0)) | |
2261 | return 0; | |
2262 | ||
2263 | n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); | |
2264 | d = prev_vddc * prev_vddc; | |
2265 | pwr_efficiency_ratio = div64_u64(n, d); | |
2266 | ||
2267 | if (pwr_efficiency_ratio > (u64)0xFFFF) | |
2268 | return 0; | |
2269 | ||
2270 | return (u16)pwr_efficiency_ratio; | |
2271 | } | |
2272 | ||
2273 | static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, | |
2274 | struct radeon_ps *radeon_state) | |
2275 | { | |
2276 | struct si_power_info *si_pi = si_get_pi(rdev); | |
2277 | ||
2278 | if (si_pi->dyn_powertune_data.disable_uvd_powertune && | |
2279 | radeon_state->vclk && radeon_state->dclk) | |
2280 | return true; | |
2281 | ||
2282 | return false; | |
2283 | } | |
2284 | ||
2285 | static int si_populate_power_containment_values(struct radeon_device *rdev, | |
2286 | struct radeon_ps *radeon_state, | |
2287 | SISLANDS_SMC_SWSTATE *smc_state) | |
2288 | { | |
2289 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
2290 | struct ni_power_info *ni_pi = ni_get_pi(rdev); | |
2291 | struct ni_ps *state = ni_get_ps(radeon_state); | |
2292 | SISLANDS_SMC_VOLTAGE_VALUE vddc; | |
2293 | u32 prev_sclk; | |
2294 | u32 max_sclk; | |
2295 | u32 min_sclk; | |
2296 | u16 prev_std_vddc; | |
2297 | u16 curr_std_vddc; | |
2298 | int i; | |
2299 | u16 pwr_efficiency_ratio; | |
2300 | u8 max_ps_percent; | |
2301 | bool disable_uvd_power_tune; | |
2302 | int ret; | |
2303 | ||
2304 | if (ni_pi->enable_power_containment == false) | |
2305 | return 0; | |
2306 | ||
2307 | if (state->performance_level_count == 0) | |
2308 | return -EINVAL; | |
2309 | ||
2310 | if (smc_state->levelCount != state->performance_level_count) | |
2311 | return -EINVAL; | |
2312 | ||
2313 | disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); | |
2314 | ||
2315 | smc_state->levels[0].dpm2.MaxPS = 0; | |
2316 | smc_state->levels[0].dpm2.NearTDPDec = 0; | |
2317 | smc_state->levels[0].dpm2.AboveSafeInc = 0; | |
2318 | smc_state->levels[0].dpm2.BelowSafeInc = 0; | |
2319 | smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; | |
2320 | ||
2321 | for (i = 1; i < state->performance_level_count; i++) { | |
2322 | prev_sclk = state->performance_levels[i-1].sclk; | |
2323 | max_sclk = state->performance_levels[i].sclk; | |
2324 | if (i == 1) | |
2325 | max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; | |
2326 | else | |
2327 | max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; | |
2328 | ||
2329 | if (prev_sclk > max_sclk) | |
2330 | return -EINVAL; | |
2331 | ||
2332 | if ((max_ps_percent == 0) || | |
2333 | (prev_sclk == max_sclk) || | |
2334 | disable_uvd_power_tune) { | |
2335 | min_sclk = max_sclk; | |
2336 | } else if (i == 1) { | |
2337 | min_sclk = prev_sclk; | |
2338 | } else { | |
2339 | min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; | |
2340 | } | |
2341 | ||
2342 | if (min_sclk < state->performance_levels[0].sclk) | |
2343 | min_sclk = state->performance_levels[0].sclk; | |
2344 | ||
2345 | if (min_sclk == 0) | |
2346 | return -EINVAL; | |
2347 | ||
2348 | ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, | |
2349 | state->performance_levels[i-1].vddc, &vddc); | |
2350 | if (ret) | |
2351 | return ret; | |
2352 | ||
2353 | ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); | |
2354 | if (ret) | |
2355 | return ret; | |
2356 | ||
2357 | ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, | |
2358 | state->performance_levels[i].vddc, &vddc); | |
2359 | if (ret) | |
2360 | return ret; | |
2361 | ||
2362 | ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); | |
2363 | if (ret) | |
2364 | return ret; | |
2365 | ||
2366 | pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, | |
2367 | prev_std_vddc, curr_std_vddc); | |
2368 | ||
2369 | smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); | |
2370 | smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; | |
2371 | smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; | |
2372 | smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; | |
2373 | smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); | |
2374 | } | |
2375 | ||
2376 | return 0; | |
2377 | } | |
2378 | ||
2379 | static int si_populate_sq_ramping_values(struct radeon_device *rdev, | |
2380 | struct radeon_ps *radeon_state, | |
2381 | SISLANDS_SMC_SWSTATE *smc_state) | |
2382 | { | |
2383 | struct ni_power_info *ni_pi = ni_get_pi(rdev); | |
2384 | struct ni_ps *state = ni_get_ps(radeon_state); | |
2385 | u32 sq_power_throttle, sq_power_throttle2; | |
2386 | bool enable_sq_ramping = ni_pi->enable_sq_ramping; | |
2387 | int i; | |
2388 | ||
2389 | if (state->performance_level_count == 0) | |
2390 | return -EINVAL; | |
2391 | ||
2392 | if (smc_state->levelCount != state->performance_level_count) | |
2393 | return -EINVAL; | |
2394 | ||
2395 | if (rdev->pm.dpm.sq_ramping_threshold == 0) | |
2396 | return -EINVAL; | |
2397 | ||
2398 | if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) | |
2399 | enable_sq_ramping = false; | |
2400 | ||
2401 | if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) | |
2402 | enable_sq_ramping = false; | |
2403 | ||
2404 | if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) | |
2405 | enable_sq_ramping = false; | |
2406 | ||
2407 | if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) | |
2408 | enable_sq_ramping = false; | |
2409 | ||
5b43c3cd | 2410 | if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) |
a9e61410 AD |
2411 | enable_sq_ramping = false; |
2412 | ||
2413 | for (i = 0; i < state->performance_level_count; i++) { | |
2414 | sq_power_throttle = 0; | |
2415 | sq_power_throttle2 = 0; | |
2416 | ||
2417 | if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && | |
2418 | enable_sq_ramping) { | |
2419 | sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); | |
2420 | sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); | |
2421 | sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); | |
2422 | sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); | |
2423 | sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); | |
2424 | } else { | |
2425 | sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; | |
2426 | sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; | |
2427 | } | |
2428 | ||
2429 | smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); | |
2430 | smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); | |
2431 | } | |
2432 | ||
2433 | return 0; | |
2434 | } | |
2435 | ||
2436 | static int si_enable_power_containment(struct radeon_device *rdev, | |
2437 | struct radeon_ps *radeon_new_state, | |
2438 | bool enable) | |
2439 | { | |
2440 | struct ni_power_info *ni_pi = ni_get_pi(rdev); | |
2441 | PPSMC_Result smc_result; | |
2442 | int ret = 0; | |
2443 | ||
2444 | if (ni_pi->enable_power_containment) { | |
2445 | if (enable) { | |
2446 | if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { | |
2447 | smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); | |
2448 | if (smc_result != PPSMC_Result_OK) { | |
2449 | ret = -EINVAL; | |
2450 | ni_pi->pc_enabled = false; | |
2451 | } else { | |
2452 | ni_pi->pc_enabled = true; | |
2453 | } | |
2454 | } | |
2455 | } else { | |
2456 | smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); | |
2457 | if (smc_result != PPSMC_Result_OK) | |
2458 | ret = -EINVAL; | |
2459 | ni_pi->pc_enabled = false; | |
2460 | } | |
2461 | } | |
2462 | ||
2463 | return ret; | |
2464 | } | |
2465 | ||
2466 | static int si_initialize_smc_dte_tables(struct radeon_device *rdev) | |
2467 | { | |
2468 | struct si_power_info *si_pi = si_get_pi(rdev); | |
2469 | int ret = 0; | |
2470 | struct si_dte_data *dte_data = &si_pi->dte_data; | |
2471 | Smc_SIslands_DTE_Configuration *dte_tables = NULL; | |
2472 | u32 table_size; | |
2473 | u8 tdep_count; | |
2474 | u32 i; | |
2475 | ||
2476 | if (dte_data == NULL) | |
2477 | si_pi->enable_dte = false; | |
2478 | ||
2479 | if (si_pi->enable_dte == false) | |
2480 | return 0; | |
2481 | ||
2482 | if (dte_data->k <= 0) | |
2483 | return -EINVAL; | |
2484 | ||
2485 | dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); | |
2486 | if (dte_tables == NULL) { | |
2487 | si_pi->enable_dte = false; | |
2488 | return -ENOMEM; | |
2489 | } | |
2490 | ||
2491 | table_size = dte_data->k; | |
2492 | ||
2493 | if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) | |
2494 | table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; | |
2495 | ||
2496 | tdep_count = dte_data->tdep_count; | |
2497 | if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) | |
2498 | tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; | |
2499 | ||
2500 | dte_tables->K = cpu_to_be32(table_size); | |
2501 | dte_tables->T0 = cpu_to_be32(dte_data->t0); | |
2502 | dte_tables->MaxT = cpu_to_be32(dte_data->max_t); | |
2503 | dte_tables->WindowSize = dte_data->window_size; | |
2504 | dte_tables->temp_select = dte_data->temp_select; | |
2505 | dte_tables->DTE_mode = dte_data->dte_mode; | |
2506 | dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); | |
2507 | ||
2508 | if (tdep_count > 0) | |
2509 | table_size--; | |
2510 | ||
2511 | for (i = 0; i < table_size; i++) { | |
2512 | dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); | |
2513 | dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); | |
2514 | } | |
2515 | ||
2516 | dte_tables->Tdep_count = tdep_count; | |
2517 | ||
2518 | for (i = 0; i < (u32)tdep_count; i++) { | |
2519 | dte_tables->T_limits[i] = dte_data->t_limits[i]; | |
2520 | dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); | |
2521 | dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); | |
2522 | } | |
2523 | ||
2524 | ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, | |
2525 | sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); | |
2526 | kfree(dte_tables); | |
2527 | ||
2528 | return ret; | |
2529 | } | |
2530 | ||
2531 | static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, | |
2532 | u16 *max, u16 *min) | |
2533 | { | |
2534 | struct si_power_info *si_pi = si_get_pi(rdev); | |
2535 | struct radeon_cac_leakage_table *table = | |
2536 | &rdev->pm.dpm.dyn_state.cac_leakage_table; | |
2537 | u32 i; | |
2538 | u32 v0_loadline; | |
2539 | ||
2540 | ||
2541 | if (table == NULL) | |
2542 | return -EINVAL; | |
2543 | ||
2544 | *max = 0; | |
2545 | *min = 0xFFFF; | |
2546 | ||
2547 | for (i = 0; i < table->count; i++) { | |
2548 | if (table->entries[i].vddc > *max) | |
2549 | *max = table->entries[i].vddc; | |
2550 | if (table->entries[i].vddc < *min) | |
2551 | *min = table->entries[i].vddc; | |
2552 | } | |
2553 | ||
2554 | if (si_pi->powertune_data->lkge_lut_v0_percent > 100) | |
2555 | return -EINVAL; | |
2556 | ||
2557 | v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; | |
2558 | ||
2559 | if (v0_loadline > 0xFFFFUL) | |
2560 | return -EINVAL; | |
2561 | ||
2562 | *min = (u16)v0_loadline; | |
2563 | ||
2564 | if ((*min > *max) || (*max == 0) || (*min == 0)) | |
2565 | return -EINVAL; | |
2566 | ||
2567 | return 0; | |
2568 | } | |
2569 | ||
2570 | static u16 si_get_cac_std_voltage_step(u16 max, u16 min) | |
2571 | { | |
2572 | return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / | |
2573 | SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; | |
2574 | } | |
2575 | ||
2576 | static int si_init_dte_leakage_table(struct radeon_device *rdev, | |
2577 | PP_SIslands_CacConfig *cac_tables, | |
2578 | u16 vddc_max, u16 vddc_min, u16 vddc_step, | |
2579 | u16 t0, u16 t_step) | |
2580 | { | |
2581 | struct si_power_info *si_pi = si_get_pi(rdev); | |
2582 | u32 leakage; | |
2583 | unsigned int i, j; | |
2584 | s32 t; | |
2585 | u32 smc_leakage; | |
2586 | u32 scaling_factor; | |
2587 | u16 voltage; | |
2588 | ||
2589 | scaling_factor = si_get_smc_power_scaling_factor(rdev); | |
2590 | ||
2591 | for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { | |
2592 | t = (1000 * (i * t_step + t0)); | |
2593 | ||
2594 | for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { | |
2595 | voltage = vddc_max - (vddc_step * j); | |
2596 | ||
2597 | si_calculate_leakage_for_v_and_t(rdev, | |
2598 | &si_pi->powertune_data->leakage_coefficients, | |
2599 | voltage, | |
2600 | t, | |
2601 | si_pi->dyn_powertune_data.cac_leakage, | |
2602 | &leakage); | |
2603 | ||
2604 | smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; | |
2605 | ||
2606 | if (smc_leakage > 0xFFFF) | |
2607 | smc_leakage = 0xFFFF; | |
2608 | ||
2609 | cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = | |
2610 | cpu_to_be16((u16)smc_leakage); | |
2611 | } | |
2612 | } | |
2613 | return 0; | |
2614 | } | |
2615 | ||
2616 | static int si_init_simplified_leakage_table(struct radeon_device *rdev, | |
2617 | PP_SIslands_CacConfig *cac_tables, | |
2618 | u16 vddc_max, u16 vddc_min, u16 vddc_step) | |
2619 | { | |
2620 | struct si_power_info *si_pi = si_get_pi(rdev); | |
2621 | u32 leakage; | |
2622 | unsigned int i, j; | |
2623 | u32 smc_leakage; | |
2624 | u32 scaling_factor; | |
2625 | u16 voltage; | |
2626 | ||
2627 | scaling_factor = si_get_smc_power_scaling_factor(rdev); | |
2628 | ||
2629 | for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { | |
2630 | voltage = vddc_max - (vddc_step * j); | |
2631 | ||
2632 | si_calculate_leakage_for_v(rdev, | |
2633 | &si_pi->powertune_data->leakage_coefficients, | |
2634 | si_pi->powertune_data->fixed_kt, | |
2635 | voltage, | |
2636 | si_pi->dyn_powertune_data.cac_leakage, | |
2637 | &leakage); | |
2638 | ||
2639 | smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; | |
2640 | ||
2641 | if (smc_leakage > 0xFFFF) | |
2642 | smc_leakage = 0xFFFF; | |
2643 | ||
2644 | for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) | |
2645 | cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = | |
2646 | cpu_to_be16((u16)smc_leakage); | |
2647 | } | |
2648 | return 0; | |
2649 | } | |
2650 | ||
2651 | static int si_initialize_smc_cac_tables(struct radeon_device *rdev) | |
2652 | { | |
2653 | struct ni_power_info *ni_pi = ni_get_pi(rdev); | |
2654 | struct si_power_info *si_pi = si_get_pi(rdev); | |
2655 | PP_SIslands_CacConfig *cac_tables = NULL; | |
2656 | u16 vddc_max, vddc_min, vddc_step; | |
2657 | u16 t0, t_step; | |
2658 | u32 load_line_slope, reg; | |
2659 | int ret = 0; | |
2660 | u32 ticks_per_us = radeon_get_xclk(rdev) / 100; | |
2661 | ||
2662 | if (ni_pi->enable_cac == false) | |
2663 | return 0; | |
2664 | ||
2665 | cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); | |
2666 | if (!cac_tables) | |
2667 | return -ENOMEM; | |
2668 | ||
2669 | reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; | |
2670 | reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); | |
2671 | WREG32(CG_CAC_CTRL, reg); | |
2672 | ||
2673 | si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; | |
2674 | si_pi->dyn_powertune_data.dc_pwr_value = | |
2675 | si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; | |
2676 | si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); | |
2677 | si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; | |
2678 | ||
2679 | si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; | |
2680 | ||
2681 | ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); | |
2682 | if (ret) | |
2683 | goto done_free; | |
2684 | ||
2685 | vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); | |
2686 | vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); | |
2687 | t_step = 4; | |
2688 | t0 = 60; | |
2689 | ||
2690 | if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) | |
2691 | ret = si_init_dte_leakage_table(rdev, cac_tables, | |
2692 | vddc_max, vddc_min, vddc_step, | |
2693 | t0, t_step); | |
2694 | else | |
2695 | ret = si_init_simplified_leakage_table(rdev, cac_tables, | |
2696 | vddc_max, vddc_min, vddc_step); | |
2697 | if (ret) | |
2698 | goto done_free; | |
2699 | ||
2700 | load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; | |
2701 | ||
2702 | cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); | |
2703 | cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; | |
2704 | cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; | |
2705 | cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); | |
2706 | cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); | |
2707 | cac_tables->R_LL = cpu_to_be32(load_line_slope); | |
2708 | cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); | |
2709 | cac_tables->calculation_repeats = cpu_to_be32(2); | |
2710 | cac_tables->dc_cac = cpu_to_be32(0); | |
2711 | cac_tables->log2_PG_LKG_SCALE = 12; | |
2712 | cac_tables->cac_temp = si_pi->powertune_data->operating_temp; | |
2713 | cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); | |
2714 | cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); | |
2715 | ||
2716 | ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, | |
2717 | sizeof(PP_SIslands_CacConfig), si_pi->sram_end); | |
2718 | ||
2719 | if (ret) | |
2720 | goto done_free; | |
2721 | ||
2722 | ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); | |
2723 | ||
2724 | done_free: | |
2725 | if (ret) { | |
2726 | ni_pi->enable_cac = false; | |
2727 | ni_pi->enable_power_containment = false; | |
2728 | } | |
2729 | ||
2730 | kfree(cac_tables); | |
2731 | ||
2732 | return 0; | |
2733 | } | |
2734 | ||
2735 | static int si_program_cac_config_registers(struct radeon_device *rdev, | |
2736 | const struct si_cac_config_reg *cac_config_regs) | |
2737 | { | |
2738 | const struct si_cac_config_reg *config_regs = cac_config_regs; | |
2739 | u32 data = 0, offset; | |
2740 | ||
2741 | if (!config_regs) | |
2742 | return -EINVAL; | |
2743 | ||
2744 | while (config_regs->offset != 0xFFFFFFFF) { | |
2745 | switch (config_regs->type) { | |
2746 | case SISLANDS_CACCONFIG_CGIND: | |
2747 | offset = SMC_CG_IND_START + config_regs->offset; | |
2748 | if (offset < SMC_CG_IND_END) | |
2749 | data = RREG32_SMC(offset); | |
2750 | break; | |
2751 | default: | |
2752 | data = RREG32(config_regs->offset << 2); | |
2753 | break; | |
2754 | } | |
2755 | ||
2756 | data &= ~config_regs->mask; | |
2757 | data |= ((config_regs->value << config_regs->shift) & config_regs->mask); | |
2758 | ||
2759 | switch (config_regs->type) { | |
2760 | case SISLANDS_CACCONFIG_CGIND: | |
2761 | offset = SMC_CG_IND_START + config_regs->offset; | |
2762 | if (offset < SMC_CG_IND_END) | |
2763 | WREG32_SMC(offset, data); | |
2764 | break; | |
2765 | default: | |
2766 | WREG32(config_regs->offset << 2, data); | |
2767 | break; | |
2768 | } | |
2769 | config_regs++; | |
2770 | } | |
2771 | return 0; | |
2772 | } | |
2773 | ||
2774 | static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) | |
2775 | { | |
2776 | struct ni_power_info *ni_pi = ni_get_pi(rdev); | |
2777 | struct si_power_info *si_pi = si_get_pi(rdev); | |
2778 | int ret; | |
2779 | ||
2780 | if ((ni_pi->enable_cac == false) || | |
2781 | (ni_pi->cac_configuration_required == false)) | |
2782 | return 0; | |
2783 | ||
2784 | ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); | |
2785 | if (ret) | |
2786 | return ret; | |
2787 | ret = si_program_cac_config_registers(rdev, si_pi->cac_override); | |
2788 | if (ret) | |
2789 | return ret; | |
2790 | ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); | |
2791 | if (ret) | |
2792 | return ret; | |
2793 | ||
2794 | return 0; | |
2795 | } | |
2796 | ||
2797 | static int si_enable_smc_cac(struct radeon_device *rdev, | |
2798 | struct radeon_ps *radeon_new_state, | |
2799 | bool enable) | |
2800 | { | |
2801 | struct ni_power_info *ni_pi = ni_get_pi(rdev); | |
2802 | struct si_power_info *si_pi = si_get_pi(rdev); | |
2803 | PPSMC_Result smc_result; | |
2804 | int ret = 0; | |
2805 | ||
2806 | if (ni_pi->enable_cac) { | |
2807 | if (enable) { | |
2808 | if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { | |
2809 | if (ni_pi->support_cac_long_term_average) { | |
2810 | smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); | |
2811 | if (smc_result != PPSMC_Result_OK) | |
2812 | ni_pi->support_cac_long_term_average = false; | |
2813 | } | |
2814 | ||
2815 | smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); | |
2816 | if (smc_result != PPSMC_Result_OK) { | |
2817 | ret = -EINVAL; | |
2818 | ni_pi->cac_enabled = false; | |
2819 | } else { | |
2820 | ni_pi->cac_enabled = true; | |
2821 | } | |
2822 | ||
2823 | if (si_pi->enable_dte) { | |
2824 | smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); | |
2825 | if (smc_result != PPSMC_Result_OK) | |
2826 | ret = -EINVAL; | |
2827 | } | |
2828 | } | |
2829 | } else if (ni_pi->cac_enabled) { | |
2830 | if (si_pi->enable_dte) | |
2831 | smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); | |
2832 | ||
2833 | smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); | |
2834 | ||
2835 | ni_pi->cac_enabled = false; | |
2836 | ||
2837 | if (ni_pi->support_cac_long_term_average) | |
2838 | smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); | |
2839 | } | |
2840 | } | |
2841 | return ret; | |
2842 | } | |
2843 | ||
2844 | static int si_init_smc_spll_table(struct radeon_device *rdev) | |
2845 | { | |
2846 | struct ni_power_info *ni_pi = ni_get_pi(rdev); | |
2847 | struct si_power_info *si_pi = si_get_pi(rdev); | |
2848 | SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; | |
2849 | SISLANDS_SMC_SCLK_VALUE sclk_params; | |
2850 | u32 fb_div, p_div; | |
2851 | u32 clk_s, clk_v; | |
2852 | u32 sclk = 0; | |
2853 | int ret = 0; | |
2854 | u32 tmp; | |
2855 | int i; | |
2856 | ||
2857 | if (si_pi->spll_table_start == 0) | |
2858 | return -EINVAL; | |
2859 | ||
2860 | spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); | |
2861 | if (spll_table == NULL) | |
2862 | return -ENOMEM; | |
2863 | ||
2864 | for (i = 0; i < 256; i++) { | |
2865 | ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); | |
2866 | if (ret) | |
2867 | break; | |
2868 | ||
2869 | p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; | |
2870 | fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; | |
2871 | clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; | |
2872 | clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; | |
2873 | ||
2874 | fb_div &= ~0x00001FFF; | |
2875 | fb_div >>= 1; | |
2876 | clk_v >>= 6; | |
2877 | ||
2878 | if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) | |
2879 | ret = -EINVAL; | |
2880 | if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) | |
2881 | ret = -EINVAL; | |
2882 | if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) | |
2883 | ret = -EINVAL; | |
2884 | if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) | |
2885 | ret = -EINVAL; | |
2886 | ||
2887 | if (ret) | |
2888 | break; | |
2889 | ||
2890 | tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | | |
2891 | ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); | |
2892 | spll_table->freq[i] = cpu_to_be32(tmp); | |
2893 | ||
2894 | tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | | |
2895 | ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); | |
2896 | spll_table->ss[i] = cpu_to_be32(tmp); | |
2897 | ||
2898 | sclk += 512; | |
2899 | } | |
2900 | ||
2901 | ||
2902 | if (!ret) | |
2903 | ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, | |
2904 | (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), | |
2905 | si_pi->sram_end); | |
2906 | ||
2907 | if (ret) | |
2908 | ni_pi->enable_power_containment = false; | |
2909 | ||
2910 | kfree(spll_table); | |
2911 | ||
2912 | return ret; | |
2913 | } | |
2914 | ||
5615f890 AD |
2915 | struct si_dpm_quirk { |
2916 | u32 chip_vendor; | |
2917 | u32 chip_device; | |
2918 | u32 subsys_vendor; | |
2919 | u32 subsys_device; | |
2920 | u32 max_sclk; | |
2921 | u32 max_mclk; | |
2922 | }; | |
2923 | ||
2924 | /* cards with dpm stability problems */ | |
2925 | static struct si_dpm_quirk si_dpm_quirk_list[] = { | |
2926 | /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */ | |
2927 | { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 }, | |
cd17e02f | 2928 | { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 }, |
f971f226 | 2929 | { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 }, |
5dfc71bc | 2930 | { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 }, |
515c752d | 2931 | { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 }, |
2b02ec79 | 2932 | { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 }, |
a64663d9 | 2933 | { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 }, |
bcb31eba | 2934 | { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 }, |
5615f890 AD |
2935 | { 0, 0, 0, 0 }, |
2936 | }; | |
2937 | ||
11586cf0 AD |
2938 | static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, |
2939 | u16 vce_voltage) | |
2940 | { | |
2941 | u16 highest_leakage = 0; | |
2942 | struct si_power_info *si_pi = si_get_pi(rdev); | |
2943 | int i; | |
2944 | ||
2945 | for (i = 0; i < si_pi->leakage_voltage.count; i++){ | |
2946 | if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) | |
2947 | highest_leakage = si_pi->leakage_voltage.entries[i].voltage; | |
2948 | } | |
2949 | ||
2950 | if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) | |
2951 | return highest_leakage; | |
2952 | ||
2953 | return vce_voltage; | |
2954 | } | |
2955 | ||
2956 | static int si_get_vce_clock_voltage(struct radeon_device *rdev, | |
2957 | u32 evclk, u32 ecclk, u16 *voltage) | |
2958 | { | |
2959 | u32 i; | |
2960 | int ret = -EINVAL; | |
2961 | struct radeon_vce_clock_voltage_dependency_table *table = | |
2962 | &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; | |
2963 | ||
2964 | if (((evclk == 0) && (ecclk == 0)) || | |
2965 | (table && (table->count == 0))) { | |
2966 | *voltage = 0; | |
2967 | return 0; | |
2968 | } | |
2969 | ||
2970 | for (i = 0; i < table->count; i++) { | |
2971 | if ((evclk <= table->entries[i].evclk) && | |
2972 | (ecclk <= table->entries[i].ecclk)) { | |
2973 | *voltage = table->entries[i].v; | |
2974 | ret = 0; | |
2975 | break; | |
2976 | } | |
2977 | } | |
2978 | ||
2979 | /* if no match return the highest voltage */ | |
2980 | if (ret) | |
2981 | *voltage = table->entries[table->count - 1].v; | |
2982 | ||
2983 | *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); | |
2984 | ||
2985 | return ret; | |
2986 | } | |
2987 | ||
a9e61410 AD |
2988 | static void si_apply_state_adjust_rules(struct radeon_device *rdev, |
2989 | struct radeon_ps *rps) | |
2990 | { | |
2991 | struct ni_ps *ps = ni_get_ps(rps); | |
2992 | struct radeon_clock_and_voltage_limits *max_limits; | |
797f203f AD |
2993 | bool disable_mclk_switching = false; |
2994 | bool disable_sclk_switching = false; | |
a9e61410 | 2995 | u32 mclk, sclk; |
11586cf0 | 2996 | u16 vddc, vddci, min_vce_voltage = 0; |
1db78024 | 2997 | u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; |
5615f890 | 2998 | u32 max_sclk = 0, max_mclk = 0; |
a9e61410 | 2999 | int i; |
5615f890 AD |
3000 | struct si_dpm_quirk *p = si_dpm_quirk_list; |
3001 | ||
3002 | /* Apply dpm quirks */ | |
3003 | while (p && p->chip_device != 0) { | |
3004 | if (rdev->pdev->vendor == p->chip_vendor && | |
3005 | rdev->pdev->device == p->chip_device && | |
3006 | rdev->pdev->subsystem_vendor == p->subsys_vendor && | |
3007 | rdev->pdev->subsystem_device == p->subsys_device) { | |
3008 | max_sclk = p->max_sclk; | |
3009 | max_mclk = p->max_mclk; | |
3010 | break; | |
3011 | } | |
3012 | ++p; | |
3013 | } | |
0e5585dc AD |
3014 | /* limit mclk on all R7 370 parts for stability */ |
3015 | if (rdev->pdev->device == 0x6811 && | |
3016 | rdev->pdev->revision == 0x81) | |
3017 | max_mclk = 120000; | |
670bb4fd AD |
3018 | /* limit sclk/mclk on Jet parts for stability */ |
3019 | if (rdev->pdev->device == 0x6665 && | |
3020 | rdev->pdev->revision == 0xc3) { | |
3021 | max_sclk = 75000; | |
3022 | max_mclk = 80000; | |
3023 | } | |
a9e61410 | 3024 | |
11586cf0 AD |
3025 | if (rps->vce_active) { |
3026 | rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; | |
3027 | rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; | |
3028 | si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, | |
3029 | &min_vce_voltage); | |
3030 | } else { | |
3031 | rps->evclk = 0; | |
3032 | rps->ecclk = 0; | |
3033 | } | |
3034 | ||
f4dec318 AD |
3035 | if ((rdev->pm.dpm.new_active_crtc_count > 1) || |
3036 | ni_dpm_vblank_too_short(rdev)) | |
a9e61410 | 3037 | disable_mclk_switching = true; |
797f203f AD |
3038 | |
3039 | if (rps->vclk || rps->dclk) { | |
3040 | disable_mclk_switching = true; | |
3041 | disable_sclk_switching = true; | |
3042 | } | |
a9e61410 AD |
3043 | |
3044 | if (rdev->pm.dpm.ac_power) | |
3045 | max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; | |
3046 | else | |
3047 | max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; | |
3048 | ||
3049 | for (i = ps->performance_level_count - 2; i >= 0; i--) { | |
3050 | if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) | |
3051 | ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; | |
3052 | } | |
3053 | if (rdev->pm.dpm.ac_power == false) { | |
3054 | for (i = 0; i < ps->performance_level_count; i++) { | |
3055 | if (ps->performance_levels[i].mclk > max_limits->mclk) | |
3056 | ps->performance_levels[i].mclk = max_limits->mclk; | |
3057 | if (ps->performance_levels[i].sclk > max_limits->sclk) | |
3058 | ps->performance_levels[i].sclk = max_limits->sclk; | |
3059 | if (ps->performance_levels[i].vddc > max_limits->vddc) | |
3060 | ps->performance_levels[i].vddc = max_limits->vddc; | |
3061 | if (ps->performance_levels[i].vddci > max_limits->vddci) | |
3062 | ps->performance_levels[i].vddci = max_limits->vddci; | |
3063 | } | |
3064 | } | |
3065 | ||
1db78024 AD |
3066 | /* limit clocks to max supported clocks based on voltage dependency tables */ |
3067 | btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, | |
3068 | &max_sclk_vddc); | |
3069 | btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, | |
3070 | &max_mclk_vddci); | |
3071 | btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, | |
3072 | &max_mclk_vddc); | |
3073 | ||
3074 | for (i = 0; i < ps->performance_level_count; i++) { | |
3075 | if (max_sclk_vddc) { | |
3076 | if (ps->performance_levels[i].sclk > max_sclk_vddc) | |
3077 | ps->performance_levels[i].sclk = max_sclk_vddc; | |
3078 | } | |
3079 | if (max_mclk_vddci) { | |
3080 | if (ps->performance_levels[i].mclk > max_mclk_vddci) | |
3081 | ps->performance_levels[i].mclk = max_mclk_vddci; | |
3082 | } | |
3083 | if (max_mclk_vddc) { | |
3084 | if (ps->performance_levels[i].mclk > max_mclk_vddc) | |
3085 | ps->performance_levels[i].mclk = max_mclk_vddc; | |
3086 | } | |
5615f890 AD |
3087 | if (max_mclk) { |
3088 | if (ps->performance_levels[i].mclk > max_mclk) | |
3089 | ps->performance_levels[i].mclk = max_mclk; | |
3090 | } | |
3091 | if (max_sclk) { | |
3092 | if (ps->performance_levels[i].sclk > max_sclk) | |
3093 | ps->performance_levels[i].sclk = max_sclk; | |
3094 | } | |
1db78024 AD |
3095 | } |
3096 | ||
a9e61410 AD |
3097 | /* XXX validate the min clocks required for display */ |
3098 | ||
3099 | if (disable_mclk_switching) { | |
3100 | mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; | |
a9e61410 AD |
3101 | vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; |
3102 | } else { | |
a9e61410 | 3103 | mclk = ps->performance_levels[0].mclk; |
a9e61410 AD |
3104 | vddci = ps->performance_levels[0].vddci; |
3105 | } | |
3106 | ||
797f203f AD |
3107 | if (disable_sclk_switching) { |
3108 | sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; | |
3109 | vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; | |
3110 | } else { | |
3111 | sclk = ps->performance_levels[0].sclk; | |
3112 | vddc = ps->performance_levels[0].vddc; | |
3113 | } | |
3114 | ||
11586cf0 AD |
3115 | if (rps->vce_active) { |
3116 | if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) | |
3117 | sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; | |
3118 | if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) | |
3119 | mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; | |
3120 | } | |
3121 | ||
a9e61410 AD |
3122 | /* adjusted low state */ |
3123 | ps->performance_levels[0].sclk = sclk; | |
3124 | ps->performance_levels[0].mclk = mclk; | |
3125 | ps->performance_levels[0].vddc = vddc; | |
3126 | ps->performance_levels[0].vddci = vddci; | |
3127 | ||
797f203f AD |
3128 | if (disable_sclk_switching) { |
3129 | sclk = ps->performance_levels[0].sclk; | |
3130 | for (i = 1; i < ps->performance_level_count; i++) { | |
3131 | if (sclk < ps->performance_levels[i].sclk) | |
3132 | sclk = ps->performance_levels[i].sclk; | |
3133 | } | |
3134 | for (i = 0; i < ps->performance_level_count; i++) { | |
3135 | ps->performance_levels[i].sclk = sclk; | |
3136 | ps->performance_levels[i].vddc = vddc; | |
3137 | } | |
3138 | } else { | |
3139 | for (i = 1; i < ps->performance_level_count; i++) { | |
3140 | if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) | |
3141 | ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; | |
3142 | if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) | |
3143 | ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; | |
3144 | } | |
a9e61410 AD |
3145 | } |
3146 | ||
3147 | if (disable_mclk_switching) { | |
3148 | mclk = ps->performance_levels[0].mclk; | |
3149 | for (i = 1; i < ps->performance_level_count; i++) { | |
3150 | if (mclk < ps->performance_levels[i].mclk) | |
3151 | mclk = ps->performance_levels[i].mclk; | |
3152 | } | |
3153 | for (i = 0; i < ps->performance_level_count; i++) { | |
3154 | ps->performance_levels[i].mclk = mclk; | |
3155 | ps->performance_levels[i].vddci = vddci; | |
3156 | } | |
3157 | } else { | |
3158 | for (i = 1; i < ps->performance_level_count; i++) { | |
3159 | if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) | |
3160 | ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; | |
3161 | if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) | |
3162 | ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; | |
3163 | } | |
3164 | } | |
3165 | ||
3cf8bb1a JG |
3166 | for (i = 0; i < ps->performance_level_count; i++) |
3167 | btc_adjust_clock_combinations(rdev, max_limits, | |
3168 | &ps->performance_levels[i]); | |
a9e61410 AD |
3169 | |
3170 | for (i = 0; i < ps->performance_level_count; i++) { | |
11586cf0 AD |
3171 | if (ps->performance_levels[i].vddc < min_vce_voltage) |
3172 | ps->performance_levels[i].vddc = min_vce_voltage; | |
a9e61410 AD |
3173 | btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, |
3174 | ps->performance_levels[i].sclk, | |
3175 | max_limits->vddc, &ps->performance_levels[i].vddc); | |
3176 | btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, | |
3177 | ps->performance_levels[i].mclk, | |
3178 | max_limits->vddci, &ps->performance_levels[i].vddci); | |
3179 | btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, | |
3180 | ps->performance_levels[i].mclk, | |
3181 | max_limits->vddc, &ps->performance_levels[i].vddc); | |
3182 | btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, | |
3183 | rdev->clock.current_dispclk, | |
3184 | max_limits->vddc, &ps->performance_levels[i].vddc); | |
3185 | } | |
3186 | ||
3187 | for (i = 0; i < ps->performance_level_count; i++) { | |
3188 | btc_apply_voltage_delta_rules(rdev, | |
3189 | max_limits->vddc, max_limits->vddci, | |
3190 | &ps->performance_levels[i].vddc, | |
3191 | &ps->performance_levels[i].vddci); | |
3192 | } | |
3193 | ||
3194 | ps->dc_compatible = true; | |
3195 | for (i = 0; i < ps->performance_level_count; i++) { | |
3196 | if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) | |
3197 | ps->dc_compatible = false; | |
3198 | } | |
a9e61410 AD |
3199 | } |
3200 | ||
3201 | #if 0 | |
3202 | static int si_read_smc_soft_register(struct radeon_device *rdev, | |
3203 | u16 reg_offset, u32 *value) | |
3204 | { | |
3205 | struct si_power_info *si_pi = si_get_pi(rdev); | |
3206 | ||
3207 | return si_read_smc_sram_dword(rdev, | |
3208 | si_pi->soft_regs_start + reg_offset, value, | |
3209 | si_pi->sram_end); | |
3210 | } | |
3211 | #endif | |
3212 | ||
3213 | static int si_write_smc_soft_register(struct radeon_device *rdev, | |
3214 | u16 reg_offset, u32 value) | |
3215 | { | |
3216 | struct si_power_info *si_pi = si_get_pi(rdev); | |
3217 | ||
3218 | return si_write_smc_sram_dword(rdev, | |
3219 | si_pi->soft_regs_start + reg_offset, | |
3220 | value, si_pi->sram_end); | |
3221 | } | |
3222 | ||
3223 | static bool si_is_special_1gb_platform(struct radeon_device *rdev) | |
3224 | { | |
3225 | bool ret = false; | |
3226 | u32 tmp, width, row, column, bank, density; | |
3227 | bool is_memory_gddr5, is_special; | |
3228 | ||
3229 | tmp = RREG32(MC_SEQ_MISC0); | |
3230 | is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); | |
3231 | is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) | |
3232 | & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); | |
3233 | ||
3234 | WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); | |
3235 | width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; | |
3236 | ||
3237 | tmp = RREG32(MC_ARB_RAMCFG); | |
3238 | row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; | |
3239 | column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; | |
3240 | bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; | |
3241 | ||
3242 | density = (1 << (row + column - 20 + bank)) * width; | |
3243 | ||
3244 | if ((rdev->pdev->device == 0x6819) && | |
3245 | is_memory_gddr5 && is_special && (density == 0x400)) | |
3246 | ret = true; | |
3247 | ||
3248 | return ret; | |
3249 | } | |
3250 | ||
3251 | static void si_get_leakage_vddc(struct radeon_device *rdev) | |
3252 | { | |
3253 | struct si_power_info *si_pi = si_get_pi(rdev); | |
3254 | u16 vddc, count = 0; | |
3255 | int i, ret; | |
3256 | ||
3257 | for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { | |
3258 | ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); | |
3259 | ||
3260 | if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { | |
3261 | si_pi->leakage_voltage.entries[count].voltage = vddc; | |
3262 | si_pi->leakage_voltage.entries[count].leakage_index = | |
3263 | SISLANDS_LEAKAGE_INDEX0 + i; | |
3264 | count++; | |
3265 | } | |
3266 | } | |
3267 | si_pi->leakage_voltage.count = count; | |
3268 | } | |
3269 | ||
3270 | static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, | |
3271 | u32 index, u16 *leakage_voltage) | |
3272 | { | |
3273 | struct si_power_info *si_pi = si_get_pi(rdev); | |
3274 | int i; | |
3275 | ||
3276 | if (leakage_voltage == NULL) | |
3277 | return -EINVAL; | |
3278 | ||
3279 | if ((index & 0xff00) != 0xff00) | |
3280 | return -EINVAL; | |
3281 | ||
3282 | if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) | |
3283 | return -EINVAL; | |
3284 | ||
3285 | if (index < SISLANDS_LEAKAGE_INDEX0) | |
3286 | return -EINVAL; | |
3287 | ||
3288 | for (i = 0; i < si_pi->leakage_voltage.count; i++) { | |
3289 | if (si_pi->leakage_voltage.entries[i].leakage_index == index) { | |
3290 | *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; | |
3291 | return 0; | |
3292 | } | |
3293 | } | |
3294 | return -EAGAIN; | |
3295 | } | |
3296 | ||
3297 | static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) | |
3298 | { | |
3299 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
3300 | bool want_thermal_protection; | |
3301 | enum radeon_dpm_event_src dpm_event_src; | |
3302 | ||
3303 | switch (sources) { | |
3304 | case 0: | |
3305 | default: | |
3306 | want_thermal_protection = false; | |
3cf8bb1a | 3307 | break; |
a9e61410 AD |
3308 | case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): |
3309 | want_thermal_protection = true; | |
3310 | dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; | |
3311 | break; | |
3312 | case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): | |
3313 | want_thermal_protection = true; | |
3314 | dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; | |
3315 | break; | |
3316 | case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | | |
3317 | (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): | |
3318 | want_thermal_protection = true; | |
3319 | dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; | |
3320 | break; | |
3321 | } | |
3322 | ||
3323 | if (want_thermal_protection) { | |
3324 | WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); | |
3325 | if (pi->thermal_protection) | |
3326 | WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); | |
3327 | } else { | |
3328 | WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); | |
3329 | } | |
3330 | } | |
3331 | ||
3332 | static void si_enable_auto_throttle_source(struct radeon_device *rdev, | |
3333 | enum radeon_dpm_auto_throttle_src source, | |
3334 | bool enable) | |
3335 | { | |
3336 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
3337 | ||
3338 | if (enable) { | |
3339 | if (!(pi->active_auto_throttle_sources & (1 << source))) { | |
3340 | pi->active_auto_throttle_sources |= 1 << source; | |
3341 | si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); | |
3342 | } | |
3343 | } else { | |
3344 | if (pi->active_auto_throttle_sources & (1 << source)) { | |
3345 | pi->active_auto_throttle_sources &= ~(1 << source); | |
3346 | si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); | |
3347 | } | |
3348 | } | |
3349 | } | |
3350 | ||
3351 | static void si_start_dpm(struct radeon_device *rdev) | |
3352 | { | |
3353 | WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); | |
3354 | } | |
3355 | ||
3356 | static void si_stop_dpm(struct radeon_device *rdev) | |
3357 | { | |
3358 | WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); | |
3359 | } | |
3360 | ||
3361 | static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) | |
3362 | { | |
3363 | if (enable) | |
3364 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); | |
3365 | else | |
3366 | WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); | |
3367 | ||
3368 | } | |
3369 | ||
3370 | #if 0 | |
3371 | static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, | |
3372 | u32 thermal_level) | |
3373 | { | |
3374 | PPSMC_Result ret; | |
3375 | ||
3376 | if (thermal_level == 0) { | |
3377 | ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); | |
3378 | if (ret == PPSMC_Result_OK) | |
3379 | return 0; | |
3380 | else | |
3381 | return -EINVAL; | |
3382 | } | |
3383 | return 0; | |
3384 | } | |
3385 | ||
3386 | static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) | |
3387 | { | |
3388 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); | |
3389 | } | |
3390 | #endif | |
3391 | ||
3392 | #if 0 | |
3393 | static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) | |
3394 | { | |
3395 | if (ac_power) | |
3396 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? | |
3397 | 0 : -EINVAL; | |
3398 | ||
3399 | return 0; | |
3400 | } | |
3401 | #endif | |
3402 | ||
3403 | static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, | |
3404 | PPSMC_Msg msg, u32 parameter) | |
3405 | { | |
3406 | WREG32(SMC_SCRATCH0, parameter); | |
3407 | return si_send_msg_to_smc(rdev, msg); | |
3408 | } | |
3409 | ||
3410 | static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) | |
3411 | { | |
3412 | if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) | |
3413 | return -EINVAL; | |
3414 | ||
3415 | return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? | |
3416 | 0 : -EINVAL; | |
3417 | } | |
3418 | ||
a160a6a3 AD |
3419 | int si_dpm_force_performance_level(struct radeon_device *rdev, |
3420 | enum radeon_dpm_forced_level level) | |
a9e61410 | 3421 | { |
a160a6a3 AD |
3422 | struct radeon_ps *rps = rdev->pm.dpm.current_ps; |
3423 | struct ni_ps *ps = ni_get_ps(rps); | |
63f22d0e | 3424 | u32 levels = ps->performance_level_count; |
a9e61410 | 3425 | |
a160a6a3 | 3426 | if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { |
63f22d0e | 3427 | if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) |
a160a6a3 AD |
3428 | return -EINVAL; |
3429 | ||
3430 | if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) | |
3431 | return -EINVAL; | |
3432 | } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { | |
3433 | if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) | |
3434 | return -EINVAL; | |
3435 | ||
63f22d0e | 3436 | if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) |
a160a6a3 AD |
3437 | return -EINVAL; |
3438 | } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { | |
3439 | if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) | |
3440 | return -EINVAL; | |
3441 | ||
63f22d0e | 3442 | if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) |
a160a6a3 AD |
3443 | return -EINVAL; |
3444 | } | |
3445 | ||
3446 | rdev->pm.dpm.forced_level = level; | |
3447 | ||
3448 | return 0; | |
a9e61410 | 3449 | } |
a9e61410 | 3450 | |
98769131 | 3451 | #if 0 |
a9e61410 AD |
3452 | static int si_set_boot_state(struct radeon_device *rdev) |
3453 | { | |
3454 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? | |
3455 | 0 : -EINVAL; | |
3456 | } | |
98769131 | 3457 | #endif |
a9e61410 AD |
3458 | |
3459 | static int si_set_sw_state(struct radeon_device *rdev) | |
3460 | { | |
3461 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? | |
3462 | 0 : -EINVAL; | |
3463 | } | |
3464 | ||
3465 | static int si_halt_smc(struct radeon_device *rdev) | |
3466 | { | |
3467 | if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) | |
3468 | return -EINVAL; | |
3469 | ||
3470 | return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? | |
3471 | 0 : -EINVAL; | |
3472 | } | |
3473 | ||
3474 | static int si_resume_smc(struct radeon_device *rdev) | |
3475 | { | |
3476 | if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) | |
3477 | return -EINVAL; | |
3478 | ||
3479 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? | |
3480 | 0 : -EINVAL; | |
3481 | } | |
3482 | ||
3483 | static void si_dpm_start_smc(struct radeon_device *rdev) | |
3484 | { | |
3485 | si_program_jump_on_start(rdev); | |
3486 | si_start_smc(rdev); | |
3487 | si_start_smc_clock(rdev); | |
3488 | } | |
3489 | ||
3490 | static void si_dpm_stop_smc(struct radeon_device *rdev) | |
3491 | { | |
3492 | si_reset_smc(rdev); | |
3493 | si_stop_smc_clock(rdev); | |
3494 | } | |
3495 | ||
3496 | static int si_process_firmware_header(struct radeon_device *rdev) | |
3497 | { | |
3498 | struct si_power_info *si_pi = si_get_pi(rdev); | |
3499 | u32 tmp; | |
3500 | int ret; | |
3501 | ||
3502 | ret = si_read_smc_sram_dword(rdev, | |
3503 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3504 | SISLANDS_SMC_FIRMWARE_HEADER_stateTable, | |
3505 | &tmp, si_pi->sram_end); | |
3506 | if (ret) | |
3507 | return ret; | |
3508 | ||
3cf8bb1a | 3509 | si_pi->state_table_start = tmp; |
a9e61410 AD |
3510 | |
3511 | ret = si_read_smc_sram_dword(rdev, | |
3512 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3513 | SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, | |
3514 | &tmp, si_pi->sram_end); | |
3515 | if (ret) | |
3516 | return ret; | |
3517 | ||
3518 | si_pi->soft_regs_start = tmp; | |
3519 | ||
3520 | ret = si_read_smc_sram_dword(rdev, | |
3521 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3522 | SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, | |
3523 | &tmp, si_pi->sram_end); | |
3524 | if (ret) | |
3525 | return ret; | |
3526 | ||
3527 | si_pi->mc_reg_table_start = tmp; | |
3528 | ||
39471ad3 AD |
3529 | ret = si_read_smc_sram_dword(rdev, |
3530 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3531 | SISLANDS_SMC_FIRMWARE_HEADER_fanTable, | |
3532 | &tmp, si_pi->sram_end); | |
3533 | if (ret) | |
3534 | return ret; | |
3535 | ||
3536 | si_pi->fan_table_start = tmp; | |
3537 | ||
a9e61410 AD |
3538 | ret = si_read_smc_sram_dword(rdev, |
3539 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3540 | SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, | |
3541 | &tmp, si_pi->sram_end); | |
3542 | if (ret) | |
3543 | return ret; | |
3544 | ||
3545 | si_pi->arb_table_start = tmp; | |
3546 | ||
3547 | ret = si_read_smc_sram_dword(rdev, | |
3548 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3549 | SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, | |
3550 | &tmp, si_pi->sram_end); | |
3551 | if (ret) | |
3552 | return ret; | |
3553 | ||
3554 | si_pi->cac_table_start = tmp; | |
3555 | ||
3556 | ret = si_read_smc_sram_dword(rdev, | |
3557 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3558 | SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, | |
3559 | &tmp, si_pi->sram_end); | |
3560 | if (ret) | |
3561 | return ret; | |
3562 | ||
3563 | si_pi->dte_table_start = tmp; | |
3564 | ||
3565 | ret = si_read_smc_sram_dword(rdev, | |
3566 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3567 | SISLANDS_SMC_FIRMWARE_HEADER_spllTable, | |
3568 | &tmp, si_pi->sram_end); | |
3569 | if (ret) | |
3570 | return ret; | |
3571 | ||
3572 | si_pi->spll_table_start = tmp; | |
3573 | ||
3574 | ret = si_read_smc_sram_dword(rdev, | |
3575 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3576 | SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, | |
3577 | &tmp, si_pi->sram_end); | |
3578 | if (ret) | |
3579 | return ret; | |
3580 | ||
3581 | si_pi->papm_cfg_table_start = tmp; | |
3582 | ||
3583 | return ret; | |
3584 | } | |
3585 | ||
3586 | static void si_read_clock_registers(struct radeon_device *rdev) | |
3587 | { | |
3588 | struct si_power_info *si_pi = si_get_pi(rdev); | |
3589 | ||
3590 | si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); | |
3591 | si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); | |
3592 | si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); | |
3593 | si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); | |
3594 | si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); | |
3595 | si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); | |
3596 | si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); | |
3597 | si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); | |
3598 | si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); | |
3599 | si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); | |
3600 | si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); | |
3601 | si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); | |
3602 | si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); | |
3603 | si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); | |
3604 | si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); | |
3605 | } | |
3606 | ||
3607 | static void si_enable_thermal_protection(struct radeon_device *rdev, | |
3608 | bool enable) | |
3609 | { | |
3610 | if (enable) | |
3611 | WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); | |
3612 | else | |
3613 | WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); | |
3614 | } | |
3615 | ||
3616 | static void si_enable_acpi_power_management(struct radeon_device *rdev) | |
3617 | { | |
3618 | WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); | |
3619 | } | |
3620 | ||
3621 | #if 0 | |
3622 | static int si_enter_ulp_state(struct radeon_device *rdev) | |
3623 | { | |
3624 | WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); | |
3625 | ||
3626 | udelay(25000); | |
3627 | ||
3628 | return 0; | |
3629 | } | |
3630 | ||
3631 | static int si_exit_ulp_state(struct radeon_device *rdev) | |
3632 | { | |
3633 | int i; | |
3634 | ||
3635 | WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); | |
3636 | ||
3637 | udelay(7000); | |
3638 | ||
3639 | for (i = 0; i < rdev->usec_timeout; i++) { | |
3640 | if (RREG32(SMC_RESP_0) == 1) | |
3641 | break; | |
3642 | udelay(1000); | |
3643 | } | |
3644 | ||
3645 | return 0; | |
3646 | } | |
3647 | #endif | |
3648 | ||
3649 | static int si_notify_smc_display_change(struct radeon_device *rdev, | |
3650 | bool has_display) | |
3651 | { | |
3652 | PPSMC_Msg msg = has_display ? | |
3653 | PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; | |
3654 | ||
3655 | return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? | |
3656 | 0 : -EINVAL; | |
3657 | } | |
3658 | ||
3659 | static void si_program_response_times(struct radeon_device *rdev) | |
3660 | { | |
3661 | u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; | |
3662 | u32 vddc_dly, acpi_dly, vbi_dly; | |
3663 | u32 reference_clock; | |
3664 | ||
3665 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); | |
3666 | ||
3667 | voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; | |
3cf8bb1a | 3668 | backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; |
a9e61410 AD |
3669 | |
3670 | if (voltage_response_time == 0) | |
3671 | voltage_response_time = 1000; | |
3672 | ||
3673 | acpi_delay_time = 15000; | |
3674 | vbi_time_out = 100000; | |
3675 | ||
3676 | reference_clock = radeon_get_xclk(rdev); | |
3677 | ||
3678 | vddc_dly = (voltage_response_time * reference_clock) / 100; | |
3679 | acpi_dly = (acpi_delay_time * reference_clock) / 100; | |
3680 | vbi_dly = (vbi_time_out * reference_clock) / 100; | |
3681 | ||
3682 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); | |
3683 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); | |
3684 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); | |
3685 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); | |
3686 | } | |
3687 | ||
3688 | static void si_program_ds_registers(struct radeon_device *rdev) | |
3689 | { | |
3690 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
3691 | u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ | |
3692 | ||
3693 | if (eg_pi->sclk_deep_sleep) { | |
3694 | WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); | |
3695 | WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, | |
3696 | ~AUTOSCALE_ON_SS_CLEAR); | |
3697 | } | |
3698 | } | |
3699 | ||
3700 | static void si_program_display_gap(struct radeon_device *rdev) | |
3701 | { | |
3702 | u32 tmp, pipe; | |
3703 | int i; | |
3704 | ||
3705 | tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); | |
3706 | if (rdev->pm.dpm.new_active_crtc_count > 0) | |
3707 | tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); | |
3708 | else | |
3709 | tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); | |
3710 | ||
3711 | if (rdev->pm.dpm.new_active_crtc_count > 1) | |
3712 | tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); | |
3713 | else | |
3714 | tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); | |
3715 | ||
3716 | WREG32(CG_DISPLAY_GAP_CNTL, tmp); | |
3717 | ||
3718 | tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); | |
3719 | pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; | |
3720 | ||
3721 | if ((rdev->pm.dpm.new_active_crtc_count > 0) && | |
3722 | (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { | |
3723 | /* find the first active crtc */ | |
3724 | for (i = 0; i < rdev->num_crtc; i++) { | |
3725 | if (rdev->pm.dpm.new_active_crtcs & (1 << i)) | |
3726 | break; | |
3727 | } | |
3728 | if (i == rdev->num_crtc) | |
3729 | pipe = 0; | |
3730 | else | |
3731 | pipe = i; | |
3732 | ||
3733 | tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; | |
3734 | tmp |= DCCG_DISP1_SLOW_SELECT(pipe); | |
3735 | WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); | |
3736 | } | |
3737 | ||
4573388c AD |
3738 | /* Setting this to false forces the performance state to low if the crtcs are disabled. |
3739 | * This can be a problem on PowerXpress systems or if you want to use the card | |
ffcda352 | 3740 | * for offscreen rendering or compute if there are no crtcs enabled. |
4573388c | 3741 | */ |
ffcda352 | 3742 | si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); |
a9e61410 AD |
3743 | } |
3744 | ||
3745 | static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) | |
3746 | { | |
3747 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
3748 | ||
3749 | if (enable) { | |
3750 | if (pi->sclk_ss) | |
3751 | WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); | |
3752 | } else { | |
3753 | WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); | |
3754 | WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); | |
3755 | } | |
3756 | } | |
3757 | ||
3758 | static void si_setup_bsp(struct radeon_device *rdev) | |
3759 | { | |
3760 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
3761 | u32 xclk = radeon_get_xclk(rdev); | |
3762 | ||
3763 | r600_calculate_u_and_p(pi->asi, | |
3764 | xclk, | |
3765 | 16, | |
3766 | &pi->bsp, | |
3767 | &pi->bsu); | |
3768 | ||
3769 | r600_calculate_u_and_p(pi->pasi, | |
3770 | xclk, | |
3771 | 16, | |
3772 | &pi->pbsp, | |
3773 | &pi->pbsu); | |
3774 | ||
3775 | ||
3cf8bb1a | 3776 | pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); |
a9e61410 AD |
3777 | pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); |
3778 | ||
3779 | WREG32(CG_BSP, pi->dsp); | |
3780 | } | |
3781 | ||
3782 | static void si_program_git(struct radeon_device *rdev) | |
3783 | { | |
3784 | WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); | |
3785 | } | |
3786 | ||
3787 | static void si_program_tp(struct radeon_device *rdev) | |
3788 | { | |
3789 | int i; | |
3790 | enum r600_td td = R600_TD_DFLT; | |
3791 | ||
3792 | for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) | |
3793 | WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); | |
3794 | ||
3795 | if (td == R600_TD_AUTO) | |
3796 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); | |
3797 | else | |
3798 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); | |
3799 | ||
3800 | if (td == R600_TD_UP) | |
3801 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); | |
3802 | ||
3803 | if (td == R600_TD_DOWN) | |
3804 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); | |
3805 | } | |
3806 | ||
3807 | static void si_program_tpp(struct radeon_device *rdev) | |
3808 | { | |
3809 | WREG32(CG_TPC, R600_TPC_DFLT); | |
3810 | } | |
3811 | ||
3812 | static void si_program_sstp(struct radeon_device *rdev) | |
3813 | { | |
3814 | WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); | |
3815 | } | |
3816 | ||
3817 | static void si_enable_display_gap(struct radeon_device *rdev) | |
3818 | { | |
3819 | u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); | |
3820 | ||
489bc476 AD |
3821 | tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); |
3822 | tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | | |
3823 | DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); | |
3824 | ||
a9e61410 | 3825 | tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); |
489bc476 | 3826 | tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | |
a9e61410 AD |
3827 | DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); |
3828 | WREG32(CG_DISPLAY_GAP_CNTL, tmp); | |
3829 | } | |
3830 | ||
3831 | static void si_program_vc(struct radeon_device *rdev) | |
3832 | { | |
3833 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
3834 | ||
3835 | WREG32(CG_FTV, pi->vrc); | |
3836 | } | |
3837 | ||
3838 | static void si_clear_vc(struct radeon_device *rdev) | |
3839 | { | |
3840 | WREG32(CG_FTV, 0); | |
3841 | } | |
3842 | ||
cc8dbbb4 | 3843 | u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) |
a9e61410 AD |
3844 | { |
3845 | u8 mc_para_index; | |
3846 | ||
3847 | if (memory_clock < 10000) | |
3848 | mc_para_index = 0; | |
3849 | else if (memory_clock >= 80000) | |
3850 | mc_para_index = 0x0f; | |
3851 | else | |
3852 | mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); | |
3853 | return mc_para_index; | |
3854 | } | |
3855 | ||
cc8dbbb4 | 3856 | u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) |
a9e61410 AD |
3857 | { |
3858 | u8 mc_para_index; | |
3859 | ||
3860 | if (strobe_mode) { | |
3861 | if (memory_clock < 12500) | |
3862 | mc_para_index = 0x00; | |
3863 | else if (memory_clock > 47500) | |
3864 | mc_para_index = 0x0f; | |
3865 | else | |
3866 | mc_para_index = (u8)((memory_clock - 10000) / 2500); | |
3867 | } else { | |
3868 | if (memory_clock < 65000) | |
3869 | mc_para_index = 0x00; | |
3870 | else if (memory_clock > 135000) | |
3871 | mc_para_index = 0x0f; | |
3872 | else | |
3873 | mc_para_index = (u8)((memory_clock - 60000) / 5000); | |
3874 | } | |
3875 | return mc_para_index; | |
3876 | } | |
3877 | ||
3878 | static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) | |
3879 | { | |
3880 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
3881 | bool strobe_mode = false; | |
3882 | u8 result = 0; | |
3883 | ||
3884 | if (mclk <= pi->mclk_strobe_mode_threshold) | |
3885 | strobe_mode = true; | |
3886 | ||
3887 | if (pi->mem_gddr5) | |
3888 | result = si_get_mclk_frequency_ratio(mclk, strobe_mode); | |
3889 | else | |
3890 | result = si_get_ddr3_mclk_frequency_ratio(mclk); | |
3891 | ||
3892 | if (strobe_mode) | |
3893 | result |= SISLANDS_SMC_STROBE_ENABLE; | |
3894 | ||
3895 | return result; | |
3896 | } | |
3897 | ||
3898 | static int si_upload_firmware(struct radeon_device *rdev) | |
3899 | { | |
3900 | struct si_power_info *si_pi = si_get_pi(rdev); | |
3901 | int ret; | |
3902 | ||
3903 | si_reset_smc(rdev); | |
3904 | si_stop_smc_clock(rdev); | |
3905 | ||
3906 | ret = si_load_smc_ucode(rdev, si_pi->sram_end); | |
3907 | ||
3908 | return ret; | |
3909 | } | |
3910 | ||
3911 | static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, | |
3912 | const struct atom_voltage_table *table, | |
3913 | const struct radeon_phase_shedding_limits_table *limits) | |
3914 | { | |
3915 | u32 data, num_bits, num_levels; | |
3916 | ||
3917 | if ((table == NULL) || (limits == NULL)) | |
3918 | return false; | |
3919 | ||
3920 | data = table->mask_low; | |
3921 | ||
3922 | num_bits = hweight32(data); | |
3923 | ||
3924 | if (num_bits == 0) | |
3925 | return false; | |
3926 | ||
3927 | num_levels = (1 << num_bits); | |
3928 | ||
3929 | if (table->count != num_levels) | |
3930 | return false; | |
3931 | ||
3932 | if (limits->count != (num_levels - 1)) | |
3933 | return false; | |
3934 | ||
3935 | return true; | |
3936 | } | |
3937 | ||
cc8dbbb4 AD |
3938 | void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, |
3939 | u32 max_voltage_steps, | |
3940 | struct atom_voltage_table *voltage_table) | |
a9e61410 AD |
3941 | { |
3942 | unsigned int i, diff; | |
3943 | ||
9dd9333b | 3944 | if (voltage_table->count <= max_voltage_steps) |
a9e61410 AD |
3945 | return; |
3946 | ||
9dd9333b | 3947 | diff = voltage_table->count - max_voltage_steps; |
a9e61410 | 3948 | |
9dd9333b | 3949 | for (i= 0; i < max_voltage_steps; i++) |
a9e61410 AD |
3950 | voltage_table->entries[i] = voltage_table->entries[i + diff]; |
3951 | ||
9dd9333b | 3952 | voltage_table->count = max_voltage_steps; |
a9e61410 AD |
3953 | } |
3954 | ||
636e2582 AD |
3955 | static int si_get_svi2_voltage_table(struct radeon_device *rdev, |
3956 | struct radeon_clock_voltage_dependency_table *voltage_dependency_table, | |
3957 | struct atom_voltage_table *voltage_table) | |
3958 | { | |
3959 | u32 i; | |
3960 | ||
3961 | if (voltage_dependency_table == NULL) | |
3962 | return -EINVAL; | |
3963 | ||
3964 | voltage_table->mask_low = 0; | |
3965 | voltage_table->phase_delay = 0; | |
3966 | ||
3967 | voltage_table->count = voltage_dependency_table->count; | |
3968 | for (i = 0; i < voltage_table->count; i++) { | |
3969 | voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; | |
3970 | voltage_table->entries[i].smio_low = 0; | |
3971 | } | |
3972 | ||
3973 | return 0; | |
3974 | } | |
3975 | ||
a9e61410 AD |
3976 | static int si_construct_voltage_tables(struct radeon_device *rdev) |
3977 | { | |
3978 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
3979 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
3980 | struct si_power_info *si_pi = si_get_pi(rdev); | |
3981 | int ret; | |
3982 | ||
636e2582 AD |
3983 | if (pi->voltage_control) { |
3984 | ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, | |
3985 | VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); | |
3986 | if (ret) | |
3987 | return ret; | |
a9e61410 | 3988 | |
636e2582 AD |
3989 | if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) |
3990 | si_trim_voltage_table_to_fit_state_table(rdev, | |
3991 | SISLANDS_MAX_NO_VREG_STEPS, | |
3992 | &eg_pi->vddc_voltage_table); | |
3993 | } else if (si_pi->voltage_control_svi2) { | |
3994 | ret = si_get_svi2_voltage_table(rdev, | |
3995 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, | |
3996 | &eg_pi->vddc_voltage_table); | |
3997 | if (ret) | |
3998 | return ret; | |
3999 | } else { | |
4000 | return -EINVAL; | |
4001 | } | |
a9e61410 AD |
4002 | |
4003 | if (eg_pi->vddci_control) { | |
4004 | ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, | |
4005 | VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); | |
4006 | if (ret) | |
4007 | return ret; | |
4008 | ||
4009 | if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) | |
9dd9333b AD |
4010 | si_trim_voltage_table_to_fit_state_table(rdev, |
4011 | SISLANDS_MAX_NO_VREG_STEPS, | |
4012 | &eg_pi->vddci_voltage_table); | |
a9e61410 | 4013 | } |
636e2582 AD |
4014 | if (si_pi->vddci_control_svi2) { |
4015 | ret = si_get_svi2_voltage_table(rdev, | |
4016 | &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, | |
4017 | &eg_pi->vddci_voltage_table); | |
4018 | if (ret) | |
4019 | return ret; | |
4020 | } | |
a9e61410 AD |
4021 | |
4022 | if (pi->mvdd_control) { | |
4023 | ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, | |
4024 | VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); | |
4025 | ||
4026 | if (ret) { | |
4027 | pi->mvdd_control = false; | |
4028 | return ret; | |
4029 | } | |
4030 | ||
4031 | if (si_pi->mvdd_voltage_table.count == 0) { | |
4032 | pi->mvdd_control = false; | |
4033 | return -EINVAL; | |
4034 | } | |
4035 | ||
4036 | if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) | |
9dd9333b AD |
4037 | si_trim_voltage_table_to_fit_state_table(rdev, |
4038 | SISLANDS_MAX_NO_VREG_STEPS, | |
4039 | &si_pi->mvdd_voltage_table); | |
a9e61410 AD |
4040 | } |
4041 | ||
4042 | if (si_pi->vddc_phase_shed_control) { | |
4043 | ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, | |
4044 | VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); | |
4045 | if (ret) | |
4046 | si_pi->vddc_phase_shed_control = false; | |
4047 | ||
4048 | if ((si_pi->vddc_phase_shed_table.count == 0) || | |
4049 | (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) | |
4050 | si_pi->vddc_phase_shed_control = false; | |
4051 | } | |
4052 | ||
4053 | return 0; | |
4054 | } | |
4055 | ||
4056 | static void si_populate_smc_voltage_table(struct radeon_device *rdev, | |
4057 | const struct atom_voltage_table *voltage_table, | |
4058 | SISLANDS_SMC_STATETABLE *table) | |
4059 | { | |
4060 | unsigned int i; | |
4061 | ||
4062 | for (i = 0; i < voltage_table->count; i++) | |
4063 | table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); | |
4064 | } | |
4065 | ||
4066 | static int si_populate_smc_voltage_tables(struct radeon_device *rdev, | |
4067 | SISLANDS_SMC_STATETABLE *table) | |
4068 | { | |
4069 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
4070 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
4071 | struct si_power_info *si_pi = si_get_pi(rdev); | |
4072 | u8 i; | |
4073 | ||
636e2582 AD |
4074 | if (si_pi->voltage_control_svi2) { |
4075 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, | |
4076 | si_pi->svc_gpio_id); | |
4077 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, | |
4078 | si_pi->svd_gpio_id); | |
4079 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, | |
4080 | 2); | |
4081 | } else { | |
4082 | if (eg_pi->vddc_voltage_table.count) { | |
4083 | si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); | |
4084 | table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = | |
4085 | cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); | |
4086 | ||
4087 | for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { | |
4088 | if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { | |
4089 | table->maxVDDCIndexInPPTable = i; | |
4090 | break; | |
4091 | } | |
a9e61410 AD |
4092 | } |
4093 | } | |
a9e61410 | 4094 | |
636e2582 AD |
4095 | if (eg_pi->vddci_voltage_table.count) { |
4096 | si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); | |
a9e61410 | 4097 | |
636e2582 AD |
4098 | table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = |
4099 | cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); | |
4100 | } | |
a9e61410 AD |
4101 | |
4102 | ||
636e2582 AD |
4103 | if (si_pi->mvdd_voltage_table.count) { |
4104 | si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); | |
a9e61410 | 4105 | |
636e2582 AD |
4106 | table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = |
4107 | cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); | |
4108 | } | |
a9e61410 | 4109 | |
636e2582 AD |
4110 | if (si_pi->vddc_phase_shed_control) { |
4111 | if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, | |
4112 | &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { | |
4113 | si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); | |
a9e61410 | 4114 | |
636e2582 AD |
4115 | table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = |
4116 | cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); | |
a9e61410 | 4117 | |
636e2582 AD |
4118 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, |
4119 | (u32)si_pi->vddc_phase_shed_table.phase_delay); | |
4120 | } else { | |
4121 | si_pi->vddc_phase_shed_control = false; | |
4122 | } | |
a9e61410 AD |
4123 | } |
4124 | } | |
4125 | ||
4126 | return 0; | |
4127 | } | |
4128 | ||
4129 | static int si_populate_voltage_value(struct radeon_device *rdev, | |
4130 | const struct atom_voltage_table *table, | |
4131 | u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) | |
4132 | { | |
4133 | unsigned int i; | |
4134 | ||
4135 | for (i = 0; i < table->count; i++) { | |
4136 | if (value <= table->entries[i].value) { | |
4137 | voltage->index = (u8)i; | |
4138 | voltage->value = cpu_to_be16(table->entries[i].value); | |
4139 | break; | |
4140 | } | |
4141 | } | |
4142 | ||
4143 | if (i >= table->count) | |
4144 | return -EINVAL; | |
4145 | ||
4146 | return 0; | |
4147 | } | |
4148 | ||
4149 | static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, | |
4150 | SISLANDS_SMC_VOLTAGE_VALUE *voltage) | |
4151 | { | |
4152 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
4153 | struct si_power_info *si_pi = si_get_pi(rdev); | |
4154 | ||
4155 | if (pi->mvdd_control) { | |
4156 | if (mclk <= pi->mvdd_split_frequency) | |
4157 | voltage->index = 0; | |
4158 | else | |
4159 | voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; | |
4160 | ||
4161 | voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); | |
4162 | } | |
4163 | return 0; | |
4164 | } | |
4165 | ||
4166 | static int si_get_std_voltage_value(struct radeon_device *rdev, | |
4167 | SISLANDS_SMC_VOLTAGE_VALUE *voltage, | |
4168 | u16 *std_voltage) | |
4169 | { | |
4170 | u16 v_index; | |
4171 | bool voltage_found = false; | |
4172 | *std_voltage = be16_to_cpu(voltage->value); | |
4173 | ||
4174 | if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { | |
4175 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { | |
4176 | if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) | |
4177 | return -EINVAL; | |
4178 | ||
4179 | for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { | |
4180 | if (be16_to_cpu(voltage->value) == | |
4181 | (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { | |
4182 | voltage_found = true; | |
4183 | if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) | |
4184 | *std_voltage = | |
4185 | rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; | |
4186 | else | |
4187 | *std_voltage = | |
4188 | rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; | |
4189 | break; | |
4190 | } | |
4191 | } | |
4192 | ||
4193 | if (!voltage_found) { | |
4194 | for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { | |
4195 | if (be16_to_cpu(voltage->value) <= | |
4196 | (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { | |
4197 | voltage_found = true; | |
4198 | if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) | |
4199 | *std_voltage = | |
4200 | rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; | |
4201 | else | |
4202 | *std_voltage = | |
4203 | rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; | |
4204 | break; | |
4205 | } | |
4206 | } | |
4207 | } | |
4208 | } else { | |
4209 | if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) | |
4210 | *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; | |
4211 | } | |
4212 | } | |
4213 | ||
4214 | return 0; | |
4215 | } | |
4216 | ||
4217 | static int si_populate_std_voltage_value(struct radeon_device *rdev, | |
4218 | u16 value, u8 index, | |
4219 | SISLANDS_SMC_VOLTAGE_VALUE *voltage) | |
4220 | { | |
4221 | voltage->index = index; | |
4222 | voltage->value = cpu_to_be16(value); | |
4223 | ||
4224 | return 0; | |
4225 | } | |
4226 | ||
4227 | static int si_populate_phase_shedding_value(struct radeon_device *rdev, | |
4228 | const struct radeon_phase_shedding_limits_table *limits, | |
4229 | u16 voltage, u32 sclk, u32 mclk, | |
4230 | SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) | |
4231 | { | |
4232 | unsigned int i; | |
4233 | ||
4234 | for (i = 0; i < limits->count; i++) { | |
4235 | if ((voltage <= limits->entries[i].voltage) && | |
4236 | (sclk <= limits->entries[i].sclk) && | |
4237 | (mclk <= limits->entries[i].mclk)) | |
4238 | break; | |
4239 | } | |
4240 | ||
4241 | smc_voltage->phase_settings = (u8)i; | |
4242 | ||
4243 | return 0; | |
4244 | } | |
4245 | ||
4246 | static int si_init_arb_table_index(struct radeon_device *rdev) | |
4247 | { | |
4248 | struct si_power_info *si_pi = si_get_pi(rdev); | |
4249 | u32 tmp; | |
4250 | int ret; | |
4251 | ||
4252 | ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); | |
4253 | if (ret) | |
4254 | return ret; | |
4255 | ||
4256 | tmp &= 0x00FFFFFF; | |
4257 | tmp |= MC_CG_ARB_FREQ_F1 << 24; | |
4258 | ||
4259 | return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); | |
4260 | } | |
4261 | ||
4262 | static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) | |
4263 | { | |
4264 | return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); | |
4265 | } | |
4266 | ||
4267 | static int si_reset_to_default(struct radeon_device *rdev) | |
4268 | { | |
4269 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? | |
4270 | 0 : -EINVAL; | |
4271 | } | |
4272 | ||
4273 | static int si_force_switch_to_arb_f0(struct radeon_device *rdev) | |
4274 | { | |
4275 | struct si_power_info *si_pi = si_get_pi(rdev); | |
4276 | u32 tmp; | |
4277 | int ret; | |
4278 | ||
4279 | ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, | |
4280 | &tmp, si_pi->sram_end); | |
4281 | if (ret) | |
4282 | return ret; | |
4283 | ||
4284 | tmp = (tmp >> 24) & 0xff; | |
4285 | ||
4286 | if (tmp == MC_CG_ARB_FREQ_F0) | |
4287 | return 0; | |
4288 | ||
4289 | return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); | |
4290 | } | |
4291 | ||
4292 | static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, | |
4293 | u32 engine_clock) | |
4294 | { | |
a9e61410 AD |
4295 | u32 dram_rows; |
4296 | u32 dram_refresh_rate; | |
4297 | u32 mc_arb_rfsh_rate; | |
4298 | u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; | |
4299 | ||
f44a0120 AD |
4300 | if (tmp >= 4) |
4301 | dram_rows = 16384; | |
a9e61410 | 4302 | else |
f44a0120 | 4303 | dram_rows = 1 << (tmp + 10); |
a9e61410 AD |
4304 | |
4305 | dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); | |
4306 | mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; | |
4307 | ||
4308 | return mc_arb_rfsh_rate; | |
4309 | } | |
4310 | ||
4311 | static int si_populate_memory_timing_parameters(struct radeon_device *rdev, | |
4312 | struct rv7xx_pl *pl, | |
4313 | SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) | |
4314 | { | |
4315 | u32 dram_timing; | |
4316 | u32 dram_timing2; | |
4317 | u32 burst_time; | |
4318 | ||
4319 | arb_regs->mc_arb_rfsh_rate = | |
4320 | (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); | |
4321 | ||
4322 | radeon_atom_set_engine_dram_timings(rdev, | |
4323 | pl->sclk, | |
3cf8bb1a | 4324 | pl->mclk); |
a9e61410 AD |
4325 | |
4326 | dram_timing = RREG32(MC_ARB_DRAM_TIMING); | |
4327 | dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); | |
4328 | burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; | |
4329 | ||
4330 | arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); | |
4331 | arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); | |
4332 | arb_regs->mc_arb_burst_time = (u8)burst_time; | |
4333 | ||
4334 | return 0; | |
4335 | } | |
4336 | ||
4337 | static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, | |
4338 | struct radeon_ps *radeon_state, | |
4339 | unsigned int first_arb_set) | |
4340 | { | |
4341 | struct si_power_info *si_pi = si_get_pi(rdev); | |
4342 | struct ni_ps *state = ni_get_ps(radeon_state); | |
4343 | SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; | |
4344 | int i, ret = 0; | |
4345 | ||
4346 | for (i = 0; i < state->performance_level_count; i++) { | |
4347 | ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); | |
4348 | if (ret) | |
4349 | break; | |
4350 | ret = si_copy_bytes_to_smc(rdev, | |
4351 | si_pi->arb_table_start + | |
4352 | offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + | |
4353 | sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), | |
4354 | (u8 *)&arb_regs, | |
4355 | sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), | |
4356 | si_pi->sram_end); | |
4357 | if (ret) | |
4358 | break; | |
3cf8bb1a | 4359 | } |
a9e61410 AD |
4360 | |
4361 | return ret; | |
4362 | } | |
4363 | ||
4364 | static int si_program_memory_timing_parameters(struct radeon_device *rdev, | |
4365 | struct radeon_ps *radeon_new_state) | |
4366 | { | |
4367 | return si_do_program_memory_timing_parameters(rdev, radeon_new_state, | |
4368 | SISLANDS_DRIVER_STATE_ARB_INDEX); | |
4369 | } | |
4370 | ||
4371 | static int si_populate_initial_mvdd_value(struct radeon_device *rdev, | |
4372 | struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) | |
4373 | { | |
4374 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
4375 | struct si_power_info *si_pi = si_get_pi(rdev); | |
4376 | ||
4377 | if (pi->mvdd_control) | |
4378 | return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, | |
4379 | si_pi->mvdd_bootup_value, voltage); | |
4380 | ||
4381 | return 0; | |
4382 | } | |
4383 | ||
4384 | static int si_populate_smc_initial_state(struct radeon_device *rdev, | |
4385 | struct radeon_ps *radeon_initial_state, | |
4386 | SISLANDS_SMC_STATETABLE *table) | |
4387 | { | |
4388 | struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); | |
4389 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
4390 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
4391 | struct si_power_info *si_pi = si_get_pi(rdev); | |
4392 | u32 reg; | |
4393 | int ret; | |
4394 | ||
4395 | table->initialState.levels[0].mclk.vDLL_CNTL = | |
4396 | cpu_to_be32(si_pi->clock_registers.dll_cntl); | |
4397 | table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = | |
4398 | cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); | |
4399 | table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = | |
4400 | cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); | |
4401 | table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = | |
4402 | cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); | |
4403 | table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = | |
4404 | cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); | |
4405 | table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = | |
4406 | cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); | |
4407 | table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = | |
4408 | cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); | |
4409 | table->initialState.levels[0].mclk.vMPLL_SS = | |
4410 | cpu_to_be32(si_pi->clock_registers.mpll_ss1); | |
4411 | table->initialState.levels[0].mclk.vMPLL_SS2 = | |
4412 | cpu_to_be32(si_pi->clock_registers.mpll_ss2); | |
4413 | ||
4414 | table->initialState.levels[0].mclk.mclk_value = | |
4415 | cpu_to_be32(initial_state->performance_levels[0].mclk); | |
4416 | ||
4417 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = | |
4418 | cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); | |
4419 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = | |
4420 | cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); | |
4421 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = | |
4422 | cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); | |
4423 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = | |
4424 | cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); | |
4425 | table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = | |
4426 | cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); | |
4427 | table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = | |
4428 | cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); | |
4429 | ||
4430 | table->initialState.levels[0].sclk.sclk_value = | |
4431 | cpu_to_be32(initial_state->performance_levels[0].sclk); | |
4432 | ||
4433 | table->initialState.levels[0].arbRefreshState = | |
4434 | SISLANDS_INITIAL_STATE_ARB_INDEX; | |
4435 | ||
4436 | table->initialState.levels[0].ACIndex = 0; | |
4437 | ||
4438 | ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, | |
4439 | initial_state->performance_levels[0].vddc, | |
4440 | &table->initialState.levels[0].vddc); | |
4441 | ||
4442 | if (!ret) { | |
4443 | u16 std_vddc; | |
4444 | ||
4445 | ret = si_get_std_voltage_value(rdev, | |
4446 | &table->initialState.levels[0].vddc, | |
4447 | &std_vddc); | |
4448 | if (!ret) | |
4449 | si_populate_std_voltage_value(rdev, std_vddc, | |
4450 | table->initialState.levels[0].vddc.index, | |
4451 | &table->initialState.levels[0].std_vddc); | |
4452 | } | |
4453 | ||
4454 | if (eg_pi->vddci_control) | |
4455 | si_populate_voltage_value(rdev, | |
4456 | &eg_pi->vddci_voltage_table, | |
4457 | initial_state->performance_levels[0].vddci, | |
4458 | &table->initialState.levels[0].vddci); | |
4459 | ||
4460 | if (si_pi->vddc_phase_shed_control) | |
4461 | si_populate_phase_shedding_value(rdev, | |
4462 | &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, | |
4463 | initial_state->performance_levels[0].vddc, | |
4464 | initial_state->performance_levels[0].sclk, | |
4465 | initial_state->performance_levels[0].mclk, | |
4466 | &table->initialState.levels[0].vddc); | |
4467 | ||
4468 | si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); | |
4469 | ||
4470 | reg = CG_R(0xffff) | CG_L(0); | |
4471 | table->initialState.levels[0].aT = cpu_to_be32(reg); | |
4472 | ||
4473 | table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); | |
4474 | ||
4475 | table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; | |
4476 | ||
4477 | if (pi->mem_gddr5) { | |
4478 | table->initialState.levels[0].strobeMode = | |
4479 | si_get_strobe_mode_settings(rdev, | |
4480 | initial_state->performance_levels[0].mclk); | |
4481 | ||
4482 | if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) | |
4483 | table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; | |
4484 | else | |
4485 | table->initialState.levels[0].mcFlags = 0; | |
4486 | } | |
4487 | ||
4488 | table->initialState.levelCount = 1; | |
4489 | ||
4490 | table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; | |
4491 | ||
4492 | table->initialState.levels[0].dpm2.MaxPS = 0; | |
4493 | table->initialState.levels[0].dpm2.NearTDPDec = 0; | |
4494 | table->initialState.levels[0].dpm2.AboveSafeInc = 0; | |
4495 | table->initialState.levels[0].dpm2.BelowSafeInc = 0; | |
4496 | table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; | |
4497 | ||
4498 | reg = MIN_POWER_MASK | MAX_POWER_MASK; | |
4499 | table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); | |
4500 | ||
4501 | reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; | |
4502 | table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); | |
4503 | ||
4504 | return 0; | |
4505 | } | |
4506 | ||
4507 | static int si_populate_smc_acpi_state(struct radeon_device *rdev, | |
4508 | SISLANDS_SMC_STATETABLE *table) | |
4509 | { | |
4510 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
4511 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
4512 | struct si_power_info *si_pi = si_get_pi(rdev); | |
4513 | u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; | |
4514 | u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; | |
4515 | u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; | |
4516 | u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; | |
4517 | u32 dll_cntl = si_pi->clock_registers.dll_cntl; | |
4518 | u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; | |
4519 | u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; | |
4520 | u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; | |
4521 | u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; | |
4522 | u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; | |
4523 | u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; | |
4524 | u32 reg; | |
4525 | int ret; | |
4526 | ||
4527 | table->ACPIState = table->initialState; | |
4528 | ||
4529 | table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; | |
4530 | ||
4531 | if (pi->acpi_vddc) { | |
4532 | ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, | |
4533 | pi->acpi_vddc, &table->ACPIState.levels[0].vddc); | |
4534 | if (!ret) { | |
4535 | u16 std_vddc; | |
4536 | ||
4537 | ret = si_get_std_voltage_value(rdev, | |
4538 | &table->ACPIState.levels[0].vddc, &std_vddc); | |
4539 | if (!ret) | |
4540 | si_populate_std_voltage_value(rdev, std_vddc, | |
4541 | table->ACPIState.levels[0].vddc.index, | |
4542 | &table->ACPIState.levels[0].std_vddc); | |
4543 | } | |
4544 | table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; | |
4545 | ||
4546 | if (si_pi->vddc_phase_shed_control) { | |
4547 | si_populate_phase_shedding_value(rdev, | |
4548 | &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, | |
4549 | pi->acpi_vddc, | |
4550 | 0, | |
4551 | 0, | |
4552 | &table->ACPIState.levels[0].vddc); | |
4553 | } | |
4554 | } else { | |
4555 | ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, | |
4556 | pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); | |
4557 | if (!ret) { | |
4558 | u16 std_vddc; | |
4559 | ||
4560 | ret = si_get_std_voltage_value(rdev, | |
4561 | &table->ACPIState.levels[0].vddc, &std_vddc); | |
4562 | ||
4563 | if (!ret) | |
4564 | si_populate_std_voltage_value(rdev, std_vddc, | |
4565 | table->ACPIState.levels[0].vddc.index, | |
4566 | &table->ACPIState.levels[0].std_vddc); | |
4567 | } | |
4568 | table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, | |
4569 | si_pi->sys_pcie_mask, | |
4570 | si_pi->boot_pcie_gen, | |
4571 | RADEON_PCIE_GEN1); | |
4572 | ||
4573 | if (si_pi->vddc_phase_shed_control) | |
4574 | si_populate_phase_shedding_value(rdev, | |
4575 | &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, | |
4576 | pi->min_vddc_in_table, | |
4577 | 0, | |
4578 | 0, | |
4579 | &table->ACPIState.levels[0].vddc); | |
4580 | } | |
4581 | ||
4582 | if (pi->acpi_vddc) { | |
4583 | if (eg_pi->acpi_vddci) | |
4584 | si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, | |
4585 | eg_pi->acpi_vddci, | |
4586 | &table->ACPIState.levels[0].vddci); | |
4587 | } | |
4588 | ||
4589 | mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; | |
4590 | mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); | |
4591 | ||
4592 | dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); | |
4593 | ||
4594 | spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; | |
4595 | spll_func_cntl_2 |= SCLK_MUX_SEL(4); | |
4596 | ||
4597 | table->ACPIState.levels[0].mclk.vDLL_CNTL = | |
4598 | cpu_to_be32(dll_cntl); | |
4599 | table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = | |
4600 | cpu_to_be32(mclk_pwrmgt_cntl); | |
4601 | table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = | |
4602 | cpu_to_be32(mpll_ad_func_cntl); | |
4603 | table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = | |
4604 | cpu_to_be32(mpll_dq_func_cntl); | |
4605 | table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = | |
4606 | cpu_to_be32(mpll_func_cntl); | |
4607 | table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = | |
4608 | cpu_to_be32(mpll_func_cntl_1); | |
4609 | table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = | |
4610 | cpu_to_be32(mpll_func_cntl_2); | |
4611 | table->ACPIState.levels[0].mclk.vMPLL_SS = | |
4612 | cpu_to_be32(si_pi->clock_registers.mpll_ss1); | |
4613 | table->ACPIState.levels[0].mclk.vMPLL_SS2 = | |
4614 | cpu_to_be32(si_pi->clock_registers.mpll_ss2); | |
4615 | ||
4616 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = | |
4617 | cpu_to_be32(spll_func_cntl); | |
4618 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = | |
4619 | cpu_to_be32(spll_func_cntl_2); | |
4620 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = | |
4621 | cpu_to_be32(spll_func_cntl_3); | |
4622 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = | |
4623 | cpu_to_be32(spll_func_cntl_4); | |
4624 | ||
4625 | table->ACPIState.levels[0].mclk.mclk_value = 0; | |
4626 | table->ACPIState.levels[0].sclk.sclk_value = 0; | |
4627 | ||
4628 | si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); | |
4629 | ||
4630 | if (eg_pi->dynamic_ac_timing) | |
4631 | table->ACPIState.levels[0].ACIndex = 0; | |
4632 | ||
4633 | table->ACPIState.levels[0].dpm2.MaxPS = 0; | |
4634 | table->ACPIState.levels[0].dpm2.NearTDPDec = 0; | |
4635 | table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; | |
4636 | table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; | |
4637 | table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; | |
4638 | ||
4639 | reg = MIN_POWER_MASK | MAX_POWER_MASK; | |
4640 | table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); | |
4641 | ||
4642 | reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; | |
4643 | table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); | |
4644 | ||
4645 | return 0; | |
4646 | } | |
4647 | ||
4648 | static int si_populate_ulv_state(struct radeon_device *rdev, | |
4649 | SISLANDS_SMC_SWSTATE *state) | |
4650 | { | |
4651 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
4652 | struct si_power_info *si_pi = si_get_pi(rdev); | |
4653 | struct si_ulv_param *ulv = &si_pi->ulv; | |
4654 | u32 sclk_in_sr = 1350; /* ??? */ | |
4655 | int ret; | |
4656 | ||
4657 | ret = si_convert_power_level_to_smc(rdev, &ulv->pl, | |
4658 | &state->levels[0]); | |
4659 | if (!ret) { | |
4660 | if (eg_pi->sclk_deep_sleep) { | |
4661 | if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) | |
4662 | state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; | |
4663 | else | |
4664 | state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; | |
4665 | } | |
4666 | if (ulv->one_pcie_lane_in_ulv) | |
4667 | state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; | |
4668 | state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); | |
4669 | state->levels[0].ACIndex = 1; | |
4670 | state->levels[0].std_vddc = state->levels[0].vddc; | |
4671 | state->levelCount = 1; | |
4672 | ||
4673 | state->flags |= PPSMC_SWSTATE_FLAG_DC; | |
4674 | } | |
4675 | ||
4676 | return ret; | |
4677 | } | |
4678 | ||
4679 | static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) | |
4680 | { | |
4681 | struct si_power_info *si_pi = si_get_pi(rdev); | |
4682 | struct si_ulv_param *ulv = &si_pi->ulv; | |
4683 | SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; | |
4684 | int ret; | |
4685 | ||
4686 | ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, | |
4687 | &arb_regs); | |
4688 | if (ret) | |
4689 | return ret; | |
4690 | ||
4691 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, | |
4692 | ulv->volt_change_delay); | |
4693 | ||
4694 | ret = si_copy_bytes_to_smc(rdev, | |
4695 | si_pi->arb_table_start + | |
4696 | offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + | |
4697 | sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, | |
4698 | (u8 *)&arb_regs, | |
4699 | sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), | |
4700 | si_pi->sram_end); | |
4701 | ||
4702 | return ret; | |
4703 | } | |
4704 | ||
4705 | static void si_get_mvdd_configuration(struct radeon_device *rdev) | |
4706 | { | |
4707 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
4708 | ||
4709 | pi->mvdd_split_frequency = 30000; | |
4710 | } | |
4711 | ||
4712 | static int si_init_smc_table(struct radeon_device *rdev) | |
4713 | { | |
4714 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
4715 | struct si_power_info *si_pi = si_get_pi(rdev); | |
4716 | struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; | |
4717 | const struct si_ulv_param *ulv = &si_pi->ulv; | |
4718 | SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; | |
4719 | int ret; | |
4720 | u32 lane_width; | |
4721 | u32 vr_hot_gpio; | |
4722 | ||
4723 | si_populate_smc_voltage_tables(rdev, table); | |
4724 | ||
4725 | switch (rdev->pm.int_thermal_type) { | |
4726 | case THERMAL_TYPE_SI: | |
4727 | case THERMAL_TYPE_EMC2103_WITH_INTERNAL: | |
4728 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; | |
4729 | break; | |
4730 | case THERMAL_TYPE_NONE: | |
4731 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; | |
4732 | break; | |
4733 | default: | |
4734 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; | |
4735 | break; | |
4736 | } | |
4737 | ||
4738 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) | |
4739 | table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; | |
4740 | ||
4741 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { | |
4742 | if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) | |
4743 | table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; | |
4744 | } | |
4745 | ||
4746 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) | |
4747 | table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; | |
4748 | ||
4749 | if (pi->mem_gddr5) | |
4750 | table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; | |
4751 | ||
4752 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) | |
6960394f | 4753 | table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; |
a9e61410 AD |
4754 | |
4755 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { | |
4756 | table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; | |
4757 | vr_hot_gpio = rdev->pm.dpm.backbias_response_time; | |
4758 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, | |
4759 | vr_hot_gpio); | |
4760 | } | |
4761 | ||
4762 | ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); | |
4763 | if (ret) | |
4764 | return ret; | |
4765 | ||
4766 | ret = si_populate_smc_acpi_state(rdev, table); | |
4767 | if (ret) | |
4768 | return ret; | |
4769 | ||
4770 | table->driverState = table->initialState; | |
4771 | ||
4772 | ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, | |
4773 | SISLANDS_INITIAL_STATE_ARB_INDEX); | |
4774 | if (ret) | |
4775 | return ret; | |
4776 | ||
4777 | if (ulv->supported && ulv->pl.vddc) { | |
4778 | ret = si_populate_ulv_state(rdev, &table->ULVState); | |
4779 | if (ret) | |
4780 | return ret; | |
4781 | ||
4782 | ret = si_program_ulv_memory_timing_parameters(rdev); | |
4783 | if (ret) | |
4784 | return ret; | |
4785 | ||
4786 | WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); | |
4787 | WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); | |
4788 | ||
4789 | lane_width = radeon_get_pcie_lanes(rdev); | |
4790 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); | |
4791 | } else { | |
4792 | table->ULVState = table->initialState; | |
4793 | } | |
4794 | ||
4795 | return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, | |
4796 | (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), | |
4797 | si_pi->sram_end); | |
4798 | } | |
4799 | ||
4800 | static int si_calculate_sclk_params(struct radeon_device *rdev, | |
4801 | u32 engine_clock, | |
4802 | SISLANDS_SMC_SCLK_VALUE *sclk) | |
4803 | { | |
4804 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
4805 | struct si_power_info *si_pi = si_get_pi(rdev); | |
4806 | struct atom_clock_dividers dividers; | |
4807 | u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; | |
4808 | u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; | |
4809 | u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; | |
4810 | u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; | |
4811 | u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; | |
4812 | u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; | |
4813 | u64 tmp; | |
4814 | u32 reference_clock = rdev->clock.spll.reference_freq; | |
4815 | u32 reference_divider; | |
4816 | u32 fbdiv; | |
4817 | int ret; | |
4818 | ||
4819 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, | |
4820 | engine_clock, false, ÷rs); | |
4821 | if (ret) | |
4822 | return ret; | |
4823 | ||
4824 | reference_divider = 1 + dividers.ref_div; | |
4825 | ||
4826 | tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; | |
4827 | do_div(tmp, reference_clock); | |
4828 | fbdiv = (u32) tmp; | |
4829 | ||
4830 | spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); | |
4831 | spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); | |
4832 | spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); | |
4833 | ||
4834 | spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; | |
4835 | spll_func_cntl_2 |= SCLK_MUX_SEL(2); | |
4836 | ||
3cf8bb1a JG |
4837 | spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; |
4838 | spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); | |
4839 | spll_func_cntl_3 |= SPLL_DITHEN; | |
a9e61410 AD |
4840 | |
4841 | if (pi->sclk_ss) { | |
4842 | struct radeon_atom_ss ss; | |
4843 | u32 vco_freq = engine_clock * dividers.post_div; | |
4844 | ||
4845 | if (radeon_atombios_get_asic_ss_info(rdev, &ss, | |
4846 | ASIC_INTERNAL_ENGINE_SS, vco_freq)) { | |
4847 | u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); | |
4848 | u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); | |
4849 | ||
4850 | cg_spll_spread_spectrum &= ~CLK_S_MASK; | |
4851 | cg_spll_spread_spectrum |= CLK_S(clk_s); | |
4852 | cg_spll_spread_spectrum |= SSEN; | |
4853 | ||
4854 | cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; | |
4855 | cg_spll_spread_spectrum_2 |= CLK_V(clk_v); | |
4856 | } | |
4857 | } | |
4858 | ||
4859 | sclk->sclk_value = engine_clock; | |
4860 | sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; | |
4861 | sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; | |
4862 | sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; | |
4863 | sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; | |
4864 | sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; | |
4865 | sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; | |
4866 | ||
4867 | return 0; | |
4868 | } | |
4869 | ||
4870 | static int si_populate_sclk_value(struct radeon_device *rdev, | |
4871 | u32 engine_clock, | |
4872 | SISLANDS_SMC_SCLK_VALUE *sclk) | |
4873 | { | |
4874 | SISLANDS_SMC_SCLK_VALUE sclk_tmp; | |
4875 | int ret; | |
4876 | ||
4877 | ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); | |
4878 | if (!ret) { | |
4879 | sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); | |
4880 | sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); | |
4881 | sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); | |
4882 | sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); | |
4883 | sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); | |
4884 | sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); | |
4885 | sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); | |
4886 | } | |
4887 | ||
4888 | return ret; | |
4889 | } | |
4890 | ||
4891 | static int si_populate_mclk_value(struct radeon_device *rdev, | |
4892 | u32 engine_clock, | |
4893 | u32 memory_clock, | |
4894 | SISLANDS_SMC_MCLK_VALUE *mclk, | |
4895 | bool strobe_mode, | |
4896 | bool dll_state_on) | |
4897 | { | |
4898 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
4899 | struct si_power_info *si_pi = si_get_pi(rdev); | |
4900 | u32 dll_cntl = si_pi->clock_registers.dll_cntl; | |
4901 | u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; | |
4902 | u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; | |
4903 | u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; | |
4904 | u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; | |
4905 | u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; | |
4906 | u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; | |
4907 | u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; | |
4908 | u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; | |
4909 | struct atom_mpll_param mpll_param; | |
4910 | int ret; | |
4911 | ||
4912 | ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); | |
4913 | if (ret) | |
4914 | return ret; | |
4915 | ||
4916 | mpll_func_cntl &= ~BWCTRL_MASK; | |
4917 | mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); | |
4918 | ||
4919 | mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); | |
4920 | mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | | |
4921 | CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); | |
4922 | ||
4923 | mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; | |
4924 | mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); | |
4925 | ||
4926 | if (pi->mem_gddr5) { | |
4927 | mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); | |
4928 | mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | | |
4929 | YCLK_POST_DIV(mpll_param.post_div); | |
4930 | } | |
4931 | ||
4932 | if (pi->mclk_ss) { | |
4933 | struct radeon_atom_ss ss; | |
4934 | u32 freq_nom; | |
4935 | u32 tmp; | |
4936 | u32 reference_clock = rdev->clock.mpll.reference_freq; | |
4937 | ||
4938 | if (pi->mem_gddr5) | |
4939 | freq_nom = memory_clock * 4; | |
4940 | else | |
4941 | freq_nom = memory_clock * 2; | |
4942 | ||
4943 | tmp = freq_nom / reference_clock; | |
4944 | tmp = tmp * tmp; | |
4945 | if (radeon_atombios_get_asic_ss_info(rdev, &ss, | |
3cf8bb1a | 4946 | ASIC_INTERNAL_MEMORY_SS, freq_nom)) { |
a9e61410 AD |
4947 | u32 clks = reference_clock * 5 / ss.rate; |
4948 | u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); | |
4949 | ||
3cf8bb1a JG |
4950 | mpll_ss1 &= ~CLKV_MASK; |
4951 | mpll_ss1 |= CLKV(clkv); | |
a9e61410 | 4952 | |
3cf8bb1a JG |
4953 | mpll_ss2 &= ~CLKS_MASK; |
4954 | mpll_ss2 |= CLKS(clks); | |
a9e61410 AD |
4955 | } |
4956 | } | |
4957 | ||
4958 | mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; | |
4959 | mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); | |
4960 | ||
4961 | if (dll_state_on) | |
4962 | mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; | |
4963 | else | |
4964 | mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); | |
4965 | ||
4966 | mclk->mclk_value = cpu_to_be32(memory_clock); | |
4967 | mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); | |
4968 | mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); | |
4969 | mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); | |
4970 | mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); | |
4971 | mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); | |
4972 | mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); | |
4973 | mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); | |
4974 | mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); | |
4975 | mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); | |
4976 | ||
4977 | return 0; | |
4978 | } | |
4979 | ||
4980 | static void si_populate_smc_sp(struct radeon_device *rdev, | |
4981 | struct radeon_ps *radeon_state, | |
4982 | SISLANDS_SMC_SWSTATE *smc_state) | |
4983 | { | |
4984 | struct ni_ps *ps = ni_get_ps(radeon_state); | |
4985 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
4986 | int i; | |
4987 | ||
4988 | for (i = 0; i < ps->performance_level_count - 1; i++) | |
4989 | smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); | |
4990 | ||
4991 | smc_state->levels[ps->performance_level_count - 1].bSP = | |
4992 | cpu_to_be32(pi->psp); | |
4993 | } | |
4994 | ||
4995 | static int si_convert_power_level_to_smc(struct radeon_device *rdev, | |
4996 | struct rv7xx_pl *pl, | |
4997 | SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) | |
4998 | { | |
4999 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
5000 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
5001 | struct si_power_info *si_pi = si_get_pi(rdev); | |
5002 | int ret; | |
5003 | bool dll_state_on; | |
5004 | u16 std_vddc; | |
5005 | bool gmc_pg = false; | |
5006 | ||
5007 | if (eg_pi->pcie_performance_request && | |
5008 | (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) | |
5009 | level->gen2PCIE = (u8)si_pi->force_pcie_gen; | |
5010 | else | |
5011 | level->gen2PCIE = (u8)pl->pcie_gen; | |
5012 | ||
5013 | ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); | |
5014 | if (ret) | |
5015 | return ret; | |
5016 | ||
5017 | level->mcFlags = 0; | |
5018 | ||
5019 | if (pi->mclk_stutter_mode_threshold && | |
5020 | (pl->mclk <= pi->mclk_stutter_mode_threshold) && | |
5021 | !eg_pi->uvd_enabled && | |
5022 | (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && | |
5023 | (rdev->pm.dpm.new_active_crtc_count <= 2)) { | |
5024 | level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; | |
5025 | ||
5026 | if (gmc_pg) | |
5027 | level->mcFlags |= SISLANDS_SMC_MC_PG_EN; | |
5028 | } | |
5029 | ||
5030 | if (pi->mem_gddr5) { | |
5031 | if (pl->mclk > pi->mclk_edc_enable_threshold) | |
5032 | level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; | |
5033 | ||
5034 | if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) | |
5035 | level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; | |
5036 | ||
5037 | level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); | |
5038 | ||
5039 | if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { | |
5040 | if (si_get_mclk_frequency_ratio(pl->mclk, true) >= | |
5041 | ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) | |
5042 | dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; | |
5043 | else | |
5044 | dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; | |
5045 | } else { | |
5046 | dll_state_on = false; | |
5047 | } | |
5048 | } else { | |
5049 | level->strobeMode = si_get_strobe_mode_settings(rdev, | |
5050 | pl->mclk); | |
5051 | ||
5052 | dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; | |
5053 | } | |
5054 | ||
5055 | ret = si_populate_mclk_value(rdev, | |
5056 | pl->sclk, | |
5057 | pl->mclk, | |
5058 | &level->mclk, | |
5059 | (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); | |
5060 | if (ret) | |
5061 | return ret; | |
5062 | ||
5063 | ret = si_populate_voltage_value(rdev, | |
5064 | &eg_pi->vddc_voltage_table, | |
5065 | pl->vddc, &level->vddc); | |
5066 | if (ret) | |
5067 | return ret; | |
5068 | ||
5069 | ||
5070 | ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); | |
5071 | if (ret) | |
5072 | return ret; | |
5073 | ||
5074 | ret = si_populate_std_voltage_value(rdev, std_vddc, | |
5075 | level->vddc.index, &level->std_vddc); | |
5076 | if (ret) | |
5077 | return ret; | |
5078 | ||
5079 | if (eg_pi->vddci_control) { | |
5080 | ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, | |
5081 | pl->vddci, &level->vddci); | |
5082 | if (ret) | |
5083 | return ret; | |
5084 | } | |
5085 | ||
5086 | if (si_pi->vddc_phase_shed_control) { | |
5087 | ret = si_populate_phase_shedding_value(rdev, | |
5088 | &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, | |
5089 | pl->vddc, | |
5090 | pl->sclk, | |
5091 | pl->mclk, | |
5092 | &level->vddc); | |
5093 | if (ret) | |
5094 | return ret; | |
5095 | } | |
5096 | ||
5097 | level->MaxPoweredUpCU = si_pi->max_cu; | |
5098 | ||
5099 | ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); | |
5100 | ||
5101 | return ret; | |
5102 | } | |
5103 | ||
5104 | static int si_populate_smc_t(struct radeon_device *rdev, | |
5105 | struct radeon_ps *radeon_state, | |
5106 | SISLANDS_SMC_SWSTATE *smc_state) | |
5107 | { | |
5108 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
5109 | struct ni_ps *state = ni_get_ps(radeon_state); | |
5110 | u32 a_t; | |
5111 | u32 t_l, t_h; | |
5112 | u32 high_bsp; | |
5113 | int i, ret; | |
5114 | ||
5115 | if (state->performance_level_count >= 9) | |
5116 | return -EINVAL; | |
5117 | ||
5118 | if (state->performance_level_count < 2) { | |
5119 | a_t = CG_R(0xffff) | CG_L(0); | |
5120 | smc_state->levels[0].aT = cpu_to_be32(a_t); | |
5121 | return 0; | |
5122 | } | |
5123 | ||
5124 | smc_state->levels[0].aT = cpu_to_be32(0); | |
5125 | ||
5126 | for (i = 0; i <= state->performance_level_count - 2; i++) { | |
5127 | ret = r600_calculate_at( | |
5128 | (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), | |
5129 | 100 * R600_AH_DFLT, | |
5130 | state->performance_levels[i + 1].sclk, | |
5131 | state->performance_levels[i].sclk, | |
5132 | &t_l, | |
5133 | &t_h); | |
5134 | ||
5135 | if (ret) { | |
5136 | t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; | |
5137 | t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; | |
5138 | } | |
5139 | ||
5140 | a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; | |
5141 | a_t |= CG_R(t_l * pi->bsp / 20000); | |
5142 | smc_state->levels[i].aT = cpu_to_be32(a_t); | |
5143 | ||
5144 | high_bsp = (i == state->performance_level_count - 2) ? | |
5145 | pi->pbsp : pi->bsp; | |
5146 | a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); | |
5147 | smc_state->levels[i + 1].aT = cpu_to_be32(a_t); | |
5148 | } | |
5149 | ||
5150 | return 0; | |
5151 | } | |
5152 | ||
5153 | static int si_disable_ulv(struct radeon_device *rdev) | |
5154 | { | |
5155 | struct si_power_info *si_pi = si_get_pi(rdev); | |
5156 | struct si_ulv_param *ulv = &si_pi->ulv; | |
5157 | ||
5158 | if (ulv->supported) | |
5159 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? | |
5160 | 0 : -EINVAL; | |
5161 | ||
5162 | return 0; | |
5163 | } | |
5164 | ||
5165 | static bool si_is_state_ulv_compatible(struct radeon_device *rdev, | |
5166 | struct radeon_ps *radeon_state) | |
5167 | { | |
5168 | const struct si_power_info *si_pi = si_get_pi(rdev); | |
5169 | const struct si_ulv_param *ulv = &si_pi->ulv; | |
5170 | const struct ni_ps *state = ni_get_ps(radeon_state); | |
5171 | int i; | |
5172 | ||
5173 | if (state->performance_levels[0].mclk != ulv->pl.mclk) | |
5174 | return false; | |
5175 | ||
5176 | /* XXX validate against display requirements! */ | |
5177 | ||
5178 | for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { | |
5179 | if (rdev->clock.current_dispclk <= | |
5180 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { | |
5181 | if (ulv->pl.vddc < | |
5182 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) | |
5183 | return false; | |
5184 | } | |
5185 | } | |
5186 | ||
5187 | if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) | |
5188 | return false; | |
5189 | ||
5190 | return true; | |
5191 | } | |
5192 | ||
5193 | static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, | |
5194 | struct radeon_ps *radeon_new_state) | |
5195 | { | |
5196 | const struct si_power_info *si_pi = si_get_pi(rdev); | |
5197 | const struct si_ulv_param *ulv = &si_pi->ulv; | |
5198 | ||
5199 | if (ulv->supported) { | |
5200 | if (si_is_state_ulv_compatible(rdev, radeon_new_state)) | |
5201 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? | |
5202 | 0 : -EINVAL; | |
5203 | } | |
5204 | return 0; | |
5205 | } | |
5206 | ||
5207 | static int si_convert_power_state_to_smc(struct radeon_device *rdev, | |
5208 | struct radeon_ps *radeon_state, | |
5209 | SISLANDS_SMC_SWSTATE *smc_state) | |
5210 | { | |
5211 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
5212 | struct ni_power_info *ni_pi = ni_get_pi(rdev); | |
5213 | struct si_power_info *si_pi = si_get_pi(rdev); | |
5214 | struct ni_ps *state = ni_get_ps(radeon_state); | |
5215 | int i, ret; | |
5216 | u32 threshold; | |
5217 | u32 sclk_in_sr = 1350; /* ??? */ | |
5218 | ||
5219 | if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) | |
5220 | return -EINVAL; | |
5221 | ||
5222 | threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; | |
5223 | ||
5224 | if (radeon_state->vclk && radeon_state->dclk) { | |
5225 | eg_pi->uvd_enabled = true; | |
5226 | if (eg_pi->smu_uvd_hs) | |
5227 | smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; | |
5228 | } else { | |
5229 | eg_pi->uvd_enabled = false; | |
5230 | } | |
5231 | ||
5232 | if (state->dc_compatible) | |
5233 | smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; | |
5234 | ||
5235 | smc_state->levelCount = 0; | |
5236 | for (i = 0; i < state->performance_level_count; i++) { | |
5237 | if (eg_pi->sclk_deep_sleep) { | |
5238 | if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { | |
5239 | if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) | |
5240 | smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; | |
5241 | else | |
5242 | smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; | |
5243 | } | |
5244 | } | |
5245 | ||
5246 | ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], | |
5247 | &smc_state->levels[i]); | |
5248 | smc_state->levels[i].arbRefreshState = | |
5249 | (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); | |
5250 | ||
5251 | if (ret) | |
5252 | return ret; | |
5253 | ||
5254 | if (ni_pi->enable_power_containment) | |
5255 | smc_state->levels[i].displayWatermark = | |
5256 | (state->performance_levels[i].sclk < threshold) ? | |
5257 | PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; | |
5258 | else | |
5259 | smc_state->levels[i].displayWatermark = (i < 2) ? | |
5260 | PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; | |
5261 | ||
5262 | if (eg_pi->dynamic_ac_timing) | |
5263 | smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; | |
5264 | else | |
5265 | smc_state->levels[i].ACIndex = 0; | |
5266 | ||
5267 | smc_state->levelCount++; | |
5268 | } | |
5269 | ||
5270 | si_write_smc_soft_register(rdev, | |
5271 | SI_SMC_SOFT_REGISTER_watermark_threshold, | |
5272 | threshold / 512); | |
5273 | ||
5274 | si_populate_smc_sp(rdev, radeon_state, smc_state); | |
5275 | ||
5276 | ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); | |
5277 | if (ret) | |
5278 | ni_pi->enable_power_containment = false; | |
5279 | ||
5280 | ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); | |
3cf8bb1a | 5281 | if (ret) |
a9e61410 AD |
5282 | ni_pi->enable_sq_ramping = false; |
5283 | ||
5284 | return si_populate_smc_t(rdev, radeon_state, smc_state); | |
5285 | } | |
5286 | ||
5287 | static int si_upload_sw_state(struct radeon_device *rdev, | |
5288 | struct radeon_ps *radeon_new_state) | |
5289 | { | |
5290 | struct si_power_info *si_pi = si_get_pi(rdev); | |
5291 | struct ni_ps *new_state = ni_get_ps(radeon_new_state); | |
5292 | int ret; | |
5293 | u32 address = si_pi->state_table_start + | |
5294 | offsetof(SISLANDS_SMC_STATETABLE, driverState); | |
5295 | u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + | |
5296 | ((new_state->performance_level_count - 1) * | |
5297 | sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); | |
5298 | SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; | |
5299 | ||
5300 | memset(smc_state, 0, state_size); | |
5301 | ||
5302 | ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); | |
5303 | if (ret) | |
5304 | return ret; | |
5305 | ||
5306 | ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, | |
5307 | state_size, si_pi->sram_end); | |
5308 | ||
5309 | return ret; | |
5310 | } | |
5311 | ||
5312 | static int si_upload_ulv_state(struct radeon_device *rdev) | |
5313 | { | |
5314 | struct si_power_info *si_pi = si_get_pi(rdev); | |
5315 | struct si_ulv_param *ulv = &si_pi->ulv; | |
5316 | int ret = 0; | |
5317 | ||
5318 | if (ulv->supported && ulv->pl.vddc) { | |
5319 | u32 address = si_pi->state_table_start + | |
5320 | offsetof(SISLANDS_SMC_STATETABLE, ULVState); | |
5321 | SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; | |
5322 | u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); | |
5323 | ||
5324 | memset(smc_state, 0, state_size); | |
5325 | ||
5326 | ret = si_populate_ulv_state(rdev, smc_state); | |
5327 | if (!ret) | |
5328 | ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, | |
5329 | state_size, si_pi->sram_end); | |
5330 | } | |
5331 | ||
5332 | return ret; | |
5333 | } | |
5334 | ||
5335 | static int si_upload_smc_data(struct radeon_device *rdev) | |
5336 | { | |
5337 | struct radeon_crtc *radeon_crtc = NULL; | |
5338 | int i; | |
5339 | ||
5340 | if (rdev->pm.dpm.new_active_crtc_count == 0) | |
5341 | return 0; | |
5342 | ||
5343 | for (i = 0; i < rdev->num_crtc; i++) { | |
5344 | if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { | |
5345 | radeon_crtc = rdev->mode_info.crtcs[i]; | |
5346 | break; | |
5347 | } | |
5348 | } | |
5349 | ||
5350 | if (radeon_crtc == NULL) | |
5351 | return 0; | |
5352 | ||
5353 | if (radeon_crtc->line_time <= 0) | |
5354 | return 0; | |
5355 | ||
5356 | if (si_write_smc_soft_register(rdev, | |
5357 | SI_SMC_SOFT_REGISTER_crtc_index, | |
5358 | radeon_crtc->crtc_id) != PPSMC_Result_OK) | |
5359 | return 0; | |
5360 | ||
5361 | if (si_write_smc_soft_register(rdev, | |
5362 | SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, | |
5363 | radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) | |
5364 | return 0; | |
5365 | ||
5366 | if (si_write_smc_soft_register(rdev, | |
5367 | SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, | |
5368 | radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) | |
5369 | return 0; | |
5370 | ||
5371 | return 0; | |
5372 | } | |
5373 | ||
5374 | static int si_set_mc_special_registers(struct radeon_device *rdev, | |
5375 | struct si_mc_reg_table *table) | |
5376 | { | |
5377 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
5378 | u8 i, j, k; | |
5379 | u32 temp_reg; | |
5380 | ||
5381 | for (i = 0, j = table->last; i < table->last; i++) { | |
5382 | if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) | |
5383 | return -EINVAL; | |
5384 | switch (table->mc_reg_address[i].s1 << 2) { | |
5385 | case MC_SEQ_MISC1: | |
5386 | temp_reg = RREG32(MC_PMG_CMD_EMRS); | |
5387 | table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; | |
5388 | table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; | |
5389 | for (k = 0; k < table->num_entries; k++) | |
5390 | table->mc_reg_table_entry[k].mc_data[j] = | |
5391 | ((temp_reg & 0xffff0000)) | | |
5392 | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); | |
5393 | j++; | |
5394 | if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) | |
5395 | return -EINVAL; | |
5396 | ||
5397 | temp_reg = RREG32(MC_PMG_CMD_MRS); | |
5398 | table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; | |
5399 | table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; | |
5400 | for (k = 0; k < table->num_entries; k++) { | |
5401 | table->mc_reg_table_entry[k].mc_data[j] = | |
5402 | (temp_reg & 0xffff0000) | | |
5403 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); | |
5404 | if (!pi->mem_gddr5) | |
5405 | table->mc_reg_table_entry[k].mc_data[j] |= 0x100; | |
5406 | } | |
5407 | j++; | |
5fd9c581 | 5408 | if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) |
a9e61410 AD |
5409 | return -EINVAL; |
5410 | ||
5411 | if (!pi->mem_gddr5) { | |
5412 | table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; | |
5413 | table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; | |
5414 | for (k = 0; k < table->num_entries; k++) | |
5415 | table->mc_reg_table_entry[k].mc_data[j] = | |
5416 | (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; | |
5417 | j++; | |
5fd9c581 | 5418 | if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) |
a9e61410 AD |
5419 | return -EINVAL; |
5420 | } | |
5421 | break; | |
5422 | case MC_SEQ_RESERVE_M: | |
5423 | temp_reg = RREG32(MC_PMG_CMD_MRS1); | |
5424 | table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; | |
5425 | table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; | |
5426 | for(k = 0; k < table->num_entries; k++) | |
5427 | table->mc_reg_table_entry[k].mc_data[j] = | |
5428 | (temp_reg & 0xffff0000) | | |
5429 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); | |
5430 | j++; | |
5fd9c581 | 5431 | if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) |
a9e61410 AD |
5432 | return -EINVAL; |
5433 | break; | |
5434 | default: | |
5435 | break; | |
5436 | } | |
5437 | } | |
5438 | ||
5439 | table->last = j; | |
5440 | ||
5441 | return 0; | |
5442 | } | |
5443 | ||
5444 | static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) | |
5445 | { | |
5446 | bool result = true; | |
5447 | ||
5448 | switch (in_reg) { | |
5449 | case MC_SEQ_RAS_TIMING >> 2: | |
5450 | *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; | |
5451 | break; | |
3cf8bb1a | 5452 | case MC_SEQ_CAS_TIMING >> 2: |
a9e61410 AD |
5453 | *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; |
5454 | break; | |
3cf8bb1a | 5455 | case MC_SEQ_MISC_TIMING >> 2: |
a9e61410 AD |
5456 | *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; |
5457 | break; | |
3cf8bb1a | 5458 | case MC_SEQ_MISC_TIMING2 >> 2: |
a9e61410 AD |
5459 | *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; |
5460 | break; | |
3cf8bb1a | 5461 | case MC_SEQ_RD_CTL_D0 >> 2: |
a9e61410 AD |
5462 | *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; |
5463 | break; | |
3cf8bb1a | 5464 | case MC_SEQ_RD_CTL_D1 >> 2: |
a9e61410 AD |
5465 | *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; |
5466 | break; | |
3cf8bb1a | 5467 | case MC_SEQ_WR_CTL_D0 >> 2: |
a9e61410 AD |
5468 | *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; |
5469 | break; | |
3cf8bb1a | 5470 | case MC_SEQ_WR_CTL_D1 >> 2: |
a9e61410 AD |
5471 | *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; |
5472 | break; | |
3cf8bb1a | 5473 | case MC_PMG_CMD_EMRS >> 2: |
a9e61410 AD |
5474 | *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; |
5475 | break; | |
3cf8bb1a | 5476 | case MC_PMG_CMD_MRS >> 2: |
a9e61410 AD |
5477 | *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; |
5478 | break; | |
3cf8bb1a | 5479 | case MC_PMG_CMD_MRS1 >> 2: |
a9e61410 AD |
5480 | *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; |
5481 | break; | |
3cf8bb1a | 5482 | case MC_SEQ_PMG_TIMING >> 2: |
a9e61410 AD |
5483 | *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; |
5484 | break; | |
3cf8bb1a | 5485 | case MC_PMG_CMD_MRS2 >> 2: |
a9e61410 AD |
5486 | *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; |
5487 | break; | |
3cf8bb1a | 5488 | case MC_SEQ_WR_CTL_2 >> 2: |
a9e61410 AD |
5489 | *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; |
5490 | break; | |
3cf8bb1a | 5491 | default: |
a9e61410 AD |
5492 | result = false; |
5493 | break; | |
5494 | } | |
5495 | ||
5496 | return result; | |
5497 | } | |
5498 | ||
5499 | static void si_set_valid_flag(struct si_mc_reg_table *table) | |
5500 | { | |
5501 | u8 i, j; | |
5502 | ||
5503 | for (i = 0; i < table->last; i++) { | |
5504 | for (j = 1; j < table->num_entries; j++) { | |
5505 | if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { | |
5506 | table->valid_flag |= 1 << i; | |
5507 | break; | |
5508 | } | |
5509 | } | |
5510 | } | |
5511 | } | |
5512 | ||
5513 | static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) | |
5514 | { | |
5515 | u32 i; | |
5516 | u16 address; | |
5517 | ||
5518 | for (i = 0; i < table->last; i++) | |
5519 | table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? | |
5520 | address : table->mc_reg_address[i].s1; | |
5521 | ||
5522 | } | |
5523 | ||
5524 | static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, | |
5525 | struct si_mc_reg_table *si_table) | |
5526 | { | |
5527 | u8 i, j; | |
5528 | ||
5529 | if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) | |
5530 | return -EINVAL; | |
5531 | if (table->num_entries > MAX_AC_TIMING_ENTRIES) | |
5532 | return -EINVAL; | |
5533 | ||
5534 | for (i = 0; i < table->last; i++) | |
5535 | si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; | |
5536 | si_table->last = table->last; | |
5537 | ||
5538 | for (i = 0; i < table->num_entries; i++) { | |
5539 | si_table->mc_reg_table_entry[i].mclk_max = | |
5540 | table->mc_reg_table_entry[i].mclk_max; | |
5541 | for (j = 0; j < table->last; j++) { | |
5542 | si_table->mc_reg_table_entry[i].mc_data[j] = | |
5543 | table->mc_reg_table_entry[i].mc_data[j]; | |
5544 | } | |
5545 | } | |
5546 | si_table->num_entries = table->num_entries; | |
5547 | ||
5548 | return 0; | |
5549 | } | |
5550 | ||
5551 | static int si_initialize_mc_reg_table(struct radeon_device *rdev) | |
5552 | { | |
5553 | struct si_power_info *si_pi = si_get_pi(rdev); | |
5554 | struct atom_mc_reg_table *table; | |
5555 | struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; | |
5556 | u8 module_index = rv770_get_memory_module_index(rdev); | |
5557 | int ret; | |
5558 | ||
5559 | table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); | |
5560 | if (!table) | |
5561 | return -ENOMEM; | |
5562 | ||
5563 | WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); | |
5564 | WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); | |
5565 | WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); | |
5566 | WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); | |
5567 | WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); | |
5568 | WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); | |
5569 | WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); | |
5570 | WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); | |
5571 | WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); | |
5572 | WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); | |
5573 | WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); | |
5574 | WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); | |
5575 | WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); | |
5576 | WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); | |
5577 | ||
3cf8bb1a JG |
5578 | ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); |
5579 | if (ret) | |
5580 | goto init_mc_done; | |
a9e61410 | 5581 | |
3cf8bb1a JG |
5582 | ret = si_copy_vbios_mc_reg_table(table, si_table); |
5583 | if (ret) | |
5584 | goto init_mc_done; | |
a9e61410 AD |
5585 | |
5586 | si_set_s0_mc_reg_index(si_table); | |
5587 | ||
5588 | ret = si_set_mc_special_registers(rdev, si_table); | |
3cf8bb1a JG |
5589 | if (ret) |
5590 | goto init_mc_done; | |
a9e61410 AD |
5591 | |
5592 | si_set_valid_flag(si_table); | |
5593 | ||
5594 | init_mc_done: | |
5595 | kfree(table); | |
5596 | ||
5597 | return ret; | |
5598 | ||
5599 | } | |
5600 | ||
5601 | static void si_populate_mc_reg_addresses(struct radeon_device *rdev, | |
5602 | SMC_SIslands_MCRegisters *mc_reg_table) | |
5603 | { | |
5604 | struct si_power_info *si_pi = si_get_pi(rdev); | |
5605 | u32 i, j; | |
5606 | ||
5607 | for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { | |
5608 | if (si_pi->mc_reg_table.valid_flag & (1 << j)) { | |
407b6dfd | 5609 | if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) |
a9e61410 AD |
5610 | break; |
5611 | mc_reg_table->address[i].s0 = | |
5612 | cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); | |
5613 | mc_reg_table->address[i].s1 = | |
5614 | cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); | |
5615 | i++; | |
5616 | } | |
5617 | } | |
5618 | mc_reg_table->last = (u8)i; | |
5619 | } | |
5620 | ||
5621 | static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, | |
5622 | SMC_SIslands_MCRegisterSet *data, | |
5623 | u32 num_entries, u32 valid_flag) | |
5624 | { | |
5625 | u32 i, j; | |
5626 | ||
5627 | for(i = 0, j = 0; j < num_entries; j++) { | |
5628 | if (valid_flag & (1 << j)) { | |
5629 | data->value[i] = cpu_to_be32(entry->mc_data[j]); | |
5630 | i++; | |
5631 | } | |
5632 | } | |
5633 | } | |
5634 | ||
5635 | static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, | |
5636 | struct rv7xx_pl *pl, | |
5637 | SMC_SIslands_MCRegisterSet *mc_reg_table_data) | |
5638 | { | |
5639 | struct si_power_info *si_pi = si_get_pi(rdev); | |
5640 | u32 i = 0; | |
5641 | ||
5642 | for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { | |
5643 | if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) | |
5644 | break; | |
5645 | } | |
5646 | ||
5647 | if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) | |
5648 | --i; | |
5649 | ||
5650 | si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], | |
5651 | mc_reg_table_data, si_pi->mc_reg_table.last, | |
5652 | si_pi->mc_reg_table.valid_flag); | |
5653 | } | |
5654 | ||
5655 | static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, | |
5656 | struct radeon_ps *radeon_state, | |
5657 | SMC_SIslands_MCRegisters *mc_reg_table) | |
5658 | { | |
5659 | struct ni_ps *state = ni_get_ps(radeon_state); | |
5660 | int i; | |
5661 | ||
5662 | for (i = 0; i < state->performance_level_count; i++) { | |
5663 | si_convert_mc_reg_table_entry_to_smc(rdev, | |
5664 | &state->performance_levels[i], | |
5665 | &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); | |
5666 | } | |
5667 | } | |
5668 | ||
5669 | static int si_populate_mc_reg_table(struct radeon_device *rdev, | |
5670 | struct radeon_ps *radeon_boot_state) | |
5671 | { | |
5672 | struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); | |
5673 | struct si_power_info *si_pi = si_get_pi(rdev); | |
5674 | struct si_ulv_param *ulv = &si_pi->ulv; | |
5675 | SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; | |
5676 | ||
5677 | memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); | |
5678 | ||
5679 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); | |
5680 | ||
5681 | si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); | |
5682 | ||
5683 | si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], | |
5684 | &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); | |
5685 | ||
5686 | si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], | |
5687 | &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], | |
5688 | si_pi->mc_reg_table.last, | |
5689 | si_pi->mc_reg_table.valid_flag); | |
5690 | ||
5691 | if (ulv->supported && ulv->pl.vddc != 0) | |
5692 | si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, | |
5693 | &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); | |
5694 | else | |
5695 | si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], | |
5696 | &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], | |
5697 | si_pi->mc_reg_table.last, | |
5698 | si_pi->mc_reg_table.valid_flag); | |
5699 | ||
5700 | si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); | |
5701 | ||
5702 | return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, | |
5703 | (u8 *)smc_mc_reg_table, | |
5704 | sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); | |
5705 | } | |
5706 | ||
5707 | static int si_upload_mc_reg_table(struct radeon_device *rdev, | |
5708 | struct radeon_ps *radeon_new_state) | |
5709 | { | |
5710 | struct ni_ps *new_state = ni_get_ps(radeon_new_state); | |
5711 | struct si_power_info *si_pi = si_get_pi(rdev); | |
5712 | u32 address = si_pi->mc_reg_table_start + | |
5713 | offsetof(SMC_SIslands_MCRegisters, | |
5714 | data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); | |
5715 | SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; | |
5716 | ||
5717 | memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); | |
5718 | ||
5719 | si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); | |
5720 | ||
5721 | ||
5722 | return si_copy_bytes_to_smc(rdev, address, | |
5723 | (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], | |
5724 | sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, | |
5725 | si_pi->sram_end); | |
5726 | ||
5727 | } | |
5728 | ||
5729 | static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) | |
5730 | { | |
3cf8bb1a JG |
5731 | if (enable) |
5732 | WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); | |
5733 | else | |
5734 | WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); | |
a9e61410 AD |
5735 | } |
5736 | ||
5737 | static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, | |
5738 | struct radeon_ps *radeon_state) | |
5739 | { | |
5740 | struct ni_ps *state = ni_get_ps(radeon_state); | |
5741 | int i; | |
5742 | u16 pcie_speed, max_speed = 0; | |
5743 | ||
5744 | for (i = 0; i < state->performance_level_count; i++) { | |
5745 | pcie_speed = state->performance_levels[i].pcie_gen; | |
5746 | if (max_speed < pcie_speed) | |
5747 | max_speed = pcie_speed; | |
5748 | } | |
5749 | return max_speed; | |
5750 | } | |
5751 | ||
5752 | static u16 si_get_current_pcie_speed(struct radeon_device *rdev) | |
5753 | { | |
5754 | u32 speed_cntl; | |
5755 | ||
5756 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; | |
5757 | speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; | |
5758 | ||
5759 | return (u16)speed_cntl; | |
5760 | } | |
5761 | ||
5762 | static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, | |
5763 | struct radeon_ps *radeon_new_state, | |
5764 | struct radeon_ps *radeon_current_state) | |
5765 | { | |
5766 | struct si_power_info *si_pi = si_get_pi(rdev); | |
5767 | enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); | |
5768 | enum radeon_pcie_gen current_link_speed; | |
5769 | ||
5770 | if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) | |
5771 | current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); | |
5772 | else | |
5773 | current_link_speed = si_pi->force_pcie_gen; | |
5774 | ||
5775 | si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; | |
5776 | si_pi->pspp_notify_required = false; | |
5777 | if (target_link_speed > current_link_speed) { | |
5778 | switch (target_link_speed) { | |
5779 | #if defined(CONFIG_ACPI) | |
5780 | case RADEON_PCIE_GEN3: | |
5781 | if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) | |
5782 | break; | |
5783 | si_pi->force_pcie_gen = RADEON_PCIE_GEN2; | |
5784 | if (current_link_speed == RADEON_PCIE_GEN2) | |
5785 | break; | |
5786 | case RADEON_PCIE_GEN2: | |
5787 | if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) | |
5788 | break; | |
5789 | #endif | |
5790 | default: | |
5791 | si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); | |
5792 | break; | |
5793 | } | |
5794 | } else { | |
5795 | if (target_link_speed < current_link_speed) | |
5796 | si_pi->pspp_notify_required = true; | |
5797 | } | |
5798 | } | |
5799 | ||
5800 | static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, | |
5801 | struct radeon_ps *radeon_new_state, | |
5802 | struct radeon_ps *radeon_current_state) | |
5803 | { | |
5804 | struct si_power_info *si_pi = si_get_pi(rdev); | |
5805 | enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); | |
5806 | u8 request; | |
5807 | ||
5808 | if (si_pi->pspp_notify_required) { | |
5809 | if (target_link_speed == RADEON_PCIE_GEN3) | |
5810 | request = PCIE_PERF_REQ_PECI_GEN3; | |
5811 | else if (target_link_speed == RADEON_PCIE_GEN2) | |
5812 | request = PCIE_PERF_REQ_PECI_GEN2; | |
5813 | else | |
5814 | request = PCIE_PERF_REQ_PECI_GEN1; | |
5815 | ||
5816 | if ((request == PCIE_PERF_REQ_PECI_GEN1) && | |
5817 | (si_get_current_pcie_speed(rdev) > 0)) | |
5818 | return; | |
5819 | ||
5820 | #if defined(CONFIG_ACPI) | |
5821 | radeon_acpi_pcie_performance_request(rdev, request, false); | |
5822 | #endif | |
5823 | } | |
5824 | } | |
5825 | ||
5826 | #if 0 | |
5827 | static int si_ds_request(struct radeon_device *rdev, | |
5828 | bool ds_status_on, u32 count_write) | |
5829 | { | |
5830 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
5831 | ||
5832 | if (eg_pi->sclk_deep_sleep) { | |
5833 | if (ds_status_on) | |
5834 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == | |
5835 | PPSMC_Result_OK) ? | |
5836 | 0 : -EINVAL; | |
5837 | else | |
5838 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == | |
5839 | PPSMC_Result_OK) ? 0 : -EINVAL; | |
5840 | } | |
5841 | return 0; | |
5842 | } | |
5843 | #endif | |
5844 | ||
5845 | static void si_set_max_cu_value(struct radeon_device *rdev) | |
5846 | { | |
5847 | struct si_power_info *si_pi = si_get_pi(rdev); | |
5848 | ||
5849 | if (rdev->family == CHIP_VERDE) { | |
5850 | switch (rdev->pdev->device) { | |
5851 | case 0x6820: | |
5852 | case 0x6825: | |
5853 | case 0x6821: | |
5854 | case 0x6823: | |
5855 | case 0x6827: | |
5856 | si_pi->max_cu = 10; | |
5857 | break; | |
5858 | case 0x682D: | |
5859 | case 0x6824: | |
5860 | case 0x682F: | |
5861 | case 0x6826: | |
5862 | si_pi->max_cu = 8; | |
5863 | break; | |
5864 | case 0x6828: | |
5865 | case 0x6830: | |
5866 | case 0x6831: | |
5867 | case 0x6838: | |
5868 | case 0x6839: | |
5869 | case 0x683D: | |
5870 | si_pi->max_cu = 10; | |
5871 | break; | |
5872 | case 0x683B: | |
5873 | case 0x683F: | |
5874 | case 0x6829: | |
5875 | si_pi->max_cu = 8; | |
5876 | break; | |
5877 | default: | |
5878 | si_pi->max_cu = 0; | |
5879 | break; | |
5880 | } | |
5881 | } else { | |
5882 | si_pi->max_cu = 0; | |
5883 | } | |
5884 | } | |
5885 | ||
5886 | static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, | |
5887 | struct radeon_clock_voltage_dependency_table *table) | |
5888 | { | |
5889 | u32 i; | |
5890 | int j; | |
5891 | u16 leakage_voltage; | |
5892 | ||
5893 | if (table) { | |
5894 | for (i = 0; i < table->count; i++) { | |
5895 | switch (si_get_leakage_voltage_from_leakage_index(rdev, | |
5896 | table->entries[i].v, | |
5897 | &leakage_voltage)) { | |
5898 | case 0: | |
5899 | table->entries[i].v = leakage_voltage; | |
5900 | break; | |
5901 | case -EAGAIN: | |
5902 | return -EINVAL; | |
5903 | case -EINVAL: | |
5904 | default: | |
5905 | break; | |
5906 | } | |
5907 | } | |
5908 | ||
5909 | for (j = (table->count - 2); j >= 0; j--) { | |
5910 | table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? | |
5911 | table->entries[j].v : table->entries[j + 1].v; | |
5912 | } | |
5913 | } | |
5914 | return 0; | |
5915 | } | |
5916 | ||
5917 | static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) | |
5918 | { | |
5919 | int ret = 0; | |
5920 | ||
5921 | ret = si_patch_single_dependency_table_based_on_leakage(rdev, | |
5922 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); | |
5923 | ret = si_patch_single_dependency_table_based_on_leakage(rdev, | |
5924 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); | |
5925 | ret = si_patch_single_dependency_table_based_on_leakage(rdev, | |
5926 | &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); | |
5927 | return ret; | |
5928 | } | |
5929 | ||
5930 | static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, | |
5931 | struct radeon_ps *radeon_new_state, | |
5932 | struct radeon_ps *radeon_current_state) | |
5933 | { | |
5934 | u32 lane_width; | |
5935 | u32 new_lane_width = | |
5936 | (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; | |
5937 | u32 current_lane_width = | |
5938 | (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; | |
5939 | ||
5940 | if (new_lane_width != current_lane_width) { | |
5941 | radeon_set_pcie_lanes(rdev, new_lane_width); | |
5942 | lane_width = radeon_get_pcie_lanes(rdev); | |
5943 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); | |
5944 | } | |
5945 | } | |
5946 | ||
11586cf0 AD |
5947 | static void si_set_vce_clock(struct radeon_device *rdev, |
5948 | struct radeon_ps *new_rps, | |
5949 | struct radeon_ps *old_rps) | |
5950 | { | |
5951 | if ((old_rps->evclk != new_rps->evclk) || | |
84bcd469 AD |
5952 | (old_rps->ecclk != new_rps->ecclk)) { |
5953 | /* turn the clocks on when encoding, off otherwise */ | |
5954 | if (new_rps->evclk || new_rps->ecclk) | |
5955 | vce_v1_0_enable_mgcg(rdev, false); | |
5956 | else | |
5957 | vce_v1_0_enable_mgcg(rdev, true); | |
11586cf0 | 5958 | radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); |
84bcd469 | 5959 | } |
11586cf0 AD |
5960 | } |
5961 | ||
a9e61410 AD |
5962 | void si_dpm_setup_asic(struct radeon_device *rdev) |
5963 | { | |
6c7bccea AD |
5964 | int r; |
5965 | ||
5966 | r = si_mc_load_microcode(rdev); | |
5967 | if (r) | |
5968 | DRM_ERROR("Failed to load MC firmware!\n"); | |
a9e61410 AD |
5969 | rv770_get_memory_type(rdev); |
5970 | si_read_clock_registers(rdev); | |
5971 | si_enable_acpi_power_management(rdev); | |
5972 | } | |
5973 | ||
2271e2e2 AD |
5974 | static int si_thermal_enable_alert(struct radeon_device *rdev, |
5975 | bool enable) | |
5976 | { | |
5977 | u32 thermal_int = RREG32(CG_THERMAL_INT); | |
5978 | ||
5979 | if (enable) { | |
5980 | PPSMC_Result result; | |
5981 | ||
39471ad3 AD |
5982 | thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); |
5983 | WREG32(CG_THERMAL_INT, thermal_int); | |
5984 | rdev->irq.dpm_thermal = false; | |
2271e2e2 AD |
5985 | result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); |
5986 | if (result != PPSMC_Result_OK) { | |
5987 | DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); | |
5988 | return -EINVAL; | |
5989 | } | |
5990 | } else { | |
39471ad3 AD |
5991 | thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; |
5992 | WREG32(CG_THERMAL_INT, thermal_int); | |
5993 | rdev->irq.dpm_thermal = true; | |
2271e2e2 AD |
5994 | } |
5995 | ||
2271e2e2 AD |
5996 | return 0; |
5997 | } | |
5998 | ||
5999 | static int si_thermal_set_temperature_range(struct radeon_device *rdev, | |
6000 | int min_temp, int max_temp) | |
a9e61410 AD |
6001 | { |
6002 | int low_temp = 0 * 1000; | |
6003 | int high_temp = 255 * 1000; | |
6004 | ||
6005 | if (low_temp < min_temp) | |
6006 | low_temp = min_temp; | |
6007 | if (high_temp > max_temp) | |
6008 | high_temp = max_temp; | |
6009 | if (high_temp < low_temp) { | |
6010 | DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); | |
6011 | return -EINVAL; | |
6012 | } | |
6013 | ||
6014 | WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); | |
6015 | WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); | |
6016 | WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); | |
6017 | ||
6018 | rdev->pm.dpm.thermal.min_temp = low_temp; | |
6019 | rdev->pm.dpm.thermal.max_temp = high_temp; | |
6020 | ||
6021 | return 0; | |
6022 | } | |
6023 | ||
39471ad3 AD |
6024 | static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) |
6025 | { | |
6026 | struct si_power_info *si_pi = si_get_pi(rdev); | |
6027 | u32 tmp; | |
6028 | ||
6029 | if (si_pi->fan_ctrl_is_in_default_mode) { | |
6030 | tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; | |
6031 | si_pi->fan_ctrl_default_mode = tmp; | |
6032 | tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; | |
6033 | si_pi->t_min = tmp; | |
6034 | si_pi->fan_ctrl_is_in_default_mode = false; | |
6035 | } | |
6036 | ||
6037 | tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; | |
6038 | tmp |= TMIN(0); | |
6039 | WREG32(CG_FDO_CTRL2, tmp); | |
6040 | ||
6554d9a0 | 6041 | tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; |
39471ad3 AD |
6042 | tmp |= FDO_PWM_MODE(mode); |
6043 | WREG32(CG_FDO_CTRL2, tmp); | |
6044 | } | |
6045 | ||
6046 | static int si_thermal_setup_fan_table(struct radeon_device *rdev) | |
6047 | { | |
6048 | struct si_power_info *si_pi = si_get_pi(rdev); | |
6049 | PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; | |
6050 | u32 duty100; | |
6051 | u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; | |
6052 | u16 fdo_min, slope1, slope2; | |
6053 | u32 reference_clock, tmp; | |
6054 | int ret; | |
6055 | u64 tmp64; | |
6056 | ||
6057 | if (!si_pi->fan_table_start) { | |
6058 | rdev->pm.dpm.fan.ucode_fan_control = false; | |
6059 | return 0; | |
6060 | } | |
6061 | ||
6062 | duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; | |
6063 | ||
6064 | if (duty100 == 0) { | |
6065 | rdev->pm.dpm.fan.ucode_fan_control = false; | |
6066 | return 0; | |
6067 | } | |
6068 | ||
6069 | tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; | |
6070 | do_div(tmp64, 10000); | |
6071 | fdo_min = (u16)tmp64; | |
6072 | ||
6073 | t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; | |
6074 | t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; | |
6075 | ||
6076 | pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; | |
6077 | pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; | |
6078 | ||
6079 | slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); | |
6080 | slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); | |
6081 | ||
47fd97ca OC |
6082 | fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); |
6083 | fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); | |
6084 | fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); | |
6085 | ||
39471ad3 AD |
6086 | fan_table.slope1 = cpu_to_be16(slope1); |
6087 | fan_table.slope2 = cpu_to_be16(slope2); | |
6088 | ||
6089 | fan_table.fdo_min = cpu_to_be16(fdo_min); | |
6090 | ||
6091 | fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); | |
6092 | ||
6093 | fan_table.hys_up = cpu_to_be16(1); | |
6094 | ||
6095 | fan_table.hys_slope = cpu_to_be16(1); | |
6096 | ||
6097 | fan_table.temp_resp_lim = cpu_to_be16(5); | |
6098 | ||
6099 | reference_clock = radeon_get_xclk(rdev); | |
6100 | ||
6101 | fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * | |
6102 | reference_clock) / 1600); | |
6103 | ||
6104 | fan_table.fdo_max = cpu_to_be16((u16)duty100); | |
6105 | ||
6106 | tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; | |
6107 | fan_table.temp_src = (uint8_t)tmp; | |
6108 | ||
6109 | ret = si_copy_bytes_to_smc(rdev, | |
6110 | si_pi->fan_table_start, | |
6111 | (u8 *)(&fan_table), | |
6112 | sizeof(fan_table), | |
6113 | si_pi->sram_end); | |
6114 | ||
6115 | if (ret) { | |
6116 | DRM_ERROR("Failed to load fan table to the SMC."); | |
6117 | rdev->pm.dpm.fan.ucode_fan_control = false; | |
6118 | } | |
6119 | ||
6120 | return 0; | |
6121 | } | |
6122 | ||
6123 | static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) | |
6124 | { | |
5e8150a6 | 6125 | struct si_power_info *si_pi = si_get_pi(rdev); |
39471ad3 AD |
6126 | PPSMC_Result ret; |
6127 | ||
6128 | ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); | |
5e8150a6 AD |
6129 | if (ret == PPSMC_Result_OK) { |
6130 | si_pi->fan_is_controlled_by_smc = true; | |
39471ad3 | 6131 | return 0; |
5e8150a6 | 6132 | } else { |
39471ad3 | 6133 | return -EINVAL; |
5e8150a6 | 6134 | } |
39471ad3 AD |
6135 | } |
6136 | ||
6137 | static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) | |
6138 | { | |
5e8150a6 | 6139 | struct si_power_info *si_pi = si_get_pi(rdev); |
39471ad3 AD |
6140 | PPSMC_Result ret; |
6141 | ||
6142 | ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); | |
5e8150a6 AD |
6143 | |
6144 | if (ret == PPSMC_Result_OK) { | |
6145 | si_pi->fan_is_controlled_by_smc = false; | |
39471ad3 | 6146 | return 0; |
5e8150a6 | 6147 | } else { |
39471ad3 | 6148 | return -EINVAL; |
5e8150a6 | 6149 | } |
39471ad3 AD |
6150 | } |
6151 | ||
5e8150a6 AD |
6152 | int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, |
6153 | u32 *speed) | |
39471ad3 AD |
6154 | { |
6155 | u32 duty, duty100; | |
6156 | u64 tmp64; | |
6157 | ||
6158 | if (rdev->pm.no_fan) | |
6159 | return -ENOENT; | |
6160 | ||
6161 | duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; | |
6162 | duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; | |
6163 | ||
6164 | if (duty100 == 0) | |
6165 | return -EINVAL; | |
6166 | ||
6167 | tmp64 = (u64)duty * 100; | |
6168 | do_div(tmp64, duty100); | |
6169 | *speed = (u32)tmp64; | |
6170 | ||
6171 | if (*speed > 100) | |
6172 | *speed = 100; | |
6173 | ||
6174 | return 0; | |
6175 | } | |
6176 | ||
5e8150a6 AD |
6177 | int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, |
6178 | u32 speed) | |
39471ad3 | 6179 | { |
47fd97ca | 6180 | struct si_power_info *si_pi = si_get_pi(rdev); |
39471ad3 AD |
6181 | u32 tmp; |
6182 | u32 duty, duty100; | |
6183 | u64 tmp64; | |
6184 | ||
6185 | if (rdev->pm.no_fan) | |
6186 | return -ENOENT; | |
6187 | ||
47fd97ca OC |
6188 | if (si_pi->fan_is_controlled_by_smc) |
6189 | return -EINVAL; | |
6190 | ||
39471ad3 AD |
6191 | if (speed > 100) |
6192 | return -EINVAL; | |
6193 | ||
39471ad3 AD |
6194 | duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; |
6195 | ||
6196 | if (duty100 == 0) | |
6197 | return -EINVAL; | |
6198 | ||
6199 | tmp64 = (u64)speed * duty100; | |
6200 | do_div(tmp64, 100); | |
6201 | duty = (u32)tmp64; | |
6202 | ||
6203 | tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; | |
6204 | tmp |= FDO_STATIC_DUTY(duty); | |
6205 | WREG32(CG_FDO_CTRL0, tmp); | |
6206 | ||
39471ad3 AD |
6207 | return 0; |
6208 | } | |
6209 | ||
5e8150a6 AD |
6210 | void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) |
6211 | { | |
6212 | if (mode) { | |
6213 | /* stop auto-manage */ | |
6214 | if (rdev->pm.dpm.fan.ucode_fan_control) | |
6215 | si_fan_ctrl_stop_smc_fan_control(rdev); | |
6216 | si_fan_ctrl_set_static_mode(rdev, mode); | |
6217 | } else { | |
6218 | /* restart auto-manage */ | |
6219 | if (rdev->pm.dpm.fan.ucode_fan_control) | |
6220 | si_thermal_start_smc_fan_control(rdev); | |
6221 | else | |
6222 | si_fan_ctrl_set_default_mode(rdev); | |
6223 | } | |
6224 | } | |
6225 | ||
6226 | u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) | |
6227 | { | |
6228 | struct si_power_info *si_pi = si_get_pi(rdev); | |
6229 | u32 tmp; | |
6230 | ||
6231 | if (si_pi->fan_is_controlled_by_smc) | |
6232 | return 0; | |
6233 | ||
6234 | tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; | |
6235 | return (tmp >> FDO_PWM_MODE_SHIFT); | |
6236 | } | |
6237 | ||
6238 | #if 0 | |
39471ad3 AD |
6239 | static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, |
6240 | u32 *speed) | |
6241 | { | |
6242 | u32 tach_period; | |
6243 | u32 xclk = radeon_get_xclk(rdev); | |
6244 | ||
6245 | if (rdev->pm.no_fan) | |
6246 | return -ENOENT; | |
6247 | ||
6248 | if (rdev->pm.fan_pulses_per_revolution == 0) | |
6249 | return -ENOENT; | |
6250 | ||
6251 | tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; | |
6252 | if (tach_period == 0) | |
6253 | return -ENOENT; | |
6254 | ||
6255 | *speed = 60 * xclk * 10000 / tach_period; | |
6256 | ||
6257 | return 0; | |
6258 | } | |
6259 | ||
6260 | static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, | |
6261 | u32 speed) | |
6262 | { | |
6263 | u32 tach_period, tmp; | |
6264 | u32 xclk = radeon_get_xclk(rdev); | |
6265 | ||
6266 | if (rdev->pm.no_fan) | |
6267 | return -ENOENT; | |
6268 | ||
6269 | if (rdev->pm.fan_pulses_per_revolution == 0) | |
6270 | return -ENOENT; | |
6271 | ||
6272 | if ((speed < rdev->pm.fan_min_rpm) || | |
6273 | (speed > rdev->pm.fan_max_rpm)) | |
6274 | return -EINVAL; | |
6275 | ||
6276 | if (rdev->pm.dpm.fan.ucode_fan_control) | |
6277 | si_fan_ctrl_stop_smc_fan_control(rdev); | |
6278 | ||
6279 | tach_period = 60 * xclk * 10000 / (8 * speed); | |
6280 | tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; | |
6281 | tmp |= TARGET_PERIOD(tach_period); | |
6282 | WREG32(CG_TACH_CTRL, tmp); | |
6283 | ||
6554d9a0 | 6284 | si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); |
39471ad3 AD |
6285 | |
6286 | return 0; | |
6287 | } | |
6288 | #endif | |
6289 | ||
6290 | static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) | |
6291 | { | |
6292 | struct si_power_info *si_pi = si_get_pi(rdev); | |
6293 | u32 tmp; | |
6294 | ||
6295 | if (!si_pi->fan_ctrl_is_in_default_mode) { | |
6296 | tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; | |
6297 | tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); | |
6298 | WREG32(CG_FDO_CTRL2, tmp); | |
6299 | ||
6554d9a0 | 6300 | tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; |
39471ad3 AD |
6301 | tmp |= TMIN(si_pi->t_min); |
6302 | WREG32(CG_FDO_CTRL2, tmp); | |
6303 | si_pi->fan_ctrl_is_in_default_mode = true; | |
6304 | } | |
6305 | } | |
6306 | ||
6307 | static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) | |
6308 | { | |
6309 | if (rdev->pm.dpm.fan.ucode_fan_control) { | |
6310 | si_fan_ctrl_start_smc_fan_control(rdev); | |
6311 | si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); | |
6312 | } | |
6313 | } | |
6314 | ||
6315 | static void si_thermal_initialize(struct radeon_device *rdev) | |
6316 | { | |
6317 | u32 tmp; | |
6318 | ||
6319 | if (rdev->pm.fan_pulses_per_revolution) { | |
6320 | tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; | |
6321 | tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); | |
6322 | WREG32(CG_TACH_CTRL, tmp); | |
6323 | } | |
6324 | ||
6325 | tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; | |
6326 | tmp |= TACH_PWM_RESP_RATE(0x28); | |
6327 | WREG32(CG_FDO_CTRL2, tmp); | |
6328 | } | |
6329 | ||
6330 | static int si_thermal_start_thermal_controller(struct radeon_device *rdev) | |
6331 | { | |
6332 | int ret; | |
6333 | ||
6334 | si_thermal_initialize(rdev); | |
6335 | ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); | |
6336 | if (ret) | |
6337 | return ret; | |
6338 | ret = si_thermal_enable_alert(rdev, true); | |
6339 | if (ret) | |
6340 | return ret; | |
6341 | if (rdev->pm.dpm.fan.ucode_fan_control) { | |
6342 | ret = si_halt_smc(rdev); | |
6343 | if (ret) | |
6344 | return ret; | |
6345 | ret = si_thermal_setup_fan_table(rdev); | |
6346 | if (ret) | |
6347 | return ret; | |
6348 | ret = si_resume_smc(rdev); | |
6349 | if (ret) | |
6350 | return ret; | |
6351 | si_thermal_start_smc_fan_control(rdev); | |
6352 | } | |
6353 | ||
6354 | return 0; | |
6355 | } | |
6356 | ||
6357 | static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) | |
6358 | { | |
6359 | if (!rdev->pm.no_fan) { | |
6360 | si_fan_ctrl_set_default_mode(rdev); | |
6361 | si_fan_ctrl_stop_smc_fan_control(rdev); | |
6362 | } | |
6363 | } | |
6364 | ||
a9e61410 AD |
6365 | int si_dpm_enable(struct radeon_device *rdev) |
6366 | { | |
6367 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
6368 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
636e2582 | 6369 | struct si_power_info *si_pi = si_get_pi(rdev); |
a9e61410 AD |
6370 | struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; |
6371 | int ret; | |
6372 | ||
6373 | if (si_is_smc_running(rdev)) | |
6374 | return -EINVAL; | |
636e2582 | 6375 | if (pi->voltage_control || si_pi->voltage_control_svi2) |
a9e61410 AD |
6376 | si_enable_voltage_control(rdev, true); |
6377 | if (pi->mvdd_control) | |
6378 | si_get_mvdd_configuration(rdev); | |
636e2582 | 6379 | if (pi->voltage_control || si_pi->voltage_control_svi2) { |
a9e61410 | 6380 | ret = si_construct_voltage_tables(rdev); |
2c48febb AD |
6381 | if (ret) { |
6382 | DRM_ERROR("si_construct_voltage_tables failed\n"); | |
a9e61410 | 6383 | return ret; |
2c48febb | 6384 | } |
a9e61410 AD |
6385 | } |
6386 | if (eg_pi->dynamic_ac_timing) { | |
6387 | ret = si_initialize_mc_reg_table(rdev); | |
6388 | if (ret) | |
6389 | eg_pi->dynamic_ac_timing = false; | |
6390 | } | |
6391 | if (pi->dynamic_ss) | |
6392 | si_enable_spread_spectrum(rdev, true); | |
6393 | if (pi->thermal_protection) | |
6394 | si_enable_thermal_protection(rdev, true); | |
6395 | si_setup_bsp(rdev); | |
6396 | si_program_git(rdev); | |
6397 | si_program_tp(rdev); | |
6398 | si_program_tpp(rdev); | |
6399 | si_program_sstp(rdev); | |
6400 | si_enable_display_gap(rdev); | |
6401 | si_program_vc(rdev); | |
6402 | ret = si_upload_firmware(rdev); | |
2c48febb AD |
6403 | if (ret) { |
6404 | DRM_ERROR("si_upload_firmware failed\n"); | |
a9e61410 | 6405 | return ret; |
2c48febb | 6406 | } |
a9e61410 | 6407 | ret = si_process_firmware_header(rdev); |
2c48febb AD |
6408 | if (ret) { |
6409 | DRM_ERROR("si_process_firmware_header failed\n"); | |
a9e61410 | 6410 | return ret; |
2c48febb | 6411 | } |
a9e61410 | 6412 | ret = si_initial_switch_from_arb_f0_to_f1(rdev); |
2c48febb AD |
6413 | if (ret) { |
6414 | DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); | |
a9e61410 | 6415 | return ret; |
2c48febb | 6416 | } |
a9e61410 | 6417 | ret = si_init_smc_table(rdev); |
2c48febb AD |
6418 | if (ret) { |
6419 | DRM_ERROR("si_init_smc_table failed\n"); | |
a9e61410 | 6420 | return ret; |
2c48febb | 6421 | } |
a9e61410 | 6422 | ret = si_init_smc_spll_table(rdev); |
2c48febb AD |
6423 | if (ret) { |
6424 | DRM_ERROR("si_init_smc_spll_table failed\n"); | |
a9e61410 | 6425 | return ret; |
2c48febb | 6426 | } |
a9e61410 | 6427 | ret = si_init_arb_table_index(rdev); |
2c48febb AD |
6428 | if (ret) { |
6429 | DRM_ERROR("si_init_arb_table_index failed\n"); | |
a9e61410 | 6430 | return ret; |
2c48febb | 6431 | } |
a9e61410 AD |
6432 | if (eg_pi->dynamic_ac_timing) { |
6433 | ret = si_populate_mc_reg_table(rdev, boot_ps); | |
2c48febb AD |
6434 | if (ret) { |
6435 | DRM_ERROR("si_populate_mc_reg_table failed\n"); | |
a9e61410 | 6436 | return ret; |
2c48febb | 6437 | } |
a9e61410 AD |
6438 | } |
6439 | ret = si_initialize_smc_cac_tables(rdev); | |
2c48febb AD |
6440 | if (ret) { |
6441 | DRM_ERROR("si_initialize_smc_cac_tables failed\n"); | |
a9e61410 | 6442 | return ret; |
2c48febb | 6443 | } |
a9e61410 | 6444 | ret = si_initialize_hardware_cac_manager(rdev); |
2c48febb AD |
6445 | if (ret) { |
6446 | DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); | |
a9e61410 | 6447 | return ret; |
2c48febb | 6448 | } |
a9e61410 | 6449 | ret = si_initialize_smc_dte_tables(rdev); |
2c48febb AD |
6450 | if (ret) { |
6451 | DRM_ERROR("si_initialize_smc_dte_tables failed\n"); | |
a9e61410 | 6452 | return ret; |
2c48febb | 6453 | } |
a9e61410 | 6454 | ret = si_populate_smc_tdp_limits(rdev, boot_ps); |
2c48febb AD |
6455 | if (ret) { |
6456 | DRM_ERROR("si_populate_smc_tdp_limits failed\n"); | |
a9e61410 | 6457 | return ret; |
2c48febb | 6458 | } |
a9e61410 | 6459 | ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); |
2c48febb AD |
6460 | if (ret) { |
6461 | DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); | |
a9e61410 | 6462 | return ret; |
2c48febb | 6463 | } |
a9e61410 AD |
6464 | si_program_response_times(rdev); |
6465 | si_program_ds_registers(rdev); | |
6466 | si_dpm_start_smc(rdev); | |
6467 | ret = si_notify_smc_display_change(rdev, false); | |
2c48febb AD |
6468 | if (ret) { |
6469 | DRM_ERROR("si_notify_smc_display_change failed\n"); | |
a9e61410 | 6470 | return ret; |
2c48febb | 6471 | } |
a9e61410 AD |
6472 | si_enable_sclk_control(rdev, true); |
6473 | si_start_dpm(rdev); | |
6474 | ||
a9e61410 AD |
6475 | si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); |
6476 | ||
39471ad3 AD |
6477 | si_thermal_start_thermal_controller(rdev); |
6478 | ||
a9e61410 AD |
6479 | ni_update_current_ps(rdev, boot_ps); |
6480 | ||
6481 | return 0; | |
6482 | } | |
6483 | ||
2271e2e2 | 6484 | static int si_set_temperature_range(struct radeon_device *rdev) |
963c115d AD |
6485 | { |
6486 | int ret; | |
6487 | ||
2271e2e2 AD |
6488 | ret = si_thermal_enable_alert(rdev, false); |
6489 | if (ret) | |
6490 | return ret; | |
6491 | ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); | |
6492 | if (ret) | |
6493 | return ret; | |
6494 | ret = si_thermal_enable_alert(rdev, true); | |
6495 | if (ret) | |
6496 | return ret; | |
963c115d | 6497 | |
2271e2e2 AD |
6498 | return ret; |
6499 | } | |
963c115d | 6500 | |
2271e2e2 AD |
6501 | int si_dpm_late_enable(struct radeon_device *rdev) |
6502 | { | |
6503 | int ret; | |
963c115d | 6504 | |
2271e2e2 AD |
6505 | ret = si_set_temperature_range(rdev); |
6506 | if (ret) | |
6507 | return ret; | |
6508 | ||
6509 | return ret; | |
963c115d AD |
6510 | } |
6511 | ||
a9e61410 AD |
6512 | void si_dpm_disable(struct radeon_device *rdev) |
6513 | { | |
6514 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
6515 | struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; | |
6516 | ||
6517 | if (!si_is_smc_running(rdev)) | |
6518 | return; | |
39471ad3 | 6519 | si_thermal_stop_thermal_controller(rdev); |
a9e61410 AD |
6520 | si_disable_ulv(rdev); |
6521 | si_clear_vc(rdev); | |
6522 | if (pi->thermal_protection) | |
6523 | si_enable_thermal_protection(rdev, false); | |
6524 | si_enable_power_containment(rdev, boot_ps, false); | |
6525 | si_enable_smc_cac(rdev, boot_ps, false); | |
6526 | si_enable_spread_spectrum(rdev, false); | |
6527 | si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); | |
6528 | si_stop_dpm(rdev); | |
6529 | si_reset_to_default(rdev); | |
6530 | si_dpm_stop_smc(rdev); | |
6531 | si_force_switch_to_arb_f0(rdev); | |
6532 | ||
6533 | ni_update_current_ps(rdev, boot_ps); | |
6534 | } | |
6535 | ||
6536 | int si_dpm_pre_set_power_state(struct radeon_device *rdev) | |
6537 | { | |
6538 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
6539 | struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; | |
6540 | struct radeon_ps *new_ps = &requested_ps; | |
6541 | ||
6542 | ni_update_requested_ps(rdev, new_ps); | |
6543 | ||
6544 | si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); | |
6545 | ||
6546 | return 0; | |
6547 | } | |
6548 | ||
a144acbc AD |
6549 | static int si_power_control_set_level(struct radeon_device *rdev) |
6550 | { | |
6551 | struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; | |
6552 | int ret; | |
6553 | ||
6554 | ret = si_restrict_performance_levels_before_switch(rdev); | |
6555 | if (ret) | |
6556 | return ret; | |
6557 | ret = si_halt_smc(rdev); | |
6558 | if (ret) | |
6559 | return ret; | |
6560 | ret = si_populate_smc_tdp_limits(rdev, new_ps); | |
6561 | if (ret) | |
6562 | return ret; | |
6563 | ret = si_populate_smc_tdp_limits_2(rdev, new_ps); | |
6564 | if (ret) | |
6565 | return ret; | |
6566 | ret = si_resume_smc(rdev); | |
6567 | if (ret) | |
6568 | return ret; | |
6569 | ret = si_set_sw_state(rdev); | |
6570 | if (ret) | |
6571 | return ret; | |
6572 | return 0; | |
6573 | } | |
6574 | ||
a9e61410 AD |
6575 | int si_dpm_set_power_state(struct radeon_device *rdev) |
6576 | { | |
6577 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
6578 | struct radeon_ps *new_ps = &eg_pi->requested_rps; | |
6579 | struct radeon_ps *old_ps = &eg_pi->current_rps; | |
6580 | int ret; | |
6581 | ||
6582 | ret = si_disable_ulv(rdev); | |
cc833b60 AD |
6583 | if (ret) { |
6584 | DRM_ERROR("si_disable_ulv failed\n"); | |
a9e61410 | 6585 | return ret; |
cc833b60 | 6586 | } |
a9e61410 | 6587 | ret = si_restrict_performance_levels_before_switch(rdev); |
cc833b60 AD |
6588 | if (ret) { |
6589 | DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); | |
a9e61410 | 6590 | return ret; |
cc833b60 | 6591 | } |
a9e61410 AD |
6592 | if (eg_pi->pcie_performance_request) |
6593 | si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); | |
e34568b8 | 6594 | ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); |
a9e61410 | 6595 | ret = si_enable_power_containment(rdev, new_ps, false); |
cc833b60 AD |
6596 | if (ret) { |
6597 | DRM_ERROR("si_enable_power_containment failed\n"); | |
a9e61410 | 6598 | return ret; |
cc833b60 | 6599 | } |
a9e61410 | 6600 | ret = si_enable_smc_cac(rdev, new_ps, false); |
cc833b60 AD |
6601 | if (ret) { |
6602 | DRM_ERROR("si_enable_smc_cac failed\n"); | |
a9e61410 | 6603 | return ret; |
cc833b60 | 6604 | } |
a9e61410 | 6605 | ret = si_halt_smc(rdev); |
cc833b60 AD |
6606 | if (ret) { |
6607 | DRM_ERROR("si_halt_smc failed\n"); | |
a9e61410 | 6608 | return ret; |
cc833b60 | 6609 | } |
a9e61410 | 6610 | ret = si_upload_sw_state(rdev, new_ps); |
cc833b60 AD |
6611 | if (ret) { |
6612 | DRM_ERROR("si_upload_sw_state failed\n"); | |
a9e61410 | 6613 | return ret; |
cc833b60 | 6614 | } |
a9e61410 | 6615 | ret = si_upload_smc_data(rdev); |
cc833b60 AD |
6616 | if (ret) { |
6617 | DRM_ERROR("si_upload_smc_data failed\n"); | |
a9e61410 | 6618 | return ret; |
cc833b60 | 6619 | } |
a9e61410 | 6620 | ret = si_upload_ulv_state(rdev); |
cc833b60 AD |
6621 | if (ret) { |
6622 | DRM_ERROR("si_upload_ulv_state failed\n"); | |
a9e61410 | 6623 | return ret; |
cc833b60 | 6624 | } |
a9e61410 AD |
6625 | if (eg_pi->dynamic_ac_timing) { |
6626 | ret = si_upload_mc_reg_table(rdev, new_ps); | |
cc833b60 AD |
6627 | if (ret) { |
6628 | DRM_ERROR("si_upload_mc_reg_table failed\n"); | |
a9e61410 | 6629 | return ret; |
cc833b60 | 6630 | } |
a9e61410 AD |
6631 | } |
6632 | ret = si_program_memory_timing_parameters(rdev, new_ps); | |
cc833b60 AD |
6633 | if (ret) { |
6634 | DRM_ERROR("si_program_memory_timing_parameters failed\n"); | |
a9e61410 | 6635 | return ret; |
cc833b60 | 6636 | } |
a9e61410 AD |
6637 | si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); |
6638 | ||
a9e61410 | 6639 | ret = si_resume_smc(rdev); |
cc833b60 AD |
6640 | if (ret) { |
6641 | DRM_ERROR("si_resume_smc failed\n"); | |
a9e61410 | 6642 | return ret; |
cc833b60 | 6643 | } |
a9e61410 | 6644 | ret = si_set_sw_state(rdev); |
cc833b60 AD |
6645 | if (ret) { |
6646 | DRM_ERROR("si_set_sw_state failed\n"); | |
a9e61410 | 6647 | return ret; |
cc833b60 | 6648 | } |
e34568b8 | 6649 | ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); |
11586cf0 | 6650 | si_set_vce_clock(rdev, new_ps, old_ps); |
a9e61410 AD |
6651 | if (eg_pi->pcie_performance_request) |
6652 | si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); | |
6653 | ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); | |
cc833b60 AD |
6654 | if (ret) { |
6655 | DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); | |
a9e61410 | 6656 | return ret; |
cc833b60 | 6657 | } |
a9e61410 | 6658 | ret = si_enable_smc_cac(rdev, new_ps, true); |
cc833b60 AD |
6659 | if (ret) { |
6660 | DRM_ERROR("si_enable_smc_cac failed\n"); | |
a9e61410 | 6661 | return ret; |
cc833b60 | 6662 | } |
a9e61410 | 6663 | ret = si_enable_power_containment(rdev, new_ps, true); |
cc833b60 AD |
6664 | if (ret) { |
6665 | DRM_ERROR("si_enable_power_containment failed\n"); | |
a9e61410 | 6666 | return ret; |
cc833b60 | 6667 | } |
a9e61410 | 6668 | |
a144acbc AD |
6669 | ret = si_power_control_set_level(rdev); |
6670 | if (ret) { | |
6671 | DRM_ERROR("si_power_control_set_level failed\n"); | |
6672 | return ret; | |
6673 | } | |
6674 | ||
a9e61410 AD |
6675 | return 0; |
6676 | } | |
6677 | ||
a9e61410 AD |
6678 | void si_dpm_post_set_power_state(struct radeon_device *rdev) |
6679 | { | |
6680 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
6681 | struct radeon_ps *new_ps = &eg_pi->requested_rps; | |
6682 | ||
6683 | ni_update_current_ps(rdev, new_ps); | |
6684 | } | |
6685 | ||
98769131 | 6686 | #if 0 |
a9e61410 AD |
6687 | void si_dpm_reset_asic(struct radeon_device *rdev) |
6688 | { | |
6689 | si_restrict_performance_levels_before_switch(rdev); | |
6690 | si_disable_ulv(rdev); | |
6691 | si_set_boot_state(rdev); | |
6692 | } | |
98769131 | 6693 | #endif |
a9e61410 AD |
6694 | |
6695 | void si_dpm_display_configuration_changed(struct radeon_device *rdev) | |
6696 | { | |
6697 | si_program_display_gap(rdev); | |
6698 | } | |
6699 | ||
6700 | union power_info { | |
6701 | struct _ATOM_POWERPLAY_INFO info; | |
6702 | struct _ATOM_POWERPLAY_INFO_V2 info_2; | |
6703 | struct _ATOM_POWERPLAY_INFO_V3 info_3; | |
6704 | struct _ATOM_PPLIB_POWERPLAYTABLE pplib; | |
6705 | struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; | |
6706 | struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; | |
6707 | }; | |
6708 | ||
6709 | union pplib_clock_info { | |
6710 | struct _ATOM_PPLIB_R600_CLOCK_INFO r600; | |
6711 | struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; | |
6712 | struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; | |
6713 | struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; | |
6714 | struct _ATOM_PPLIB_SI_CLOCK_INFO si; | |
6715 | }; | |
6716 | ||
6717 | union pplib_power_state { | |
6718 | struct _ATOM_PPLIB_STATE v1; | |
6719 | struct _ATOM_PPLIB_STATE_V2 v2; | |
6720 | }; | |
6721 | ||
6722 | static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, | |
6723 | struct radeon_ps *rps, | |
6724 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, | |
6725 | u8 table_rev) | |
6726 | { | |
6727 | rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); | |
6728 | rps->class = le16_to_cpu(non_clock_info->usClassification); | |
6729 | rps->class2 = le16_to_cpu(non_clock_info->usClassification2); | |
6730 | ||
6731 | if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { | |
6732 | rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); | |
6733 | rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); | |
6734 | } else if (r600_is_uvd_state(rps->class, rps->class2)) { | |
6735 | rps->vclk = RV770_DEFAULT_VCLK_FREQ; | |
6736 | rps->dclk = RV770_DEFAULT_DCLK_FREQ; | |
6737 | } else { | |
6738 | rps->vclk = 0; | |
6739 | rps->dclk = 0; | |
6740 | } | |
6741 | ||
6742 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) | |
6743 | rdev->pm.dpm.boot_ps = rps; | |
6744 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) | |
6745 | rdev->pm.dpm.uvd_ps = rps; | |
6746 | } | |
6747 | ||
6748 | static void si_parse_pplib_clock_info(struct radeon_device *rdev, | |
6749 | struct radeon_ps *rps, int index, | |
6750 | union pplib_clock_info *clock_info) | |
6751 | { | |
6752 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |
6753 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
6754 | struct si_power_info *si_pi = si_get_pi(rdev); | |
6755 | struct ni_ps *ps = ni_get_ps(rps); | |
6756 | u16 leakage_voltage; | |
6757 | struct rv7xx_pl *pl = &ps->performance_levels[index]; | |
6758 | int ret; | |
6759 | ||
6760 | ps->performance_level_count = index + 1; | |
6761 | ||
6762 | pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); | |
6763 | pl->sclk |= clock_info->si.ucEngineClockHigh << 16; | |
6764 | pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); | |
6765 | pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; | |
6766 | ||
6767 | pl->vddc = le16_to_cpu(clock_info->si.usVDDC); | |
6768 | pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); | |
6769 | pl->flags = le32_to_cpu(clock_info->si.ulFlags); | |
6770 | pl->pcie_gen = r600_get_pcie_gen_support(rdev, | |
6771 | si_pi->sys_pcie_mask, | |
6772 | si_pi->boot_pcie_gen, | |
6773 | clock_info->si.ucPCIEGen); | |
6774 | ||
6775 | /* patch up vddc if necessary */ | |
6776 | ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, | |
6777 | &leakage_voltage); | |
6778 | if (ret == 0) | |
6779 | pl->vddc = leakage_voltage; | |
6780 | ||
6781 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { | |
6782 | pi->acpi_vddc = pl->vddc; | |
6783 | eg_pi->acpi_vddci = pl->vddci; | |
6784 | si_pi->acpi_pcie_gen = pl->pcie_gen; | |
6785 | } | |
6786 | ||
6787 | if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && | |
6788 | index == 0) { | |
6789 | /* XXX disable for A0 tahiti */ | |
6fa45593 | 6790 | si_pi->ulv.supported = false; |
a9e61410 AD |
6791 | si_pi->ulv.pl = *pl; |
6792 | si_pi->ulv.one_pcie_lane_in_ulv = false; | |
6793 | si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; | |
6794 | si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; | |
6795 | si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; | |
6796 | } | |
6797 | ||
6798 | if (pi->min_vddc_in_table > pl->vddc) | |
6799 | pi->min_vddc_in_table = pl->vddc; | |
6800 | ||
6801 | if (pi->max_vddc_in_table < pl->vddc) | |
6802 | pi->max_vddc_in_table = pl->vddc; | |
6803 | ||
6804 | /* patch up boot state */ | |
6805 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { | |
6806 | u16 vddc, vddci, mvdd; | |
6807 | radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); | |
6808 | pl->mclk = rdev->clock.default_mclk; | |
6809 | pl->sclk = rdev->clock.default_sclk; | |
6810 | pl->vddc = vddc; | |
6811 | pl->vddci = vddci; | |
6812 | si_pi->mvdd_bootup_value = mvdd; | |
6813 | } | |
6814 | ||
6815 | if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == | |
6816 | ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { | |
6817 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; | |
6818 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; | |
6819 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; | |
6820 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; | |
6821 | } | |
6822 | } | |
6823 | ||
6824 | static int si_parse_power_table(struct radeon_device *rdev) | |
6825 | { | |
6826 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
6827 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; | |
6828 | union pplib_power_state *power_state; | |
6829 | int i, j, k, non_clock_array_index, clock_array_index; | |
6830 | union pplib_clock_info *clock_info; | |
6831 | struct _StateArray *state_array; | |
6832 | struct _ClockInfoArray *clock_info_array; | |
6833 | struct _NonClockInfoArray *non_clock_info_array; | |
6834 | union power_info *power_info; | |
6835 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); | |
3cf8bb1a | 6836 | u16 data_offset; |
a9e61410 AD |
6837 | u8 frev, crev; |
6838 | u8 *power_state_offset; | |
6839 | struct ni_ps *ps; | |
6840 | ||
6841 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, | |
6842 | &frev, &crev, &data_offset)) | |
6843 | return -EINVAL; | |
6844 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); | |
6845 | ||
6846 | state_array = (struct _StateArray *) | |
6847 | (mode_info->atom_context->bios + data_offset + | |
6848 | le16_to_cpu(power_info->pplib.usStateArrayOffset)); | |
6849 | clock_info_array = (struct _ClockInfoArray *) | |
6850 | (mode_info->atom_context->bios + data_offset + | |
6851 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); | |
6852 | non_clock_info_array = (struct _NonClockInfoArray *) | |
6853 | (mode_info->atom_context->bios + data_offset + | |
6854 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); | |
6855 | ||
6856 | rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * | |
6857 | state_array->ucNumEntries, GFP_KERNEL); | |
6858 | if (!rdev->pm.dpm.ps) | |
6859 | return -ENOMEM; | |
6860 | power_state_offset = (u8 *)state_array->states; | |
a9e61410 | 6861 | for (i = 0; i < state_array->ucNumEntries; i++) { |
53f3b252 | 6862 | u8 *idx; |
a9e61410 AD |
6863 | power_state = (union pplib_power_state *)power_state_offset; |
6864 | non_clock_array_index = power_state->v2.nonClockInfoIndex; | |
6865 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) | |
6866 | &non_clock_info_array->nonClockInfo[non_clock_array_index]; | |
6867 | if (!rdev->pm.power_state[i].clock_info) | |
6868 | return -EINVAL; | |
6869 | ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); | |
6870 | if (ps == NULL) { | |
6871 | kfree(rdev->pm.dpm.ps); | |
6872 | return -ENOMEM; | |
6873 | } | |
6874 | rdev->pm.dpm.ps[i].ps_priv = ps; | |
6875 | si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], | |
6876 | non_clock_info, | |
6877 | non_clock_info_array->ucEntrySize); | |
6878 | k = 0; | |
53f3b252 | 6879 | idx = (u8 *)&power_state->v2.clockInfoIndex[0]; |
a9e61410 | 6880 | for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { |
53f3b252 | 6881 | clock_array_index = idx[j]; |
a9e61410 AD |
6882 | if (clock_array_index >= clock_info_array->ucNumEntries) |
6883 | continue; | |
6884 | if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) | |
6885 | break; | |
6886 | clock_info = (union pplib_clock_info *) | |
53f3b252 AD |
6887 | ((u8 *)&clock_info_array->clockInfo[0] + |
6888 | (clock_array_index * clock_info_array->ucEntrySize)); | |
a9e61410 AD |
6889 | si_parse_pplib_clock_info(rdev, |
6890 | &rdev->pm.dpm.ps[i], k, | |
6891 | clock_info); | |
6892 | k++; | |
6893 | } | |
6894 | power_state_offset += 2 + power_state->v2.ucNumDPMLevels; | |
6895 | } | |
6896 | rdev->pm.dpm.num_ps = state_array->ucNumEntries; | |
11586cf0 AD |
6897 | |
6898 | /* fill in the vce power states */ | |
6899 | for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { | |
6900 | u32 sclk, mclk; | |
6901 | clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; | |
6902 | clock_info = (union pplib_clock_info *) | |
6903 | &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; | |
6904 | sclk = le16_to_cpu(clock_info->si.usEngineClockLow); | |
6905 | sclk |= clock_info->si.ucEngineClockHigh << 16; | |
6906 | mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); | |
6907 | mclk |= clock_info->si.ucMemoryClockHigh << 16; | |
6908 | rdev->pm.dpm.vce_states[i].sclk = sclk; | |
6909 | rdev->pm.dpm.vce_states[i].mclk = mclk; | |
6910 | } | |
6911 | ||
a9e61410 AD |
6912 | return 0; |
6913 | } | |
6914 | ||
6915 | int si_dpm_init(struct radeon_device *rdev) | |
6916 | { | |
6917 | struct rv7xx_power_info *pi; | |
6918 | struct evergreen_power_info *eg_pi; | |
6919 | struct ni_power_info *ni_pi; | |
6920 | struct si_power_info *si_pi; | |
a9e61410 AD |
6921 | struct atom_clock_dividers dividers; |
6922 | int ret; | |
6923 | u32 mask; | |
6924 | ||
6925 | si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); | |
6926 | if (si_pi == NULL) | |
6927 | return -ENOMEM; | |
6928 | rdev->pm.dpm.priv = si_pi; | |
6929 | ni_pi = &si_pi->ni; | |
6930 | eg_pi = &ni_pi->eg; | |
6931 | pi = &eg_pi->rv7xx; | |
6932 | ||
6933 | ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); | |
6934 | if (ret) | |
6935 | si_pi->sys_pcie_mask = 0; | |
6936 | else | |
6937 | si_pi->sys_pcie_mask = mask; | |
6938 | si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; | |
6939 | si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); | |
6940 | ||
6941 | si_set_max_cu_value(rdev); | |
6942 | ||
6943 | rv770_get_max_vddc(rdev); | |
6944 | si_get_leakage_vddc(rdev); | |
6945 | si_patch_dependency_tables_based_on_leakage(rdev); | |
6946 | ||
6947 | pi->acpi_vddc = 0; | |
6948 | eg_pi->acpi_vddci = 0; | |
6949 | pi->min_vddc_in_table = 0; | |
6950 | pi->max_vddc_in_table = 0; | |
6951 | ||
82f79cc5 AD |
6952 | ret = r600_get_platform_caps(rdev); |
6953 | if (ret) | |
6954 | return ret; | |
6955 | ||
11586cf0 | 6956 | ret = r600_parse_extended_power_table(rdev); |
a9e61410 AD |
6957 | if (ret) |
6958 | return ret; | |
11586cf0 AD |
6959 | |
6960 | ret = si_parse_power_table(rdev); | |
a9e61410 AD |
6961 | if (ret) |
6962 | return ret; | |
6963 | ||
6964 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = | |
6965 | kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); | |
6966 | if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { | |
6967 | r600_free_extended_power_table(rdev); | |
6968 | return -ENOMEM; | |
6969 | } | |
6970 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; | |
6971 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; | |
6972 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; | |
6973 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; | |
6974 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; | |
6975 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; | |
6976 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; | |
6977 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; | |
6978 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; | |
6979 | ||
6980 | if (rdev->pm.dpm.voltage_response_time == 0) | |
6981 | rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; | |
6982 | if (rdev->pm.dpm.backbias_response_time == 0) | |
6983 | rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; | |
6984 | ||
6985 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, | |
6986 | 0, false, ÷rs); | |
6987 | if (ret) | |
6988 | pi->ref_div = dividers.ref_div + 1; | |
6989 | else | |
6990 | pi->ref_div = R600_REFERENCEDIVIDER_DFLT; | |
6991 | ||
6992 | eg_pi->smu_uvd_hs = false; | |
6993 | ||
6994 | pi->mclk_strobe_mode_threshold = 40000; | |
6995 | if (si_is_special_1gb_platform(rdev)) | |
6996 | pi->mclk_stutter_mode_threshold = 0; | |
6997 | else | |
6998 | pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; | |
6999 | pi->mclk_edc_enable_threshold = 40000; | |
7000 | eg_pi->mclk_edc_wr_enable_threshold = 40000; | |
7001 | ||
7002 | ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; | |
7003 | ||
7004 | pi->voltage_control = | |
636e2582 AD |
7005 | radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, |
7006 | VOLTAGE_OBJ_GPIO_LUT); | |
7007 | if (!pi->voltage_control) { | |
7008 | si_pi->voltage_control_svi2 = | |
7009 | radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, | |
7010 | VOLTAGE_OBJ_SVID2); | |
7011 | if (si_pi->voltage_control_svi2) | |
7012 | radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, | |
7013 | &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); | |
7014 | } | |
a9e61410 AD |
7015 | |
7016 | pi->mvdd_control = | |
636e2582 AD |
7017 | radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, |
7018 | VOLTAGE_OBJ_GPIO_LUT); | |
a9e61410 AD |
7019 | |
7020 | eg_pi->vddci_control = | |
636e2582 AD |
7021 | radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, |
7022 | VOLTAGE_OBJ_GPIO_LUT); | |
7023 | if (!eg_pi->vddci_control) | |
7024 | si_pi->vddci_control_svi2 = | |
7025 | radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, | |
7026 | VOLTAGE_OBJ_SVID2); | |
a9e61410 AD |
7027 | |
7028 | si_pi->vddc_phase_shed_control = | |
636e2582 AD |
7029 | radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, |
7030 | VOLTAGE_OBJ_PHASE_LUT); | |
a9e61410 | 7031 | |
b841ce7b | 7032 | rv770_get_engine_memory_ss(rdev); |
a9e61410 AD |
7033 | |
7034 | pi->asi = RV770_ASI_DFLT; | |
7035 | pi->pasi = CYPRESS_HASI_DFLT; | |
7036 | pi->vrc = SISLANDS_VRC_DFLT; | |
7037 | ||
7038 | pi->gfx_clock_gating = true; | |
7039 | ||
7040 | eg_pi->sclk_deep_sleep = true; | |
7041 | si_pi->sclk_deep_sleep_above_low = false; | |
7042 | ||
fda83724 | 7043 | if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) |
a9e61410 AD |
7044 | pi->thermal_protection = true; |
7045 | else | |
7046 | pi->thermal_protection = false; | |
7047 | ||
7048 | eg_pi->dynamic_ac_timing = true; | |
7049 | ||
7050 | eg_pi->light_sleep = true; | |
7051 | #if defined(CONFIG_ACPI) | |
7052 | eg_pi->pcie_performance_request = | |
7053 | radeon_acpi_is_pcie_performance_request_supported(rdev); | |
7054 | #else | |
7055 | eg_pi->pcie_performance_request = false; | |
7056 | #endif | |
7057 | ||
7058 | si_pi->sram_end = SMC_RAM_END; | |
7059 | ||
7060 | rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; | |
7061 | rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; | |
7062 | rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; | |
7063 | rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; | |
7064 | rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; | |
7065 | rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; | |
7066 | rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; | |
7067 | ||
7068 | si_initialize_powertune_defaults(rdev); | |
7069 | ||
1ff60ddb AD |
7070 | /* make sure dc limits are valid */ |
7071 | if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || | |
7072 | (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) | |
7073 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = | |
7074 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; | |
7075 | ||
39471ad3 | 7076 | si_pi->fan_ctrl_is_in_default_mode = true; |
39471ad3 | 7077 | |
a9e61410 AD |
7078 | return 0; |
7079 | } | |
7080 | ||
7081 | void si_dpm_fini(struct radeon_device *rdev) | |
7082 | { | |
7083 | int i; | |
7084 | ||
7085 | for (i = 0; i < rdev->pm.dpm.num_ps; i++) { | |
7086 | kfree(rdev->pm.dpm.ps[i].ps_priv); | |
7087 | } | |
7088 | kfree(rdev->pm.dpm.ps); | |
7089 | kfree(rdev->pm.dpm.priv); | |
7090 | kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); | |
7091 | r600_free_extended_power_table(rdev); | |
7092 | } | |
7093 | ||
7982128c AD |
7094 | void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
7095 | struct seq_file *m) | |
7096 | { | |
9f3f63f2 AD |
7097 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
7098 | struct radeon_ps *rps = &eg_pi->current_rps; | |
7982128c AD |
7099 | struct ni_ps *ps = ni_get_ps(rps); |
7100 | struct rv7xx_pl *pl; | |
7101 | u32 current_index = | |
7102 | (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> | |
7103 | CURRENT_STATE_INDEX_SHIFT; | |
7104 | ||
7105 | if (current_index >= ps->performance_level_count) { | |
7106 | seq_printf(m, "invalid dpm profile %d\n", current_index); | |
7107 | } else { | |
7108 | pl = &ps->performance_levels[current_index]; | |
7109 | seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); | |
7110 | seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", | |
7111 | current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); | |
7112 | } | |
7113 | } | |
ca1110bc AD |
7114 | |
7115 | u32 si_dpm_get_current_sclk(struct radeon_device *rdev) | |
7116 | { | |
7117 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
7118 | struct radeon_ps *rps = &eg_pi->current_rps; | |
7119 | struct ni_ps *ps = ni_get_ps(rps); | |
7120 | struct rv7xx_pl *pl; | |
7121 | u32 current_index = | |
7122 | (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> | |
7123 | CURRENT_STATE_INDEX_SHIFT; | |
7124 | ||
7125 | if (current_index >= ps->performance_level_count) { | |
7126 | return 0; | |
7127 | } else { | |
7128 | pl = &ps->performance_levels[current_index]; | |
7129 | return pl->sclk; | |
7130 | } | |
7131 | } | |
7132 | ||
7133 | u32 si_dpm_get_current_mclk(struct radeon_device *rdev) | |
7134 | { | |
7135 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); | |
7136 | struct radeon_ps *rps = &eg_pi->current_rps; | |
7137 | struct ni_ps *ps = ni_get_ps(rps); | |
7138 | struct rv7xx_pl *pl; | |
7139 | u32 current_index = | |
7140 | (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> | |
7141 | CURRENT_STATE_INDEX_SHIFT; | |
7142 | ||
7143 | if (current_index >= ps->performance_level_count) { | |
7144 | return 0; | |
7145 | } else { | |
7146 | pl = &ps->performance_levels[current_index]; | |
7147 | return pl->mclk; | |
7148 | } | |
7149 | } |