drm/radeon: init UVD clocks to sane defaults
[linux-2.6-block.git] / drivers / gpu / drm / radeon / rv770d.h
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1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27#ifndef RV770_H
28#define RV770_H
29
30#define R7XX_MAX_SH_GPRS 256
31#define R7XX_MAX_TEMP_GPRS 16
32#define R7XX_MAX_SH_THREADS 256
33#define R7XX_MAX_SH_STACK_ENTRIES 4096
34#define R7XX_MAX_BACKENDS 8
35#define R7XX_MAX_BACKENDS_MASK 0xff
36#define R7XX_MAX_SIMDS 16
37#define R7XX_MAX_SIMDS_MASK 0xffff
38#define R7XX_MAX_PIPES 8
39#define R7XX_MAX_PIPES_MASK 0xff
40
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41/* discrete uvd clocks */
42#define CG_UPLL_FUNC_CNTL 0x718
43# define UPLL_RESET_MASK 0x00000001
44# define UPLL_SLEEP_MASK 0x00000002
45# define UPLL_BYPASS_EN_MASK 0x00000004
46# define UPLL_CTLREQ_MASK 0x00000008
47# define UPLL_REF_DIV(x) ((x) << 16)
48# define UPLL_REF_DIV_MASK 0x001F0000
49# define UPLL_CTLACK_MASK 0x40000000
50# define UPLL_CTLACK2_MASK 0x80000000
51#define CG_UPLL_FUNC_CNTL_2 0x71c
52# define UPLL_SW_HILEN(x) ((x) << 0)
53# define UPLL_SW_LOLEN(x) ((x) << 4)
54# define UPLL_SW_HILEN2(x) ((x) << 8)
55# define UPLL_SW_LOLEN2(x) ((x) << 12)
56# define UPLL_SW_MASK 0x0000FFFF
57# define VCLK_SRC_SEL(x) ((x) << 20)
58# define VCLK_SRC_SEL_MASK 0x01F00000
59# define DCLK_SRC_SEL(x) ((x) << 25)
60# define DCLK_SRC_SEL_MASK 0x3E000000
61#define CG_UPLL_FUNC_CNTL_3 0x720
62# define UPLL_FB_DIV(x) ((x) << 0)
63# define UPLL_FB_DIV_MASK 0x01FFFFFF
64
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65/* Registers */
66#define CB_COLOR0_BASE 0x28040
67#define CB_COLOR1_BASE 0x28044
68#define CB_COLOR2_BASE 0x28048
69#define CB_COLOR3_BASE 0x2804C
70#define CB_COLOR4_BASE 0x28050
71#define CB_COLOR5_BASE 0x28054
72#define CB_COLOR6_BASE 0x28058
73#define CB_COLOR7_BASE 0x2805C
74#define CB_COLOR7_FRAG 0x280FC
75
76#define CC_GC_SHADER_PIPE_CONFIG 0x8950
77#define CC_RB_BACKEND_DISABLE 0x98F4
78#define BACKEND_DISABLE(x) ((x) << 16)
79#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
80
81#define CGTS_SYS_TCC_DISABLE 0x3F90
82#define CGTS_TCC_DISABLE 0x9148
83#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
84#define CGTS_USER_TCC_DISABLE 0x914C
85
86#define CONFIG_MEMSIZE 0x5428
87
88#define CP_ME_CNTL 0x86D8
89#define CP_ME_HALT (1<<28)
90#define CP_PFP_HALT (1<<26)
91#define CP_ME_RAM_DATA 0xC160
92#define CP_ME_RAM_RADDR 0xC158
93#define CP_ME_RAM_WADDR 0xC15C
94#define CP_MEQ_THRESHOLDS 0x8764
95#define STQ_SPLIT(x) ((x) << 0)
96#define CP_PERFMON_CNTL 0x87FC
97#define CP_PFP_UCODE_ADDR 0xC150
98#define CP_PFP_UCODE_DATA 0xC154
99#define CP_QUEUE_THRESHOLDS 0x8760
100#define ROQ_IB1_START(x) ((x) << 0)
101#define ROQ_IB2_START(x) ((x) << 8)
102#define CP_RB_CNTL 0xC104
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103#define RB_BUFSZ(x) ((x) << 0)
104#define RB_BLKSZ(x) ((x) << 8)
105#define RB_NO_UPDATE (1 << 27)
106#define RB_RPTR_WR_ENA (1 << 31)
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107#define BUF_SWAP_32BIT (2 << 16)
108#define CP_RB_RPTR 0x8700
109#define CP_RB_RPTR_ADDR 0xC10C
110#define CP_RB_RPTR_ADDR_HI 0xC110
111#define CP_RB_RPTR_WR 0xC108
112#define CP_RB_WPTR 0xC114
113#define CP_RB_WPTR_ADDR 0xC118
114#define CP_RB_WPTR_ADDR_HI 0xC11C
115#define CP_RB_WPTR_DELAY 0x8704
116#define CP_SEM_WAIT_TIMER 0x85BC
117
118#define DB_DEBUG3 0x98B0
119#define DB_CLK_OFF_DELAY(x) ((x) << 11)
120#define DB_DEBUG4 0x9B8C
121#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
122
123#define DCP_TILING_CONFIG 0x6CA0
124#define PIPE_TILING(x) ((x) << 1)
125#define BANK_TILING(x) ((x) << 4)
126#define GROUP_SIZE(x) ((x) << 6)
127#define ROW_TILING(x) ((x) << 8)
128#define BANK_SWAPS(x) ((x) << 11)
129#define SAMPLE_SPLIT(x) ((x) << 14)
130#define BACKEND_MAP(x) ((x) << 16)
131
132#define GB_TILING_CONFIG 0x98F0
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133#define PIPE_TILING__SHIFT 1
134#define PIPE_TILING__MASK 0x0000000e
3ce0a23d 135
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136#define DMA_TILING_CONFIG 0x3ec8
137#define DMA_TILING_CONFIG2 0xd0b8
138
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139#define GC_USER_SHADER_PIPE_CONFIG 0x8954
140#define INACTIVE_QD_PIPES(x) ((x) << 8)
141#define INACTIVE_QD_PIPES_MASK 0x0000FF00
416a2bd2 142#define INACTIVE_QD_PIPES_SHIFT 8
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143#define INACTIVE_SIMDS(x) ((x) << 16)
144#define INACTIVE_SIMDS_MASK 0x00FF0000
145
146#define GRBM_CNTL 0x8000
147#define GRBM_READ_TIMEOUT(x) ((x) << 0)
148#define GRBM_SOFT_RESET 0x8020
149#define SOFT_RESET_CP (1<<0)
150#define GRBM_STATUS 0x8010
151#define CMDFIFO_AVAIL_MASK 0x0000000F
152#define GUI_ACTIVE (1<<31)
153#define GRBM_STATUS2 0x8014
154
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155#define CG_CLKPIN_CNTL 0x660
156# define MUX_TCLK_TO_XCLK (1 << 8)
157# define XTALIN_DIVIDE (1 << 9)
158
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159#define CG_MULT_THERMAL_STATUS 0x740
160#define ASIC_T(x) ((x) << 16)
161#define ASIC_T_MASK 0x3FF0000
162#define ASIC_T_SHIFT 16
163
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164#define HDP_HOST_PATH_CNTL 0x2C00
165#define HDP_NONSURFACE_BASE 0x2C04
166#define HDP_NONSURFACE_INFO 0x2C08
167#define HDP_NONSURFACE_SIZE 0x2C0C
168#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
169#define HDP_TILING_CONFIG 0x2F3C
812d0469 170#define HDP_DEBUG1 0x2F34
3ce0a23d 171
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172#define MC_SHARED_CHMAP 0x2004
173#define NOOFCHAN_SHIFT 12
174#define NOOFCHAN_MASK 0x00003000
9535ab73 175#define MC_SHARED_CHREMAP 0x2008
5885b7a9 176
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177#define MC_ARB_RAMCFG 0x2760
178#define NOOFBANK_SHIFT 0
179#define NOOFBANK_MASK 0x00000003
180#define NOOFRANK_SHIFT 2
181#define NOOFRANK_MASK 0x00000004
182#define NOOFROWS_SHIFT 3
183#define NOOFROWS_MASK 0x00000038
184#define NOOFCOLS_SHIFT 6
185#define NOOFCOLS_MASK 0x000000C0
186#define CHANSIZE_SHIFT 8
187#define CHANSIZE_MASK 0x00000100
188#define BURSTLENGTH_SHIFT 9
189#define BURSTLENGTH_MASK 0x00000200
5885b7a9 190#define CHANSIZE_OVERRIDE (1 << 11)
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191#define MC_VM_AGP_TOP 0x2028
192#define MC_VM_AGP_BOT 0x202C
193#define MC_VM_AGP_BASE 0x2030
194#define MC_VM_FB_LOCATION 0x2024
195#define MC_VM_MB_L1_TLB0_CNTL 0x2234
196#define MC_VM_MB_L1_TLB1_CNTL 0x2238
197#define MC_VM_MB_L1_TLB2_CNTL 0x223C
198#define MC_VM_MB_L1_TLB3_CNTL 0x2240
199#define ENABLE_L1_TLB (1 << 0)
200#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
201#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
202#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
203#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
204#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
205#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
206#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
207#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
208#define MC_VM_MD_L1_TLB0_CNTL 0x2654
209#define MC_VM_MD_L1_TLB1_CNTL 0x2658
210#define MC_VM_MD_L1_TLB2_CNTL 0x265C
0b8c30bc 211#define MC_VM_MD_L1_TLB3_CNTL 0x2698
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212#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
213#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
214#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
215
216#define PA_CL_ENHANCE 0x8A14
217#define CLIP_VTX_REORDER_ENA (1 << 0)
218#define NUM_CLIP_SEQ(x) ((x) << 1)
219#define PA_SC_AA_CONFIG 0x28C04
220#define PA_SC_CLIPRECT_RULE 0x2820C
221#define PA_SC_EDGERULE 0x28230
222#define PA_SC_FIFO_SIZE 0x8BCC
223#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
224#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
225#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
226#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0)
227#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16)
228#define PA_SC_LINE_STIPPLE 0x28A0C
229#define PA_SC_LINE_STIPPLE_STATE 0x8B10
230#define PA_SC_MODE_CNTL 0x28A4C
231#define PA_SC_MULTI_CHIP_CNTL 0x8B20
232#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
233
234#define SCRATCH_REG0 0x8500
235#define SCRATCH_REG1 0x8504
236#define SCRATCH_REG2 0x8508
237#define SCRATCH_REG3 0x850C
238#define SCRATCH_REG4 0x8510
239#define SCRATCH_REG5 0x8514
240#define SCRATCH_REG6 0x8518
241#define SCRATCH_REG7 0x851C
242#define SCRATCH_UMSK 0x8540
243#define SCRATCH_ADDR 0x8544
244
b866d133 245#define SMX_SAR_CTL0 0xA008
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246#define SMX_DC_CTL0 0xA020
247#define USE_HASH_FUNCTION (1 << 0)
248#define CACHE_DEPTH(x) ((x) << 1)
249#define FLUSH_ALL_ON_EVENT (1 << 10)
250#define STALL_ON_EVENT (1 << 11)
251#define SMX_EVENT_CTL 0xA02C
252#define ES_FLUSH_CTL(x) ((x) << 0)
253#define GS_FLUSH_CTL(x) ((x) << 3)
254#define ACK_FLUSH_CTL(x) ((x) << 6)
255#define SYNC_FLUSH_CTL (1 << 8)
256
257#define SPI_CONFIG_CNTL 0x9100
258#define GPR_WRITE_PRIORITY(x) ((x) << 0)
259#define DISABLE_INTERP_1 (1 << 5)
260#define SPI_CONFIG_CNTL_1 0x913C
261#define VTX_DONE_DELAY(x) ((x) << 0)
262#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
263#define SPI_INPUT_Z 0x286D8
264#define SPI_PS_IN_CONTROL_0 0x286CC
265#define NUM_INTERP(x) ((x)<<0)
266#define POSITION_ENA (1<<8)
267#define POSITION_CENTROID (1<<9)
268#define POSITION_ADDR(x) ((x)<<10)
269#define PARAM_GEN(x) ((x)<<15)
270#define PARAM_GEN_ADDR(x) ((x)<<19)
271#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
272#define PERSP_GRADIENT_ENA (1<<28)
273#define LINEAR_GRADIENT_ENA (1<<29)
274#define POSITION_SAMPLE (1<<30)
275#define BARYC_AT_SAMPLE_ENA (1<<31)
276
277#define SQ_CONFIG 0x8C00
278#define VC_ENABLE (1 << 0)
279#define EXPORT_SRC_C (1 << 1)
280#define DX9_CONSTS (1 << 2)
281#define ALU_INST_PREFER_VECTOR (1 << 3)
282#define DX10_CLAMP (1 << 4)
283#define CLAUSE_SEQ_PRIO(x) ((x) << 8)
284#define PS_PRIO(x) ((x) << 24)
285#define VS_PRIO(x) ((x) << 26)
286#define GS_PRIO(x) ((x) << 28)
287#define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0
288#define SIMDA_RING0(x) ((x)<<0)
289#define SIMDA_RING1(x) ((x)<<8)
290#define SIMDB_RING0(x) ((x)<<16)
291#define SIMDB_RING1(x) ((x)<<24)
292#define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4
293#define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8
294#define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC
295#define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0
296#define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4
297#define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8
298#define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC
299#define ES_PRIO(x) ((x) << 30)
300#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
301#define NUM_PS_GPRS(x) ((x) << 0)
302#define NUM_VS_GPRS(x) ((x) << 16)
303#define DYN_GPR_ENABLE (1 << 27)
304#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
305#define SQ_GPR_RESOURCE_MGMT_2 0x8C08
306#define NUM_GS_GPRS(x) ((x) << 0)
307#define NUM_ES_GPRS(x) ((x) << 16)
308#define SQ_MS_FIFO_SIZES 0x8CF0
309#define CACHE_FIFO_SIZE(x) ((x) << 0)
310#define FETCH_FIFO_HIWATER(x) ((x) << 8)
311#define DONE_FIFO_HIWATER(x) ((x) << 16)
312#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
313#define SQ_STACK_RESOURCE_MGMT_1 0x8C10
314#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
315#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
316#define SQ_STACK_RESOURCE_MGMT_2 0x8C14
317#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
318#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
319#define SQ_THREAD_RESOURCE_MGMT 0x8C0C
320#define NUM_PS_THREADS(x) ((x) << 0)
321#define NUM_VS_THREADS(x) ((x) << 8)
322#define NUM_GS_THREADS(x) ((x) << 16)
323#define NUM_ES_THREADS(x) ((x) << 24)
324
325#define SX_DEBUG_1 0x9058
326#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
327#define SX_EXPORT_BUFFER_SIZES 0x900C
328#define COLOR_BUFFER_SIZE(x) ((x) << 0)
329#define POSITION_BUFFER_SIZE(x) ((x) << 8)
330#define SMX_BUFFER_SIZE(x) ((x) << 16)
331#define SX_MISC 0x28350
332
333#define TA_CNTL_AUX 0x9508
334#define DISABLE_CUBE_WRAP (1 << 0)
335#define DISABLE_CUBE_ANISO (1 << 1)
336#define SYNC_GRADIENT (1 << 24)
337#define SYNC_WALKER (1 << 25)
338#define SYNC_ALIGNER (1 << 26)
339#define BILINEAR_PRECISION_6_BIT (0 << 31)
340#define BILINEAR_PRECISION_8_BIT (1 << 31)
341
342#define TCP_CNTL 0x9610
9535ab73 343#define TCP_CHAN_STEER 0x9614
3ce0a23d 344
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345#define VC_ENHANCE 0x9714
346
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347#define VGT_CACHE_INVALIDATION 0x88C4
348#define CACHE_INVALIDATION(x) ((x)<<0)
349#define VC_ONLY 0
350#define TC_ONLY 1
351#define VC_AND_TC 2
352#define AUTO_INVLD_EN(x) ((x) << 6)
353#define NO_AUTO 0
354#define ES_AUTO 1
355#define GS_AUTO 2
356#define ES_AND_GS_AUTO 3
357#define VGT_ES_PER_GS 0x88CC
358#define VGT_GS_PER_ES 0x88C8
359#define VGT_GS_PER_VS 0x88E8
360#define VGT_GS_VERTEX_REUSE 0x88D4
361#define VGT_NUM_INSTANCES 0x8974
362#define VGT_OUT_DEALLOC_CNTL 0x28C5C
363#define DEALLOC_DIST_MASK 0x0000007F
364#define VGT_STRMOUT_EN 0x28AB0
365#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
366#define VTX_REUSE_DEPTH_MASK 0x000000FF
367
368#define VM_CONTEXT0_CNTL 0x1410
369#define ENABLE_CONTEXT (1 << 0)
370#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
371#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
372#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
373#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
374#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
375#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
376#define VM_L2_CNTL 0x1400
377#define ENABLE_L2_CACHE (1 << 0)
378#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
379#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
380#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
381#define VM_L2_CNTL2 0x1404
382#define INVALIDATE_ALL_L1_TLBS (1 << 0)
383#define INVALIDATE_L2_CACHE (1 << 1)
384#define VM_L2_CNTL3 0x1408
385#define BANK_SELECT(x) ((x) << 0)
386#define CACHE_UPDATE_MODE(x) ((x) << 6)
387#define VM_L2_STATUS 0x140C
388#define L2_BUSY (1 << 0)
389
390#define WAIT_UNTIL 0x8040
391
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392/* async DMA */
393#define DMA_RB_RPTR 0xd008
394#define DMA_RB_WPTR 0xd00c
395
396/* async DMA packets */
397#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
398 (((t) & 0x1) << 23) | \
399 (((s) & 0x1) << 22) | \
400 (((n) & 0xFFFF) << 0))
401/* async DMA Packet types */
402#define DMA_PACKET_WRITE 0x2
403#define DMA_PACKET_COPY 0x3
404#define DMA_PACKET_INDIRECT_BUFFER 0x4
405#define DMA_PACKET_SEMAPHORE 0x5
406#define DMA_PACKET_FENCE 0x6
407#define DMA_PACKET_TRAP 0x7
408#define DMA_PACKET_CONSTANT_FILL 0xd
409#define DMA_PACKET_NOP 0xf
410
411
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412#define SRBM_STATUS 0x0E50
413
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414/* DCE 3.2 HDMI */
415#define HDMI_CONTROL 0x7400
416# define HDMI_KEEPOUT_MODE (1 << 0)
417# define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */
418# define HDMI_ERROR_ACK (1 << 8)
419# define HDMI_ERROR_MASK (1 << 9)
420#define HDMI_STATUS 0x7404
421# define HDMI_ACTIVE_AVMUTE (1 << 0)
422# define HDMI_AUDIO_PACKET_ERROR (1 << 16)
423# define HDMI_VBI_PACKET_ERROR (1 << 20)
424#define HDMI_AUDIO_PACKET_CONTROL 0x7408
425# define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4)
426# define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)
427#define HDMI_ACR_PACKET_CONTROL 0x740c
428# define HDMI_ACR_SEND (1 << 0)
429# define HDMI_ACR_CONT (1 << 1)
430# define HDMI_ACR_SELECT(x) (((x) & 3) << 4)
431# define HDMI_ACR_HW 0
432# define HDMI_ACR_32 1
433# define HDMI_ACR_44 2
434# define HDMI_ACR_48 3
435# define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
436# define HDMI_ACR_AUTO_SEND (1 << 12)
437#define HDMI_VBI_PACKET_CONTROL 0x7410
438# define HDMI_NULL_SEND (1 << 0)
439# define HDMI_GC_SEND (1 << 4)
440# define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
441#define HDMI_INFOFRAME_CONTROL0 0x7414
442# define HDMI_AVI_INFO_SEND (1 << 0)
443# define HDMI_AVI_INFO_CONT (1 << 1)
444# define HDMI_AUDIO_INFO_SEND (1 << 4)
445# define HDMI_AUDIO_INFO_CONT (1 << 5)
446# define HDMI_MPEG_INFO_SEND (1 << 8)
447# define HDMI_MPEG_INFO_CONT (1 << 9)
448#define HDMI_INFOFRAME_CONTROL1 0x7418
449# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
450# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
451# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
452#define HDMI_GENERIC_PACKET_CONTROL 0x741c
453# define HDMI_GENERIC0_SEND (1 << 0)
454# define HDMI_GENERIC0_CONT (1 << 1)
455# define HDMI_GENERIC1_SEND (1 << 4)
456# define HDMI_GENERIC1_CONT (1 << 5)
457# define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16)
458# define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24)
459#define HDMI_GC 0x7428
460# define HDMI_GC_AVMUTE (1 << 0)
461#define AFMT_AUDIO_PACKET_CONTROL2 0x742c
462# define AFMT_AUDIO_LAYOUT_OVRD (1 << 0)
463# define AFMT_AUDIO_LAYOUT_SELECT (1 << 1)
464# define AFMT_60958_CS_SOURCE (1 << 4)
465# define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8)
466# define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16)
467#define AFMT_AVI_INFO0 0x7454
468# define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
469# define AFMT_AVI_INFO_S(x) (((x) & 3) << 8)
470# define AFMT_AVI_INFO_B(x) (((x) & 3) << 10)
471# define AFMT_AVI_INFO_A(x) (((x) & 1) << 12)
472# define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13)
473# define AFMT_AVI_INFO_Y_RGB 0
474# define AFMT_AVI_INFO_Y_YCBCR422 1
475# define AFMT_AVI_INFO_Y_YCBCR444 2
476# define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)
477# define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16)
478# define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20)
479# define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22)
480# define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)
481# define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24)
482# define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26)
483# define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28)
484# define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31)
485# define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)
486#define AFMT_AVI_INFO1 0x7458
487# define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
488# define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
489# define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)
490#define AFMT_AVI_INFO2 0x745c
491# define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)
492# define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)
493#define AFMT_AVI_INFO3 0x7460
494# define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)
495# define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24)
496#define AFMT_MPEG_INFO0 0x7464
497# define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
498# define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)
499# define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)
500# define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)
501#define AFMT_MPEG_INFO1 0x7468
502# define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)
503# define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8)
504# define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12)
505#define AFMT_GENERIC0_HDR 0x746c
506#define AFMT_GENERIC0_0 0x7470
507#define AFMT_GENERIC0_1 0x7474
508#define AFMT_GENERIC0_2 0x7478
509#define AFMT_GENERIC0_3 0x747c
510#define AFMT_GENERIC0_4 0x7480
511#define AFMT_GENERIC0_5 0x7484
512#define AFMT_GENERIC0_6 0x7488
513#define AFMT_GENERIC1_HDR 0x748c
514#define AFMT_GENERIC1_0 0x7490
515#define AFMT_GENERIC1_1 0x7494
516#define AFMT_GENERIC1_2 0x7498
517#define AFMT_GENERIC1_3 0x749c
518#define AFMT_GENERIC1_4 0x74a0
519#define AFMT_GENERIC1_5 0x74a4
520#define AFMT_GENERIC1_6 0x74a8
521#define HDMI_ACR_32_0 0x74ac
522# define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
523#define HDMI_ACR_32_1 0x74b0
524# define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0)
525#define HDMI_ACR_44_0 0x74b4
526# define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12)
527#define HDMI_ACR_44_1 0x74b8
528# define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0)
529#define HDMI_ACR_48_0 0x74bc
530# define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
531#define HDMI_ACR_48_1 0x74c0
532# define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0)
533#define HDMI_ACR_STATUS_0 0x74c4
534#define HDMI_ACR_STATUS_1 0x74c8
535#define AFMT_AUDIO_INFO0 0x74cc
536# define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
537# define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8)
538# define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16)
539#define AFMT_AUDIO_INFO1 0x74d0
540# define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)
541# define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)
542# define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)
543# define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)
544#define AFMT_60958_0 0x74d4
545# define AFMT_60958_CS_A(x) (((x) & 1) << 0)
546# define AFMT_60958_CS_B(x) (((x) & 1) << 1)
547# define AFMT_60958_CS_C(x) (((x) & 1) << 2)
548# define AFMT_60958_CS_D(x) (((x) & 3) << 3)
549# define AFMT_60958_CS_MODE(x) (((x) & 3) << 6)
550# define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)
551# define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)
552# define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)
553# define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
554# define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)
555#define AFMT_60958_1 0x74d8
556# define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)
557# define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)
558# define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16)
559# define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18)
560# define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)
561#define AFMT_AUDIO_CRC_CONTROL 0x74dc
562# define AFMT_AUDIO_CRC_EN (1 << 0)
563#define AFMT_RAMP_CONTROL0 0x74e0
564# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
565# define AFMT_RAMP_DATA_SIGN (1 << 31)
566#define AFMT_RAMP_CONTROL1 0x74e4
567# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
568# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)
569#define AFMT_RAMP_CONTROL2 0x74e8
570# define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)
571#define AFMT_RAMP_CONTROL3 0x74ec
572# define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)
573#define AFMT_60958_2 0x74f0
574# define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)
575# define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)
576# define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)
577# define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)
578# define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)
579# define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)
580#define AFMT_STATUS 0x7600
581# define AFMT_AUDIO_ENABLE (1 << 4)
582# define AFMT_AZ_FORMAT_WTRIG (1 << 28)
583# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)
584# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)
585#define AFMT_AUDIO_PACKET_CONTROL 0x7604
586# define AFMT_AUDIO_SAMPLE_SEND (1 << 0)
587# define AFMT_AUDIO_TEST_EN (1 << 12)
588# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)
589# define AFMT_60958_CS_UPDATE (1 << 26)
590# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
591# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)
592# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
593# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
594#define AFMT_VBI_PACKET_CONTROL 0x7608
595# define AFMT_GENERIC0_UPDATE (1 << 2)
596#define AFMT_INFOFRAME_CONTROL0 0x760c
597# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */
598# define AFMT_AUDIO_INFO_UPDATE (1 << 7)
599# define AFMT_MPEG_INFO_UPDATE (1 << 10)
600#define AFMT_GENERIC0_7 0x7610
601/* second instance starts at 0x7800 */
602#define HDMI_OFFSET0 (0x7400 - 0x7400)
603#define HDMI_OFFSET1 (0x7800 - 0x7400)
604
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605/* DCE3.2 ELD audio interface */
606#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */
607#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */
608#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */
609#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */
610#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */
611#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */
612#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */
613#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */
614#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */
615#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */
616#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */
617#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */
618#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */
619#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */
620# define MAX_CHANNELS(x) (((x) & 0x7) << 0)
621/* max channels minus one. 7 = 8 channels */
622# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
623# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
624# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
625/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
626 * bit0 = 32 kHz
627 * bit1 = 44.1 kHz
628 * bit2 = 48 kHz
629 * bit3 = 88.2 kHz
630 * bit4 = 96 kHz
631 * bit5 = 176.4 kHz
632 * bit6 = 192 kHz
633 */
634
635#define AZ_HOT_PLUG_CONTROL 0x7300
636# define AZ_FORCE_CODEC_WAKE (1 << 0)
637# define PIN0_JACK_DETECTION_ENABLE (1 << 4)
638# define PIN1_JACK_DETECTION_ENABLE (1 << 5)
639# define PIN2_JACK_DETECTION_ENABLE (1 << 6)
640# define PIN3_JACK_DETECTION_ENABLE (1 << 7)
641# define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8)
642# define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9)
643# define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10)
644# define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11)
645# define CODEC_HOT_PLUG_ENABLE (1 << 12)
646# define PIN0_AUDIO_ENABLED (1 << 24)
647# define PIN1_AUDIO_ENABLED (1 << 25)
648# define PIN2_AUDIO_ENABLED (1 << 26)
649# define PIN3_AUDIO_ENABLED (1 << 27)
650# define AUDIO_ENABLED (1 << 31)
651
652
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653#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
654#define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
655#define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
656#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
657#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
658#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
659
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660/* PCIE link stuff */
661#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
662#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
663# define LC_LINK_WIDTH_SHIFT 0
664# define LC_LINK_WIDTH_MASK 0x7
665# define LC_LINK_WIDTH_X0 0
666# define LC_LINK_WIDTH_X1 1
667# define LC_LINK_WIDTH_X2 2
668# define LC_LINK_WIDTH_X4 3
669# define LC_LINK_WIDTH_X8 4
670# define LC_LINK_WIDTH_X16 6
671# define LC_LINK_WIDTH_RD_SHIFT 4
672# define LC_LINK_WIDTH_RD_MASK 0x70
673# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
674# define LC_RECONFIG_NOW (1 << 8)
675# define LC_RENEGOTIATION_SUPPORT (1 << 9)
676# define LC_RENEGOTIATE_EN (1 << 10)
677# define LC_SHORT_RECONFIG_EN (1 << 11)
678# define LC_UPCONFIGURE_SUPPORT (1 << 12)
679# define LC_UPCONFIGURE_DIS (1 << 13)
680#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
681# define LC_GEN2_EN_STRAP (1 << 0)
682# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
683# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
684# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
685# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
686# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
687# define LC_CURRENT_DATA_RATE (1 << 11)
688# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
689# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
690# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
691# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
692#define MM_CFGREGS_CNTL 0x544c
693# define MM_WR_TO_CFG_EN (1 << 3)
694#define LINK_CNTL2 0x88 /* F0 */
695# define TARGET_LINK_SPEED_MASK (0xf << 0)
696# define SELECTABLE_DEEMPHASIS (1 << 6)
697
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698/* UVD */
699#define UVD_LMI_EXT40_ADDR 0xf498
700#define UVD_VCPU_CHIP_ID 0xf4d4
701#define UVD_VCPU_CACHE_OFFSET0 0xf4d8
702#define UVD_VCPU_CACHE_SIZE0 0xf4dc
703#define UVD_VCPU_CACHE_OFFSET1 0xf4e0
704#define UVD_VCPU_CACHE_SIZE1 0xf4e4
705#define UVD_VCPU_CACHE_OFFSET2 0xf4e8
706#define UVD_VCPU_CACHE_SIZE2 0xf4ec
707#define UVD_LMI_ADDR_EXT 0xf594
708
709#define UVD_RBC_RB_RPTR 0xf690
710#define UVD_RBC_RB_WPTR 0xf694
711
3ce0a23d 712#endif