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drm/radeon/kms/evergreen: setup and enable the CP
[linux-2.6-block.git] / drivers / gpu / drm / radeon / rv770.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
3ce0a23d
JG		 28#include <linux/firmware.h>
29#include <linux/platform_device.h>
771fe6b9 30#include "drmP.h"
771fe6b9 31#include "radeon.h"
e6990375 32#include "radeon_asic.h"
4153e584 33#include "radeon_drm.h"
3ce0a23d 34#include "rv770d.h"
3ce0a23d 35#include "atom.h"
d39c3b89 36#include "avivod.h"
771fe6b9 37
3ce0a23d
JG		 38#define R700_PFP_UCODE_SIZE 848
39#define R700_PM4_UCODE_SIZE 1360
771fe6b9 40
3ce0a23d
JG		 41static void rv770_gpu_init(struct radeon_device *rdev);
42void rv770_fini(struct radeon_device *rdev);
771fe6b9
JG		 43
44
45/*
3ce0a23d 46 * GART
771fe6b9 47 */
3ce0a23d 48int rv770_pcie_gart_enable(struct radeon_device *rdev)
771fe6b9 49{
3ce0a23d
JG		 50 u32 tmp;
51 int r, i;
771fe6b9 52
4aac0473
JG		 53 if (rdev->gart.table.vram.robj == NULL) {
54 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
55 return -EINVAL;
3ce0a23d 56 }
4aac0473
JG		 57 r = radeon_gart_table_vram_pin(rdev);
58 if (r)
3ce0a23d 59 return r;
82568565 60 radeon_gart_restore(rdev);
3ce0a23d
JG		 61 /* Setup L2 cache */
62 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
63 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
64 EFFECTIVE_L2_QUEUE_SIZE(7));
65 WREG32(VM_L2_CNTL2, 0);
66 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
67 /* Setup TLB control */
68 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
69 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
70 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
71 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
72 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
73 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
74 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
75 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
76 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
77 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
78 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
79 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 80 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 81 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
82 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
83 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
84 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
85 (u32)(rdev->dummy_page.addr >> 12));
86 for (i = 1; i < 7; i++)
87 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 88
3ce0a23d
JG		 89 r600_pcie_gart_tlb_flush(rdev);
90 rdev->gart.ready = true;
771fe6b9
JG		 91 return 0;
92}
93
3ce0a23d 94void rv770_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 95{
3ce0a23d 96 u32 tmp;
4c788679 97 int i, r;
3ce0a23d 98
3ce0a23d
JG		 99 /* Disable all tables */
100 for (i = 0; i < 7; i++)
101 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
102
103 /* Setup L2 cache */
104 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
105 EFFECTIVE_L2_QUEUE_SIZE(7));
106 WREG32(VM_L2_CNTL2, 0);
107 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
108 /* Setup TLB control */
109 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
110 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
111 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
112 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
113 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
114 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
115 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
116 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
4aac0473 117 if (rdev->gart.table.vram.robj) {
4c788679
JG		 118 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
119 if (likely(r == 0)) {
120 radeon_bo_kunmap(rdev->gart.table.vram.robj);
121 radeon_bo_unpin(rdev->gart.table.vram.robj);
122 radeon_bo_unreserve(rdev->gart.table.vram.robj);
123 }
4aac0473
JG		 124 }
125}
126
127void rv770_pcie_gart_fini(struct radeon_device *rdev)
128{
f9274562 129 radeon_gart_fini(rdev);
4aac0473
JG		 130 rv770_pcie_gart_disable(rdev);
131 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 132}
133
134
1a029b76
JG		 135void rv770_agp_enable(struct radeon_device *rdev)
136{
137 u32 tmp;
138 int i;
139
140 /* Setup L2 cache */
141 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
142 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
143 EFFECTIVE_L2_QUEUE_SIZE(7));
144 WREG32(VM_L2_CNTL2, 0);
145 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
146 /* Setup TLB control */
147 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
148 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
149 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
150 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
151 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
152 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
153 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
154 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
155 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
156 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
157 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
158 for (i = 0; i < 7; i++)
159 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
160}
161
a3c1945a 162static void rv770_mc_program(struct radeon_device *rdev)
771fe6b9 163{
a3c1945a 164 struct rv515_mc_save save;
3ce0a23d
JG		 165 u32 tmp;
166 int i, j;
167
168 /* Initialize HDP */
169 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
170 WREG32((0x2c14 + j), 0x00000000);
171 WREG32((0x2c18 + j), 0x00000000);
172 WREG32((0x2c1c + j), 0x00000000);
173 WREG32((0x2c20 + j), 0x00000000);
174 WREG32((0x2c24 + j), 0x00000000);
175 }
176 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
177
a3c1945a 178 rv515_mc_stop(rdev, &save);
3ce0a23d 179 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 180 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 181 }
3ce0a23d
JG		 182 /* Lockout access through VGA aperture*/
183 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 184 /* Update configuration */
1a029b76
JG		 185 if (rdev->flags & RADEON_IS_AGP) {
186 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
187 /* VRAM before AGP */
188 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
189 rdev->mc.vram_start >> 12);
190 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
191 rdev->mc.gtt_end >> 12);
192 } else {
193 /* VRAM after AGP */
194 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
195 rdev->mc.gtt_start >> 12);
196 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
197 rdev->mc.vram_end >> 12);
198 }
199 } else {
200 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
201 rdev->mc.vram_start >> 12);
202 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
203 rdev->mc.vram_end >> 12);
204 }
3ce0a23d 205 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 206 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 207 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
208 WREG32(MC_VM_FB_LOCATION, tmp);
209 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
210 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
211 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
212 if (rdev->flags & RADEON_IS_AGP) {
1a029b76 213 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
3ce0a23d
JG		 214 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
215 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
216 } else {
217 WREG32(MC_VM_AGP_BASE, 0);
218 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
219 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
220 }
3ce0a23d 221 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 222 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 223 }
a3c1945a 224 rv515_mc_resume(rdev, &save);
698443d9
DA		 225 /* we need to own VRAM, so turn off the VGA renderer here
226 * to stop it overwriting our objects */
d39c3b89 227 rv515_vga_render_disable(rdev);
771fe6b9
JG		 228}
229
3ce0a23d
JG		 230
231/*
232 * CP.
233 */
234void r700_cp_stop(struct radeon_device *rdev)
771fe6b9 235{
3ce0a23d 236 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
771fe6b9
JG		 237}
238
3ce0a23d 239static int rv770_cp_load_microcode(struct radeon_device *rdev)
771fe6b9 240{
3ce0a23d
JG		 241 const __be32 *fw_data;
242 int i;
243
244 if (!rdev->me_fw || !rdev->pfp_fw)
245 return -EINVAL;
246
247 r700_cp_stop(rdev);
248 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
249
250 /* Reset cp */
251 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
252 RREG32(GRBM_SOFT_RESET);
253 mdelay(15);
254 WREG32(GRBM_SOFT_RESET, 0);
255
256 fw_data = (const __be32 *)rdev->pfp_fw->data;
257 WREG32(CP_PFP_UCODE_ADDR, 0);
258 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
259 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
260 WREG32(CP_PFP_UCODE_ADDR, 0);
261
262 fw_data = (const __be32 *)rdev->me_fw->data;
263 WREG32(CP_ME_RAM_WADDR, 0);
264 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
265 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
266
267 WREG32(CP_PFP_UCODE_ADDR, 0);
268 WREG32(CP_ME_RAM_WADDR, 0);
269 WREG32(CP_ME_RAM_RADDR, 0);
270 return 0;
771fe6b9
JG		 271}
272
fe251e2f
AD		 273void r700_cp_fini(struct radeon_device *rdev)
274{
275 r700_cp_stop(rdev);
276 radeon_ring_fini(rdev);
277}
771fe6b9
JG		 278
279/*
3ce0a23d 280 * Core functions
771fe6b9 281 */
d03f5d59
AD		 282static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
283 u32 num_tile_pipes,
284 u32 num_backends,
285 u32 backend_disable_mask)
771fe6b9 286{
3ce0a23d
JG		 287 u32 backend_map = 0;
288 u32 enabled_backends_mask;
289 u32 enabled_backends_count;
290 u32 cur_pipe;
291 u32 swizzle_pipe[R7XX_MAX_PIPES];
292 u32 cur_backend;
293 u32 i;
d03f5d59 294 bool force_no_swizzle;
3ce0a23d
JG		 295
296 if (num_tile_pipes > R7XX_MAX_PIPES)
297 num_tile_pipes = R7XX_MAX_PIPES;
298 if (num_tile_pipes < 1)
299 num_tile_pipes = 1;
300 if (num_backends > R7XX_MAX_BACKENDS)
301 num_backends = R7XX_MAX_BACKENDS;
302 if (num_backends < 1)
303 num_backends = 1;
304
305 enabled_backends_mask = 0;
306 enabled_backends_count = 0;
307 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
308 if (((backend_disable_mask >> i) & 1) == 0) {
309 enabled_backends_mask |= (1 << i);
310 ++enabled_backends_count;
311 }
312 if (enabled_backends_count == num_backends)
313 break;
314 }
315
316 if (enabled_backends_count == 0) {
317 enabled_backends_mask = 1;
318 enabled_backends_count = 1;
319 }
320
321 if (enabled_backends_count != num_backends)
322 num_backends = enabled_backends_count;
323
d03f5d59
AD		 324 switch (rdev->family) {
325 case CHIP_RV770:
326 case CHIP_RV730:
327 force_no_swizzle = false;
328 break;
329 case CHIP_RV710:
330 case CHIP_RV740:
331 default:
332 force_no_swizzle = true;
333 break;
334 }
335
3ce0a23d
JG		 336 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
337 switch (num_tile_pipes) {
338 case 1:
339 swizzle_pipe[0] = 0;
340 break;
341 case 2:
342 swizzle_pipe[0] = 0;
343 swizzle_pipe[1] = 1;
344 break;
345 case 3:
d03f5d59
AD		 346 if (force_no_swizzle) {
347 swizzle_pipe[0] = 0;
348 swizzle_pipe[1] = 1;
349 swizzle_pipe[2] = 2;
350 } else {
351 swizzle_pipe[0] = 0;
352 swizzle_pipe[1] = 2;
353 swizzle_pipe[2] = 1;
354 }
3ce0a23d
JG		 355 break;
356 case 4:
d03f5d59
AD		 357 if (force_no_swizzle) {
358 swizzle_pipe[0] = 0;
359 swizzle_pipe[1] = 1;
360 swizzle_pipe[2] = 2;
361 swizzle_pipe[3] = 3;
362 } else {
363 swizzle_pipe[0] = 0;
364 swizzle_pipe[1] = 2;
365 swizzle_pipe[2] = 3;
366 swizzle_pipe[3] = 1;
367 }
3ce0a23d
JG		 368 break;
369 case 5:
d03f5d59
AD		 370 if (force_no_swizzle) {
371 swizzle_pipe[0] = 0;
372 swizzle_pipe[1] = 1;
373 swizzle_pipe[2] = 2;
374 swizzle_pipe[3] = 3;
375 swizzle_pipe[4] = 4;
376 } else {
377 swizzle_pipe[0] = 0;
378 swizzle_pipe[1] = 2;
379 swizzle_pipe[2] = 4;
380 swizzle_pipe[3] = 1;
381 swizzle_pipe[4] = 3;
382 }
3ce0a23d
JG		 383 break;
384 case 6:
d03f5d59
AD		 385 if (force_no_swizzle) {
386 swizzle_pipe[0] = 0;
387 swizzle_pipe[1] = 1;
388 swizzle_pipe[2] = 2;
389 swizzle_pipe[3] = 3;
390 swizzle_pipe[4] = 4;
391 swizzle_pipe[5] = 5;
392 } else {
393 swizzle_pipe[0] = 0;
394 swizzle_pipe[1] = 2;
395 swizzle_pipe[2] = 4;
396 swizzle_pipe[3] = 5;
397 swizzle_pipe[4] = 3;
398 swizzle_pipe[5] = 1;
399 }
3ce0a23d
JG		 400 break;
401 case 7:
d03f5d59
AD		 402 if (force_no_swizzle) {
403 swizzle_pipe[0] = 0;
404 swizzle_pipe[1] = 1;
405 swizzle_pipe[2] = 2;
406 swizzle_pipe[3] = 3;
407 swizzle_pipe[4] = 4;
408 swizzle_pipe[5] = 5;
409 swizzle_pipe[6] = 6;
410 } else {
411 swizzle_pipe[0] = 0;
412 swizzle_pipe[1] = 2;
413 swizzle_pipe[2] = 4;
414 swizzle_pipe[3] = 6;
415 swizzle_pipe[4] = 3;
416 swizzle_pipe[5] = 1;
417 swizzle_pipe[6] = 5;
418 }
3ce0a23d
JG		 419 break;
420 case 8:
d03f5d59
AD		 421 if (force_no_swizzle) {
422 swizzle_pipe[0] = 0;
423 swizzle_pipe[1] = 1;
424 swizzle_pipe[2] = 2;
425 swizzle_pipe[3] = 3;
426 swizzle_pipe[4] = 4;
427 swizzle_pipe[5] = 5;
428 swizzle_pipe[6] = 6;
429 swizzle_pipe[7] = 7;
430 } else {
431 swizzle_pipe[0] = 0;
432 swizzle_pipe[1] = 2;
433 swizzle_pipe[2] = 4;
434 swizzle_pipe[3] = 6;
435 swizzle_pipe[4] = 3;
436 swizzle_pipe[5] = 1;
437 swizzle_pipe[6] = 7;
438 swizzle_pipe[7] = 5;
439 }
3ce0a23d
JG		 440 break;
441 }
442
443 cur_backend = 0;
444 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
445 while (((1 << cur_backend) & enabled_backends_mask) == 0)
446 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
447
448 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
449
450 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
451 }
452
453 return backend_map;
771fe6b9
JG		 454}
455
3ce0a23d 456static void rv770_gpu_init(struct radeon_device *rdev)
771fe6b9 457{
3ce0a23d 458 int i, j, num_qd_pipes;
d03f5d59 459 u32 ta_aux_cntl;
3ce0a23d
JG		 460 u32 sx_debug_1;
461 u32 smx_dc_ctl0;
d03f5d59 462 u32 db_debug3;
3ce0a23d
JG		 463 u32 num_gs_verts_per_thread;
464 u32 vgt_gs_per_es;
465 u32 gs_prim_buffer_depth = 0;
466 u32 sq_ms_fifo_sizes;
467 u32 sq_config;
468 u32 sq_thread_resource_mgmt;
469 u32 hdp_host_path_cntl;
470 u32 sq_dyn_gpr_size_simd_ab_0;
471 u32 backend_map;
472 u32 gb_tiling_config = 0;
473 u32 cc_rb_backend_disable = 0;
474 u32 cc_gc_shader_pipe_config = 0;
475 u32 mc_arb_ramcfg;
476 u32 db_debug4;
771fe6b9 477
3ce0a23d
JG		 478 /* setup chip specs */
479 switch (rdev->family) {
480 case CHIP_RV770:
481 rdev->config.rv770.max_pipes = 4;
482 rdev->config.rv770.max_tile_pipes = 8;
483 rdev->config.rv770.max_simds = 10;
484 rdev->config.rv770.max_backends = 4;
485 rdev->config.rv770.max_gprs = 256;
486 rdev->config.rv770.max_threads = 248;
487 rdev->config.rv770.max_stack_entries = 512;
488 rdev->config.rv770.max_hw_contexts = 8;
489 rdev->config.rv770.max_gs_threads = 16 * 2;
490 rdev->config.rv770.sx_max_export_size = 128;
491 rdev->config.rv770.sx_max_export_pos_size = 16;
492 rdev->config.rv770.sx_max_export_smx_size = 112;
493 rdev->config.rv770.sq_num_cf_insts = 2;
494
495 rdev->config.rv770.sx_num_of_sets = 7;
496 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
497 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
498 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
499 break;
500 case CHIP_RV730:
501 rdev->config.rv770.max_pipes = 2;
502 rdev->config.rv770.max_tile_pipes = 4;
503 rdev->config.rv770.max_simds = 8;
504 rdev->config.rv770.max_backends = 2;
505 rdev->config.rv770.max_gprs = 128;
506 rdev->config.rv770.max_threads = 248;
507 rdev->config.rv770.max_stack_entries = 256;
508 rdev->config.rv770.max_hw_contexts = 8;
509 rdev->config.rv770.max_gs_threads = 16 * 2;
510 rdev->config.rv770.sx_max_export_size = 256;
511 rdev->config.rv770.sx_max_export_pos_size = 32;
512 rdev->config.rv770.sx_max_export_smx_size = 224;
513 rdev->config.rv770.sq_num_cf_insts = 2;
514
515 rdev->config.rv770.sx_num_of_sets = 7;
516 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
517 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
518 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
519 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
520 rdev->config.rv770.sx_max_export_pos_size -= 16;
521 rdev->config.rv770.sx_max_export_smx_size += 16;
522 }
523 break;
524 case CHIP_RV710:
525 rdev->config.rv770.max_pipes = 2;
526 rdev->config.rv770.max_tile_pipes = 2;
527 rdev->config.rv770.max_simds = 2;
528 rdev->config.rv770.max_backends = 1;
529 rdev->config.rv770.max_gprs = 256;
530 rdev->config.rv770.max_threads = 192;
531 rdev->config.rv770.max_stack_entries = 256;
532 rdev->config.rv770.max_hw_contexts = 4;
533 rdev->config.rv770.max_gs_threads = 8 * 2;
534 rdev->config.rv770.sx_max_export_size = 128;
535 rdev->config.rv770.sx_max_export_pos_size = 16;
536 rdev->config.rv770.sx_max_export_smx_size = 112;
537 rdev->config.rv770.sq_num_cf_insts = 1;
538
539 rdev->config.rv770.sx_num_of_sets = 7;
540 rdev->config.rv770.sc_prim_fifo_size = 0x40;
541 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
542 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
543 break;
544 case CHIP_RV740:
545 rdev->config.rv770.max_pipes = 4;
546 rdev->config.rv770.max_tile_pipes = 4;
547 rdev->config.rv770.max_simds = 8;
548 rdev->config.rv770.max_backends = 4;
549 rdev->config.rv770.max_gprs = 256;
550 rdev->config.rv770.max_threads = 248;
551 rdev->config.rv770.max_stack_entries = 512;
552 rdev->config.rv770.max_hw_contexts = 8;
553 rdev->config.rv770.max_gs_threads = 16 * 2;
554 rdev->config.rv770.sx_max_export_size = 256;
555 rdev->config.rv770.sx_max_export_pos_size = 32;
556 rdev->config.rv770.sx_max_export_smx_size = 224;
557 rdev->config.rv770.sq_num_cf_insts = 2;
558
559 rdev->config.rv770.sx_num_of_sets = 7;
560 rdev->config.rv770.sc_prim_fifo_size = 0x100;
561 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
562 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
563
564 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
565 rdev->config.rv770.sx_max_export_pos_size -= 16;
566 rdev->config.rv770.sx_max_export_smx_size += 16;
567 }
568 break;
569 default:
570 break;
571 }
572
573 /* Initialize HDP */
574 j = 0;
575 for (i = 0; i < 32; i++) {
576 WREG32((0x2c14 + j), 0x00000000);
577 WREG32((0x2c18 + j), 0x00000000);
578 WREG32((0x2c1c + j), 0x00000000);
579 WREG32((0x2c20 + j), 0x00000000);
580 WREG32((0x2c24 + j), 0x00000000);
581 j += 0x18;
582 }
583
584 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
585
586 /* setup tiling, simd, pipe config */
587 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
588
589 switch (rdev->config.rv770.max_tile_pipes) {
590 case 1:
d03f5d59 591 default:
3ce0a23d
JG		 592 gb_tiling_config |= PIPE_TILING(0);
593 break;
594 case 2:
595 gb_tiling_config |= PIPE_TILING(1);
596 break;
597 case 4:
598 gb_tiling_config |= PIPE_TILING(2);
599 break;
600 case 8:
601 gb_tiling_config |= PIPE_TILING(3);
3ce0a23d
JG		 602 break;
603 }
d03f5d59 604 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
3ce0a23d
JG		 605
606 if (rdev->family == CHIP_RV770)
607 gb_tiling_config |= BANK_TILING(1);
608 else
e29649db 609 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
961fb597 610 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
3ce0a23d
JG		 611
612 gb_tiling_config |= GROUP_SIZE(0);
961fb597 613 rdev->config.rv770.tiling_group_size = 256;
3ce0a23d 614
e29649db 615 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
3ce0a23d
JG		 616 gb_tiling_config |= ROW_TILING(3);
617 gb_tiling_config |= SAMPLE_SPLIT(3);
618 } else {
619 gb_tiling_config |=
620 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
621 gb_tiling_config |=
622 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
623 }
624
625 gb_tiling_config |= BANK_SWAPS(1);
626
d03f5d59
AD		 627 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
628 cc_rb_backend_disable |=
629 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
3ce0a23d 630
d03f5d59
AD		 631 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
632 cc_gc_shader_pipe_config |=
3ce0a23d
JG		 633 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
634 cc_gc_shader_pipe_config |=
635 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
636
d03f5d59
AD		 637 if (rdev->family == CHIP_RV740)
638 backend_map = 0x28;
639 else
640 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
641 rdev->config.rv770.max_tile_pipes,
642 (R7XX_MAX_BACKENDS -
643 r600_count_pipe_bits((cc_rb_backend_disable &
644 R7XX_MAX_BACKENDS_MASK) >> 16)),
645 (cc_rb_backend_disable >> 16));
646 gb_tiling_config |= BACKEND_MAP(backend_map);
647
3ce0a23d
JG		 648
649 WREG32(GB_TILING_CONFIG, gb_tiling_config);
650 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
651 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
652
653 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
654 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 655 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
d03f5d59 656 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
3ce0a23d 657
3ce0a23d
JG		 658 WREG32(CGTS_SYS_TCC_DISABLE, 0);
659 WREG32(CGTS_TCC_DISABLE, 0);
f867c60d
AD		 660 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
661 WREG32(CGTS_USER_TCC_DISABLE, 0);
3ce0a23d
JG		 662
663 num_qd_pipes =
d03f5d59 664 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 665 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
666 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
667
668 /* set HW defaults for 3D engine */
669 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
e29649db 670 ROQ_IB2_START(0x2b)));
3ce0a23d
JG		 671
672 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
673
d03f5d59
AD		 674 ta_aux_cntl = RREG32(TA_CNTL_AUX);
675 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
3ce0a23d
JG		 676
677 sx_debug_1 = RREG32(SX_DEBUG_1);
678 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
679 WREG32(SX_DEBUG_1, sx_debug_1);
680
681 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
682 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
683 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
684 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
685
d03f5d59
AD		 686 if (rdev->family != CHIP_RV740)
687 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
688 GS_FLUSH_CTL(4) |
689 ACK_FLUSH_CTL(3) |
690 SYNC_FLUSH_CTL));
3ce0a23d 691
d03f5d59
AD		 692 db_debug3 = RREG32(DB_DEBUG3);
693 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
694 switch (rdev->family) {
695 case CHIP_RV770:
696 case CHIP_RV740:
697 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
698 break;
699 case CHIP_RV710:
700 case CHIP_RV730:
701 default:
702 db_debug3 |= DB_CLK_OFF_DELAY(2);
703 break;
704 }
705 WREG32(DB_DEBUG3, db_debug3);
706
707 if (rdev->family != CHIP_RV770) {
3ce0a23d
JG		 708 db_debug4 = RREG32(DB_DEBUG4);
709 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
710 WREG32(DB_DEBUG4, db_debug4);
711 }
712
713 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
e29649db
AD		 714 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
715 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
3ce0a23d
JG		 716
717 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
e29649db
AD		 718 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
719 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
3ce0a23d
JG		 720
721 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
722
723 WREG32(VGT_NUM_INSTANCES, 1);
724
725 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
726
727 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
728
729 WREG32(CP_PERFMON_CNTL, 0);
730
731 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
732 DONE_FIFO_HIWATER(0xe0) |
733 ALU_UPDATE_FIFO_HIWATER(0x8));
734 switch (rdev->family) {
735 case CHIP_RV770:
3ce0a23d
JG		 736 case CHIP_RV730:
737 case CHIP_RV710:
d03f5d59
AD		 738 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
739 break;
3ce0a23d
JG		 740 case CHIP_RV740:
741 default:
742 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
743 break;
744 }
745 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
746
747 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
748 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
749 */
750 sq_config = RREG32(SQ_CONFIG);
751 sq_config &= ~(PS_PRIO(3) |
752 VS_PRIO(3) |
753 GS_PRIO(3) |
754 ES_PRIO(3));
755 sq_config |= (DX9_CONSTS |
756 VC_ENABLE |
757 EXPORT_SRC_C |
758 PS_PRIO(0) |
759 VS_PRIO(1) |
760 GS_PRIO(2) |
761 ES_PRIO(3));
762 if (rdev->family == CHIP_RV710)
763 /* no vertex cache */
764 sq_config &= ~VC_ENABLE;
765
766 WREG32(SQ_CONFIG, sq_config);
767
768 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
fe62e1a4
DA		 769 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
770 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
3ce0a23d
JG		 771
772 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
fe62e1a4 773 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
3ce0a23d
JG		 774
775 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
776 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
777 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
778 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
779 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
780 else
781 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
782 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
783
784 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
785 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
786
787 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
788 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
789
790 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
791 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
792 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
793 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
794
795 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
796 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
797 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
798 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
799 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
800 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
801 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
802 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
803
804 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
fe62e1a4 805 FORCE_EOV_MAX_REZ_CNT(255)));
3ce0a23d
JG		 806
807 if (rdev->family == CHIP_RV710)
808 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
fe62e1a4 809 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
3ce0a23d
JG		 810 else
811 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
fe62e1a4 812 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
3ce0a23d
JG		 813
814 switch (rdev->family) {
815 case CHIP_RV770:
816 case CHIP_RV730:
817 case CHIP_RV740:
818 gs_prim_buffer_depth = 384;
819 break;
820 case CHIP_RV710:
821 gs_prim_buffer_depth = 128;
822 break;
823 default:
824 break;
825 }
826
827 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
828 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
829 /* Max value for this is 256 */
830 if (vgt_gs_per_es > 256)
831 vgt_gs_per_es = 256;
832
833 WREG32(VGT_ES_PER_GS, 128);
834 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
835 WREG32(VGT_GS_PER_VS, 2);
836
837 /* more default values. 2D/3D driver should adjust as needed */
838 WREG32(VGT_GS_VERTEX_REUSE, 16);
839 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
840 WREG32(VGT_STRMOUT_EN, 0);
841 WREG32(SX_MISC, 0);
842 WREG32(PA_SC_MODE_CNTL, 0);
843 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
844 WREG32(PA_SC_AA_CONFIG, 0);
845 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
846 WREG32(PA_SC_LINE_STIPPLE, 0);
847 WREG32(SPI_INPUT_Z, 0);
848 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
849 WREG32(CB_COLOR7_FRAG, 0);
850
851 /* clear render buffer base addresses */
852 WREG32(CB_COLOR0_BASE, 0);
853 WREG32(CB_COLOR1_BASE, 0);
854 WREG32(CB_COLOR2_BASE, 0);
855 WREG32(CB_COLOR3_BASE, 0);
856 WREG32(CB_COLOR4_BASE, 0);
857 WREG32(CB_COLOR5_BASE, 0);
858 WREG32(CB_COLOR6_BASE, 0);
859 WREG32(CB_COLOR7_BASE, 0);
860
861 WREG32(TCP_CNTL, 0);
862
863 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
864 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
865
866 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
867
868 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
869 NUM_CLIP_SEQ(3)));
870
871}
872
873int rv770_mc_init(struct radeon_device *rdev)
874{
3ce0a23d 875 u32 tmp;
5885b7a9 876 int chansize, numchan;
3ce0a23d
JG		 877
878 /* Get VRAM informations */
3ce0a23d 879 rdev->mc.vram_is_ddr = true;
5885b7a9
AD		 880 tmp = RREG32(MC_ARB_RAMCFG);
881 if (tmp & CHANSIZE_OVERRIDE) {
882 chansize = 16;
883 } else if (tmp & CHANSIZE_MASK) {
884 chansize = 64;
885 } else {
886 chansize = 32;
887 }
888 tmp = RREG32(MC_SHARED_CHMAP);
889 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
890 case 0:
891 default:
892 numchan = 1;
893 break;
894 case 1:
895 numchan = 2;
896 break;
897 case 2:
898 numchan = 4;
899 break;
900 case 3:
901 numchan = 8;
902 break;
903 }
904 rdev->mc.vram_width = numchan * chansize;
771fe6b9
JG		 905 /* Could aper size report 0 ? */
906 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
907 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
3ce0a23d
JG		 908 /* Setup GPU memory space */
909 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
910 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 911 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a
JG		 912 /* FIXME remove this once we support unmappable VRAM */
913 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
974b16e3 914 rdev->mc.mc_vram_size = rdev->mc.aper_size;
974b16e3 915 rdev->mc.real_vram_size = rdev->mc.aper_size;
3ce0a23d 916 }
d594e46a 917 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 918 radeon_update_bandwidth_info(rdev);
919
3ce0a23d
JG		 920 return 0;
921}
d594e46a 922
fc30b8ef 923static int rv770_startup(struct radeon_device *rdev)
3ce0a23d
JG		 924{
925 int r;
926
779720a3
AD		 927 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
928 r = r600_init_microcode(rdev);
929 if (r) {
930 DRM_ERROR("Failed to load firmware!\n");
931 return r;
932 }
933 }
934
a3c1945a 935 rv770_mc_program(rdev);
1a029b76
JG		 936 if (rdev->flags & RADEON_IS_AGP) {
937 rv770_agp_enable(rdev);
938 } else {
939 r = rv770_pcie_gart_enable(rdev);
940 if (r)
941 return r;
942 }
3ce0a23d 943 rv770_gpu_init(rdev);
c38c7b64
JG		 944 r = r600_blit_init(rdev);
945 if (r) {
946 r600_blit_fini(rdev);
947 rdev->asic->copy = NULL;
948 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
949 }
ff82f052
JG		 950 /* pin copy shader into vram */
951 if (rdev->r600_blit.shader_obj) {
952 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
953 if (unlikely(r != 0))
954 return r;
955 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
956 &rdev->r600_blit.shader_gpu_addr);
957 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
7923c615 958 if (r) {
ff82f052 959 DRM_ERROR("failed to pin blit object %d\n", r);
7923c615
AD		 960 return r;
961 }
962 }
d8f60cfc 963 /* Enable IRQ */
d8f60cfc
AD		 964 r = r600_irq_init(rdev);
965 if (r) {
966 DRM_ERROR("radeon: IH init failed (%d).\n", r);
967 radeon_irq_kms_fini(rdev);
968 return r;
969 }
970 r600_irq_set(rdev);
971
3ce0a23d
JG		 972 r = radeon_ring_init(rdev, rdev->cp.ring_size);
973 if (r)
974 return r;
975 r = rv770_cp_load_microcode(rdev);
976 if (r)
977 return r;
978 r = r600_cp_resume(rdev);
979 if (r)
980 return r;
81cc35bf
JG		 981 /* write back buffer are not vital so don't worry about failure */
982 r600_wb_enable(rdev);
3ce0a23d
JG		 983 return 0;
984}
985
fc30b8ef
DA		 986int rv770_resume(struct radeon_device *rdev)
987{
988 int r;
989
1a029b76
JG		 990 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
991 * posting will perform necessary task to bring back GPU into good
992 * shape.
993 */
fc30b8ef 994 /* post card */
e7d40b9a 995 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 996 /* Initialize clocks */
997 r = radeon_clocks_init(rdev);
998 if (r) {
999 return r;
1000 }
1001
1002 r = rv770_startup(rdev);
1003 if (r) {
1004 DRM_ERROR("r600 startup failed on resume\n");
1005 return r;
1006 }
1007
62a8ea3f 1008 r = r600_ib_test(rdev);
fc30b8ef
DA		 1009 if (r) {
1010 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1011 return r;
1012 }
8a8c6e7c
RM		 1013
1014 r = r600_audio_init(rdev);
1015 if (r) {
1016 dev_err(rdev->dev, "radeon: audio init failed\n");
1017 return r;
1018 }
1019
fc30b8ef
DA		 1020 return r;
1021
1022}
1023
3ce0a23d
JG		 1024int rv770_suspend(struct radeon_device *rdev)
1025{
4c788679
JG		 1026 int r;
1027
8a8c6e7c 1028 r600_audio_fini(rdev);
3ce0a23d
JG		 1029 /* FIXME: we should wait for ring to be empty */
1030 r700_cp_stop(rdev);
4153e584 1031 rdev->cp.ready = false;
0c45249f 1032 r600_irq_suspend(rdev);
81cc35bf 1033 r600_wb_disable(rdev);
4aac0473 1034 rv770_pcie_gart_disable(rdev);
4153e584 1035 /* unpin shaders bo */
30d2d9a5
JG		 1036 if (rdev->r600_blit.shader_obj) {
1037 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1038 if (likely(r == 0)) {
1039 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1040 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1041 }
4c788679 1042 }
3ce0a23d
JG		 1043 return 0;
1044}
1045
1046/* Plan is to move initialization in that function and use
1047 * helper function so that radeon_device_init pretty much
1048 * do nothing more than calling asic specific function. This
1049 * should also allow to remove a bunch of callback function
1050 * like vram_info.
1051 */
1052int rv770_init(struct radeon_device *rdev)
1053{
1054 int r;
1055
3ce0a23d
JG		 1056 r = radeon_dummy_page_init(rdev);
1057 if (r)
1058 return r;
1059 /* This don't do much */
1060 r = radeon_gem_init(rdev);
1061 if (r)
1062 return r;
1063 /* Read BIOS */
1064 if (!radeon_get_bios(rdev)) {
1065 if (ASIC_IS_AVIVO(rdev))
1066 return -EINVAL;
1067 }
1068 /* Must be an ATOMBIOS */
e7d40b9a
JG		 1069 if (!rdev->is_atom_bios) {
1070 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 1071 return -EINVAL;
e7d40b9a 1072 }
3ce0a23d
JG		 1073 r = radeon_atombios_init(rdev);
1074 if (r)
1075 return r;
1076 /* Post card if necessary */
72542d77
DA		 1077 if (!r600_card_posted(rdev)) {
1078 if (!rdev->bios) {
1079 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1080 return -EINVAL;
1081 }
3ce0a23d
JG		 1082 DRM_INFO("GPU not posted. posting now...\n");
1083 atom_asic_init(rdev->mode_info.atom_context);
1084 }
1085 /* Initialize scratch registers */
1086 r600_scratch_init(rdev);
1087 /* Initialize surface registers */
1088 radeon_surface_init(rdev);
7433874e 1089 /* Initialize clocks */
5e6dde7e 1090 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 1091 r = radeon_clocks_init(rdev);
1092 if (r)
1093 return r;
7433874e
RM		 1094 /* Initialize power management */
1095 radeon_pm_init(rdev);
3ce0a23d
JG		 1096 /* Fence driver */
1097 r = radeon_fence_driver_init(rdev);
1098 if (r)
1099 return r;
d594e46a 1100 /* initialize AGP */
700a0cc0
JG		 1101 if (rdev->flags & RADEON_IS_AGP) {
1102 r = radeon_agp_init(rdev);
1103 if (r)
1104 radeon_agp_disable(rdev);
1105 }
3ce0a23d 1106 r = rv770_mc_init(rdev);
b574f251 1107 if (r)
3ce0a23d 1108 return r;
3ce0a23d 1109 /* Memory manager */
4c788679 1110 r = radeon_bo_init(rdev);
3ce0a23d
JG		 1111 if (r)
1112 return r;
d8f60cfc
AD		 1113
1114 r = radeon_irq_kms_init(rdev);
1115 if (r)
1116 return r;
1117
3ce0a23d
JG		 1118 rdev->cp.ring_obj = NULL;
1119 r600_ring_init(rdev, 1024 * 1024);
1120
d8f60cfc
AD		 1121 rdev->ih.ring_obj = NULL;
1122 r600_ih_ring_init(rdev, 64 * 1024);
1123
4aac0473
JG		 1124 r = r600_pcie_gart_init(rdev);
1125 if (r)
1126 return r;
1127
779720a3 1128 rdev->accel_working = true;
fc30b8ef 1129 r = rv770_startup(rdev);
3ce0a23d 1130 if (r) {
655efd3d 1131 dev_err(rdev->dev, "disabling GPU acceleration\n");
fe251e2f 1132 r700_cp_fini(rdev);
75c81298 1133 r600_wb_fini(rdev);
655efd3d
JG		 1134 r600_irq_fini(rdev);
1135 radeon_irq_kms_fini(rdev);
75c81298 1136 rv770_pcie_gart_fini(rdev);
733289c2 1137 rdev->accel_working = false;
3ce0a23d 1138 }
733289c2 1139 if (rdev->accel_working) {
733289c2
JG		 1140 r = radeon_ib_pool_init(rdev);
1141 if (r) {
db96380e 1142 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 1143 rdev->accel_working = false;
db96380e
JG		 1144 } else {
1145 r = r600_ib_test(rdev);
1146 if (r) {
1147 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1148 rdev->accel_working = false;
1149 }
733289c2 1150 }
3ce0a23d 1151 }
8a8c6e7c
RM		 1152
1153 r = r600_audio_init(rdev);
1154 if (r) {
1155 dev_err(rdev->dev, "radeon: audio init failed\n");
1156 return r;
1157 }
1158
3ce0a23d
JG		 1159 return 0;
1160}
1161
1162void rv770_fini(struct radeon_device *rdev)
1163{
29fb52ca 1164 radeon_pm_fini(rdev);
3ce0a23d 1165 r600_blit_fini(rdev);
fe251e2f 1166 r700_cp_fini(rdev);
655efd3d 1167 r600_wb_fini(rdev);
d8f60cfc
AD		 1168 r600_irq_fini(rdev);
1169 radeon_irq_kms_fini(rdev);
4aac0473 1170 rv770_pcie_gart_fini(rdev);
3ce0a23d
JG		 1171 radeon_gem_fini(rdev);
1172 radeon_fence_driver_fini(rdev);
1173 radeon_clocks_fini(rdev);
d0269ed8 1174 radeon_agp_fini(rdev);
4c788679 1175 radeon_bo_fini(rdev);
e7d40b9a 1176 radeon_atombios_fini(rdev);
3ce0a23d
JG		 1177 kfree(rdev->bios);
1178 rdev->bios = NULL;
1179 radeon_dummy_page_fini(rdev);
771fe6b9 1180}
Linux 6.x block layer and io_uring tree(s)