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drm/radeon: enable HDMI on DCE5 (AKA NI excluding Aruba)
[linux-block.git] / drivers / gpu / drm / radeon / rv770.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
3ce0a23d
JG		 28#include <linux/firmware.h>
29#include <linux/platform_device.h>
5a0e3ad6 30#include <linux/slab.h>
771fe6b9 31#include "drmP.h"
771fe6b9 32#include "radeon.h"
e6990375 33#include "radeon_asic.h"
4153e584 34#include "radeon_drm.h"
3ce0a23d 35#include "rv770d.h"
3ce0a23d 36#include "atom.h"
d39c3b89 37#include "avivod.h"
771fe6b9 38
3ce0a23d
JG		 39#define R700_PFP_UCODE_SIZE 848
40#define R700_PM4_UCODE_SIZE 1360
771fe6b9 41
3ce0a23d
JG		 42static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev);
9e46a48d 44static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
771fe6b9 45
6f34be50
AD		 46u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
47{
48 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
49 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
f6496479 50 int i;
6f34be50
AD		 51
52 /* Lock the graphics update lock */
53 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
54 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
55
56 /* update the scanout addresses */
57 if (radeon_crtc->crtc_id) {
58 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
59 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
60 } else {
61 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
62 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
63 }
64 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
65 (u32)crtc_base);
66 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
67 (u32)crtc_base);
68
69 /* Wait for update_pending to go high. */
f6496479
AD		 70 for (i = 0; i < rdev->usec_timeout; i++) {
71 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
72 break;
73 udelay(1);
74 }
6f34be50
AD		 75 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
76
77 /* Unlock the lock, so double-buffering can take place inside vblank */
78 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
79 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
80
81 /* Return current update_pending status: */
82 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
83}
84
21a8122a 85/* get temperature in millidegrees */
20d391d7 86int rv770_get_temp(struct radeon_device *rdev)
21a8122a
AD		 87{
88 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
89 ASIC_T_SHIFT;
20d391d7 90 int actual_temp;
21a8122a 91
20d391d7
AD		 92 if (temp & 0x400)
93 actual_temp = -256;
94 else if (temp & 0x200)
95 actual_temp = 255;
96 else if (temp & 0x100) {
97 actual_temp = temp & 0x1ff;
98 actual_temp |= ~0x1ff;
99 } else
100 actual_temp = temp & 0xff;
21a8122a 101
20d391d7 102 return (actual_temp * 1000) / 2;
21a8122a
AD		 103}
104
49e02b73
AD		 105void rv770_pm_misc(struct radeon_device *rdev)
106{
a081a9d6
RM		 107 int req_ps_idx = rdev->pm.requested_power_state_index;
108 int req_cm_idx = rdev->pm.requested_clock_mode_index;
109 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
110 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
4d60173f
AD		 111
112 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
a377e187
AD		 113 /* 0xff01 is a flag rather then an actual voltage */
114 if (voltage->voltage == 0xff01)
115 return;
4d60173f 116 if (voltage->voltage != rdev->pm.current_vddc) {
8a83ec5e 117 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 118 rdev->pm.current_vddc = voltage->voltage;
0fcbe947 119 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 120 }
121 }
49e02b73 122}
771fe6b9
JG		 123
124/*
3ce0a23d 125 * GART
771fe6b9 126 */
3ce0a23d 127int rv770_pcie_gart_enable(struct radeon_device *rdev)
771fe6b9 128{
3ce0a23d
JG		 129 u32 tmp;
130 int r, i;
771fe6b9 131
c9a1be96 132 if (rdev->gart.robj == NULL) {
4aac0473
JG		 133 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
134 return -EINVAL;
3ce0a23d 135 }
4aac0473
JG		 136 r = radeon_gart_table_vram_pin(rdev);
137 if (r)
3ce0a23d 138 return r;
82568565 139 radeon_gart_restore(rdev);
3ce0a23d
JG		 140 /* Setup L2 cache */
141 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
142 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
143 EFFECTIVE_L2_QUEUE_SIZE(7));
144 WREG32(VM_L2_CNTL2, 0);
145 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
146 /* Setup TLB control */
147 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
148 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
149 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
150 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
151 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
152 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
153 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
0b8c30bc
AD		 154 if (rdev->family == CHIP_RV740)
155 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
3ce0a23d
JG		 156 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
157 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
158 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
159 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
160 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 161 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 162 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
163 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
164 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
165 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
166 (u32)(rdev->dummy_page.addr >> 12));
167 for (i = 1; i < 7; i++)
168 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 169
3ce0a23d 170 r600_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 171 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
172 (unsigned)(rdev->mc.gtt_size >> 20),
173 (unsigned long long)rdev->gart.table_addr);
3ce0a23d 174 rdev->gart.ready = true;
771fe6b9
JG		 175 return 0;
176}
177
3ce0a23d 178void rv770_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 179{
3ce0a23d 180 u32 tmp;
c9a1be96 181 int i;
3ce0a23d 182
3ce0a23d
JG		 183 /* Disable all tables */
184 for (i = 0; i < 7; i++)
185 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
186
187 /* Setup L2 cache */
188 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
189 EFFECTIVE_L2_QUEUE_SIZE(7));
190 WREG32(VM_L2_CNTL2, 0);
191 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
192 /* Setup TLB control */
193 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
194 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
195 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
196 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
197 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
198 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
199 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
200 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
c9a1be96 201 radeon_gart_table_vram_unpin(rdev);
4aac0473
JG		 202}
203
204void rv770_pcie_gart_fini(struct radeon_device *rdev)
205{
f9274562 206 radeon_gart_fini(rdev);
4aac0473
JG		 207 rv770_pcie_gart_disable(rdev);
208 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 209}
210
211
1a029b76
JG		 212void rv770_agp_enable(struct radeon_device *rdev)
213{
214 u32 tmp;
215 int i;
216
217 /* Setup L2 cache */
218 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
219 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
220 EFFECTIVE_L2_QUEUE_SIZE(7));
221 WREG32(VM_L2_CNTL2, 0);
222 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
223 /* Setup TLB control */
224 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
225 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
226 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
227 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
228 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
229 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
230 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
231 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
232 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
233 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
234 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
235 for (i = 0; i < 7; i++)
236 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
237}
238
a3c1945a 239static void rv770_mc_program(struct radeon_device *rdev)
771fe6b9 240{
a3c1945a 241 struct rv515_mc_save save;
3ce0a23d
JG		 242 u32 tmp;
243 int i, j;
244
245 /* Initialize HDP */
246 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
247 WREG32((0x2c14 + j), 0x00000000);
248 WREG32((0x2c18 + j), 0x00000000);
249 WREG32((0x2c1c + j), 0x00000000);
250 WREG32((0x2c20 + j), 0x00000000);
251 WREG32((0x2c24 + j), 0x00000000);
252 }
812d0469
AD		 253 /* r7xx hw bug. Read from HDP_DEBUG1 rather
254 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
255 */
256 tmp = RREG32(HDP_DEBUG1);
3ce0a23d 257
a3c1945a 258 rv515_mc_stop(rdev, &save);
3ce0a23d 259 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 260 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 261 }
3ce0a23d
JG		 262 /* Lockout access through VGA aperture*/
263 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 264 /* Update configuration */
1a029b76
JG		 265 if (rdev->flags & RADEON_IS_AGP) {
266 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
267 /* VRAM before AGP */
268 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
269 rdev->mc.vram_start >> 12);
270 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
271 rdev->mc.gtt_end >> 12);
272 } else {
273 /* VRAM after AGP */
274 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
275 rdev->mc.gtt_start >> 12);
276 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
277 rdev->mc.vram_end >> 12);
278 }
279 } else {
280 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
281 rdev->mc.vram_start >> 12);
282 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
283 rdev->mc.vram_end >> 12);
284 }
16cdf04d 285 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1a029b76 286 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 287 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
288 WREG32(MC_VM_FB_LOCATION, tmp);
289 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
290 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 291 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 292 if (rdev->flags & RADEON_IS_AGP) {
1a029b76 293 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
3ce0a23d
JG		 294 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
295 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
296 } else {
297 WREG32(MC_VM_AGP_BASE, 0);
298 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
299 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
300 }
3ce0a23d 301 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 302 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 303 }
a3c1945a 304 rv515_mc_resume(rdev, &save);
698443d9
DA		 305 /* we need to own VRAM, so turn off the VGA renderer here
306 * to stop it overwriting our objects */
d39c3b89 307 rv515_vga_render_disable(rdev);
771fe6b9
JG		 308}
309
3ce0a23d
JG		 310
311/*
312 * CP.
313 */
314void r700_cp_stop(struct radeon_device *rdev)
771fe6b9 315{
53595338 316 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3ce0a23d 317 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
724c80e1 318 WREG32(SCRATCH_UMSK, 0);
771fe6b9
JG		 319}
320
3ce0a23d 321static int rv770_cp_load_microcode(struct radeon_device *rdev)
771fe6b9 322{
3ce0a23d
JG		 323 const __be32 *fw_data;
324 int i;
325
326 if (!rdev->me_fw || !rdev->pfp_fw)
327 return -EINVAL;
328
329 r700_cp_stop(rdev);
4eace7fd
CC		 330 WREG32(CP_RB_CNTL,
331#ifdef __BIG_ENDIAN
332 BUF_SWAP_32BIT |
333#endif
334 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
3ce0a23d
JG		 335
336 /* Reset cp */
337 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
338 RREG32(GRBM_SOFT_RESET);
339 mdelay(15);
340 WREG32(GRBM_SOFT_RESET, 0);
341
342 fw_data = (const __be32 *)rdev->pfp_fw->data;
343 WREG32(CP_PFP_UCODE_ADDR, 0);
344 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
345 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
346 WREG32(CP_PFP_UCODE_ADDR, 0);
347
348 fw_data = (const __be32 *)rdev->me_fw->data;
349 WREG32(CP_ME_RAM_WADDR, 0);
350 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
351 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
352
353 WREG32(CP_PFP_UCODE_ADDR, 0);
354 WREG32(CP_ME_RAM_WADDR, 0);
355 WREG32(CP_ME_RAM_RADDR, 0);
356 return 0;
771fe6b9
JG		 357}
358
fe251e2f
AD		 359void r700_cp_fini(struct radeon_device *rdev)
360{
361 r700_cp_stop(rdev);
e32eb50d 362 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
fe251e2f 363}
771fe6b9
JG		 364
365/*
3ce0a23d 366 * Core functions
771fe6b9 367 */
3ce0a23d 368static void rv770_gpu_init(struct radeon_device *rdev)
771fe6b9 369{
3ce0a23d 370 int i, j, num_qd_pipes;
d03f5d59 371 u32 ta_aux_cntl;
3ce0a23d
JG		 372 u32 sx_debug_1;
373 u32 smx_dc_ctl0;
d03f5d59 374 u32 db_debug3;
3ce0a23d
JG		 375 u32 num_gs_verts_per_thread;
376 u32 vgt_gs_per_es;
377 u32 gs_prim_buffer_depth = 0;
378 u32 sq_ms_fifo_sizes;
379 u32 sq_config;
380 u32 sq_thread_resource_mgmt;
381 u32 hdp_host_path_cntl;
382 u32 sq_dyn_gpr_size_simd_ab_0;
3ce0a23d
JG		 383 u32 gb_tiling_config = 0;
384 u32 cc_rb_backend_disable = 0;
385 u32 cc_gc_shader_pipe_config = 0;
386 u32 mc_arb_ramcfg;
416a2bd2
AD		 387 u32 db_debug4, tmp;
388 u32 inactive_pipes, shader_pipe_config;
389 u32 disabled_rb_mask;
390 unsigned active_number;
771fe6b9 391
3ce0a23d 392 /* setup chip specs */
416a2bd2 393 rdev->config.rv770.tiling_group_size = 256;
3ce0a23d
JG		 394 switch (rdev->family) {
395 case CHIP_RV770:
396 rdev->config.rv770.max_pipes = 4;
397 rdev->config.rv770.max_tile_pipes = 8;
398 rdev->config.rv770.max_simds = 10;
399 rdev->config.rv770.max_backends = 4;
400 rdev->config.rv770.max_gprs = 256;
401 rdev->config.rv770.max_threads = 248;
402 rdev->config.rv770.max_stack_entries = 512;
403 rdev->config.rv770.max_hw_contexts = 8;
404 rdev->config.rv770.max_gs_threads = 16 * 2;
405 rdev->config.rv770.sx_max_export_size = 128;
406 rdev->config.rv770.sx_max_export_pos_size = 16;
407 rdev->config.rv770.sx_max_export_smx_size = 112;
408 rdev->config.rv770.sq_num_cf_insts = 2;
409
410 rdev->config.rv770.sx_num_of_sets = 7;
411 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
412 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
413 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
414 break;
415 case CHIP_RV730:
416 rdev->config.rv770.max_pipes = 2;
417 rdev->config.rv770.max_tile_pipes = 4;
418 rdev->config.rv770.max_simds = 8;
419 rdev->config.rv770.max_backends = 2;
420 rdev->config.rv770.max_gprs = 128;
421 rdev->config.rv770.max_threads = 248;
422 rdev->config.rv770.max_stack_entries = 256;
423 rdev->config.rv770.max_hw_contexts = 8;
424 rdev->config.rv770.max_gs_threads = 16 * 2;
425 rdev->config.rv770.sx_max_export_size = 256;
426 rdev->config.rv770.sx_max_export_pos_size = 32;
427 rdev->config.rv770.sx_max_export_smx_size = 224;
428 rdev->config.rv770.sq_num_cf_insts = 2;
429
430 rdev->config.rv770.sx_num_of_sets = 7;
431 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
432 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
433 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
434 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
435 rdev->config.rv770.sx_max_export_pos_size -= 16;
436 rdev->config.rv770.sx_max_export_smx_size += 16;
437 }
438 break;
439 case CHIP_RV710:
440 rdev->config.rv770.max_pipes = 2;
441 rdev->config.rv770.max_tile_pipes = 2;
442 rdev->config.rv770.max_simds = 2;
443 rdev->config.rv770.max_backends = 1;
444 rdev->config.rv770.max_gprs = 256;
445 rdev->config.rv770.max_threads = 192;
446 rdev->config.rv770.max_stack_entries = 256;
447 rdev->config.rv770.max_hw_contexts = 4;
448 rdev->config.rv770.max_gs_threads = 8 * 2;
449 rdev->config.rv770.sx_max_export_size = 128;
450 rdev->config.rv770.sx_max_export_pos_size = 16;
451 rdev->config.rv770.sx_max_export_smx_size = 112;
452 rdev->config.rv770.sq_num_cf_insts = 1;
453
454 rdev->config.rv770.sx_num_of_sets = 7;
455 rdev->config.rv770.sc_prim_fifo_size = 0x40;
456 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
457 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
458 break;
459 case CHIP_RV740:
460 rdev->config.rv770.max_pipes = 4;
461 rdev->config.rv770.max_tile_pipes = 4;
462 rdev->config.rv770.max_simds = 8;
463 rdev->config.rv770.max_backends = 4;
464 rdev->config.rv770.max_gprs = 256;
465 rdev->config.rv770.max_threads = 248;
466 rdev->config.rv770.max_stack_entries = 512;
467 rdev->config.rv770.max_hw_contexts = 8;
468 rdev->config.rv770.max_gs_threads = 16 * 2;
469 rdev->config.rv770.sx_max_export_size = 256;
470 rdev->config.rv770.sx_max_export_pos_size = 32;
471 rdev->config.rv770.sx_max_export_smx_size = 224;
472 rdev->config.rv770.sq_num_cf_insts = 2;
473
474 rdev->config.rv770.sx_num_of_sets = 7;
475 rdev->config.rv770.sc_prim_fifo_size = 0x100;
476 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
477 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
478
479 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
480 rdev->config.rv770.sx_max_export_pos_size -= 16;
481 rdev->config.rv770.sx_max_export_smx_size += 16;
482 }
483 break;
484 default:
485 break;
486 }
487
488 /* Initialize HDP */
489 j = 0;
490 for (i = 0; i < 32; i++) {
491 WREG32((0x2c14 + j), 0x00000000);
492 WREG32((0x2c18 + j), 0x00000000);
493 WREG32((0x2c1c + j), 0x00000000);
494 WREG32((0x2c20 + j), 0x00000000);
495 WREG32((0x2c24 + j), 0x00000000);
496 j += 0x18;
497 }
498
499 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
500
501 /* setup tiling, simd, pipe config */
502 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
503
416a2bd2
AD		 504 shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
505 inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
506 for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
507 if (!(inactive_pipes & tmp)) {
508 active_number++;
509 }
510 tmp <<= 1;
511 }
512 if (active_number == 1) {
513 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);
514 } else {
515 WREG32(SPI_CONFIG_CNTL, 0);
516 }
517
518 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
519 tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16);
520 if (tmp < rdev->config.rv770.max_backends) {
521 rdev->config.rv770.max_backends = tmp;
522 }
523
524 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
525 tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK);
526 if (tmp < rdev->config.rv770.max_pipes) {
527 rdev->config.rv770.max_pipes = tmp;
528 }
529 tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
530 if (tmp < rdev->config.rv770.max_simds) {
531 rdev->config.rv770.max_simds = tmp;
532 }
533
3ce0a23d
JG		 534 switch (rdev->config.rv770.max_tile_pipes) {
535 case 1:
d03f5d59 536 default:
416a2bd2 537 gb_tiling_config = PIPE_TILING(0);
3ce0a23d
JG		 538 break;
539 case 2:
416a2bd2 540 gb_tiling_config = PIPE_TILING(1);
3ce0a23d
JG		 541 break;
542 case 4:
416a2bd2 543 gb_tiling_config = PIPE_TILING(2);
3ce0a23d
JG		 544 break;
545 case 8:
416a2bd2 546 gb_tiling_config = PIPE_TILING(3);
3ce0a23d
JG		 547 break;
548 }
d03f5d59 549 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
3ce0a23d 550
416a2bd2
AD		 551 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
552 tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
553 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
554 R7XX_MAX_BACKENDS, disabled_rb_mask);
555 gb_tiling_config |= tmp << 16;
556 rdev->config.rv770.backend_map = tmp;
557
3ce0a23d
JG		 558 if (rdev->family == CHIP_RV770)
559 gb_tiling_config |= BANK_TILING(1);
29d65406
AD		 560 else {
561 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
562 gb_tiling_config |= BANK_TILING(1);
563 else
564 gb_tiling_config |= BANK_TILING(0);
565 }
961fb597 566 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
881fe6c1 567 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
e29649db 568 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
3ce0a23d
JG		 569 gb_tiling_config |= ROW_TILING(3);
570 gb_tiling_config |= SAMPLE_SPLIT(3);
571 } else {
572 gb_tiling_config |=
573 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
574 gb_tiling_config |=
575 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
576 }
577
578 gb_tiling_config |= BANK_SWAPS(1);
e7aeeba6 579 rdev->config.rv770.tile_config = gb_tiling_config;
3ce0a23d
JG		 580
581 WREG32(GB_TILING_CONFIG, gb_tiling_config);
582 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
583 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
584
3ce0a23d
JG		 585 WREG32(CGTS_SYS_TCC_DISABLE, 0);
586 WREG32(CGTS_TCC_DISABLE, 0);
f867c60d
AD		 587 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
588 WREG32(CGTS_USER_TCC_DISABLE, 0);
3ce0a23d 589
416a2bd2
AD		 590
591 num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 592 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
593 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
594
595 /* set HW defaults for 3D engine */
596 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
e29649db 597 ROQ_IB2_START(0x2b)));
3ce0a23d
JG		 598
599 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
600
d03f5d59
AD		 601 ta_aux_cntl = RREG32(TA_CNTL_AUX);
602 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
3ce0a23d
JG		 603
604 sx_debug_1 = RREG32(SX_DEBUG_1);
605 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
606 WREG32(SX_DEBUG_1, sx_debug_1);
607
608 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
609 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
610 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
611 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
612
d03f5d59
AD		 613 if (rdev->family != CHIP_RV740)
614 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
615 GS_FLUSH_CTL(4) |
616 ACK_FLUSH_CTL(3) |
617 SYNC_FLUSH_CTL));
3ce0a23d 618
d03f5d59
AD		 619 db_debug3 = RREG32(DB_DEBUG3);
620 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
621 switch (rdev->family) {
622 case CHIP_RV770:
623 case CHIP_RV740:
624 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
625 break;
626 case CHIP_RV710:
627 case CHIP_RV730:
628 default:
629 db_debug3 |= DB_CLK_OFF_DELAY(2);
630 break;
631 }
632 WREG32(DB_DEBUG3, db_debug3);
633
634 if (rdev->family != CHIP_RV770) {
3ce0a23d
JG		 635 db_debug4 = RREG32(DB_DEBUG4);
636 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
637 WREG32(DB_DEBUG4, db_debug4);
638 }
639
640 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
e29649db
AD		 641 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
642 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
3ce0a23d
JG		 643
644 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
e29649db
AD		 645 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
646 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
3ce0a23d
JG		 647
648 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
649
650 WREG32(VGT_NUM_INSTANCES, 1);
651
3ce0a23d
JG		 652 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
653
654 WREG32(CP_PERFMON_CNTL, 0);
655
656 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
657 DONE_FIFO_HIWATER(0xe0) |
658 ALU_UPDATE_FIFO_HIWATER(0x8));
659 switch (rdev->family) {
660 case CHIP_RV770:
3ce0a23d
JG		 661 case CHIP_RV730:
662 case CHIP_RV710:
d03f5d59
AD		 663 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
664 break;
3ce0a23d
JG		 665 case CHIP_RV740:
666 default:
667 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
668 break;
669 }
670 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
671
672 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
673 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
674 */
675 sq_config = RREG32(SQ_CONFIG);
676 sq_config &= ~(PS_PRIO(3) |
677 VS_PRIO(3) |
678 GS_PRIO(3) |
679 ES_PRIO(3));
680 sq_config |= (DX9_CONSTS |
681 VC_ENABLE |
682 EXPORT_SRC_C |
683 PS_PRIO(0) |
684 VS_PRIO(1) |
685 GS_PRIO(2) |
686 ES_PRIO(3));
687 if (rdev->family == CHIP_RV710)
688 /* no vertex cache */
689 sq_config &= ~VC_ENABLE;
690
691 WREG32(SQ_CONFIG, sq_config);
692
693 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
fe62e1a4
DA		 694 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
695 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
3ce0a23d
JG		 696
697 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
fe62e1a4 698 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
3ce0a23d
JG		 699
700 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
701 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
702 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
703 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
704 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
705 else
706 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
707 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
708
709 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
710 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
711
712 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
713 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
714
715 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
716 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
717 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
718 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
719
720 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
721 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
722 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
723 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
724 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
725 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
726 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
727 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
728
729 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
fe62e1a4 730 FORCE_EOV_MAX_REZ_CNT(255)));
3ce0a23d
JG		 731
732 if (rdev->family == CHIP_RV710)
733 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
fe62e1a4 734 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
3ce0a23d
JG		 735 else
736 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
fe62e1a4 737 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
3ce0a23d
JG		 738
739 switch (rdev->family) {
740 case CHIP_RV770:
741 case CHIP_RV730:
742 case CHIP_RV740:
743 gs_prim_buffer_depth = 384;
744 break;
745 case CHIP_RV710:
746 gs_prim_buffer_depth = 128;
747 break;
748 default:
749 break;
750 }
751
752 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
753 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
754 /* Max value for this is 256 */
755 if (vgt_gs_per_es > 256)
756 vgt_gs_per_es = 256;
757
758 WREG32(VGT_ES_PER_GS, 128);
759 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
760 WREG32(VGT_GS_PER_VS, 2);
761
762 /* more default values. 2D/3D driver should adjust as needed */
763 WREG32(VGT_GS_VERTEX_REUSE, 16);
764 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
765 WREG32(VGT_STRMOUT_EN, 0);
766 WREG32(SX_MISC, 0);
767 WREG32(PA_SC_MODE_CNTL, 0);
768 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
769 WREG32(PA_SC_AA_CONFIG, 0);
770 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
771 WREG32(PA_SC_LINE_STIPPLE, 0);
772 WREG32(SPI_INPUT_Z, 0);
773 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
774 WREG32(CB_COLOR7_FRAG, 0);
775
776 /* clear render buffer base addresses */
777 WREG32(CB_COLOR0_BASE, 0);
778 WREG32(CB_COLOR1_BASE, 0);
779 WREG32(CB_COLOR2_BASE, 0);
780 WREG32(CB_COLOR3_BASE, 0);
781 WREG32(CB_COLOR4_BASE, 0);
782 WREG32(CB_COLOR5_BASE, 0);
783 WREG32(CB_COLOR6_BASE, 0);
784 WREG32(CB_COLOR7_BASE, 0);
785
786 WREG32(TCP_CNTL, 0);
787
788 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
789 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
790
791 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
792
793 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
794 NUM_CLIP_SEQ(3)));
795
796}
797
0ef0c1f7
AD		 798void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
799{
800 u64 size_bf, size_af;
801
802 if (mc->mc_vram_size > 0xE0000000) {
803 /* leave room for at least 512M GTT */
804 dev_warn(rdev->dev, "limiting VRAM\n");
805 mc->real_vram_size = 0xE0000000;
806 mc->mc_vram_size = 0xE0000000;
807 }
808 if (rdev->flags & RADEON_IS_AGP) {
809 size_bf = mc->gtt_start;
dfc6ae5b 810 size_af = 0xFFFFFFFF - mc->gtt_end;
0ef0c1f7
AD		 811 if (size_bf > size_af) {
812 if (mc->mc_vram_size > size_bf) {
813 dev_warn(rdev->dev, "limiting VRAM\n");
814 mc->real_vram_size = size_bf;
815 mc->mc_vram_size = size_bf;
816 }
817 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
818 } else {
819 if (mc->mc_vram_size > size_af) {
820 dev_warn(rdev->dev, "limiting VRAM\n");
821 mc->real_vram_size = size_af;
822 mc->mc_vram_size = size_af;
823 }
dfc6ae5b 824 mc->vram_start = mc->gtt_end + 1;
0ef0c1f7
AD		 825 }
826 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
827 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
828 mc->mc_vram_size >> 20, mc->vram_start,
829 mc->vram_end, mc->real_vram_size >> 20);
830 } else {
b4183e30 831 radeon_vram_location(rdev, &rdev->mc, 0);
0ef0c1f7
AD		 832 rdev->mc.gtt_base_align = 0;
833 radeon_gtt_location(rdev, mc);
834 }
835}
836
3ce0a23d
JG		 837int rv770_mc_init(struct radeon_device *rdev)
838{
3ce0a23d 839 u32 tmp;
5885b7a9 840 int chansize, numchan;
3ce0a23d
JG		 841
842 /* Get VRAM informations */
3ce0a23d 843 rdev->mc.vram_is_ddr = true;
5885b7a9
AD		 844 tmp = RREG32(MC_ARB_RAMCFG);
845 if (tmp & CHANSIZE_OVERRIDE) {
846 chansize = 16;
847 } else if (tmp & CHANSIZE_MASK) {
848 chansize = 64;
849 } else {
850 chansize = 32;
851 }
852 tmp = RREG32(MC_SHARED_CHMAP);
853 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
854 case 0:
855 default:
856 numchan = 1;
857 break;
858 case 1:
859 numchan = 2;
860 break;
861 case 2:
862 numchan = 4;
863 break;
864 case 3:
865 numchan = 8;
866 break;
867 }
868 rdev->mc.vram_width = numchan * chansize;
771fe6b9 869 /* Could aper size report 0 ? */
01d73a69
JC		 870 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
871 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 872 /* Setup GPU memory space */
873 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
874 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 875 rdev->mc.visible_vram_size = rdev->mc.aper_size;
0ef0c1f7 876 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 877 radeon_update_bandwidth_info(rdev);
878
3ce0a23d
JG		 879 return 0;
880}
d594e46a 881
fc30b8ef 882static int rv770_startup(struct radeon_device *rdev)
3ce0a23d 883{
e32eb50d 884 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 885 int r;
886
9e46a48d
AD		 887 /* enable pcie gen2 link */
888 rv770_pcie_gen2_enable(rdev);
889
779720a3
AD		 890 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
891 r = r600_init_microcode(rdev);
892 if (r) {
893 DRM_ERROR("Failed to load firmware!\n");
894 return r;
895 }
896 }
897
16cdf04d
AD		 898 r = r600_vram_scratch_init(rdev);
899 if (r)
900 return r;
901
a3c1945a 902 rv770_mc_program(rdev);
1a029b76
JG		 903 if (rdev->flags & RADEON_IS_AGP) {
904 rv770_agp_enable(rdev);
905 } else {
906 r = rv770_pcie_gart_enable(rdev);
907 if (r)
908 return r;
909 }
16cdf04d 910
3ce0a23d 911 rv770_gpu_init(rdev);
c38c7b64
JG		 912 r = r600_blit_init(rdev);
913 if (r) {
914 r600_blit_fini(rdev);
27cd7769 915 rdev->asic->copy.copy = NULL;
c38c7b64
JG		 916 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
917 }
b70d6bb3 918
724c80e1
AD		 919 /* allocate wb buffer */
920 r = radeon_wb_init(rdev);
921 if (r)
922 return r;
923
30eb77f4
JG		 924 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
925 if (r) {
926 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
927 return r;
928 }
929
d8f60cfc 930 /* Enable IRQ */
d8f60cfc
AD		 931 r = r600_irq_init(rdev);
932 if (r) {
933 DRM_ERROR("radeon: IH init failed (%d).\n", r);
934 radeon_irq_kms_fini(rdev);
935 return r;
936 }
937 r600_irq_set(rdev);
938
e32eb50d 939 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 940 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
941 0, 0xfffff, RADEON_CP_PACKET2);
3ce0a23d
JG		 942 if (r)
943 return r;
944 r = rv770_cp_load_microcode(rdev);
945 if (r)
946 return r;
947 r = r600_cp_resume(rdev);
948 if (r)
949 return r;
724c80e1 950
b15ba512
JG		 951 r = radeon_ib_pool_start(rdev);
952 if (r)
953 return r;
954
7bd560e8
CK		 955 r = radeon_ib_ring_tests(rdev);
956 if (r)
b15ba512 957 return r;
b15ba512 958
d4e30ef0
AD		 959 r = r600_audio_init(rdev);
960 if (r) {
961 DRM_ERROR("radeon: audio init failed\n");
962 return r;
963 }
964
3ce0a23d
JG		 965 return 0;
966}
967
fc30b8ef
DA		 968int rv770_resume(struct radeon_device *rdev)
969{
970 int r;
971
1a029b76
JG		 972 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
973 * posting will perform necessary task to bring back GPU into good
974 * shape.
975 */
fc30b8ef 976 /* post card */
e7d40b9a 977 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef 978
b15ba512 979 rdev->accel_working = true;
fc30b8ef
DA		 980 r = rv770_startup(rdev);
981 if (r) {
982 DRM_ERROR("r600 startup failed on resume\n");
6b7746e8 983 rdev->accel_working = false;
fc30b8ef
DA		 984 return r;
985 }
986
fc30b8ef
DA		 987 return r;
988
989}
990
3ce0a23d
JG		 991int rv770_suspend(struct radeon_device *rdev)
992{
8a8c6e7c 993 r600_audio_fini(rdev);
b15ba512
JG		 994 radeon_ib_pool_suspend(rdev);
995 r600_blit_suspend(rdev);
3ce0a23d
JG		 996 /* FIXME: we should wait for ring to be empty */
997 r700_cp_stop(rdev);
e32eb50d 998 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
0c45249f 999 r600_irq_suspend(rdev);
724c80e1 1000 radeon_wb_disable(rdev);
4aac0473 1001 rv770_pcie_gart_disable(rdev);
6ddddfe7 1002
3ce0a23d
JG		 1003 return 0;
1004}
1005
1006/* Plan is to move initialization in that function and use
1007 * helper function so that radeon_device_init pretty much
1008 * do nothing more than calling asic specific function. This
1009 * should also allow to remove a bunch of callback function
1010 * like vram_info.
1011 */
1012int rv770_init(struct radeon_device *rdev)
1013{
1014 int r;
1015
3ce0a23d
JG		 1016 /* Read BIOS */
1017 if (!radeon_get_bios(rdev)) {
1018 if (ASIC_IS_AVIVO(rdev))
1019 return -EINVAL;
1020 }
1021 /* Must be an ATOMBIOS */
e7d40b9a
JG		 1022 if (!rdev->is_atom_bios) {
1023 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 1024 return -EINVAL;
e7d40b9a 1025 }
3ce0a23d
JG		 1026 r = radeon_atombios_init(rdev);
1027 if (r)
1028 return r;
1029 /* Post card if necessary */
fd909c37 1030 if (!radeon_card_posted(rdev)) {
72542d77
DA		 1031 if (!rdev->bios) {
1032 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1033 return -EINVAL;
1034 }
3ce0a23d
JG		 1035 DRM_INFO("GPU not posted. posting now...\n");
1036 atom_asic_init(rdev->mode_info.atom_context);
1037 }
1038 /* Initialize scratch registers */
1039 r600_scratch_init(rdev);
1040 /* Initialize surface registers */
1041 radeon_surface_init(rdev);
7433874e 1042 /* Initialize clocks */
5e6dde7e 1043 radeon_get_clock_info(rdev->ddev);
3ce0a23d 1044 /* Fence driver */
30eb77f4 1045 r = radeon_fence_driver_init(rdev);
3ce0a23d
JG		 1046 if (r)
1047 return r;
d594e46a 1048 /* initialize AGP */
700a0cc0
JG		 1049 if (rdev->flags & RADEON_IS_AGP) {
1050 r = radeon_agp_init(rdev);
1051 if (r)
1052 radeon_agp_disable(rdev);
1053 }
3ce0a23d 1054 r = rv770_mc_init(rdev);
b574f251 1055 if (r)
3ce0a23d 1056 return r;
3ce0a23d 1057 /* Memory manager */
4c788679 1058 r = radeon_bo_init(rdev);
3ce0a23d
JG		 1059 if (r)
1060 return r;
d8f60cfc
AD		 1061
1062 r = radeon_irq_kms_init(rdev);
1063 if (r)
1064 return r;
1065
e32eb50d
CK		 1066 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
1067 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3ce0a23d 1068
d8f60cfc
AD		 1069 rdev->ih.ring_obj = NULL;
1070 r600_ih_ring_init(rdev, 64 * 1024);
1071
4aac0473
JG		 1072 r = r600_pcie_gart_init(rdev);
1073 if (r)
1074 return r;
1075
b15ba512 1076 r = radeon_ib_pool_init(rdev);
779720a3 1077 rdev->accel_working = true;
b15ba512
JG		 1078 if (r) {
1079 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1080 rdev->accel_working = false;
1081 }
1082
fc30b8ef 1083 r = rv770_startup(rdev);
3ce0a23d 1084 if (r) {
655efd3d 1085 dev_err(rdev->dev, "disabling GPU acceleration\n");
fe251e2f 1086 r700_cp_fini(rdev);
655efd3d 1087 r600_irq_fini(rdev);
724c80e1 1088 radeon_wb_fini(rdev);
b15ba512 1089 r100_ib_fini(rdev);
655efd3d 1090 radeon_irq_kms_fini(rdev);
75c81298 1091 rv770_pcie_gart_fini(rdev);
733289c2 1092 rdev->accel_working = false;
3ce0a23d 1093 }
8a8c6e7c 1094
3ce0a23d
JG		 1095 return 0;
1096}
1097
1098void rv770_fini(struct radeon_device *rdev)
1099{
1100 r600_blit_fini(rdev);
fe251e2f 1101 r700_cp_fini(rdev);
d8f60cfc 1102 r600_irq_fini(rdev);
724c80e1 1103 radeon_wb_fini(rdev);
b15ba512 1104 r100_ib_fini(rdev);
d8f60cfc 1105 radeon_irq_kms_fini(rdev);
4aac0473 1106 rv770_pcie_gart_fini(rdev);
16cdf04d 1107 r600_vram_scratch_fini(rdev);
3ce0a23d
JG		 1108 radeon_gem_fini(rdev);
1109 radeon_fence_driver_fini(rdev);
d0269ed8 1110 radeon_agp_fini(rdev);
4c788679 1111 radeon_bo_fini(rdev);
e7d40b9a 1112 radeon_atombios_fini(rdev);
3ce0a23d
JG		 1113 kfree(rdev->bios);
1114 rdev->bios = NULL;
771fe6b9 1115}
9e46a48d
AD		 1116
1117static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1118{
1119 u32 link_width_cntl, lanes, speed_cntl, tmp;
1120 u16 link_cntl2;
1121
d42dd579
AD		 1122 if (radeon_pcie_gen2 == 0)
1123 return;
1124
9e46a48d
AD		 1125 if (rdev->flags & RADEON_IS_IGP)
1126 return;
1127
1128 if (!(rdev->flags & RADEON_IS_PCIE))
1129 return;
1130
1131 /* x2 cards have a special sequence */
1132 if (ASIC_IS_X2(rdev))
1133 return;
1134
1135 /* advertise upconfig capability */
1136 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1137 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1138 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1139 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1140 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1141 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1142 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1143 LC_RECONFIG_ARC_MISSING_ESCAPE);
1144 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1145 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1146 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1147 } else {
1148 link_width_cntl |= LC_UPCONFIGURE_DIS;
1149 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1150 }
1151
1152 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1153 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1154 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1155
1156 tmp = RREG32(0x541c);
1157 WREG32(0x541c, tmp | 0x8);
1158 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1159 link_cntl2 = RREG16(0x4088);
1160 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1161 link_cntl2 |= 0x2;
1162 WREG16(0x4088, link_cntl2);
1163 WREG32(MM_CFGREGS_CNTL, 0);
1164
1165 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1166 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1167 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1168
1169 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1170 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1171 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1172
1173 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1174 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1175 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1176
1177 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1178 speed_cntl |= LC_GEN2_EN_STRAP;
1179 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1180
1181 } else {
1182 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1183 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1184 if (1)
1185 link_width_cntl |= LC_UPCONFIGURE_DIS;
1186 else
1187 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1188 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1189 }
1190}
Linux 6.x block layer and io_uring tree(s)