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drm/radeon/kms: more alignment for rv770.c with r600.c
[linux-block.git] / drivers / gpu / drm / radeon / rv770.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
3ce0a23d
JG		 28#include <linux/firmware.h>
29#include <linux/platform_device.h>
771fe6b9 30#include "drmP.h"
771fe6b9 31#include "radeon.h"
4153e584 32#include "radeon_drm.h"
3ce0a23d
JG		 33#include "rv770d.h"
34#include "avivod.h"
35#include "atom.h"
771fe6b9 36
3ce0a23d
JG		 37#define R700_PFP_UCODE_SIZE 848
38#define R700_PM4_UCODE_SIZE 1360
771fe6b9 39
3ce0a23d
JG		 40static void rv770_gpu_init(struct radeon_device *rdev);
41void rv770_fini(struct radeon_device *rdev);
771fe6b9
JG		 42
43
44/*
3ce0a23d 45 * GART
771fe6b9 46 */
3ce0a23d 47int rv770_pcie_gart_enable(struct radeon_device *rdev)
771fe6b9 48{
3ce0a23d
JG		 49 u32 tmp;
50 int r, i;
771fe6b9 51
4aac0473
JG		 52 if (rdev->gart.table.vram.robj == NULL) {
53 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
54 return -EINVAL;
3ce0a23d 55 }
4aac0473
JG		 56 r = radeon_gart_table_vram_pin(rdev);
57 if (r)
3ce0a23d 58 return r;
3ce0a23d
JG		 59 for (i = 0; i < rdev->gart.num_gpu_pages; i++)
60 r600_gart_clear_page(rdev, i);
61 /* Setup L2 cache */
62 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
63 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
64 EFFECTIVE_L2_QUEUE_SIZE(7));
65 WREG32(VM_L2_CNTL2, 0);
66 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
67 /* Setup TLB control */
68 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
69 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
70 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
71 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
72 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
73 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
74 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
75 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
76 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
77 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
78 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
79 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
80 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
81 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
82 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
83 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
84 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
85 (u32)(rdev->dummy_page.addr >> 12));
86 for (i = 1; i < 7; i++)
87 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 88
3ce0a23d
JG		 89 r600_pcie_gart_tlb_flush(rdev);
90 rdev->gart.ready = true;
771fe6b9
JG		 91 return 0;
92}
93
3ce0a23d 94void rv770_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 95{
3ce0a23d
JG		 96 u32 tmp;
97 int i;
98
3ce0a23d
JG		 99 /* Disable all tables */
100 for (i = 0; i < 7; i++)
101 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
102
103 /* Setup L2 cache */
104 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
105 EFFECTIVE_L2_QUEUE_SIZE(7));
106 WREG32(VM_L2_CNTL2, 0);
107 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
108 /* Setup TLB control */
109 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
110 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
111 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
112 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
113 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
114 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
115 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
116 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
4aac0473
JG		 117 if (rdev->gart.table.vram.robj) {
118 radeon_object_kunmap(rdev->gart.table.vram.robj);
119 radeon_object_unpin(rdev->gart.table.vram.robj);
120 }
121}
122
123void rv770_pcie_gart_fini(struct radeon_device *rdev)
124{
125 rv770_pcie_gart_disable(rdev);
126 radeon_gart_table_vram_free(rdev);
127 radeon_gart_fini(rdev);
771fe6b9
JG		 128}
129
130
131/*
3ce0a23d 132 * MC
771fe6b9 133 */
3ce0a23d 134static void rv770_mc_resume(struct radeon_device *rdev)
771fe6b9 135{
3ce0a23d
JG		 136 u32 d1vga_control, d2vga_control;
137 u32 vga_render_control, vga_hdp_control;
138 u32 d1crtc_control, d2crtc_control;
139 u32 new_d1grph_primary, new_d1grph_secondary;
140 u32 new_d2grph_primary, new_d2grph_secondary;
141 u64 old_vram_start;
142 u32 tmp;
143 int i, j;
144
145 /* Initialize HDP */
146 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
147 WREG32((0x2c14 + j), 0x00000000);
148 WREG32((0x2c18 + j), 0x00000000);
149 WREG32((0x2c1c + j), 0x00000000);
150 WREG32((0x2c20 + j), 0x00000000);
151 WREG32((0x2c24 + j), 0x00000000);
152 }
153 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
154
155 d1vga_control = RREG32(D1VGA_CONTROL);
156 d2vga_control = RREG32(D2VGA_CONTROL);
157 vga_render_control = RREG32(VGA_RENDER_CONTROL);
158 vga_hdp_control = RREG32(VGA_HDP_CONTROL);
159 d1crtc_control = RREG32(D1CRTC_CONTROL);
160 d2crtc_control = RREG32(D2CRTC_CONTROL);
161 old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
162 new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
163 new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
164 new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
165 new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
166 new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
167 new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
168 new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
169 new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
170
171 /* Stop all video */
172 WREG32(D1VGA_CONTROL, 0);
173 WREG32(D2VGA_CONTROL, 0);
174 WREG32(VGA_RENDER_CONTROL, 0);
175 WREG32(D1CRTC_UPDATE_LOCK, 1);
176 WREG32(D2CRTC_UPDATE_LOCK, 1);
177 WREG32(D1CRTC_CONTROL, 0);
178 WREG32(D2CRTC_CONTROL, 0);
179 WREG32(D1CRTC_UPDATE_LOCK, 0);
180 WREG32(D2CRTC_UPDATE_LOCK, 0);
181
182 mdelay(1);
183 if (r600_mc_wait_for_idle(rdev)) {
184 printk(KERN_WARNING "[drm] MC not idle !\n");
185 }
186
187 /* Lockout access through VGA aperture*/
188 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
189
190 /* Update configuration */
191 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
192 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
193 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
194 tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
195 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
196 WREG32(MC_VM_FB_LOCATION, tmp);
197 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
198 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
199 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
200 if (rdev->flags & RADEON_IS_AGP) {
201 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
202 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
203 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
204 } else {
205 WREG32(MC_VM_AGP_BASE, 0);
206 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
207 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
208 }
209 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
210 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
211 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
212 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
213 WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
214
215 /* Unlock host access */
216 WREG32(VGA_HDP_CONTROL, vga_hdp_control);
217
218 mdelay(1);
219 if (r600_mc_wait_for_idle(rdev)) {
220 printk(KERN_WARNING "[drm] MC not idle !\n");
221 }
222
223 /* Restore video state */
224 WREG32(D1CRTC_UPDATE_LOCK, 1);
225 WREG32(D2CRTC_UPDATE_LOCK, 1);
226 WREG32(D1CRTC_CONTROL, d1crtc_control);
227 WREG32(D2CRTC_CONTROL, d2crtc_control);
228 WREG32(D1CRTC_UPDATE_LOCK, 0);
229 WREG32(D2CRTC_UPDATE_LOCK, 0);
230 WREG32(D1VGA_CONTROL, d1vga_control);
231 WREG32(D2VGA_CONTROL, d2vga_control);
232 WREG32(VGA_RENDER_CONTROL, vga_render_control);
698443d9
DA		 233
234 /* we need to own VRAM, so turn off the VGA renderer here
235 * to stop it overwriting our objects */
236 radeon_avivo_vga_render_disable(rdev);
771fe6b9
JG		 237}
238
3ce0a23d
JG		 239
240/*
241 * CP.
242 */
243void r700_cp_stop(struct radeon_device *rdev)
771fe6b9 244{
3ce0a23d 245 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
771fe6b9
JG		 246}
247
3ce0a23d
JG		 248
249static int rv770_cp_load_microcode(struct radeon_device *rdev)
771fe6b9 250{
3ce0a23d
JG		 251 const __be32 *fw_data;
252 int i;
253
254 if (!rdev->me_fw || !rdev->pfp_fw)
255 return -EINVAL;
256
257 r700_cp_stop(rdev);
258 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
259
260 /* Reset cp */
261 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
262 RREG32(GRBM_SOFT_RESET);
263 mdelay(15);
264 WREG32(GRBM_SOFT_RESET, 0);
265
266 fw_data = (const __be32 *)rdev->pfp_fw->data;
267 WREG32(CP_PFP_UCODE_ADDR, 0);
268 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
269 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
270 WREG32(CP_PFP_UCODE_ADDR, 0);
271
272 fw_data = (const __be32 *)rdev->me_fw->data;
273 WREG32(CP_ME_RAM_WADDR, 0);
274 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
275 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
276
277 WREG32(CP_PFP_UCODE_ADDR, 0);
278 WREG32(CP_ME_RAM_WADDR, 0);
279 WREG32(CP_ME_RAM_RADDR, 0);
280 return 0;
771fe6b9
JG		 281}
282
283
284/*
3ce0a23d 285 * Core functions
771fe6b9 286 */
3ce0a23d
JG		 287static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
288 u32 num_backends,
289 u32 backend_disable_mask)
771fe6b9 290{
3ce0a23d
JG		 291 u32 backend_map = 0;
292 u32 enabled_backends_mask;
293 u32 enabled_backends_count;
294 u32 cur_pipe;
295 u32 swizzle_pipe[R7XX_MAX_PIPES];
296 u32 cur_backend;
297 u32 i;
298
299 if (num_tile_pipes > R7XX_MAX_PIPES)
300 num_tile_pipes = R7XX_MAX_PIPES;
301 if (num_tile_pipes < 1)
302 num_tile_pipes = 1;
303 if (num_backends > R7XX_MAX_BACKENDS)
304 num_backends = R7XX_MAX_BACKENDS;
305 if (num_backends < 1)
306 num_backends = 1;
307
308 enabled_backends_mask = 0;
309 enabled_backends_count = 0;
310 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
311 if (((backend_disable_mask >> i) & 1) == 0) {
312 enabled_backends_mask |= (1 << i);
313 ++enabled_backends_count;
314 }
315 if (enabled_backends_count == num_backends)
316 break;
317 }
318
319 if (enabled_backends_count == 0) {
320 enabled_backends_mask = 1;
321 enabled_backends_count = 1;
322 }
323
324 if (enabled_backends_count != num_backends)
325 num_backends = enabled_backends_count;
326
327 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
328 switch (num_tile_pipes) {
329 case 1:
330 swizzle_pipe[0] = 0;
331 break;
332 case 2:
333 swizzle_pipe[0] = 0;
334 swizzle_pipe[1] = 1;
335 break;
336 case 3:
337 swizzle_pipe[0] = 0;
338 swizzle_pipe[1] = 2;
339 swizzle_pipe[2] = 1;
340 break;
341 case 4:
342 swizzle_pipe[0] = 0;
343 swizzle_pipe[1] = 2;
344 swizzle_pipe[2] = 3;
345 swizzle_pipe[3] = 1;
346 break;
347 case 5:
348 swizzle_pipe[0] = 0;
349 swizzle_pipe[1] = 2;
350 swizzle_pipe[2] = 4;
351 swizzle_pipe[3] = 1;
352 swizzle_pipe[4] = 3;
353 break;
354 case 6:
355 swizzle_pipe[0] = 0;
356 swizzle_pipe[1] = 2;
357 swizzle_pipe[2] = 4;
358 swizzle_pipe[3] = 5;
359 swizzle_pipe[4] = 3;
360 swizzle_pipe[5] = 1;
361 break;
362 case 7:
363 swizzle_pipe[0] = 0;
364 swizzle_pipe[1] = 2;
365 swizzle_pipe[2] = 4;
366 swizzle_pipe[3] = 6;
367 swizzle_pipe[4] = 3;
368 swizzle_pipe[5] = 1;
369 swizzle_pipe[6] = 5;
370 break;
371 case 8:
372 swizzle_pipe[0] = 0;
373 swizzle_pipe[1] = 2;
374 swizzle_pipe[2] = 4;
375 swizzle_pipe[3] = 6;
376 swizzle_pipe[4] = 3;
377 swizzle_pipe[5] = 1;
378 swizzle_pipe[6] = 7;
379 swizzle_pipe[7] = 5;
380 break;
381 }
382
383 cur_backend = 0;
384 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
385 while (((1 << cur_backend) & enabled_backends_mask) == 0)
386 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
387
388 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
389
390 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
391 }
392
393 return backend_map;
771fe6b9
JG		 394}
395
3ce0a23d 396static void rv770_gpu_init(struct radeon_device *rdev)
771fe6b9 397{
3ce0a23d
JG		 398 int i, j, num_qd_pipes;
399 u32 sx_debug_1;
400 u32 smx_dc_ctl0;
401 u32 num_gs_verts_per_thread;
402 u32 vgt_gs_per_es;
403 u32 gs_prim_buffer_depth = 0;
404 u32 sq_ms_fifo_sizes;
405 u32 sq_config;
406 u32 sq_thread_resource_mgmt;
407 u32 hdp_host_path_cntl;
408 u32 sq_dyn_gpr_size_simd_ab_0;
409 u32 backend_map;
410 u32 gb_tiling_config = 0;
411 u32 cc_rb_backend_disable = 0;
412 u32 cc_gc_shader_pipe_config = 0;
413 u32 mc_arb_ramcfg;
414 u32 db_debug4;
771fe6b9 415
3ce0a23d
JG		 416 /* setup chip specs */
417 switch (rdev->family) {
418 case CHIP_RV770:
419 rdev->config.rv770.max_pipes = 4;
420 rdev->config.rv770.max_tile_pipes = 8;
421 rdev->config.rv770.max_simds = 10;
422 rdev->config.rv770.max_backends = 4;
423 rdev->config.rv770.max_gprs = 256;
424 rdev->config.rv770.max_threads = 248;
425 rdev->config.rv770.max_stack_entries = 512;
426 rdev->config.rv770.max_hw_contexts = 8;
427 rdev->config.rv770.max_gs_threads = 16 * 2;
428 rdev->config.rv770.sx_max_export_size = 128;
429 rdev->config.rv770.sx_max_export_pos_size = 16;
430 rdev->config.rv770.sx_max_export_smx_size = 112;
431 rdev->config.rv770.sq_num_cf_insts = 2;
432
433 rdev->config.rv770.sx_num_of_sets = 7;
434 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
435 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
436 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
437 break;
438 case CHIP_RV730:
439 rdev->config.rv770.max_pipes = 2;
440 rdev->config.rv770.max_tile_pipes = 4;
441 rdev->config.rv770.max_simds = 8;
442 rdev->config.rv770.max_backends = 2;
443 rdev->config.rv770.max_gprs = 128;
444 rdev->config.rv770.max_threads = 248;
445 rdev->config.rv770.max_stack_entries = 256;
446 rdev->config.rv770.max_hw_contexts = 8;
447 rdev->config.rv770.max_gs_threads = 16 * 2;
448 rdev->config.rv770.sx_max_export_size = 256;
449 rdev->config.rv770.sx_max_export_pos_size = 32;
450 rdev->config.rv770.sx_max_export_smx_size = 224;
451 rdev->config.rv770.sq_num_cf_insts = 2;
452
453 rdev->config.rv770.sx_num_of_sets = 7;
454 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
455 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
456 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
457 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
458 rdev->config.rv770.sx_max_export_pos_size -= 16;
459 rdev->config.rv770.sx_max_export_smx_size += 16;
460 }
461 break;
462 case CHIP_RV710:
463 rdev->config.rv770.max_pipes = 2;
464 rdev->config.rv770.max_tile_pipes = 2;
465 rdev->config.rv770.max_simds = 2;
466 rdev->config.rv770.max_backends = 1;
467 rdev->config.rv770.max_gprs = 256;
468 rdev->config.rv770.max_threads = 192;
469 rdev->config.rv770.max_stack_entries = 256;
470 rdev->config.rv770.max_hw_contexts = 4;
471 rdev->config.rv770.max_gs_threads = 8 * 2;
472 rdev->config.rv770.sx_max_export_size = 128;
473 rdev->config.rv770.sx_max_export_pos_size = 16;
474 rdev->config.rv770.sx_max_export_smx_size = 112;
475 rdev->config.rv770.sq_num_cf_insts = 1;
476
477 rdev->config.rv770.sx_num_of_sets = 7;
478 rdev->config.rv770.sc_prim_fifo_size = 0x40;
479 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
480 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
481 break;
482 case CHIP_RV740:
483 rdev->config.rv770.max_pipes = 4;
484 rdev->config.rv770.max_tile_pipes = 4;
485 rdev->config.rv770.max_simds = 8;
486 rdev->config.rv770.max_backends = 4;
487 rdev->config.rv770.max_gprs = 256;
488 rdev->config.rv770.max_threads = 248;
489 rdev->config.rv770.max_stack_entries = 512;
490 rdev->config.rv770.max_hw_contexts = 8;
491 rdev->config.rv770.max_gs_threads = 16 * 2;
492 rdev->config.rv770.sx_max_export_size = 256;
493 rdev->config.rv770.sx_max_export_pos_size = 32;
494 rdev->config.rv770.sx_max_export_smx_size = 224;
495 rdev->config.rv770.sq_num_cf_insts = 2;
496
497 rdev->config.rv770.sx_num_of_sets = 7;
498 rdev->config.rv770.sc_prim_fifo_size = 0x100;
499 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
500 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
501
502 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
503 rdev->config.rv770.sx_max_export_pos_size -= 16;
504 rdev->config.rv770.sx_max_export_smx_size += 16;
505 }
506 break;
507 default:
508 break;
509 }
510
511 /* Initialize HDP */
512 j = 0;
513 for (i = 0; i < 32; i++) {
514 WREG32((0x2c14 + j), 0x00000000);
515 WREG32((0x2c18 + j), 0x00000000);
516 WREG32((0x2c1c + j), 0x00000000);
517 WREG32((0x2c20 + j), 0x00000000);
518 WREG32((0x2c24 + j), 0x00000000);
519 j += 0x18;
520 }
521
522 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
523
524 /* setup tiling, simd, pipe config */
525 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
526
527 switch (rdev->config.rv770.max_tile_pipes) {
528 case 1:
529 gb_tiling_config |= PIPE_TILING(0);
530 break;
531 case 2:
532 gb_tiling_config |= PIPE_TILING(1);
533 break;
534 case 4:
535 gb_tiling_config |= PIPE_TILING(2);
536 break;
537 case 8:
538 gb_tiling_config |= PIPE_TILING(3);
539 break;
540 default:
541 break;
542 }
543
544 if (rdev->family == CHIP_RV770)
545 gb_tiling_config |= BANK_TILING(1);
546 else
547 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK);
548
549 gb_tiling_config |= GROUP_SIZE(0);
550
551 if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) {
552 gb_tiling_config |= ROW_TILING(3);
553 gb_tiling_config |= SAMPLE_SPLIT(3);
554 } else {
555 gb_tiling_config |=
556 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
557 gb_tiling_config |=
558 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
559 }
560
561 gb_tiling_config |= BANK_SWAPS(1);
562
563 backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes,
564 rdev->config.rv770.max_backends,
565 (0xff << rdev->config.rv770.max_backends) & 0xff);
566 gb_tiling_config |= BACKEND_MAP(backend_map);
567
568 cc_gc_shader_pipe_config =
569 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
570 cc_gc_shader_pipe_config |=
571 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
572
573 cc_rb_backend_disable =
574 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
575
576 WREG32(GB_TILING_CONFIG, gb_tiling_config);
577 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
578 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
579
580 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
581 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
582 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
583
584 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
585 WREG32(CGTS_SYS_TCC_DISABLE, 0);
586 WREG32(CGTS_TCC_DISABLE, 0);
587 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
588 WREG32(CGTS_USER_TCC_DISABLE, 0);
589
590 num_qd_pipes =
591 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK);
592 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
593 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
594
595 /* set HW defaults for 3D engine */
596 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
597 ROQ_IB2_START(0x2b)));
598
599 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
600
601 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
602 SYNC_GRADIENT |
603 SYNC_WALKER |
604 SYNC_ALIGNER));
605
606 sx_debug_1 = RREG32(SX_DEBUG_1);
607 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
608 WREG32(SX_DEBUG_1, sx_debug_1);
609
610 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
611 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
612 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
613 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
614
615 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
616 GS_FLUSH_CTL(4) |
617 ACK_FLUSH_CTL(3) |
618 SYNC_FLUSH_CTL));
619
620 if (rdev->family == CHIP_RV770)
621 WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
622 else {
623 db_debug4 = RREG32(DB_DEBUG4);
624 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
625 WREG32(DB_DEBUG4, db_debug4);
626 }
627
628 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
629 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
630 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
631
632 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
633 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
634 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
635
636 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
637
638 WREG32(VGT_NUM_INSTANCES, 1);
639
640 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
641
642 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
643
644 WREG32(CP_PERFMON_CNTL, 0);
645
646 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
647 DONE_FIFO_HIWATER(0xe0) |
648 ALU_UPDATE_FIFO_HIWATER(0x8));
649 switch (rdev->family) {
650 case CHIP_RV770:
651 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
652 break;
653 case CHIP_RV730:
654 case CHIP_RV710:
655 case CHIP_RV740:
656 default:
657 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
658 break;
659 }
660 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
661
662 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
663 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
664 */
665 sq_config = RREG32(SQ_CONFIG);
666 sq_config &= ~(PS_PRIO(3) |
667 VS_PRIO(3) |
668 GS_PRIO(3) |
669 ES_PRIO(3));
670 sq_config |= (DX9_CONSTS |
671 VC_ENABLE |
672 EXPORT_SRC_C |
673 PS_PRIO(0) |
674 VS_PRIO(1) |
675 GS_PRIO(2) |
676 ES_PRIO(3));
677 if (rdev->family == CHIP_RV710)
678 /* no vertex cache */
679 sq_config &= ~VC_ENABLE;
680
681 WREG32(SQ_CONFIG, sq_config);
682
683 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
684 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
685 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
686
687 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
688 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
689
690 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
691 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
692 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
693 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
694 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
695 else
696 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
697 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
698
699 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
700 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
701
702 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
703 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
704
705 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
706 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
707 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
708 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
709
710 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
711 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
712 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
713 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
714 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
715 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
716 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
717 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
718
719 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
720 FORCE_EOV_MAX_REZ_CNT(255)));
721
722 if (rdev->family == CHIP_RV710)
723 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
724 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
725 else
726 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
727 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
728
729 switch (rdev->family) {
730 case CHIP_RV770:
731 case CHIP_RV730:
732 case CHIP_RV740:
733 gs_prim_buffer_depth = 384;
734 break;
735 case CHIP_RV710:
736 gs_prim_buffer_depth = 128;
737 break;
738 default:
739 break;
740 }
741
742 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
743 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
744 /* Max value for this is 256 */
745 if (vgt_gs_per_es > 256)
746 vgt_gs_per_es = 256;
747
748 WREG32(VGT_ES_PER_GS, 128);
749 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
750 WREG32(VGT_GS_PER_VS, 2);
751
752 /* more default values. 2D/3D driver should adjust as needed */
753 WREG32(VGT_GS_VERTEX_REUSE, 16);
754 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
755 WREG32(VGT_STRMOUT_EN, 0);
756 WREG32(SX_MISC, 0);
757 WREG32(PA_SC_MODE_CNTL, 0);
758 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
759 WREG32(PA_SC_AA_CONFIG, 0);
760 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
761 WREG32(PA_SC_LINE_STIPPLE, 0);
762 WREG32(SPI_INPUT_Z, 0);
763 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
764 WREG32(CB_COLOR7_FRAG, 0);
765
766 /* clear render buffer base addresses */
767 WREG32(CB_COLOR0_BASE, 0);
768 WREG32(CB_COLOR1_BASE, 0);
769 WREG32(CB_COLOR2_BASE, 0);
770 WREG32(CB_COLOR3_BASE, 0);
771 WREG32(CB_COLOR4_BASE, 0);
772 WREG32(CB_COLOR5_BASE, 0);
773 WREG32(CB_COLOR6_BASE, 0);
774 WREG32(CB_COLOR7_BASE, 0);
775
776 WREG32(TCP_CNTL, 0);
777
778 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
779 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
780
781 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
782
783 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
784 NUM_CLIP_SEQ(3)));
785
786}
787
788int rv770_mc_init(struct radeon_device *rdev)
789{
790 fixed20_12 a;
791 u32 tmp;
792 int r;
793
794 /* Get VRAM informations */
795 /* FIXME: Don't know how to determine vram width, need to check
796 * vram_width usage
797 */
798 rdev->mc.vram_width = 128;
799 rdev->mc.vram_is_ddr = true;
771fe6b9
JG		 800 /* Could aper size report 0 ? */
801 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
802 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
3ce0a23d
JG		 803 /* Setup GPU memory space */
804 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
805 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
806 if (rdev->flags & RADEON_IS_AGP) {
807 r = radeon_agp_init(rdev);
808 if (r)
809 return r;
810 /* gtt_size is setup by radeon_agp_init */
811 rdev->mc.gtt_location = rdev->mc.agp_base;
812 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
813 /* Try to put vram before or after AGP because we
814 * we want SYSTEM_APERTURE to cover both VRAM and
815 * AGP so that GPU can catch out of VRAM/AGP access
816 */
817 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
818 /* Enought place before */
819 rdev->mc.vram_location = rdev->mc.gtt_location -
820 rdev->mc.mc_vram_size;
821 } else if (tmp > rdev->mc.mc_vram_size) {
822 /* Enought place after */
823 rdev->mc.vram_location = rdev->mc.gtt_location +
824 rdev->mc.gtt_size;
825 } else {
826 /* Try to setup VRAM then AGP might not
827 * not work on some card
828 */
829 rdev->mc.vram_location = 0x00000000UL;
830 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
831 }
832 } else {
833 rdev->mc.vram_location = 0x00000000UL;
834 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
835 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
836 }
837 rdev->mc.vram_start = rdev->mc.vram_location;
838 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
839 rdev->mc.gtt_start = rdev->mc.gtt_location;
840 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
841 /* FIXME: we should enforce default clock in case GPU is not in
842 * default setup
843 */
844 a.full = rfixed_const(100);
845 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
846 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
847 return 0;
848}
849int rv770_gpu_reset(struct radeon_device *rdev)
850{
851 /* FIXME: implement */
852 return 0;
853}
854
fc30b8ef 855static int rv770_startup(struct radeon_device *rdev)
3ce0a23d
JG		 856{
857 int r;
858
859 rv770_mc_resume(rdev);
860 r = rv770_pcie_gart_enable(rdev);
861 if (r)
862 return r;
863 rv770_gpu_init(rdev);
9052aa24
DA		 864
865 r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
866 &rdev->r600_blit.shader_gpu_addr);
867 if (r) {
868 DRM_ERROR("failed to pin blit object %d\n", r);
869 return r;
870 }
871
3ce0a23d
JG		 872 r = radeon_ring_init(rdev, rdev->cp.ring_size);
873 if (r)
874 return r;
875 r = rv770_cp_load_microcode(rdev);
876 if (r)
877 return r;
878 r = r600_cp_resume(rdev);
879 if (r)
880 return r;
881 r = r600_wb_init(rdev);
882 if (r)
883 return r;
884 return 0;
885}
886
fc30b8ef
DA		 887int rv770_resume(struct radeon_device *rdev)
888{
889 int r;
890
891 if (radeon_gpu_reset(rdev)) {
892 /* FIXME: what do we want to do here ? */
893 }
894 /* post card */
895 if (rdev->is_atom_bios) {
896 atom_asic_init(rdev->mode_info.atom_context);
897 } else {
898 radeon_combios_asic_init(rdev->ddev);
899 }
900 /* Initialize clocks */
901 r = radeon_clocks_init(rdev);
902 if (r) {
903 return r;
904 }
905
906 r = rv770_startup(rdev);
907 if (r) {
908 DRM_ERROR("r600 startup failed on resume\n");
909 return r;
910 }
911
912 r = radeon_ib_test(rdev);
913 if (r) {
914 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
915 return r;
916 }
917 return r;
918
919}
920
3ce0a23d
JG		 921int rv770_suspend(struct radeon_device *rdev)
922{
923 /* FIXME: we should wait for ring to be empty */
924 r700_cp_stop(rdev);
4153e584 925 rdev->cp.ready = false;
4aac0473 926 rv770_pcie_gart_disable(rdev);
4153e584
DA		 927
928 /* unpin shaders bo */
929 radeon_object_unpin(rdev->r600_blit.shader_obj);
3ce0a23d
JG		 930 return 0;
931}
932
933/* Plan is to move initialization in that function and use
934 * helper function so that radeon_device_init pretty much
935 * do nothing more than calling asic specific function. This
936 * should also allow to remove a bunch of callback function
937 * like vram_info.
938 */
939int rv770_init(struct radeon_device *rdev)
940{
941 int r;
942
943 rdev->new_init_path = true;
944 r = radeon_dummy_page_init(rdev);
945 if (r)
946 return r;
947 /* This don't do much */
948 r = radeon_gem_init(rdev);
949 if (r)
950 return r;
951 /* Read BIOS */
952 if (!radeon_get_bios(rdev)) {
953 if (ASIC_IS_AVIVO(rdev))
954 return -EINVAL;
955 }
956 /* Must be an ATOMBIOS */
957 if (!rdev->is_atom_bios)
958 return -EINVAL;
959 r = radeon_atombios_init(rdev);
960 if (r)
961 return r;
962 /* Post card if necessary */
963 if (!r600_card_posted(rdev) && rdev->bios) {
964 DRM_INFO("GPU not posted. posting now...\n");
965 atom_asic_init(rdev->mode_info.atom_context);
966 }
967 /* Initialize scratch registers */
968 r600_scratch_init(rdev);
969 /* Initialize surface registers */
970 radeon_surface_init(rdev);
5e6dde7e 971 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 972 r = radeon_clocks_init(rdev);
973 if (r)
974 return r;
975 /* Fence driver */
976 r = radeon_fence_driver_init(rdev);
977 if (r)
978 return r;
979 r = rv770_mc_init(rdev);
980 if (r) {
981 if (rdev->flags & RADEON_IS_AGP) {
982 /* Retry with disabling AGP */
983 rv770_fini(rdev);
984 rdev->flags &= ~RADEON_IS_AGP;
985 return rv770_init(rdev);
986 }
987 return r;
988 }
989 /* Memory manager */
990 r = radeon_object_init(rdev);
991 if (r)
992 return r;
993 rdev->cp.ring_obj = NULL;
994 r600_ring_init(rdev, 1024 * 1024);
995
996 if (!rdev->me_fw || !rdev->pfp_fw) {
997 r = r600_cp_init_microcode(rdev);
998 if (r) {
999 DRM_ERROR("Failed to load firmware!\n");
1000 return r;
1001 }
1002 }
1003
4aac0473
JG		 1004 r = r600_pcie_gart_init(rdev);
1005 if (r)
1006 return r;
1007
733289c2 1008 rdev->accel_working = true;
9052aa24
DA		 1009 r = r600_blit_init(rdev);
1010 if (r) {
1011 DRM_ERROR("radeon: failled blitter (%d).\n", r);
1012 rdev->accel_working = false;
1013 }
1014
fc30b8ef 1015 r = rv770_startup(rdev);
3ce0a23d
JG		 1016 if (r) {
1017 if (rdev->flags & RADEON_IS_AGP) {
1018 /* Retry with disabling AGP */
1019 rv770_fini(rdev);
1020 rdev->flags &= ~RADEON_IS_AGP;
1021 return rv770_init(rdev);
1022 }
733289c2 1023 rdev->accel_working = false;
3ce0a23d 1024 }
733289c2 1025 if (rdev->accel_working) {
733289c2
JG		 1026 r = radeon_ib_pool_init(rdev);
1027 if (r) {
1028 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1029 rdev->accel_working = false;
1030 }
1031 r = radeon_ib_test(rdev);
1032 if (r) {
1033 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1034 rdev->accel_working = false;
1035 }
3ce0a23d
JG		 1036 }
1037 return 0;
1038}
1039
1040void rv770_fini(struct radeon_device *rdev)
1041{
1042 r600_blit_fini(rdev);
1043 radeon_ring_fini(rdev);
4aac0473 1044 rv770_pcie_gart_fini(rdev);
3ce0a23d
JG		 1045 radeon_gem_fini(rdev);
1046 radeon_fence_driver_fini(rdev);
1047 radeon_clocks_fini(rdev);
1048#if __OS_HAS_AGP
1049 if (rdev->flags & RADEON_IS_AGP)
1050 radeon_agp_fini(rdev);
1051#endif
1052 radeon_object_fini(rdev);
1053 if (rdev->is_atom_bios) {
1054 radeon_atombios_fini(rdev);
1055 } else {
1056 radeon_combios_fini(rdev);
1057 }
1058 kfree(rdev->bios);
1059 rdev->bios = NULL;
1060 radeon_dummy_page_fini(rdev);
771fe6b9 1061}
Linux 6.x block layer and io_uring tree(s)