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drm/radeon: add set_uvd_clocks callback for SI
[linux-block.git] / drivers / gpu / drm / radeon / rv770.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
3ce0a23d
JG		 28#include <linux/firmware.h>
29#include <linux/platform_device.h>
5a0e3ad6 30#include <linux/slab.h>
760285e7 31#include <drm/drmP.h>
771fe6b9 32#include "radeon.h"
e6990375 33#include "radeon_asic.h"
760285e7 34#include <drm/radeon_drm.h>
3ce0a23d 35#include "rv770d.h"
3ce0a23d 36#include "atom.h"
d39c3b89 37#include "avivod.h"
771fe6b9 38
3ce0a23d
JG		 39#define R700_PFP_UCODE_SIZE 848
40#define R700_PM4_UCODE_SIZE 1360
771fe6b9 41
3ce0a23d
JG		 42static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev);
9e46a48d 44static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
771fe6b9 45
454d2e2a
AD		 46#define PCIE_BUS_CLK 10000
47#define TCLK (PCIE_BUS_CLK / 10)
48
49/**
50 * rv770_get_xclk - get the xclk
51 *
52 * @rdev: radeon_device pointer
53 *
54 * Returns the reference clock used by the gfx engine
55 * (r7xx-cayman).
56 */
57u32 rv770_get_xclk(struct radeon_device *rdev)
58{
59 u32 reference_clock = rdev->clock.spll.reference_freq;
60 u32 tmp = RREG32(CG_CLKPIN_CNTL);
61
62 if (tmp & MUX_TCLK_TO_XCLK)
63 return TCLK;
64
65 if (tmp & XTALIN_DIVIDE)
66 return reference_clock / 4;
67
68 return reference_clock;
69}
70
f2ba57b5
CK		 71int rv770_uvd_resume(struct radeon_device *rdev)
72{
73 uint64_t addr;
74 uint32_t chip_id, size;
75 int r;
76
77 r = radeon_uvd_resume(rdev);
78 if (r)
79 return r;
80
81 /* programm the VCPU memory controller bits 0-27 */
82 addr = rdev->uvd.gpu_addr >> 3;
83 size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
84 WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
85 WREG32(UVD_VCPU_CACHE_SIZE0, size);
86
87 addr += size;
88 size = RADEON_UVD_STACK_SIZE >> 3;
89 WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
90 WREG32(UVD_VCPU_CACHE_SIZE1, size);
91
92 addr += size;
93 size = RADEON_UVD_HEAP_SIZE >> 3;
94 WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
95 WREG32(UVD_VCPU_CACHE_SIZE2, size);
96
97 /* bits 28-31 */
98 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
99 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
100
101 /* bits 32-39 */
102 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
103 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
104
105 /* tell firmware which hardware it is running on */
106 switch (rdev->family) {
107 default:
108 return -EINVAL;
109 case CHIP_RV710:
110 chip_id = 0x01000005;
111 break;
112 case CHIP_RV730:
113 chip_id = 0x01000006;
114 break;
115 case CHIP_RV740:
116 chip_id = 0x01000007;
117 break;
118 case CHIP_CYPRESS:
119 case CHIP_HEMLOCK:
120 chip_id = 0x01000008;
121 break;
122 case CHIP_JUNIPER:
123 chip_id = 0x01000009;
124 break;
125 case CHIP_REDWOOD:
126 chip_id = 0x0100000a;
127 break;
128 case CHIP_CEDAR:
129 chip_id = 0x0100000b;
130 break;
131 case CHIP_SUMO:
132 chip_id = 0x0100000c;
133 break;
134 case CHIP_SUMO2:
135 chip_id = 0x0100000d;
136 break;
137 case CHIP_PALM:
138 chip_id = 0x0100000e;
139 break;
140 case CHIP_CAYMAN:
141 chip_id = 0x0100000f;
142 break;
143 case CHIP_BARTS:
144 chip_id = 0x01000010;
145 break;
146 case CHIP_TURKS:
147 chip_id = 0x01000011;
148 break;
149 case CHIP_CAICOS:
150 chip_id = 0x01000012;
151 break;
152 case CHIP_TAHITI:
153 chip_id = 0x01000014;
154 break;
155 case CHIP_VERDE:
156 chip_id = 0x01000015;
157 break;
158 case CHIP_PITCAIRN:
159 chip_id = 0x01000016;
160 break;
161 case CHIP_ARUBA:
162 chip_id = 0x01000017;
163 break;
164 }
165 WREG32(UVD_VCPU_CHIP_ID, chip_id);
166
167 return 0;
168}
169
6f34be50
AD		 170u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
171{
172 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
173 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
f6496479 174 int i;
6f34be50
AD		 175
176 /* Lock the graphics update lock */
177 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
178 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
179
180 /* update the scanout addresses */
181 if (radeon_crtc->crtc_id) {
182 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
183 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
184 } else {
185 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
186 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
187 }
188 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
189 (u32)crtc_base);
190 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
191 (u32)crtc_base);
192
193 /* Wait for update_pending to go high. */
f6496479
AD		 194 for (i = 0; i < rdev->usec_timeout; i++) {
195 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
196 break;
197 udelay(1);
198 }
6f34be50
AD		 199 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
200
201 /* Unlock the lock, so double-buffering can take place inside vblank */
202 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
203 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
204
205 /* Return current update_pending status: */
206 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
207}
208
21a8122a 209/* get temperature in millidegrees */
20d391d7 210int rv770_get_temp(struct radeon_device *rdev)
21a8122a
AD		 211{
212 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
213 ASIC_T_SHIFT;
20d391d7 214 int actual_temp;
21a8122a 215
20d391d7
AD		 216 if (temp & 0x400)
217 actual_temp = -256;
218 else if (temp & 0x200)
219 actual_temp = 255;
220 else if (temp & 0x100) {
221 actual_temp = temp & 0x1ff;
222 actual_temp |= ~0x1ff;
223 } else
224 actual_temp = temp & 0xff;
21a8122a 225
20d391d7 226 return (actual_temp * 1000) / 2;
21a8122a
AD		 227}
228
49e02b73
AD		 229void rv770_pm_misc(struct radeon_device *rdev)
230{
a081a9d6
RM		 231 int req_ps_idx = rdev->pm.requested_power_state_index;
232 int req_cm_idx = rdev->pm.requested_clock_mode_index;
233 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
234 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
4d60173f
AD		 235
236 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
a377e187
AD		 237 /* 0xff01 is a flag rather then an actual voltage */
238 if (voltage->voltage == 0xff01)
239 return;
4d60173f 240 if (voltage->voltage != rdev->pm.current_vddc) {
8a83ec5e 241 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 242 rdev->pm.current_vddc = voltage->voltage;
0fcbe947 243 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 244 }
245 }
49e02b73 246}
771fe6b9
JG		 247
248/*
3ce0a23d 249 * GART
771fe6b9 250 */
1109ca09 251static int rv770_pcie_gart_enable(struct radeon_device *rdev)
771fe6b9 252{
3ce0a23d
JG		 253 u32 tmp;
254 int r, i;
771fe6b9 255
c9a1be96 256 if (rdev->gart.robj == NULL) {
4aac0473
JG		 257 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
258 return -EINVAL;
3ce0a23d 259 }
4aac0473
JG		 260 r = radeon_gart_table_vram_pin(rdev);
261 if (r)
3ce0a23d 262 return r;
82568565 263 radeon_gart_restore(rdev);
3ce0a23d
JG		 264 /* Setup L2 cache */
265 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
266 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
267 EFFECTIVE_L2_QUEUE_SIZE(7));
268 WREG32(VM_L2_CNTL2, 0);
269 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
270 /* Setup TLB control */
271 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
272 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
273 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
274 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
275 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
276 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
277 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
0b8c30bc
AD		 278 if (rdev->family == CHIP_RV740)
279 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
3ce0a23d
JG		 280 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
281 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
282 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
283 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
284 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 285 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 286 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
287 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
288 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
289 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
290 (u32)(rdev->dummy_page.addr >> 12));
291 for (i = 1; i < 7; i++)
292 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 293
3ce0a23d 294 r600_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 295 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
296 (unsigned)(rdev->mc.gtt_size >> 20),
297 (unsigned long long)rdev->gart.table_addr);
3ce0a23d 298 rdev->gart.ready = true;
771fe6b9
JG		 299 return 0;
300}
301
1109ca09 302static void rv770_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 303{
3ce0a23d 304 u32 tmp;
c9a1be96 305 int i;
3ce0a23d 306
3ce0a23d
JG		 307 /* Disable all tables */
308 for (i = 0; i < 7; i++)
309 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
310
311 /* Setup L2 cache */
312 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
313 EFFECTIVE_L2_QUEUE_SIZE(7));
314 WREG32(VM_L2_CNTL2, 0);
315 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
316 /* Setup TLB control */
317 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
318 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
319 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
320 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
321 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
322 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
323 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
324 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
c9a1be96 325 radeon_gart_table_vram_unpin(rdev);
4aac0473
JG		 326}
327
1109ca09 328static void rv770_pcie_gart_fini(struct radeon_device *rdev)
4aac0473 329{
f9274562 330 radeon_gart_fini(rdev);
4aac0473
JG		 331 rv770_pcie_gart_disable(rdev);
332 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 333}
334
335
1109ca09 336static void rv770_agp_enable(struct radeon_device *rdev)
1a029b76
JG		 337{
338 u32 tmp;
339 int i;
340
341 /* Setup L2 cache */
342 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
343 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
344 EFFECTIVE_L2_QUEUE_SIZE(7));
345 WREG32(VM_L2_CNTL2, 0);
346 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
347 /* Setup TLB control */
348 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
349 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
350 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
351 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
352 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
353 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
354 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
355 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
356 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
357 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
358 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
359 for (i = 0; i < 7; i++)
360 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
361}
362
a3c1945a 363static void rv770_mc_program(struct radeon_device *rdev)
771fe6b9 364{
a3c1945a 365 struct rv515_mc_save save;
3ce0a23d
JG		 366 u32 tmp;
367 int i, j;
368
369 /* Initialize HDP */
370 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
371 WREG32((0x2c14 + j), 0x00000000);
372 WREG32((0x2c18 + j), 0x00000000);
373 WREG32((0x2c1c + j), 0x00000000);
374 WREG32((0x2c20 + j), 0x00000000);
375 WREG32((0x2c24 + j), 0x00000000);
376 }
812d0469
AD		 377 /* r7xx hw bug. Read from HDP_DEBUG1 rather
378 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
379 */
380 tmp = RREG32(HDP_DEBUG1);
3ce0a23d 381
a3c1945a 382 rv515_mc_stop(rdev, &save);
3ce0a23d 383 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 384 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 385 }
3ce0a23d
JG		 386 /* Lockout access through VGA aperture*/
387 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 388 /* Update configuration */
1a029b76
JG		 389 if (rdev->flags & RADEON_IS_AGP) {
390 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
391 /* VRAM before AGP */
392 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
393 rdev->mc.vram_start >> 12);
394 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
395 rdev->mc.gtt_end >> 12);
396 } else {
397 /* VRAM after AGP */
398 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
399 rdev->mc.gtt_start >> 12);
400 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
401 rdev->mc.vram_end >> 12);
402 }
403 } else {
404 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
405 rdev->mc.vram_start >> 12);
406 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
407 rdev->mc.vram_end >> 12);
408 }
16cdf04d 409 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1a029b76 410 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 411 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
412 WREG32(MC_VM_FB_LOCATION, tmp);
413 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
414 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 415 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 416 if (rdev->flags & RADEON_IS_AGP) {
1a029b76 417 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
3ce0a23d
JG		 418 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
419 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
420 } else {
421 WREG32(MC_VM_AGP_BASE, 0);
422 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
423 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
424 }
3ce0a23d 425 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 426 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 427 }
a3c1945a 428 rv515_mc_resume(rdev, &save);
698443d9
DA		 429 /* we need to own VRAM, so turn off the VGA renderer here
430 * to stop it overwriting our objects */
d39c3b89 431 rv515_vga_render_disable(rdev);
771fe6b9
JG		 432}
433
3ce0a23d
JG		 434
435/*
436 * CP.
437 */
438void r700_cp_stop(struct radeon_device *rdev)
771fe6b9 439{
53595338 440 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3ce0a23d 441 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
724c80e1 442 WREG32(SCRATCH_UMSK, 0);
4d75658b 443 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
771fe6b9
JG		 444}
445
3ce0a23d 446static int rv770_cp_load_microcode(struct radeon_device *rdev)
771fe6b9 447{
3ce0a23d
JG		 448 const __be32 *fw_data;
449 int i;
450
451 if (!rdev->me_fw || !rdev->pfp_fw)
452 return -EINVAL;
453
454 r700_cp_stop(rdev);
4eace7fd
CC		 455 WREG32(CP_RB_CNTL,
456#ifdef __BIG_ENDIAN
457 BUF_SWAP_32BIT |
458#endif
459 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
3ce0a23d
JG		 460
461 /* Reset cp */
462 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
463 RREG32(GRBM_SOFT_RESET);
464 mdelay(15);
465 WREG32(GRBM_SOFT_RESET, 0);
466
467 fw_data = (const __be32 *)rdev->pfp_fw->data;
468 WREG32(CP_PFP_UCODE_ADDR, 0);
469 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
470 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
471 WREG32(CP_PFP_UCODE_ADDR, 0);
472
473 fw_data = (const __be32 *)rdev->me_fw->data;
474 WREG32(CP_ME_RAM_WADDR, 0);
475 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
476 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
477
478 WREG32(CP_PFP_UCODE_ADDR, 0);
479 WREG32(CP_ME_RAM_WADDR, 0);
480 WREG32(CP_ME_RAM_RADDR, 0);
481 return 0;
771fe6b9
JG		 482}
483
fe251e2f
AD		 484void r700_cp_fini(struct radeon_device *rdev)
485{
45df6803 486 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
fe251e2f 487 r700_cp_stop(rdev);
45df6803
CK		 488 radeon_ring_fini(rdev, ring);
489 radeon_scratch_free(rdev, ring->rptr_save_reg);
fe251e2f 490}
771fe6b9
JG		 491
492/*
3ce0a23d 493 * Core functions
771fe6b9 494 */
3ce0a23d 495static void rv770_gpu_init(struct radeon_device *rdev)
771fe6b9 496{
3ce0a23d 497 int i, j, num_qd_pipes;
d03f5d59 498 u32 ta_aux_cntl;
3ce0a23d
JG		 499 u32 sx_debug_1;
500 u32 smx_dc_ctl0;
d03f5d59 501 u32 db_debug3;
3ce0a23d
JG		 502 u32 num_gs_verts_per_thread;
503 u32 vgt_gs_per_es;
504 u32 gs_prim_buffer_depth = 0;
505 u32 sq_ms_fifo_sizes;
506 u32 sq_config;
507 u32 sq_thread_resource_mgmt;
508 u32 hdp_host_path_cntl;
509 u32 sq_dyn_gpr_size_simd_ab_0;
3ce0a23d
JG		 510 u32 gb_tiling_config = 0;
511 u32 cc_rb_backend_disable = 0;
512 u32 cc_gc_shader_pipe_config = 0;
513 u32 mc_arb_ramcfg;
416a2bd2
AD		 514 u32 db_debug4, tmp;
515 u32 inactive_pipes, shader_pipe_config;
516 u32 disabled_rb_mask;
517 unsigned active_number;
771fe6b9 518
3ce0a23d 519 /* setup chip specs */
416a2bd2 520 rdev->config.rv770.tiling_group_size = 256;
3ce0a23d
JG		 521 switch (rdev->family) {
522 case CHIP_RV770:
523 rdev->config.rv770.max_pipes = 4;
524 rdev->config.rv770.max_tile_pipes = 8;
525 rdev->config.rv770.max_simds = 10;
526 rdev->config.rv770.max_backends = 4;
527 rdev->config.rv770.max_gprs = 256;
528 rdev->config.rv770.max_threads = 248;
529 rdev->config.rv770.max_stack_entries = 512;
530 rdev->config.rv770.max_hw_contexts = 8;
531 rdev->config.rv770.max_gs_threads = 16 * 2;
532 rdev->config.rv770.sx_max_export_size = 128;
533 rdev->config.rv770.sx_max_export_pos_size = 16;
534 rdev->config.rv770.sx_max_export_smx_size = 112;
535 rdev->config.rv770.sq_num_cf_insts = 2;
536
537 rdev->config.rv770.sx_num_of_sets = 7;
538 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
539 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
540 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
541 break;
542 case CHIP_RV730:
543 rdev->config.rv770.max_pipes = 2;
544 rdev->config.rv770.max_tile_pipes = 4;
545 rdev->config.rv770.max_simds = 8;
546 rdev->config.rv770.max_backends = 2;
547 rdev->config.rv770.max_gprs = 128;
548 rdev->config.rv770.max_threads = 248;
549 rdev->config.rv770.max_stack_entries = 256;
550 rdev->config.rv770.max_hw_contexts = 8;
551 rdev->config.rv770.max_gs_threads = 16 * 2;
552 rdev->config.rv770.sx_max_export_size = 256;
553 rdev->config.rv770.sx_max_export_pos_size = 32;
554 rdev->config.rv770.sx_max_export_smx_size = 224;
555 rdev->config.rv770.sq_num_cf_insts = 2;
556
557 rdev->config.rv770.sx_num_of_sets = 7;
558 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
559 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
560 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
561 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
562 rdev->config.rv770.sx_max_export_pos_size -= 16;
563 rdev->config.rv770.sx_max_export_smx_size += 16;
564 }
565 break;
566 case CHIP_RV710:
567 rdev->config.rv770.max_pipes = 2;
568 rdev->config.rv770.max_tile_pipes = 2;
569 rdev->config.rv770.max_simds = 2;
570 rdev->config.rv770.max_backends = 1;
571 rdev->config.rv770.max_gprs = 256;
572 rdev->config.rv770.max_threads = 192;
573 rdev->config.rv770.max_stack_entries = 256;
574 rdev->config.rv770.max_hw_contexts = 4;
575 rdev->config.rv770.max_gs_threads = 8 * 2;
576 rdev->config.rv770.sx_max_export_size = 128;
577 rdev->config.rv770.sx_max_export_pos_size = 16;
578 rdev->config.rv770.sx_max_export_smx_size = 112;
579 rdev->config.rv770.sq_num_cf_insts = 1;
580
581 rdev->config.rv770.sx_num_of_sets = 7;
582 rdev->config.rv770.sc_prim_fifo_size = 0x40;
583 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
584 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
585 break;
586 case CHIP_RV740:
587 rdev->config.rv770.max_pipes = 4;
588 rdev->config.rv770.max_tile_pipes = 4;
589 rdev->config.rv770.max_simds = 8;
590 rdev->config.rv770.max_backends = 4;
591 rdev->config.rv770.max_gprs = 256;
592 rdev->config.rv770.max_threads = 248;
593 rdev->config.rv770.max_stack_entries = 512;
594 rdev->config.rv770.max_hw_contexts = 8;
595 rdev->config.rv770.max_gs_threads = 16 * 2;
596 rdev->config.rv770.sx_max_export_size = 256;
597 rdev->config.rv770.sx_max_export_pos_size = 32;
598 rdev->config.rv770.sx_max_export_smx_size = 224;
599 rdev->config.rv770.sq_num_cf_insts = 2;
600
601 rdev->config.rv770.sx_num_of_sets = 7;
602 rdev->config.rv770.sc_prim_fifo_size = 0x100;
603 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
604 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
605
606 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
607 rdev->config.rv770.sx_max_export_pos_size -= 16;
608 rdev->config.rv770.sx_max_export_smx_size += 16;
609 }
610 break;
611 default:
612 break;
613 }
614
615 /* Initialize HDP */
616 j = 0;
617 for (i = 0; i < 32; i++) {
618 WREG32((0x2c14 + j), 0x00000000);
619 WREG32((0x2c18 + j), 0x00000000);
620 WREG32((0x2c1c + j), 0x00000000);
621 WREG32((0x2c20 + j), 0x00000000);
622 WREG32((0x2c24 + j), 0x00000000);
623 j += 0x18;
624 }
625
626 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
627
628 /* setup tiling, simd, pipe config */
629 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
630
416a2bd2
AD		 631 shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
632 inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
633 for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
634 if (!(inactive_pipes & tmp)) {
635 active_number++;
636 }
637 tmp <<= 1;
638 }
639 if (active_number == 1) {
640 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);
641 } else {
642 WREG32(SPI_CONFIG_CNTL, 0);
643 }
644
645 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
646 tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16);
647 if (tmp < rdev->config.rv770.max_backends) {
648 rdev->config.rv770.max_backends = tmp;
649 }
650
651 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
652 tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK);
653 if (tmp < rdev->config.rv770.max_pipes) {
654 rdev->config.rv770.max_pipes = tmp;
655 }
656 tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
657 if (tmp < rdev->config.rv770.max_simds) {
658 rdev->config.rv770.max_simds = tmp;
659 }
660
3ce0a23d
JG		 661 switch (rdev->config.rv770.max_tile_pipes) {
662 case 1:
d03f5d59 663 default:
416a2bd2 664 gb_tiling_config = PIPE_TILING(0);
3ce0a23d
JG		 665 break;
666 case 2:
416a2bd2 667 gb_tiling_config = PIPE_TILING(1);
3ce0a23d
JG		 668 break;
669 case 4:
416a2bd2 670 gb_tiling_config = PIPE_TILING(2);
3ce0a23d
JG		 671 break;
672 case 8:
416a2bd2 673 gb_tiling_config = PIPE_TILING(3);
3ce0a23d
JG		 674 break;
675 }
d03f5d59 676 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
3ce0a23d 677
416a2bd2
AD		 678 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
679 tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
680 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
681 R7XX_MAX_BACKENDS, disabled_rb_mask);
682 gb_tiling_config |= tmp << 16;
683 rdev->config.rv770.backend_map = tmp;
684
3ce0a23d
JG		 685 if (rdev->family == CHIP_RV770)
686 gb_tiling_config |= BANK_TILING(1);
29d65406
AD		 687 else {
688 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
689 gb_tiling_config |= BANK_TILING(1);
690 else
691 gb_tiling_config |= BANK_TILING(0);
692 }
961fb597 693 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
881fe6c1 694 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
e29649db 695 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
3ce0a23d
JG		 696 gb_tiling_config |= ROW_TILING(3);
697 gb_tiling_config |= SAMPLE_SPLIT(3);
698 } else {
699 gb_tiling_config |=
700 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
701 gb_tiling_config |=
702 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
703 }
704
705 gb_tiling_config |= BANK_SWAPS(1);
e7aeeba6 706 rdev->config.rv770.tile_config = gb_tiling_config;
3ce0a23d
JG		 707
708 WREG32(GB_TILING_CONFIG, gb_tiling_config);
709 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
710 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
4d75658b
AD		 711 WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
712 WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
3ce0a23d 713
3ce0a23d
JG		 714 WREG32(CGTS_SYS_TCC_DISABLE, 0);
715 WREG32(CGTS_TCC_DISABLE, 0);
f867c60d
AD		 716 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
717 WREG32(CGTS_USER_TCC_DISABLE, 0);
3ce0a23d 718
416a2bd2
AD		 719
720 num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 721 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
722 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
723
724 /* set HW defaults for 3D engine */
725 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
e29649db 726 ROQ_IB2_START(0x2b)));
3ce0a23d
JG		 727
728 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
729
d03f5d59
AD		 730 ta_aux_cntl = RREG32(TA_CNTL_AUX);
731 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
3ce0a23d
JG		 732
733 sx_debug_1 = RREG32(SX_DEBUG_1);
734 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
735 WREG32(SX_DEBUG_1, sx_debug_1);
736
737 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
738 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
739 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
740 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
741
d03f5d59
AD		 742 if (rdev->family != CHIP_RV740)
743 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
744 GS_FLUSH_CTL(4) |
745 ACK_FLUSH_CTL(3) |
746 SYNC_FLUSH_CTL));
3ce0a23d 747
b866d133
AD		 748 if (rdev->family != CHIP_RV770)
749 WREG32(SMX_SAR_CTL0, 0x00003f3f);
750
d03f5d59
AD		 751 db_debug3 = RREG32(DB_DEBUG3);
752 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
753 switch (rdev->family) {
754 case CHIP_RV770:
755 case CHIP_RV740:
756 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
757 break;
758 case CHIP_RV710:
759 case CHIP_RV730:
760 default:
761 db_debug3 |= DB_CLK_OFF_DELAY(2);
762 break;
763 }
764 WREG32(DB_DEBUG3, db_debug3);
765
766 if (rdev->family != CHIP_RV770) {
3ce0a23d
JG		 767 db_debug4 = RREG32(DB_DEBUG4);
768 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
769 WREG32(DB_DEBUG4, db_debug4);
770 }
771
772 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
e29649db
AD		 773 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
774 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
3ce0a23d
JG		 775
776 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
e29649db
AD		 777 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
778 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
3ce0a23d
JG		 779
780 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
781
782 WREG32(VGT_NUM_INSTANCES, 1);
783
3ce0a23d
JG		 784 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
785
786 WREG32(CP_PERFMON_CNTL, 0);
787
788 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
789 DONE_FIFO_HIWATER(0xe0) |
790 ALU_UPDATE_FIFO_HIWATER(0x8));
791 switch (rdev->family) {
792 case CHIP_RV770:
3ce0a23d
JG		 793 case CHIP_RV730:
794 case CHIP_RV710:
d03f5d59
AD		 795 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
796 break;
3ce0a23d
JG		 797 case CHIP_RV740:
798 default:
799 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
800 break;
801 }
802 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
803
804 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
805 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
806 */
807 sq_config = RREG32(SQ_CONFIG);
808 sq_config &= ~(PS_PRIO(3) |
809 VS_PRIO(3) |
810 GS_PRIO(3) |
811 ES_PRIO(3));
812 sq_config |= (DX9_CONSTS |
813 VC_ENABLE |
814 EXPORT_SRC_C |
815 PS_PRIO(0) |
816 VS_PRIO(1) |
817 GS_PRIO(2) |
818 ES_PRIO(3));
819 if (rdev->family == CHIP_RV710)
820 /* no vertex cache */
821 sq_config &= ~VC_ENABLE;
822
823 WREG32(SQ_CONFIG, sq_config);
824
825 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
fe62e1a4
DA		 826 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
827 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
3ce0a23d
JG		 828
829 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
fe62e1a4 830 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
3ce0a23d
JG		 831
832 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
833 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
834 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
835 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
836 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
837 else
838 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
839 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
840
841 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
842 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
843
844 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
845 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
846
847 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
848 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
849 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
850 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
851
852 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
853 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
854 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
855 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
856 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
857 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
858 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
859 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
860
861 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
fe62e1a4 862 FORCE_EOV_MAX_REZ_CNT(255)));
3ce0a23d
JG		 863
864 if (rdev->family == CHIP_RV710)
865 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
fe62e1a4 866 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
3ce0a23d
JG		 867 else
868 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
fe62e1a4 869 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
3ce0a23d
JG		 870
871 switch (rdev->family) {
872 case CHIP_RV770:
873 case CHIP_RV730:
874 case CHIP_RV740:
875 gs_prim_buffer_depth = 384;
876 break;
877 case CHIP_RV710:
878 gs_prim_buffer_depth = 128;
879 break;
880 default:
881 break;
882 }
883
884 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
885 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
886 /* Max value for this is 256 */
887 if (vgt_gs_per_es > 256)
888 vgt_gs_per_es = 256;
889
890 WREG32(VGT_ES_PER_GS, 128);
891 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
892 WREG32(VGT_GS_PER_VS, 2);
893
894 /* more default values. 2D/3D driver should adjust as needed */
895 WREG32(VGT_GS_VERTEX_REUSE, 16);
896 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
897 WREG32(VGT_STRMOUT_EN, 0);
898 WREG32(SX_MISC, 0);
899 WREG32(PA_SC_MODE_CNTL, 0);
900 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
901 WREG32(PA_SC_AA_CONFIG, 0);
902 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
903 WREG32(PA_SC_LINE_STIPPLE, 0);
904 WREG32(SPI_INPUT_Z, 0);
905 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
906 WREG32(CB_COLOR7_FRAG, 0);
907
908 /* clear render buffer base addresses */
909 WREG32(CB_COLOR0_BASE, 0);
910 WREG32(CB_COLOR1_BASE, 0);
911 WREG32(CB_COLOR2_BASE, 0);
912 WREG32(CB_COLOR3_BASE, 0);
913 WREG32(CB_COLOR4_BASE, 0);
914 WREG32(CB_COLOR5_BASE, 0);
915 WREG32(CB_COLOR6_BASE, 0);
916 WREG32(CB_COLOR7_BASE, 0);
917
918 WREG32(TCP_CNTL, 0);
919
920 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
921 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
922
923 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
924
925 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
926 NUM_CLIP_SEQ(3)));
b866d133 927 WREG32(VC_ENHANCE, 0);
3ce0a23d
JG		 928}
929
0ef0c1f7
AD		 930void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
931{
932 u64 size_bf, size_af;
933
934 if (mc->mc_vram_size > 0xE0000000) {
935 /* leave room for at least 512M GTT */
936 dev_warn(rdev->dev, "limiting VRAM\n");
937 mc->real_vram_size = 0xE0000000;
938 mc->mc_vram_size = 0xE0000000;
939 }
940 if (rdev->flags & RADEON_IS_AGP) {
941 size_bf = mc->gtt_start;
9ed8b1f9 942 size_af = mc->mc_mask - mc->gtt_end;
0ef0c1f7
AD		 943 if (size_bf > size_af) {
944 if (mc->mc_vram_size > size_bf) {
945 dev_warn(rdev->dev, "limiting VRAM\n");
946 mc->real_vram_size = size_bf;
947 mc->mc_vram_size = size_bf;
948 }
949 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
950 } else {
951 if (mc->mc_vram_size > size_af) {
952 dev_warn(rdev->dev, "limiting VRAM\n");
953 mc->real_vram_size = size_af;
954 mc->mc_vram_size = size_af;
955 }
dfc6ae5b 956 mc->vram_start = mc->gtt_end + 1;
0ef0c1f7
AD		 957 }
958 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
959 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
960 mc->mc_vram_size >> 20, mc->vram_start,
961 mc->vram_end, mc->real_vram_size >> 20);
962 } else {
b4183e30 963 radeon_vram_location(rdev, &rdev->mc, 0);
0ef0c1f7
AD		 964 rdev->mc.gtt_base_align = 0;
965 radeon_gtt_location(rdev, mc);
966 }
967}
968
1109ca09 969static int rv770_mc_init(struct radeon_device *rdev)
3ce0a23d 970{
3ce0a23d 971 u32 tmp;
5885b7a9 972 int chansize, numchan;
3ce0a23d
JG		 973
974 /* Get VRAM informations */
3ce0a23d 975 rdev->mc.vram_is_ddr = true;
5885b7a9
AD		 976 tmp = RREG32(MC_ARB_RAMCFG);
977 if (tmp & CHANSIZE_OVERRIDE) {
978 chansize = 16;
979 } else if (tmp & CHANSIZE_MASK) {
980 chansize = 64;
981 } else {
982 chansize = 32;
983 }
984 tmp = RREG32(MC_SHARED_CHMAP);
985 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
986 case 0:
987 default:
988 numchan = 1;
989 break;
990 case 1:
991 numchan = 2;
992 break;
993 case 2:
994 numchan = 4;
995 break;
996 case 3:
997 numchan = 8;
998 break;
999 }
1000 rdev->mc.vram_width = numchan * chansize;
771fe6b9 1001 /* Could aper size report 0 ? */
01d73a69
JC		 1002 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1003 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1004 /* Setup GPU memory space */
1005 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1006 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1007 rdev->mc.visible_vram_size = rdev->mc.aper_size;
0ef0c1f7 1008 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 1009 radeon_update_bandwidth_info(rdev);
1010
3ce0a23d
JG		 1011 return 0;
1012}
d594e46a 1013
43fb7787
AD		 1014/**
1015 * rv770_copy_dma - copy pages using the DMA engine
1016 *
1017 * @rdev: radeon_device pointer
1018 * @src_offset: src GPU address
1019 * @dst_offset: dst GPU address
1020 * @num_gpu_pages: number of GPU pages to xfer
1021 * @fence: radeon fence object
1022 *
1023 * Copy GPU paging using the DMA engine (r7xx).
1024 * Used by the radeon ttm implementation to move pages if
1025 * registered as the asic copy callback.
1026 */
1027int rv770_copy_dma(struct radeon_device *rdev,
1028 uint64_t src_offset, uint64_t dst_offset,
1029 unsigned num_gpu_pages,
1030 struct radeon_fence **fence)
1031{
1032 struct radeon_semaphore *sem = NULL;
1033 int ring_index = rdev->asic->copy.dma_ring_index;
1034 struct radeon_ring *ring = &rdev->ring[ring_index];
1035 u32 size_in_dw, cur_size_in_dw;
1036 int i, num_loops;
1037 int r = 0;
1038
1039 r = radeon_semaphore_create(rdev, &sem);
1040 if (r) {
1041 DRM_ERROR("radeon: moving bo (%d).\n", r);
1042 return r;
1043 }
1044
1045 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
1046 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF);
1047 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
1048 if (r) {
1049 DRM_ERROR("radeon: moving bo (%d).\n", r);
1050 radeon_semaphore_free(rdev, &sem, NULL);
1051 return r;
1052 }
1053
1054 if (radeon_fence_need_sync(*fence, ring->idx)) {
1055 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
1056 ring->idx);
1057 radeon_fence_note_sync(*fence, ring->idx);
1058 } else {
1059 radeon_semaphore_free(rdev, &sem, NULL);
1060 }
1061
1062 for (i = 0; i < num_loops; i++) {
1063 cur_size_in_dw = size_in_dw;
1064 if (cur_size_in_dw > 0xFFFF)
1065 cur_size_in_dw = 0xFFFF;
1066 size_in_dw -= cur_size_in_dw;
1067 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
1068 radeon_ring_write(ring, dst_offset & 0xfffffffc);
1069 radeon_ring_write(ring, src_offset & 0xfffffffc);
1070 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
1071 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
1072 src_offset += cur_size_in_dw * 4;
1073 dst_offset += cur_size_in_dw * 4;
1074 }
1075
1076 r = radeon_fence_emit(rdev, fence, ring->idx);
1077 if (r) {
1078 radeon_ring_unlock_undo(rdev, ring);
1079 return r;
1080 }
1081
1082 radeon_ring_unlock_commit(rdev, ring);
1083 radeon_semaphore_free(rdev, &sem, *fence);
1084
1085 return r;
1086}
1087
fc30b8ef 1088static int rv770_startup(struct radeon_device *rdev)
3ce0a23d 1089{
4d75658b 1090 struct radeon_ring *ring;
3ce0a23d
JG		 1091 int r;
1092
9e46a48d
AD		 1093 /* enable pcie gen2 link */
1094 rv770_pcie_gen2_enable(rdev);
1095
779720a3
AD		 1096 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1097 r = r600_init_microcode(rdev);
1098 if (r) {
1099 DRM_ERROR("Failed to load firmware!\n");
1100 return r;
1101 }
1102 }
1103
16cdf04d
AD		 1104 r = r600_vram_scratch_init(rdev);
1105 if (r)
1106 return r;
1107
a3c1945a 1108 rv770_mc_program(rdev);
1a029b76
JG		 1109 if (rdev->flags & RADEON_IS_AGP) {
1110 rv770_agp_enable(rdev);
1111 } else {
1112 r = rv770_pcie_gart_enable(rdev);
1113 if (r)
1114 return r;
1115 }
16cdf04d 1116
3ce0a23d 1117 rv770_gpu_init(rdev);
c38c7b64
JG		 1118 r = r600_blit_init(rdev);
1119 if (r) {
1120 r600_blit_fini(rdev);
27cd7769 1121 rdev->asic->copy.copy = NULL;
c38c7b64
JG		 1122 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1123 }
b70d6bb3 1124
724c80e1
AD		 1125 /* allocate wb buffer */
1126 r = radeon_wb_init(rdev);
1127 if (r)
1128 return r;
1129
30eb77f4
JG		 1130 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1131 if (r) {
1132 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1133 return r;
1134 }
1135
4d75658b
AD		 1136 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1137 if (r) {
1138 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1139 return r;
1140 }
1141
f2ba57b5
CK		 1142 r = rv770_uvd_resume(rdev);
1143 if (!r) {
1144 r = radeon_fence_driver_start_ring(rdev,
1145 R600_RING_TYPE_UVD_INDEX);
1146 if (r)
1147 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1148 }
1149
1150 if (r)
1151 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1152
d8f60cfc 1153 /* Enable IRQ */
d8f60cfc
AD		 1154 r = r600_irq_init(rdev);
1155 if (r) {
1156 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1157 radeon_irq_kms_fini(rdev);
1158 return r;
1159 }
1160 r600_irq_set(rdev);
1161
4d75658b 1162 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
e32eb50d 1163 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 1164 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
1165 0, 0xfffff, RADEON_CP_PACKET2);
3ce0a23d
JG		 1166 if (r)
1167 return r;
4d75658b
AD		 1168
1169 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1170 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1171 DMA_RB_RPTR, DMA_RB_WPTR,
1172 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1173 if (r)
1174 return r;
1175
3ce0a23d
JG		 1176 r = rv770_cp_load_microcode(rdev);
1177 if (r)
1178 return r;
1179 r = r600_cp_resume(rdev);
1180 if (r)
1181 return r;
724c80e1 1182
4d75658b
AD		 1183 r = r600_dma_resume(rdev);
1184 if (r)
1185 return r;
1186
f2ba57b5
CK		 1187 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1188 if (ring->ring_size) {
1189 r = radeon_ring_init(rdev, ring, ring->ring_size,
1190 R600_WB_UVD_RPTR_OFFSET,
1191 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
1192 0, 0xfffff, RADEON_CP_PACKET2);
1193 if (!r)
1194 r = r600_uvd_init(rdev);
1195
1196 if (r)
1197 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
1198 }
1199
2898c348
CK		 1200 r = radeon_ib_pool_init(rdev);
1201 if (r) {
1202 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 1203 return r;
2898c348 1204 }
b15ba512 1205
d4e30ef0
AD		 1206 r = r600_audio_init(rdev);
1207 if (r) {
1208 DRM_ERROR("radeon: audio init failed\n");
1209 return r;
1210 }
1211
3ce0a23d
JG		 1212 return 0;
1213}
1214
fc30b8ef
DA		 1215int rv770_resume(struct radeon_device *rdev)
1216{
1217 int r;
1218
1a029b76
JG		 1219 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1220 * posting will perform necessary task to bring back GPU into good
1221 * shape.
1222 */
fc30b8ef 1223 /* post card */
e7d40b9a 1224 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef 1225
b15ba512 1226 rdev->accel_working = true;
fc30b8ef
DA		 1227 r = rv770_startup(rdev);
1228 if (r) {
1229 DRM_ERROR("r600 startup failed on resume\n");
6b7746e8 1230 rdev->accel_working = false;
fc30b8ef
DA		 1231 return r;
1232 }
1233
fc30b8ef
DA		 1234 return r;
1235
1236}
1237
3ce0a23d
JG		 1238int rv770_suspend(struct radeon_device *rdev)
1239{
8a8c6e7c 1240 r600_audio_fini(rdev);
f2ba57b5 1241 radeon_uvd_suspend(rdev);
3ce0a23d 1242 r700_cp_stop(rdev);
4d75658b 1243 r600_dma_stop(rdev);
0c45249f 1244 r600_irq_suspend(rdev);
724c80e1 1245 radeon_wb_disable(rdev);
4aac0473 1246 rv770_pcie_gart_disable(rdev);
6ddddfe7 1247
3ce0a23d
JG		 1248 return 0;
1249}
1250
1251/* Plan is to move initialization in that function and use
1252 * helper function so that radeon_device_init pretty much
1253 * do nothing more than calling asic specific function. This
1254 * should also allow to remove a bunch of callback function
1255 * like vram_info.
1256 */
1257int rv770_init(struct radeon_device *rdev)
1258{
1259 int r;
1260
3ce0a23d
JG		 1261 /* Read BIOS */
1262 if (!radeon_get_bios(rdev)) {
1263 if (ASIC_IS_AVIVO(rdev))
1264 return -EINVAL;
1265 }
1266 /* Must be an ATOMBIOS */
e7d40b9a
JG		 1267 if (!rdev->is_atom_bios) {
1268 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 1269 return -EINVAL;
e7d40b9a 1270 }
3ce0a23d
JG		 1271 r = radeon_atombios_init(rdev);
1272 if (r)
1273 return r;
1274 /* Post card if necessary */
fd909c37 1275 if (!radeon_card_posted(rdev)) {
72542d77
DA		 1276 if (!rdev->bios) {
1277 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1278 return -EINVAL;
1279 }
3ce0a23d
JG		 1280 DRM_INFO("GPU not posted. posting now...\n");
1281 atom_asic_init(rdev->mode_info.atom_context);
1282 }
1283 /* Initialize scratch registers */
1284 r600_scratch_init(rdev);
1285 /* Initialize surface registers */
1286 radeon_surface_init(rdev);
7433874e 1287 /* Initialize clocks */
5e6dde7e 1288 radeon_get_clock_info(rdev->ddev);
3ce0a23d 1289 /* Fence driver */
30eb77f4 1290 r = radeon_fence_driver_init(rdev);
3ce0a23d
JG		 1291 if (r)
1292 return r;
d594e46a 1293 /* initialize AGP */
700a0cc0
JG		 1294 if (rdev->flags & RADEON_IS_AGP) {
1295 r = radeon_agp_init(rdev);
1296 if (r)
1297 radeon_agp_disable(rdev);
1298 }
3ce0a23d 1299 r = rv770_mc_init(rdev);
b574f251 1300 if (r)
3ce0a23d 1301 return r;
3ce0a23d 1302 /* Memory manager */
4c788679 1303 r = radeon_bo_init(rdev);
3ce0a23d
JG		 1304 if (r)
1305 return r;
d8f60cfc
AD		 1306
1307 r = radeon_irq_kms_init(rdev);
1308 if (r)
1309 return r;
1310
e32eb50d
CK		 1311 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
1312 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3ce0a23d 1313
4d75658b
AD		 1314 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
1315 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
1316
f2ba57b5
CK		 1317 r = radeon_uvd_init(rdev);
1318 if (!r) {
1319 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
1320 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
1321 4096);
1322 }
1323
d8f60cfc
AD		 1324 rdev->ih.ring_obj = NULL;
1325 r600_ih_ring_init(rdev, 64 * 1024);
1326
4aac0473
JG		 1327 r = r600_pcie_gart_init(rdev);
1328 if (r)
1329 return r;
1330
779720a3 1331 rdev->accel_working = true;
fc30b8ef 1332 r = rv770_startup(rdev);
3ce0a23d 1333 if (r) {
655efd3d 1334 dev_err(rdev->dev, "disabling GPU acceleration\n");
fe251e2f 1335 r700_cp_fini(rdev);
4d75658b 1336 r600_dma_fini(rdev);
655efd3d 1337 r600_irq_fini(rdev);
724c80e1 1338 radeon_wb_fini(rdev);
2898c348 1339 radeon_ib_pool_fini(rdev);
655efd3d 1340 radeon_irq_kms_fini(rdev);
75c81298 1341 rv770_pcie_gart_fini(rdev);
733289c2 1342 rdev->accel_working = false;
3ce0a23d 1343 }
8a8c6e7c 1344
3ce0a23d
JG		 1345 return 0;
1346}
1347
1348void rv770_fini(struct radeon_device *rdev)
1349{
1350 r600_blit_fini(rdev);
fe251e2f 1351 r700_cp_fini(rdev);
4d75658b 1352 r600_dma_fini(rdev);
d8f60cfc 1353 r600_irq_fini(rdev);
724c80e1 1354 radeon_wb_fini(rdev);
2898c348 1355 radeon_ib_pool_fini(rdev);
d8f60cfc 1356 radeon_irq_kms_fini(rdev);
4aac0473 1357 rv770_pcie_gart_fini(rdev);
f2ba57b5 1358 radeon_uvd_fini(rdev);
16cdf04d 1359 r600_vram_scratch_fini(rdev);
3ce0a23d
JG		 1360 radeon_gem_fini(rdev);
1361 radeon_fence_driver_fini(rdev);
d0269ed8 1362 radeon_agp_fini(rdev);
4c788679 1363 radeon_bo_fini(rdev);
e7d40b9a 1364 radeon_atombios_fini(rdev);
3ce0a23d
JG		 1365 kfree(rdev->bios);
1366 rdev->bios = NULL;
771fe6b9 1367}
9e46a48d
AD		 1368
1369static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1370{
1371 u32 link_width_cntl, lanes, speed_cntl, tmp;
1372 u16 link_cntl2;
197bbb3d
DA		 1373 u32 mask;
1374 int ret;
9e46a48d 1375
d42dd579
AD		 1376 if (radeon_pcie_gen2 == 0)
1377 return;
1378
9e46a48d
AD		 1379 if (rdev->flags & RADEON_IS_IGP)
1380 return;
1381
1382 if (!(rdev->flags & RADEON_IS_PCIE))
1383 return;
1384
1385 /* x2 cards have a special sequence */
1386 if (ASIC_IS_X2(rdev))
1387 return;
1388
197bbb3d
DA		 1389 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
1390 if (ret != 0)
1391 return;
1392
1393 if (!(mask & DRM_PCIE_SPEED_50))
1394 return;
1395
1396 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
1397
9e46a48d
AD		 1398 /* advertise upconfig capability */
1399 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1400 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1401 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1402 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1403 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1404 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1405 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1406 LC_RECONFIG_ARC_MISSING_ESCAPE);
1407 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1408 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1409 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1410 } else {
1411 link_width_cntl |= LC_UPCONFIGURE_DIS;
1412 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1413 }
1414
1415 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1416 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1417 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1418
1419 tmp = RREG32(0x541c);
1420 WREG32(0x541c, tmp | 0x8);
1421 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1422 link_cntl2 = RREG16(0x4088);
1423 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1424 link_cntl2 |= 0x2;
1425 WREG16(0x4088, link_cntl2);
1426 WREG32(MM_CFGREGS_CNTL, 0);
1427
1428 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1429 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1430 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1431
1432 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1433 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1434 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1435
1436 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1437 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1438 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1439
1440 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1441 speed_cntl |= LC_GEN2_EN_STRAP;
1442 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1443
1444 } else {
1445 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1446 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1447 if (1)
1448 link_width_cntl |= LC_UPCONFIGURE_DIS;
1449 else
1450 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1451 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1452 }
1453}
Linux 6.x block layer and io_uring tree(s)