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4a6369e9 AD |
1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | ||
25 | #include "drmP.h" | |
26 | #include "radeon.h" | |
27 | #include "rv6xxd.h" | |
28 | #include "r600_dpm.h" | |
29 | #include "rv6xx_dpm.h" | |
30 | #include "atom.h" | |
bf0936e1 | 31 | #include <linux/seq_file.h> |
4a6369e9 AD |
32 | |
33 | static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev, | |
34 | u32 unscaled_count, u32 unit); | |
35 | ||
36 | static struct rv6xx_ps *rv6xx_get_ps(struct radeon_ps *rps) | |
37 | { | |
38 | struct rv6xx_ps *ps = rps->ps_priv; | |
39 | ||
40 | return ps; | |
41 | } | |
42 | ||
43 | static struct rv6xx_power_info *rv6xx_get_pi(struct radeon_device *rdev) | |
44 | { | |
45 | struct rv6xx_power_info *pi = rdev->pm.dpm.priv; | |
46 | ||
47 | return pi; | |
48 | } | |
49 | ||
50 | static void rv6xx_force_pcie_gen1(struct radeon_device *rdev) | |
51 | { | |
52 | u32 tmp; | |
53 | int i; | |
54 | ||
55 | tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); | |
56 | tmp &= LC_GEN2_EN; | |
57 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp); | |
58 | ||
59 | tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); | |
60 | tmp |= LC_INITIATE_LINK_SPEED_CHANGE; | |
61 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp); | |
62 | ||
63 | for (i = 0; i < rdev->usec_timeout; i++) { | |
64 | if (!(RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE)) | |
65 | break; | |
66 | udelay(1); | |
67 | } | |
68 | ||
69 | tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); | |
70 | tmp &= ~LC_INITIATE_LINK_SPEED_CHANGE; | |
71 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp); | |
72 | } | |
73 | ||
74 | static void rv6xx_enable_pcie_gen2_support(struct radeon_device *rdev) | |
75 | { | |
76 | u32 tmp; | |
77 | ||
78 | tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); | |
79 | ||
80 | if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) && | |
81 | (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) { | |
82 | tmp |= LC_GEN2_EN; | |
83 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp); | |
84 | } | |
85 | } | |
86 | ||
87 | static void rv6xx_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev, | |
88 | bool enable) | |
89 | { | |
90 | u32 tmp; | |
91 | ||
92 | tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & ~LC_HW_VOLTAGE_IF_CONTROL_MASK; | |
93 | if (enable) | |
94 | tmp |= LC_HW_VOLTAGE_IF_CONTROL(1); | |
95 | else | |
96 | tmp |= LC_HW_VOLTAGE_IF_CONTROL(0); | |
97 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp); | |
98 | } | |
99 | ||
100 | static void rv6xx_enable_l0s(struct radeon_device *rdev) | |
101 | { | |
102 | u32 tmp; | |
103 | ||
104 | tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L0S_INACTIVITY_MASK; | |
105 | tmp |= LC_L0S_INACTIVITY(3); | |
106 | WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp); | |
107 | } | |
108 | ||
109 | static void rv6xx_enable_l1(struct radeon_device *rdev) | |
110 | { | |
111 | u32 tmp; | |
112 | ||
113 | tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL); | |
114 | tmp &= ~LC_L1_INACTIVITY_MASK; | |
115 | tmp |= LC_L1_INACTIVITY(4); | |
116 | tmp &= ~LC_PMI_TO_L1_DIS; | |
117 | tmp &= ~LC_ASPM_TO_L1_DIS; | |
118 | WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp); | |
119 | } | |
120 | ||
121 | static void rv6xx_enable_pll_sleep_in_l1(struct radeon_device *rdev) | |
122 | { | |
123 | u32 tmp; | |
124 | ||
125 | tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L1_INACTIVITY_MASK; | |
126 | tmp |= LC_L1_INACTIVITY(8); | |
127 | WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp); | |
128 | ||
129 | /* NOTE, this is a PCIE indirect reg, not PCIE PORT */ | |
130 | tmp = RREG32_PCIE(PCIE_P_CNTL); | |
131 | tmp |= P_PLL_PWRDN_IN_L1L23; | |
132 | tmp &= ~P_PLL_BUF_PDNB; | |
133 | tmp &= ~P_PLL_PDNB; | |
134 | tmp |= P_ALLOW_PRX_FRONTEND_SHUTOFF; | |
135 | WREG32_PCIE(PCIE_P_CNTL, tmp); | |
136 | } | |
137 | ||
138 | static int rv6xx_convert_clock_to_stepping(struct radeon_device *rdev, | |
139 | u32 clock, struct rv6xx_sclk_stepping *step) | |
140 | { | |
141 | int ret; | |
142 | struct atom_clock_dividers dividers; | |
143 | ||
144 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, | |
145 | clock, false, ÷rs); | |
146 | if (ret) | |
147 | return ret; | |
148 | ||
149 | if (dividers.enable_post_div) | |
150 | step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); | |
151 | else | |
152 | step->post_divider = 1; | |
153 | ||
154 | step->vco_frequency = clock * step->post_divider; | |
155 | ||
156 | return 0; | |
157 | } | |
158 | ||
159 | static void rv6xx_output_stepping(struct radeon_device *rdev, | |
160 | u32 step_index, struct rv6xx_sclk_stepping *step) | |
161 | { | |
162 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
163 | u32 ref_clk = rdev->clock.spll.reference_freq; | |
164 | u32 fb_divider; | |
165 | u32 spll_step_count = rv6xx_scale_count_given_unit(rdev, | |
166 | R600_SPLLSTEPTIME_DFLT * | |
167 | pi->spll_ref_div, | |
168 | R600_SPLLSTEPUNIT_DFLT); | |
169 | ||
170 | r600_engine_clock_entry_enable(rdev, step_index, true); | |
171 | r600_engine_clock_entry_enable_pulse_skipping(rdev, step_index, false); | |
172 | ||
173 | if (step->post_divider == 1) | |
174 | r600_engine_clock_entry_enable_post_divider(rdev, step_index, false); | |
175 | else { | |
176 | u32 lo_len = (step->post_divider - 2) / 2; | |
177 | u32 hi_len = step->post_divider - 2 - lo_len; | |
178 | ||
179 | r600_engine_clock_entry_enable_post_divider(rdev, step_index, true); | |
180 | r600_engine_clock_entry_set_post_divider(rdev, step_index, (hi_len << 4) | lo_len); | |
181 | } | |
182 | ||
183 | fb_divider = ((step->vco_frequency * pi->spll_ref_div) / ref_clk) >> | |
184 | pi->fb_div_scale; | |
185 | ||
186 | r600_engine_clock_entry_set_reference_divider(rdev, step_index, | |
187 | pi->spll_ref_div - 1); | |
188 | r600_engine_clock_entry_set_feedback_divider(rdev, step_index, fb_divider); | |
189 | r600_engine_clock_entry_set_step_time(rdev, step_index, spll_step_count); | |
190 | ||
191 | } | |
192 | ||
193 | static struct rv6xx_sclk_stepping rv6xx_next_vco_step(struct radeon_device *rdev, | |
194 | struct rv6xx_sclk_stepping *cur, | |
195 | bool increasing_vco, u32 step_size) | |
196 | { | |
197 | struct rv6xx_sclk_stepping next; | |
198 | ||
199 | next.post_divider = cur->post_divider; | |
200 | ||
201 | if (increasing_vco) | |
202 | next.vco_frequency = (cur->vco_frequency * (100 + step_size)) / 100; | |
203 | else | |
204 | next.vco_frequency = (cur->vco_frequency * 100 + 99 + step_size) / (100 + step_size); | |
205 | ||
206 | return next; | |
207 | } | |
208 | ||
209 | static bool rv6xx_can_step_post_div(struct radeon_device *rdev, | |
210 | struct rv6xx_sclk_stepping *cur, | |
211 | struct rv6xx_sclk_stepping *target) | |
212 | { | |
213 | return (cur->post_divider > target->post_divider) && | |
214 | ((cur->vco_frequency * target->post_divider) <= | |
215 | (target->vco_frequency * (cur->post_divider - 1))); | |
216 | } | |
217 | ||
218 | static struct rv6xx_sclk_stepping rv6xx_next_post_div_step(struct radeon_device *rdev, | |
219 | struct rv6xx_sclk_stepping *cur, | |
220 | struct rv6xx_sclk_stepping *target) | |
221 | { | |
222 | struct rv6xx_sclk_stepping next = *cur; | |
223 | ||
224 | while (rv6xx_can_step_post_div(rdev, &next, target)) | |
225 | next.post_divider--; | |
226 | ||
227 | return next; | |
228 | } | |
229 | ||
230 | static bool rv6xx_reached_stepping_target(struct radeon_device *rdev, | |
231 | struct rv6xx_sclk_stepping *cur, | |
232 | struct rv6xx_sclk_stepping *target, | |
233 | bool increasing_vco) | |
234 | { | |
235 | return (increasing_vco && (cur->vco_frequency >= target->vco_frequency)) || | |
236 | (!increasing_vco && (cur->vco_frequency <= target->vco_frequency)); | |
237 | } | |
238 | ||
239 | static void rv6xx_generate_steps(struct radeon_device *rdev, | |
240 | u32 low, u32 high, | |
241 | u32 start_index, u8 *end_index) | |
242 | { | |
243 | struct rv6xx_sclk_stepping cur; | |
244 | struct rv6xx_sclk_stepping target; | |
245 | bool increasing_vco; | |
246 | u32 step_index = start_index; | |
247 | ||
248 | rv6xx_convert_clock_to_stepping(rdev, low, &cur); | |
249 | rv6xx_convert_clock_to_stepping(rdev, high, &target); | |
250 | ||
251 | rv6xx_output_stepping(rdev, step_index++, &cur); | |
252 | ||
253 | increasing_vco = (target.vco_frequency >= cur.vco_frequency); | |
254 | ||
255 | if (target.post_divider > cur.post_divider) | |
256 | cur.post_divider = target.post_divider; | |
257 | ||
258 | while (1) { | |
259 | struct rv6xx_sclk_stepping next; | |
260 | ||
261 | if (rv6xx_can_step_post_div(rdev, &cur, &target)) | |
262 | next = rv6xx_next_post_div_step(rdev, &cur, &target); | |
263 | else | |
264 | next = rv6xx_next_vco_step(rdev, &cur, increasing_vco, R600_VCOSTEPPCT_DFLT); | |
265 | ||
266 | if (rv6xx_reached_stepping_target(rdev, &next, &target, increasing_vco)) { | |
267 | struct rv6xx_sclk_stepping tiny = | |
268 | rv6xx_next_vco_step(rdev, &target, !increasing_vco, R600_ENDINGVCOSTEPPCT_DFLT); | |
269 | tiny.post_divider = next.post_divider; | |
270 | ||
271 | if (!rv6xx_reached_stepping_target(rdev, &tiny, &cur, !increasing_vco)) | |
272 | rv6xx_output_stepping(rdev, step_index++, &tiny); | |
273 | ||
274 | if ((next.post_divider != target.post_divider) && | |
275 | (next.vco_frequency != target.vco_frequency)) { | |
276 | struct rv6xx_sclk_stepping final_vco; | |
277 | ||
278 | final_vco.vco_frequency = target.vco_frequency; | |
279 | final_vco.post_divider = next.post_divider; | |
280 | ||
281 | rv6xx_output_stepping(rdev, step_index++, &final_vco); | |
282 | } | |
283 | ||
284 | rv6xx_output_stepping(rdev, step_index++, &target); | |
285 | break; | |
286 | } else | |
287 | rv6xx_output_stepping(rdev, step_index++, &next); | |
288 | ||
289 | cur = next; | |
290 | } | |
291 | ||
292 | *end_index = (u8)step_index - 1; | |
293 | ||
294 | } | |
295 | ||
296 | static void rv6xx_generate_single_step(struct radeon_device *rdev, | |
297 | u32 clock, u32 index) | |
298 | { | |
299 | struct rv6xx_sclk_stepping step; | |
300 | ||
301 | rv6xx_convert_clock_to_stepping(rdev, clock, &step); | |
302 | rv6xx_output_stepping(rdev, index, &step); | |
303 | } | |
304 | ||
305 | static void rv6xx_invalidate_intermediate_steps_range(struct radeon_device *rdev, | |
306 | u32 start_index, u32 end_index) | |
307 | { | |
308 | u32 step_index; | |
309 | ||
310 | for (step_index = start_index + 1; step_index < end_index; step_index++) | |
311 | r600_engine_clock_entry_enable(rdev, step_index, false); | |
312 | } | |
313 | ||
314 | static void rv6xx_set_engine_spread_spectrum_clk_s(struct radeon_device *rdev, | |
315 | u32 index, u32 clk_s) | |
316 | { | |
317 | WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), | |
318 | CLKS(clk_s), ~CLKS_MASK); | |
319 | } | |
320 | ||
321 | static void rv6xx_set_engine_spread_spectrum_clk_v(struct radeon_device *rdev, | |
322 | u32 index, u32 clk_v) | |
323 | { | |
324 | WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), | |
325 | CLKV(clk_v), ~CLKV_MASK); | |
326 | } | |
327 | ||
328 | static void rv6xx_enable_engine_spread_spectrum(struct radeon_device *rdev, | |
329 | u32 index, bool enable) | |
330 | { | |
331 | if (enable) | |
332 | WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), | |
333 | SSEN, ~SSEN); | |
334 | else | |
335 | WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), | |
336 | 0, ~SSEN); | |
337 | } | |
338 | ||
339 | static void rv6xx_set_memory_spread_spectrum_clk_s(struct radeon_device *rdev, | |
340 | u32 clk_s) | |
341 | { | |
342 | WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK); | |
343 | } | |
344 | ||
345 | static void rv6xx_set_memory_spread_spectrum_clk_v(struct radeon_device *rdev, | |
346 | u32 clk_v) | |
347 | { | |
348 | WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK); | |
349 | } | |
350 | ||
351 | static void rv6xx_enable_memory_spread_spectrum(struct radeon_device *rdev, | |
352 | bool enable) | |
353 | { | |
354 | if (enable) | |
355 | WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN); | |
356 | else | |
357 | WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); | |
358 | } | |
359 | ||
360 | static void rv6xx_enable_dynamic_spread_spectrum(struct radeon_device *rdev, | |
361 | bool enable) | |
362 | { | |
363 | if (enable) | |
364 | WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); | |
365 | else | |
366 | WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); | |
367 | } | |
368 | ||
369 | static void rv6xx_memory_clock_entry_enable_post_divider(struct radeon_device *rdev, | |
370 | u32 index, bool enable) | |
371 | { | |
372 | if (enable) | |
373 | WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), | |
374 | LEVEL0_MPLL_DIV_EN, ~LEVEL0_MPLL_DIV_EN); | |
375 | else | |
376 | WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN); | |
377 | } | |
378 | ||
379 | static void rv6xx_memory_clock_entry_set_post_divider(struct radeon_device *rdev, | |
380 | u32 index, u32 divider) | |
381 | { | |
382 | WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), | |
383 | LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK); | |
384 | } | |
385 | ||
386 | static void rv6xx_memory_clock_entry_set_feedback_divider(struct radeon_device *rdev, | |
387 | u32 index, u32 divider) | |
388 | { | |
389 | WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider), | |
390 | ~LEVEL0_MPLL_FB_DIV_MASK); | |
391 | } | |
392 | ||
393 | static void rv6xx_memory_clock_entry_set_reference_divider(struct radeon_device *rdev, | |
394 | u32 index, u32 divider) | |
395 | { | |
396 | WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), | |
397 | LEVEL0_MPLL_REF_DIV(divider), ~LEVEL0_MPLL_REF_DIV_MASK); | |
398 | } | |
399 | ||
400 | static void rv6xx_vid_response_set_brt(struct radeon_device *rdev, u32 rt) | |
401 | { | |
402 | WREG32_P(VID_RT, BRT(rt), ~BRT_MASK); | |
403 | } | |
404 | ||
405 | static void rv6xx_enable_engine_feedback_and_reference_sync(struct radeon_device *rdev) | |
406 | { | |
407 | WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC); | |
408 | } | |
409 | ||
410 | static u64 rv6xx_clocks_per_unit(u32 unit) | |
411 | { | |
412 | u64 tmp = 1 << (2 * unit); | |
413 | ||
414 | return tmp; | |
415 | } | |
416 | ||
417 | static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev, | |
418 | u32 unscaled_count, u32 unit) | |
419 | { | |
420 | u32 count_per_unit = (u32)rv6xx_clocks_per_unit(unit); | |
421 | ||
422 | return (unscaled_count + count_per_unit - 1) / count_per_unit; | |
423 | } | |
424 | ||
425 | static u32 rv6xx_compute_count_for_delay(struct radeon_device *rdev, | |
426 | u32 delay_us, u32 unit) | |
427 | { | |
428 | u32 ref_clk = rdev->clock.spll.reference_freq; | |
429 | ||
430 | return rv6xx_scale_count_given_unit(rdev, delay_us * (ref_clk / 100), unit); | |
431 | } | |
432 | ||
433 | static void rv6xx_calculate_engine_speed_stepping_parameters(struct radeon_device *rdev, | |
434 | struct rv6xx_ps *state) | |
435 | { | |
436 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
437 | ||
438 | pi->hw.sclks[R600_POWER_LEVEL_LOW] = | |
439 | state->low.sclk; | |
440 | pi->hw.sclks[R600_POWER_LEVEL_MEDIUM] = | |
441 | state->medium.sclk; | |
442 | pi->hw.sclks[R600_POWER_LEVEL_HIGH] = | |
443 | state->high.sclk; | |
444 | ||
445 | pi->hw.low_sclk_index = R600_POWER_LEVEL_LOW; | |
446 | pi->hw.medium_sclk_index = R600_POWER_LEVEL_MEDIUM; | |
447 | pi->hw.high_sclk_index = R600_POWER_LEVEL_HIGH; | |
448 | } | |
449 | ||
450 | static void rv6xx_calculate_memory_clock_stepping_parameters(struct radeon_device *rdev, | |
451 | struct rv6xx_ps *state) | |
452 | { | |
453 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
454 | ||
455 | pi->hw.mclks[R600_POWER_LEVEL_CTXSW] = | |
456 | state->high.mclk; | |
457 | pi->hw.mclks[R600_POWER_LEVEL_HIGH] = | |
458 | state->high.mclk; | |
459 | pi->hw.mclks[R600_POWER_LEVEL_MEDIUM] = | |
460 | state->medium.mclk; | |
461 | pi->hw.mclks[R600_POWER_LEVEL_LOW] = | |
462 | state->low.mclk; | |
463 | ||
464 | pi->hw.high_mclk_index = R600_POWER_LEVEL_HIGH; | |
465 | ||
466 | if (state->high.mclk == state->medium.mclk) | |
467 | pi->hw.medium_mclk_index = | |
468 | pi->hw.high_mclk_index; | |
469 | else | |
470 | pi->hw.medium_mclk_index = R600_POWER_LEVEL_MEDIUM; | |
471 | ||
472 | ||
473 | if (state->medium.mclk == state->low.mclk) | |
474 | pi->hw.low_mclk_index = | |
475 | pi->hw.medium_mclk_index; | |
476 | else | |
477 | pi->hw.low_mclk_index = R600_POWER_LEVEL_LOW; | |
478 | } | |
479 | ||
480 | static void rv6xx_calculate_voltage_stepping_parameters(struct radeon_device *rdev, | |
481 | struct rv6xx_ps *state) | |
482 | { | |
483 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
484 | ||
485 | pi->hw.vddc[R600_POWER_LEVEL_CTXSW] = state->high.vddc; | |
486 | pi->hw.vddc[R600_POWER_LEVEL_HIGH] = state->high.vddc; | |
487 | pi->hw.vddc[R600_POWER_LEVEL_MEDIUM] = state->medium.vddc; | |
488 | pi->hw.vddc[R600_POWER_LEVEL_LOW] = state->low.vddc; | |
489 | ||
490 | pi->hw.backbias[R600_POWER_LEVEL_CTXSW] = | |
491 | (state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false; | |
492 | pi->hw.backbias[R600_POWER_LEVEL_HIGH] = | |
493 | (state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false; | |
494 | pi->hw.backbias[R600_POWER_LEVEL_MEDIUM] = | |
495 | (state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false; | |
496 | pi->hw.backbias[R600_POWER_LEVEL_LOW] = | |
497 | (state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false; | |
498 | ||
499 | pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH] = | |
500 | (state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false; | |
501 | pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM] = | |
502 | (state->medium.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false; | |
503 | pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW] = | |
504 | (state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false; | |
505 | ||
506 | pi->hw.high_vddc_index = R600_POWER_LEVEL_HIGH; | |
507 | ||
508 | if ((state->high.vddc == state->medium.vddc) && | |
509 | ((state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) == | |
510 | (state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE))) | |
511 | pi->hw.medium_vddc_index = | |
512 | pi->hw.high_vddc_index; | |
513 | else | |
514 | pi->hw.medium_vddc_index = R600_POWER_LEVEL_MEDIUM; | |
515 | ||
516 | if ((state->medium.vddc == state->low.vddc) && | |
517 | ((state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) == | |
518 | (state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE))) | |
519 | pi->hw.low_vddc_index = | |
520 | pi->hw.medium_vddc_index; | |
521 | else | |
522 | pi->hw.medium_vddc_index = R600_POWER_LEVEL_LOW; | |
523 | } | |
524 | ||
525 | static inline u32 rv6xx_calculate_vco_frequency(u32 ref_clock, | |
526 | struct atom_clock_dividers *dividers, | |
527 | u32 fb_divider_scale) | |
528 | { | |
529 | return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / | |
530 | (dividers->ref_div + 1); | |
531 | } | |
532 | ||
533 | static inline u32 rv6xx_calculate_spread_spectrum_clk_v(u32 vco_freq, u32 ref_freq, | |
534 | u32 ss_rate, u32 ss_percent, | |
535 | u32 fb_divider_scale) | |
536 | { | |
537 | u32 fb_divider = vco_freq / ref_freq; | |
538 | ||
539 | return (ss_percent * ss_rate * 4 * (fb_divider * fb_divider) / | |
540 | (5375 * ((vco_freq * 10) / (4096 >> fb_divider_scale)))); | |
541 | } | |
542 | ||
543 | static inline u32 rv6xx_calculate_spread_spectrum_clk_s(u32 ss_rate, u32 ref_freq) | |
544 | { | |
545 | return (((ref_freq * 10) / (ss_rate * 2)) - 1) / 4; | |
546 | } | |
547 | ||
548 | static void rv6xx_program_engine_spread_spectrum(struct radeon_device *rdev, | |
549 | u32 clock, enum r600_power_level level) | |
550 | { | |
551 | u32 ref_clk = rdev->clock.spll.reference_freq; | |
552 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
553 | struct atom_clock_dividers dividers; | |
554 | struct radeon_atom_ss ss; | |
555 | u32 vco_freq, clk_v, clk_s; | |
556 | ||
557 | rv6xx_enable_engine_spread_spectrum(rdev, level, false); | |
558 | ||
559 | if (clock && pi->sclk_ss) { | |
560 | if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) == 0) { | |
561 | vco_freq = rv6xx_calculate_vco_frequency(ref_clk, ÷rs, | |
562 | pi->fb_div_scale); | |
563 | ||
564 | if (radeon_atombios_get_asic_ss_info(rdev, &ss, | |
565 | ASIC_INTERNAL_ENGINE_SS, vco_freq)) { | |
566 | clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq, | |
567 | (ref_clk / (dividers.ref_div + 1)), | |
568 | ss.rate, | |
569 | ss.percentage, | |
570 | pi->fb_div_scale); | |
571 | ||
572 | clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate, | |
573 | (ref_clk / (dividers.ref_div + 1))); | |
574 | ||
575 | rv6xx_set_engine_spread_spectrum_clk_v(rdev, level, clk_v); | |
576 | rv6xx_set_engine_spread_spectrum_clk_s(rdev, level, clk_s); | |
577 | rv6xx_enable_engine_spread_spectrum(rdev, level, true); | |
578 | } | |
579 | } | |
580 | } | |
581 | } | |
582 | ||
583 | static void rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(struct radeon_device *rdev) | |
584 | { | |
585 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
586 | ||
587 | rv6xx_program_engine_spread_spectrum(rdev, | |
588 | pi->hw.sclks[R600_POWER_LEVEL_HIGH], | |
589 | R600_POWER_LEVEL_HIGH); | |
590 | ||
591 | rv6xx_program_engine_spread_spectrum(rdev, | |
592 | pi->hw.sclks[R600_POWER_LEVEL_MEDIUM], | |
593 | R600_POWER_LEVEL_MEDIUM); | |
594 | ||
595 | } | |
596 | ||
597 | static int rv6xx_program_mclk_stepping_entry(struct radeon_device *rdev, | |
598 | u32 entry, u32 clock) | |
599 | { | |
600 | struct atom_clock_dividers dividers; | |
601 | ||
602 | if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, ÷rs)) | |
603 | return -EINVAL; | |
604 | ||
605 | ||
606 | rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div); | |
607 | rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div); | |
608 | rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div); | |
609 | ||
610 | if (dividers.enable_post_div) | |
611 | rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, true); | |
612 | else | |
613 | rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, false); | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
618 | static void rv6xx_program_mclk_stepping_parameters_except_lowest_entry(struct radeon_device *rdev) | |
619 | { | |
620 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
621 | int i; | |
622 | ||
623 | for (i = 1; i < R600_PM_NUMBER_OF_MCLKS; i++) { | |
624 | if (pi->hw.mclks[i]) | |
625 | rv6xx_program_mclk_stepping_entry(rdev, i, | |
626 | pi->hw.mclks[i]); | |
627 | } | |
628 | } | |
629 | ||
630 | static void rv6xx_find_memory_clock_with_highest_vco(struct radeon_device *rdev, | |
631 | u32 requested_memory_clock, | |
632 | u32 ref_clk, | |
633 | struct atom_clock_dividers *dividers, | |
634 | u32 *vco_freq) | |
635 | { | |
636 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
637 | struct atom_clock_dividers req_dividers; | |
638 | u32 vco_freq_temp; | |
639 | ||
640 | if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, | |
641 | requested_memory_clock, false, &req_dividers) == 0) { | |
642 | vco_freq_temp = rv6xx_calculate_vco_frequency(ref_clk, &req_dividers, | |
643 | pi->fb_div_scale); | |
644 | ||
645 | if (vco_freq_temp > *vco_freq) { | |
646 | *dividers = req_dividers; | |
647 | *vco_freq = vco_freq_temp; | |
648 | } | |
649 | } | |
650 | } | |
651 | ||
652 | static void rv6xx_program_mclk_spread_spectrum_parameters(struct radeon_device *rdev) | |
653 | { | |
654 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
655 | u32 ref_clk = rdev->clock.mpll.reference_freq; | |
656 | struct atom_clock_dividers dividers; | |
657 | struct radeon_atom_ss ss; | |
658 | u32 vco_freq = 0, clk_v, clk_s; | |
659 | ||
660 | rv6xx_enable_memory_spread_spectrum(rdev, false); | |
661 | ||
662 | if (pi->mclk_ss) { | |
663 | rv6xx_find_memory_clock_with_highest_vco(rdev, | |
664 | pi->hw.mclks[pi->hw.high_mclk_index], | |
665 | ref_clk, | |
666 | ÷rs, | |
667 | &vco_freq); | |
668 | ||
669 | rv6xx_find_memory_clock_with_highest_vco(rdev, | |
670 | pi->hw.mclks[pi->hw.medium_mclk_index], | |
671 | ref_clk, | |
672 | ÷rs, | |
673 | &vco_freq); | |
674 | ||
675 | rv6xx_find_memory_clock_with_highest_vco(rdev, | |
676 | pi->hw.mclks[pi->hw.low_mclk_index], | |
677 | ref_clk, | |
678 | ÷rs, | |
679 | &vco_freq); | |
680 | ||
681 | if (vco_freq) { | |
682 | if (radeon_atombios_get_asic_ss_info(rdev, &ss, | |
683 | ASIC_INTERNAL_MEMORY_SS, vco_freq)) { | |
684 | clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq, | |
685 | (ref_clk / (dividers.ref_div + 1)), | |
686 | ss.rate, | |
687 | ss.percentage, | |
688 | pi->fb_div_scale); | |
689 | ||
690 | clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate, | |
691 | (ref_clk / (dividers.ref_div + 1))); | |
692 | ||
693 | rv6xx_set_memory_spread_spectrum_clk_v(rdev, clk_v); | |
694 | rv6xx_set_memory_spread_spectrum_clk_s(rdev, clk_s); | |
695 | rv6xx_enable_memory_spread_spectrum(rdev, true); | |
696 | } | |
697 | } | |
698 | } | |
699 | } | |
700 | ||
701 | static int rv6xx_program_voltage_stepping_entry(struct radeon_device *rdev, | |
702 | u32 entry, u16 voltage) | |
703 | { | |
704 | u32 mask, set_pins; | |
705 | int ret; | |
706 | ||
707 | ret = radeon_atom_get_voltage_gpio_settings(rdev, voltage, | |
708 | SET_VOLTAGE_TYPE_ASIC_VDDC, | |
709 | &set_pins, &mask); | |
710 | if (ret) | |
711 | return ret; | |
712 | ||
713 | r600_voltage_control_program_voltages(rdev, entry, set_pins); | |
714 | ||
715 | return 0; | |
716 | } | |
717 | ||
718 | static void rv6xx_program_voltage_stepping_parameters_except_lowest_entry(struct radeon_device *rdev) | |
719 | { | |
720 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
721 | int i; | |
722 | ||
723 | for (i = 1; i < R600_PM_NUMBER_OF_VOLTAGE_LEVELS; i++) | |
724 | rv6xx_program_voltage_stepping_entry(rdev, i, | |
725 | pi->hw.vddc[i]); | |
726 | ||
727 | } | |
728 | ||
729 | static void rv6xx_program_backbias_stepping_parameters_except_lowest_entry(struct radeon_device *rdev) | |
730 | { | |
731 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
732 | ||
733 | if (pi->hw.backbias[1]) | |
734 | WREG32_P(VID_UPPER_GPIO_CNTL, MEDIUM_BACKBIAS_VALUE, ~MEDIUM_BACKBIAS_VALUE); | |
735 | else | |
736 | WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~MEDIUM_BACKBIAS_VALUE); | |
737 | ||
738 | if (pi->hw.backbias[2]) | |
739 | WREG32_P(VID_UPPER_GPIO_CNTL, HIGH_BACKBIAS_VALUE, ~HIGH_BACKBIAS_VALUE); | |
740 | else | |
741 | WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~HIGH_BACKBIAS_VALUE); | |
742 | } | |
743 | ||
744 | static void rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(struct radeon_device *rdev) | |
745 | { | |
746 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
747 | ||
748 | rv6xx_program_engine_spread_spectrum(rdev, | |
749 | pi->hw.sclks[R600_POWER_LEVEL_LOW], | |
750 | R600_POWER_LEVEL_LOW); | |
751 | } | |
752 | ||
753 | static void rv6xx_program_mclk_stepping_parameters_lowest_entry(struct radeon_device *rdev) | |
754 | { | |
755 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
756 | ||
757 | if (pi->hw.mclks[0]) | |
758 | rv6xx_program_mclk_stepping_entry(rdev, 0, | |
759 | pi->hw.mclks[0]); | |
760 | } | |
761 | ||
762 | static void rv6xx_program_voltage_stepping_parameters_lowest_entry(struct radeon_device *rdev) | |
763 | { | |
764 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
765 | ||
766 | rv6xx_program_voltage_stepping_entry(rdev, 0, | |
767 | pi->hw.vddc[0]); | |
768 | ||
769 | } | |
770 | ||
771 | static void rv6xx_program_backbias_stepping_parameters_lowest_entry(struct radeon_device *rdev) | |
772 | { | |
773 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
774 | ||
775 | if (pi->hw.backbias[0]) | |
776 | WREG32_P(VID_UPPER_GPIO_CNTL, LOW_BACKBIAS_VALUE, ~LOW_BACKBIAS_VALUE); | |
777 | else | |
778 | WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~LOW_BACKBIAS_VALUE); | |
779 | } | |
780 | ||
781 | static u32 calculate_memory_refresh_rate(struct radeon_device *rdev, | |
782 | u32 engine_clock) | |
783 | { | |
784 | u32 dram_rows, dram_refresh_rate; | |
785 | u32 tmp; | |
786 | ||
787 | tmp = (RREG32(RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; | |
788 | dram_rows = 1 << (tmp + 10); | |
789 | dram_refresh_rate = 1 << ((RREG32(MC_SEQ_RESERVE_M) & 0x3) + 3); | |
790 | ||
791 | return ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; | |
792 | } | |
793 | ||
794 | static void rv6xx_program_memory_timing_parameters(struct radeon_device *rdev) | |
795 | { | |
796 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
797 | u32 sqm_ratio; | |
798 | u32 arb_refresh_rate; | |
799 | u32 high_clock; | |
800 | ||
801 | if (pi->hw.sclks[R600_POWER_LEVEL_HIGH] < | |
802 | (pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40)) | |
803 | high_clock = pi->hw.sclks[R600_POWER_LEVEL_HIGH]; | |
804 | else | |
805 | high_clock = | |
806 | pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40; | |
807 | ||
808 | radeon_atom_set_engine_dram_timings(rdev, high_clock, 0); | |
809 | ||
810 | sqm_ratio = (STATE0(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_LOW]) | | |
811 | STATE1(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_MEDIUM]) | | |
812 | STATE2(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]) | | |
813 | STATE3(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH])); | |
814 | WREG32(SQM_RATIO, sqm_ratio); | |
815 | ||
816 | arb_refresh_rate = | |
817 | (POWERMODE0(calculate_memory_refresh_rate(rdev, | |
818 | pi->hw.sclks[R600_POWER_LEVEL_LOW])) | | |
819 | POWERMODE1(calculate_memory_refresh_rate(rdev, | |
820 | pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) | | |
821 | POWERMODE2(calculate_memory_refresh_rate(rdev, | |
e3c736fe | 822 | pi->hw.sclks[R600_POWER_LEVEL_HIGH])) | |
4a6369e9 AD |
823 | POWERMODE3(calculate_memory_refresh_rate(rdev, |
824 | pi->hw.sclks[R600_POWER_LEVEL_HIGH]))); | |
825 | WREG32(ARB_RFSH_RATE, arb_refresh_rate); | |
826 | } | |
827 | ||
828 | static void rv6xx_program_mpll_timing_parameters(struct radeon_device *rdev) | |
829 | { | |
830 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
831 | ||
832 | r600_set_mpll_lock_time(rdev, R600_MPLLLOCKTIME_DFLT * | |
833 | pi->mpll_ref_div); | |
834 | r600_set_mpll_reset_time(rdev, R600_MPLLRESETTIME_DFLT); | |
835 | } | |
836 | ||
837 | static void rv6xx_program_bsp(struct radeon_device *rdev) | |
838 | { | |
839 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
840 | u32 ref_clk = rdev->clock.spll.reference_freq; | |
841 | ||
842 | r600_calculate_u_and_p(R600_ASI_DFLT, | |
843 | ref_clk, 16, | |
844 | &pi->bsp, | |
845 | &pi->bsu); | |
846 | ||
847 | r600_set_bsp(rdev, pi->bsu, pi->bsp); | |
848 | } | |
849 | ||
850 | static void rv6xx_program_at(struct radeon_device *rdev) | |
851 | { | |
852 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
853 | ||
854 | r600_set_at(rdev, | |
855 | (pi->hw.rp[0] * pi->bsp) / 200, | |
856 | (pi->hw.rp[1] * pi->bsp) / 200, | |
857 | (pi->hw.lp[2] * pi->bsp) / 200, | |
858 | (pi->hw.lp[1] * pi->bsp) / 200); | |
859 | } | |
860 | ||
861 | static void rv6xx_program_git(struct radeon_device *rdev) | |
862 | { | |
863 | r600_set_git(rdev, R600_GICST_DFLT); | |
864 | } | |
865 | ||
866 | static void rv6xx_program_tp(struct radeon_device *rdev) | |
867 | { | |
868 | int i; | |
869 | ||
870 | for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) | |
871 | r600_set_tc(rdev, i, r600_utc[i], r600_dtc[i]); | |
872 | ||
873 | r600_select_td(rdev, R600_TD_DFLT); | |
874 | } | |
875 | ||
876 | static void rv6xx_program_vc(struct radeon_device *rdev) | |
877 | { | |
878 | r600_set_vrc(rdev, R600_VRC_DFLT); | |
879 | } | |
880 | ||
881 | static void rv6xx_clear_vc(struct radeon_device *rdev) | |
882 | { | |
883 | r600_set_vrc(rdev, 0); | |
884 | } | |
885 | ||
886 | static void rv6xx_program_tpp(struct radeon_device *rdev) | |
887 | { | |
888 | r600_set_tpu(rdev, R600_TPU_DFLT); | |
889 | r600_set_tpc(rdev, R600_TPC_DFLT); | |
890 | } | |
891 | ||
892 | static void rv6xx_program_sstp(struct radeon_device *rdev) | |
893 | { | |
894 | r600_set_sstu(rdev, R600_SSTU_DFLT); | |
895 | r600_set_sst(rdev, R600_SST_DFLT); | |
896 | } | |
897 | ||
898 | static void rv6xx_program_fcp(struct radeon_device *rdev) | |
899 | { | |
900 | r600_set_fctu(rdev, R600_FCTU_DFLT); | |
901 | r600_set_fct(rdev, R600_FCT_DFLT); | |
902 | } | |
903 | ||
904 | static void rv6xx_program_vddc3d_parameters(struct radeon_device *rdev) | |
905 | { | |
906 | r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT); | |
907 | r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT); | |
908 | r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT); | |
909 | r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT); | |
910 | r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT); | |
911 | } | |
912 | ||
913 | static void rv6xx_program_voltage_timing_parameters(struct radeon_device *rdev) | |
914 | { | |
915 | u32 rt; | |
916 | ||
917 | r600_vid_rt_set_vru(rdev, R600_VRU_DFLT); | |
918 | ||
919 | r600_vid_rt_set_vrt(rdev, | |
920 | rv6xx_compute_count_for_delay(rdev, | |
921 | rdev->pm.dpm.voltage_response_time, | |
922 | R600_VRU_DFLT)); | |
923 | ||
924 | rt = rv6xx_compute_count_for_delay(rdev, | |
925 | rdev->pm.dpm.backbias_response_time, | |
926 | R600_VRU_DFLT); | |
927 | ||
928 | rv6xx_vid_response_set_brt(rdev, (rt + 0x1F) >> 5); | |
929 | } | |
930 | ||
931 | static void rv6xx_program_engine_speed_parameters(struct radeon_device *rdev) | |
932 | { | |
933 | r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT); | |
934 | rv6xx_enable_engine_feedback_and_reference_sync(rdev); | |
935 | } | |
936 | ||
937 | static u64 rv6xx_get_master_voltage_mask(struct radeon_device *rdev) | |
938 | { | |
939 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
940 | u64 master_mask = 0; | |
941 | int i; | |
942 | ||
943 | for (i = 0; i < R600_PM_NUMBER_OF_VOLTAGE_LEVELS; i++) { | |
944 | u32 tmp_mask, tmp_set_pins; | |
945 | int ret; | |
946 | ||
947 | ret = radeon_atom_get_voltage_gpio_settings(rdev, | |
948 | pi->hw.vddc[i], | |
949 | SET_VOLTAGE_TYPE_ASIC_VDDC, | |
950 | &tmp_set_pins, &tmp_mask); | |
951 | ||
952 | if (ret == 0) | |
953 | master_mask |= tmp_mask; | |
954 | } | |
955 | ||
956 | return master_mask; | |
957 | } | |
958 | ||
959 | static void rv6xx_program_voltage_gpio_pins(struct radeon_device *rdev) | |
960 | { | |
961 | r600_voltage_control_enable_pins(rdev, | |
962 | rv6xx_get_master_voltage_mask(rdev)); | |
963 | } | |
964 | ||
c70d4553 AD |
965 | static void rv6xx_enable_static_voltage_control(struct radeon_device *rdev, |
966 | struct radeon_ps *new_ps, | |
967 | bool enable) | |
4a6369e9 | 968 | { |
c70d4553 | 969 | struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps); |
4a6369e9 AD |
970 | |
971 | if (enable) | |
972 | radeon_atom_set_voltage(rdev, | |
973 | new_state->low.vddc, | |
974 | SET_VOLTAGE_TYPE_ASIC_VDDC); | |
975 | else | |
976 | r600_voltage_control_deactivate_static_control(rdev, | |
977 | rv6xx_get_master_voltage_mask(rdev)); | |
978 | } | |
979 | ||
980 | static void rv6xx_enable_display_gap(struct radeon_device *rdev, bool enable) | |
981 | { | |
982 | if (enable) { | |
983 | u32 tmp = (DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) | | |
984 | DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) | | |
985 | DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) | | |
986 | DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) | | |
987 | VBI_TIMER_COUNT(0x3FFF) | | |
988 | VBI_TIMER_UNIT(7)); | |
989 | WREG32(CG_DISPLAY_GAP_CNTL, tmp); | |
990 | ||
991 | WREG32_P(MCLK_PWRMGT_CNTL, USE_DISPLAY_GAP, ~USE_DISPLAY_GAP); | |
992 | } else | |
993 | WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP); | |
994 | } | |
995 | ||
996 | static void rv6xx_program_power_level_enter_state(struct radeon_device *rdev) | |
997 | { | |
998 | r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_MEDIUM); | |
999 | } | |
1000 | ||
1001 | static void rv6xx_calculate_t(u32 l_f, u32 h_f, int h, | |
1002 | int d_l, int d_r, u8 *l, u8 *r) | |
1003 | { | |
1004 | int a_n, a_d, h_r, l_r; | |
1005 | ||
1006 | h_r = d_l; | |
1007 | l_r = 100 - d_r; | |
1008 | ||
1009 | a_n = (int)h_f * d_l + (int)l_f * (h - d_r); | |
1010 | a_d = (int)l_f * l_r + (int)h_f * h_r; | |
1011 | ||
1012 | if (a_d != 0) { | |
1013 | *l = d_l - h_r * a_n / a_d; | |
1014 | *r = d_r + l_r * a_n / a_d; | |
1015 | } | |
1016 | } | |
1017 | ||
1018 | static void rv6xx_calculate_ap(struct radeon_device *rdev, | |
1019 | struct rv6xx_ps *state) | |
1020 | { | |
1021 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
1022 | ||
1023 | pi->hw.lp[0] = 0; | |
1024 | pi->hw.rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS - 1] | |
1025 | = 100; | |
1026 | ||
1027 | rv6xx_calculate_t(state->low.sclk, | |
1028 | state->medium.sclk, | |
1029 | R600_AH_DFLT, | |
1030 | R600_LMP_DFLT, | |
1031 | R600_RLP_DFLT, | |
1032 | &pi->hw.lp[1], | |
1033 | &pi->hw.rp[0]); | |
1034 | ||
1035 | rv6xx_calculate_t(state->medium.sclk, | |
1036 | state->high.sclk, | |
1037 | R600_AH_DFLT, | |
1038 | R600_LHP_DFLT, | |
1039 | R600_RMP_DFLT, | |
1040 | &pi->hw.lp[2], | |
1041 | &pi->hw.rp[1]); | |
1042 | ||
1043 | } | |
1044 | ||
c70d4553 AD |
1045 | static void rv6xx_calculate_stepping_parameters(struct radeon_device *rdev, |
1046 | struct radeon_ps *new_ps) | |
4a6369e9 | 1047 | { |
c70d4553 | 1048 | struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps); |
4a6369e9 AD |
1049 | |
1050 | rv6xx_calculate_engine_speed_stepping_parameters(rdev, new_state); | |
1051 | rv6xx_calculate_memory_clock_stepping_parameters(rdev, new_state); | |
1052 | rv6xx_calculate_voltage_stepping_parameters(rdev, new_state); | |
1053 | rv6xx_calculate_ap(rdev, new_state); | |
1054 | } | |
1055 | ||
1056 | static void rv6xx_program_stepping_parameters_except_lowest_entry(struct radeon_device *rdev) | |
1057 | { | |
1058 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
1059 | ||
1060 | rv6xx_program_mclk_stepping_parameters_except_lowest_entry(rdev); | |
1061 | if (pi->voltage_control) | |
1062 | rv6xx_program_voltage_stepping_parameters_except_lowest_entry(rdev); | |
1063 | rv6xx_program_backbias_stepping_parameters_except_lowest_entry(rdev); | |
1064 | rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(rdev); | |
1065 | rv6xx_program_mclk_spread_spectrum_parameters(rdev); | |
1066 | rv6xx_program_memory_timing_parameters(rdev); | |
1067 | } | |
1068 | ||
1069 | static void rv6xx_program_stepping_parameters_lowest_entry(struct radeon_device *rdev) | |
1070 | { | |
1071 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
1072 | ||
1073 | rv6xx_program_mclk_stepping_parameters_lowest_entry(rdev); | |
1074 | if (pi->voltage_control) | |
1075 | rv6xx_program_voltage_stepping_parameters_lowest_entry(rdev); | |
1076 | rv6xx_program_backbias_stepping_parameters_lowest_entry(rdev); | |
1077 | rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(rdev); | |
1078 | } | |
1079 | ||
1080 | static void rv6xx_program_power_level_low(struct radeon_device *rdev) | |
1081 | { | |
1082 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
1083 | ||
1084 | r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, | |
1085 | pi->hw.low_vddc_index); | |
1086 | r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, | |
1087 | pi->hw.low_mclk_index); | |
1088 | r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, | |
1089 | pi->hw.low_sclk_index); | |
1090 | r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, | |
1091 | R600_DISPLAY_WATERMARK_LOW); | |
1092 | r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW, | |
1093 | pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]); | |
1094 | } | |
1095 | ||
1096 | static void rv6xx_program_power_level_low_to_lowest_state(struct radeon_device *rdev) | |
1097 | { | |
1098 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
1099 | ||
1100 | r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0); | |
1101 | r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0); | |
1102 | r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0); | |
1103 | ||
1104 | r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, | |
1105 | R600_DISPLAY_WATERMARK_LOW); | |
1106 | ||
1107 | r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW, | |
1108 | pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]); | |
1109 | ||
1110 | } | |
1111 | ||
1112 | static void rv6xx_program_power_level_medium(struct radeon_device *rdev) | |
1113 | { | |
1114 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
1115 | ||
1116 | r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, | |
1117 | pi->hw.medium_vddc_index); | |
1118 | r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, | |
1119 | pi->hw.medium_mclk_index); | |
1120 | r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, | |
1121 | pi->hw.medium_sclk_index); | |
1122 | r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, | |
1123 | R600_DISPLAY_WATERMARK_LOW); | |
1124 | r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM, | |
1125 | pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM]); | |
1126 | } | |
1127 | ||
1128 | static void rv6xx_program_power_level_medium_for_transition(struct radeon_device *rdev) | |
1129 | { | |
1130 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
1131 | ||
1132 | rv6xx_program_mclk_stepping_entry(rdev, | |
1133 | R600_POWER_LEVEL_CTXSW, | |
1134 | pi->hw.mclks[pi->hw.low_mclk_index]); | |
1135 | ||
1136 | r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 1); | |
1137 | ||
1138 | r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, | |
1139 | R600_POWER_LEVEL_CTXSW); | |
1140 | r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, | |
1141 | pi->hw.medium_sclk_index); | |
1142 | ||
1143 | r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, | |
1144 | R600_DISPLAY_WATERMARK_LOW); | |
1145 | ||
1146 | rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false); | |
1147 | ||
1148 | r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM, | |
1149 | pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]); | |
1150 | } | |
1151 | ||
1152 | static void rv6xx_program_power_level_high(struct radeon_device *rdev) | |
1153 | { | |
1154 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
1155 | ||
1156 | r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH, | |
1157 | pi->hw.high_vddc_index); | |
1158 | r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH, | |
1159 | pi->hw.high_mclk_index); | |
1160 | r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH, | |
1161 | pi->hw.high_sclk_index); | |
1162 | ||
1163 | r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH, | |
1164 | R600_DISPLAY_WATERMARK_HIGH); | |
1165 | ||
1166 | r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_HIGH, | |
1167 | pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH]); | |
1168 | } | |
1169 | ||
1170 | static void rv6xx_enable_backbias(struct radeon_device *rdev, bool enable) | |
1171 | { | |
1172 | if (enable) | |
1173 | WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL, | |
1174 | ~(BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL)); | |
1175 | else | |
1176 | WREG32_P(GENERAL_PWRMGT, 0, | |
1177 | ~(BACKBIAS_VALUE | BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL)); | |
1178 | } | |
1179 | ||
1180 | static void rv6xx_program_display_gap(struct radeon_device *rdev) | |
1181 | { | |
1182 | u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); | |
1183 | ||
1184 | tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); | |
2333a003 | 1185 | if (rdev->pm.dpm.new_active_crtcs & 1) { |
4a6369e9 AD |
1186 | tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK); |
1187 | tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE); | |
2333a003 | 1188 | } else if (rdev->pm.dpm.new_active_crtcs & 2) { |
4a6369e9 AD |
1189 | tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE); |
1190 | tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK); | |
1191 | } else { | |
1192 | tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE); | |
1193 | tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE); | |
1194 | } | |
1195 | WREG32(CG_DISPLAY_GAP_CNTL, tmp); | |
1196 | } | |
1197 | ||
c70d4553 AD |
1198 | static void rv6xx_set_sw_voltage_to_safe(struct radeon_device *rdev, |
1199 | struct radeon_ps *new_ps, | |
1200 | struct radeon_ps *old_ps) | |
4a6369e9 | 1201 | { |
c70d4553 AD |
1202 | struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps); |
1203 | struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps); | |
4a6369e9 AD |
1204 | u16 safe_voltage; |
1205 | ||
1206 | safe_voltage = (new_state->low.vddc >= old_state->low.vddc) ? | |
1207 | new_state->low.vddc : old_state->low.vddc; | |
1208 | ||
1209 | rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW, | |
1210 | safe_voltage); | |
1211 | ||
1212 | WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW), | |
1213 | ~SW_GPIO_INDEX_MASK); | |
1214 | } | |
1215 | ||
c70d4553 AD |
1216 | static void rv6xx_set_sw_voltage_to_low(struct radeon_device *rdev, |
1217 | struct radeon_ps *old_ps) | |
4a6369e9 | 1218 | { |
c70d4553 | 1219 | struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps); |
4a6369e9 AD |
1220 | |
1221 | rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW, | |
1222 | old_state->low.vddc); | |
1223 | ||
1224 | WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW), | |
1225 | ~SW_GPIO_INDEX_MASK); | |
1226 | } | |
1227 | ||
c70d4553 AD |
1228 | static void rv6xx_set_safe_backbias(struct radeon_device *rdev, |
1229 | struct radeon_ps *new_ps, | |
1230 | struct radeon_ps *old_ps) | |
4a6369e9 | 1231 | { |
c70d4553 AD |
1232 | struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps); |
1233 | struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps); | |
4a6369e9 AD |
1234 | |
1235 | if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) && | |
1236 | (old_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE)) | |
1237 | WREG32_P(GENERAL_PWRMGT, BACKBIAS_VALUE, ~BACKBIAS_VALUE); | |
1238 | else | |
1239 | WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE); | |
1240 | } | |
1241 | ||
c70d4553 AD |
1242 | static void rv6xx_set_safe_pcie_gen2(struct radeon_device *rdev, |
1243 | struct radeon_ps *new_ps, | |
1244 | struct radeon_ps *old_ps) | |
4a6369e9 | 1245 | { |
c70d4553 AD |
1246 | struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps); |
1247 | struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps); | |
4a6369e9 AD |
1248 | |
1249 | if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) != | |
1250 | (old_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)) | |
1251 | rv6xx_force_pcie_gen1(rdev); | |
1252 | } | |
1253 | ||
1254 | static void rv6xx_enable_dynamic_voltage_control(struct radeon_device *rdev, | |
1255 | bool enable) | |
1256 | { | |
1257 | if (enable) | |
1258 | WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); | |
1259 | else | |
1260 | WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); | |
1261 | } | |
1262 | ||
1263 | static void rv6xx_enable_dynamic_backbias_control(struct radeon_device *rdev, | |
1264 | bool enable) | |
1265 | { | |
1266 | if (enable) | |
1267 | WREG32_P(GENERAL_PWRMGT, BACKBIAS_DPM_CNTL, ~BACKBIAS_DPM_CNTL); | |
1268 | else | |
1269 | WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_DPM_CNTL); | |
1270 | } | |
1271 | ||
1272 | static int rv6xx_step_sw_voltage(struct radeon_device *rdev, | |
1273 | u16 initial_voltage, | |
1274 | u16 target_voltage) | |
1275 | { | |
1276 | u16 current_voltage; | |
1277 | u16 true_target_voltage; | |
1278 | u16 voltage_step; | |
1279 | int signed_voltage_step; | |
1280 | ||
1281 | if ((radeon_atom_get_voltage_step(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, | |
1282 | &voltage_step)) || | |
1283 | (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, | |
1284 | initial_voltage, ¤t_voltage)) || | |
1285 | (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, | |
1286 | target_voltage, &true_target_voltage))) | |
1287 | return -EINVAL; | |
1288 | ||
1289 | if (true_target_voltage < current_voltage) | |
1290 | signed_voltage_step = -(int)voltage_step; | |
1291 | else | |
1292 | signed_voltage_step = voltage_step; | |
1293 | ||
1294 | while (current_voltage != true_target_voltage) { | |
1295 | current_voltage += signed_voltage_step; | |
1296 | rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW, | |
1297 | current_voltage); | |
1298 | msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000); | |
1299 | } | |
1300 | ||
1301 | return 0; | |
1302 | } | |
1303 | ||
c70d4553 AD |
1304 | static int rv6xx_step_voltage_if_increasing(struct radeon_device *rdev, |
1305 | struct radeon_ps *new_ps, | |
1306 | struct radeon_ps *old_ps) | |
4a6369e9 | 1307 | { |
c70d4553 AD |
1308 | struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps); |
1309 | struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps); | |
4a6369e9 AD |
1310 | |
1311 | if (new_state->low.vddc > old_state->low.vddc) | |
1312 | return rv6xx_step_sw_voltage(rdev, | |
1313 | old_state->low.vddc, | |
1314 | new_state->low.vddc); | |
1315 | ||
1316 | return 0; | |
1317 | } | |
1318 | ||
c70d4553 AD |
1319 | static int rv6xx_step_voltage_if_decreasing(struct radeon_device *rdev, |
1320 | struct radeon_ps *new_ps, | |
1321 | struct radeon_ps *old_ps) | |
4a6369e9 | 1322 | { |
c70d4553 AD |
1323 | struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps); |
1324 | struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps); | |
4a6369e9 AD |
1325 | |
1326 | if (new_state->low.vddc < old_state->low.vddc) | |
1327 | return rv6xx_step_sw_voltage(rdev, | |
1328 | old_state->low.vddc, | |
1329 | new_state->low.vddc); | |
1330 | else | |
1331 | return 0; | |
1332 | } | |
1333 | ||
1334 | static void rv6xx_enable_high(struct radeon_device *rdev) | |
1335 | { | |
1336 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
1337 | ||
1338 | if ((pi->restricted_levels < 1) || | |
1339 | (pi->restricted_levels == 3)) | |
1340 | r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true); | |
1341 | } | |
1342 | ||
1343 | static void rv6xx_enable_medium(struct radeon_device *rdev) | |
1344 | { | |
1345 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
1346 | ||
1347 | if (pi->restricted_levels < 2) | |
1348 | r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true); | |
1349 | } | |
1350 | ||
1351 | static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) | |
1352 | { | |
1353 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
1354 | bool want_thermal_protection; | |
1355 | enum radeon_dpm_event_src dpm_event_src; | |
1356 | ||
1357 | switch (sources) { | |
1358 | case 0: | |
1359 | default: | |
1360 | want_thermal_protection = false; | |
1361 | break; | |
1362 | case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): | |
1363 | want_thermal_protection = true; | |
1364 | dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; | |
1365 | break; | |
1366 | ||
1367 | case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): | |
1368 | want_thermal_protection = true; | |
1369 | dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; | |
1370 | break; | |
1371 | ||
1372 | case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | | |
1373 | (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): | |
1374 | want_thermal_protection = true; | |
1375 | dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; | |
1376 | break; | |
1377 | } | |
1378 | ||
1379 | if (want_thermal_protection) { | |
1380 | WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); | |
1381 | if (pi->thermal_protection) | |
1382 | WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); | |
1383 | } else { | |
1384 | WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); | |
1385 | } | |
1386 | } | |
1387 | ||
1388 | static void rv6xx_enable_auto_throttle_source(struct radeon_device *rdev, | |
1389 | enum radeon_dpm_auto_throttle_src source, | |
1390 | bool enable) | |
1391 | { | |
1392 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
1393 | ||
1394 | if (enable) { | |
1395 | if (!(pi->active_auto_throttle_sources & (1 << source))) { | |
1396 | pi->active_auto_throttle_sources |= 1 << source; | |
1397 | rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); | |
1398 | } | |
1399 | } else { | |
1400 | if (pi->active_auto_throttle_sources & (1 << source)) { | |
1401 | pi->active_auto_throttle_sources &= ~(1 << source); | |
1402 | rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); | |
1403 | } | |
1404 | } | |
1405 | } | |
1406 | ||
1407 | ||
1408 | static void rv6xx_enable_thermal_protection(struct radeon_device *rdev, | |
1409 | bool enable) | |
1410 | { | |
1411 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
1412 | ||
1413 | if (pi->active_auto_throttle_sources) | |
1414 | r600_enable_thermal_protection(rdev, enable); | |
1415 | } | |
1416 | ||
c70d4553 AD |
1417 | static void rv6xx_generate_transition_stepping(struct radeon_device *rdev, |
1418 | struct radeon_ps *new_ps, | |
1419 | struct radeon_ps *old_ps) | |
4a6369e9 | 1420 | { |
c70d4553 AD |
1421 | struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps); |
1422 | struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps); | |
4a6369e9 AD |
1423 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); |
1424 | ||
1425 | rv6xx_generate_steps(rdev, | |
1426 | old_state->low.sclk, | |
1427 | new_state->low.sclk, | |
1428 | 0, &pi->hw.medium_sclk_index); | |
1429 | } | |
1430 | ||
c70d4553 AD |
1431 | static void rv6xx_generate_low_step(struct radeon_device *rdev, |
1432 | struct radeon_ps *new_ps) | |
4a6369e9 | 1433 | { |
c70d4553 | 1434 | struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps); |
4a6369e9 AD |
1435 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); |
1436 | ||
1437 | pi->hw.low_sclk_index = 0; | |
1438 | rv6xx_generate_single_step(rdev, | |
1439 | new_state->low.sclk, | |
1440 | 0); | |
1441 | } | |
1442 | ||
1443 | static void rv6xx_invalidate_intermediate_steps(struct radeon_device *rdev) | |
1444 | { | |
1445 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
1446 | ||
1447 | rv6xx_invalidate_intermediate_steps_range(rdev, 0, | |
1448 | pi->hw.medium_sclk_index); | |
1449 | } | |
1450 | ||
c70d4553 AD |
1451 | static void rv6xx_generate_stepping_table(struct radeon_device *rdev, |
1452 | struct radeon_ps *new_ps) | |
4a6369e9 | 1453 | { |
c70d4553 | 1454 | struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps); |
4a6369e9 AD |
1455 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); |
1456 | ||
1457 | pi->hw.low_sclk_index = 0; | |
1458 | ||
1459 | rv6xx_generate_steps(rdev, | |
1460 | new_state->low.sclk, | |
1461 | new_state->medium.sclk, | |
1462 | 0, | |
1463 | &pi->hw.medium_sclk_index); | |
1464 | rv6xx_generate_steps(rdev, | |
1465 | new_state->medium.sclk, | |
1466 | new_state->high.sclk, | |
1467 | pi->hw.medium_sclk_index, | |
1468 | &pi->hw.high_sclk_index); | |
1469 | } | |
1470 | ||
1471 | static void rv6xx_enable_spread_spectrum(struct radeon_device *rdev, | |
1472 | bool enable) | |
1473 | { | |
1474 | if (enable) | |
1475 | rv6xx_enable_dynamic_spread_spectrum(rdev, true); | |
1476 | else { | |
1477 | rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_LOW, false); | |
1478 | rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false); | |
1479 | rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_HIGH, false); | |
1480 | rv6xx_enable_dynamic_spread_spectrum(rdev, false); | |
1481 | rv6xx_enable_memory_spread_spectrum(rdev, false); | |
1482 | } | |
1483 | } | |
1484 | ||
1485 | static void rv6xx_reset_lvtm_data_sync(struct radeon_device *rdev) | |
1486 | { | |
1487 | if (ASIC_IS_DCE3(rdev)) | |
1488 | WREG32_P(DCE3_LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG); | |
1489 | else | |
1490 | WREG32_P(LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG); | |
1491 | } | |
1492 | ||
1493 | static void rv6xx_enable_dynamic_pcie_gen2(struct radeon_device *rdev, | |
c70d4553 | 1494 | struct radeon_ps *new_ps, |
4a6369e9 AD |
1495 | bool enable) |
1496 | { | |
c70d4553 | 1497 | struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps); |
4a6369e9 AD |
1498 | |
1499 | if (enable) { | |
1500 | rv6xx_enable_bif_dynamic_pcie_gen2(rdev, true); | |
1501 | rv6xx_enable_pcie_gen2_support(rdev); | |
1502 | r600_enable_dynamic_pcie_gen2(rdev, true); | |
1503 | } else { | |
1504 | if (!(new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)) | |
1505 | rv6xx_force_pcie_gen1(rdev); | |
1506 | rv6xx_enable_bif_dynamic_pcie_gen2(rdev, false); | |
1507 | r600_enable_dynamic_pcie_gen2(rdev, false); | |
1508 | } | |
1509 | } | |
1510 | ||
02478a10 AD |
1511 | static void rv6xx_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, |
1512 | struct radeon_ps *new_ps, | |
1513 | struct radeon_ps *old_ps) | |
1514 | { | |
1515 | struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps); | |
1516 | struct rv6xx_ps *current_state = rv6xx_get_ps(old_ps); | |
1517 | ||
1518 | if ((new_ps->vclk == old_ps->vclk) && | |
1519 | (new_ps->dclk == old_ps->dclk)) | |
1520 | return; | |
1521 | ||
1522 | if (new_state->high.sclk >= current_state->high.sclk) | |
1523 | return; | |
1524 | ||
1525 | radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); | |
1526 | } | |
1527 | ||
1528 | static void rv6xx_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, | |
1529 | struct radeon_ps *new_ps, | |
1530 | struct radeon_ps *old_ps) | |
1531 | { | |
1532 | struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps); | |
1533 | struct rv6xx_ps *current_state = rv6xx_get_ps(old_ps); | |
1534 | ||
1535 | if ((new_ps->vclk == old_ps->vclk) && | |
1536 | (new_ps->dclk == old_ps->dclk)) | |
1537 | return; | |
1538 | ||
1539 | if (new_state->high.sclk < current_state->high.sclk) | |
1540 | return; | |
1541 | ||
1542 | radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); | |
1543 | } | |
1544 | ||
4a6369e9 AD |
1545 | int rv6xx_dpm_enable(struct radeon_device *rdev) |
1546 | { | |
1547 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
c70d4553 | 1548 | struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; |
ac0cdcb5 | 1549 | int ret; |
4a6369e9 AD |
1550 | |
1551 | if (r600_dynamicpm_enabled(rdev)) | |
1552 | return -EINVAL; | |
1553 | ||
1554 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) | |
1555 | rv6xx_enable_backbias(rdev, true); | |
1556 | ||
1557 | if (pi->dynamic_ss) | |
1558 | rv6xx_enable_spread_spectrum(rdev, true); | |
1559 | ||
1560 | rv6xx_program_mpll_timing_parameters(rdev); | |
1561 | rv6xx_program_bsp(rdev); | |
1562 | rv6xx_program_git(rdev); | |
1563 | rv6xx_program_tp(rdev); | |
1564 | rv6xx_program_tpp(rdev); | |
1565 | rv6xx_program_sstp(rdev); | |
1566 | rv6xx_program_fcp(rdev); | |
1567 | rv6xx_program_vddc3d_parameters(rdev); | |
1568 | rv6xx_program_voltage_timing_parameters(rdev); | |
1569 | rv6xx_program_engine_speed_parameters(rdev); | |
1570 | ||
1571 | rv6xx_enable_display_gap(rdev, true); | |
1572 | if (pi->display_gap == false) | |
1573 | rv6xx_enable_display_gap(rdev, false); | |
1574 | ||
1575 | rv6xx_program_power_level_enter_state(rdev); | |
1576 | ||
c70d4553 | 1577 | rv6xx_calculate_stepping_parameters(rdev, boot_ps); |
4a6369e9 AD |
1578 | |
1579 | if (pi->voltage_control) | |
1580 | rv6xx_program_voltage_gpio_pins(rdev); | |
1581 | ||
c70d4553 | 1582 | rv6xx_generate_stepping_table(rdev, boot_ps); |
4a6369e9 AD |
1583 | |
1584 | rv6xx_program_stepping_parameters_except_lowest_entry(rdev); | |
1585 | rv6xx_program_stepping_parameters_lowest_entry(rdev); | |
1586 | ||
1587 | rv6xx_program_power_level_low(rdev); | |
1588 | rv6xx_program_power_level_medium(rdev); | |
1589 | rv6xx_program_power_level_high(rdev); | |
1590 | rv6xx_program_vc(rdev); | |
1591 | rv6xx_program_at(rdev); | |
1592 | ||
1593 | r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); | |
1594 | r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true); | |
1595 | r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true); | |
1596 | ||
1597 | if (rdev->irq.installed && | |
1598 | r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { | |
ac0cdcb5 AD |
1599 | ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); |
1600 | if (ret) | |
1601 | return ret; | |
4a6369e9 AD |
1602 | rdev->irq.dpm_thermal = true; |
1603 | radeon_irq_set(rdev); | |
1604 | } | |
1605 | ||
1606 | rv6xx_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); | |
1607 | ||
1608 | r600_start_dpm(rdev); | |
1609 | ||
1610 | if (pi->voltage_control) | |
c70d4553 | 1611 | rv6xx_enable_static_voltage_control(rdev, boot_ps, false); |
4a6369e9 AD |
1612 | |
1613 | if (pi->dynamic_pcie_gen2) | |
c70d4553 | 1614 | rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, true); |
4a6369e9 AD |
1615 | |
1616 | if (pi->gfx_clock_gating) | |
1617 | r600_gfx_clockgating_enable(rdev, true); | |
1618 | ||
1619 | return 0; | |
1620 | } | |
1621 | ||
1622 | void rv6xx_dpm_disable(struct radeon_device *rdev) | |
1623 | { | |
1624 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
c70d4553 | 1625 | struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; |
4a6369e9 AD |
1626 | |
1627 | if (!r600_dynamicpm_enabled(rdev)) | |
1628 | return; | |
1629 | ||
1630 | r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); | |
1631 | r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true); | |
1632 | rv6xx_enable_display_gap(rdev, false); | |
1633 | rv6xx_clear_vc(rdev); | |
1634 | r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF); | |
1635 | ||
1636 | if (pi->thermal_protection) | |
1637 | r600_enable_thermal_protection(rdev, false); | |
1638 | ||
1639 | r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW); | |
1640 | r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false); | |
1641 | r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); | |
1642 | ||
1643 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) | |
1644 | rv6xx_enable_backbias(rdev, false); | |
1645 | ||
1646 | rv6xx_enable_spread_spectrum(rdev, false); | |
1647 | ||
1648 | if (pi->voltage_control) | |
c70d4553 | 1649 | rv6xx_enable_static_voltage_control(rdev, boot_ps, true); |
4a6369e9 AD |
1650 | |
1651 | if (pi->dynamic_pcie_gen2) | |
c70d4553 | 1652 | rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, false); |
4a6369e9 AD |
1653 | |
1654 | if (rdev->irq.installed && | |
1655 | r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { | |
1656 | rdev->irq.dpm_thermal = false; | |
1657 | radeon_irq_set(rdev); | |
1658 | } | |
1659 | ||
1660 | if (pi->gfx_clock_gating) | |
1661 | r600_gfx_clockgating_enable(rdev, false); | |
1662 | ||
1663 | r600_stop_dpm(rdev); | |
1664 | } | |
1665 | ||
1666 | int rv6xx_dpm_set_power_state(struct radeon_device *rdev) | |
1667 | { | |
1668 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
c70d4553 AD |
1669 | struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; |
1670 | struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; | |
ac0cdcb5 | 1671 | int ret; |
4a6369e9 | 1672 | |
f4f85a8c AD |
1673 | pi->restricted_levels = 0; |
1674 | ||
02478a10 AD |
1675 | rv6xx_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); |
1676 | ||
4a6369e9 AD |
1677 | rv6xx_clear_vc(rdev); |
1678 | r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); | |
1679 | r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF); | |
1680 | ||
1681 | if (pi->thermal_protection) | |
1682 | r600_enable_thermal_protection(rdev, false); | |
1683 | ||
1684 | r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW); | |
1685 | r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false); | |
1686 | r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); | |
1687 | ||
c70d4553 | 1688 | rv6xx_generate_transition_stepping(rdev, new_ps, old_ps); |
4a6369e9 AD |
1689 | rv6xx_program_power_level_medium_for_transition(rdev); |
1690 | ||
1691 | if (pi->voltage_control) { | |
c70d4553 | 1692 | rv6xx_set_sw_voltage_to_safe(rdev, new_ps, old_ps); |
4a6369e9 | 1693 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) |
c70d4553 | 1694 | rv6xx_set_sw_voltage_to_low(rdev, old_ps); |
4a6369e9 AD |
1695 | } |
1696 | ||
1697 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) | |
c70d4553 | 1698 | rv6xx_set_safe_backbias(rdev, new_ps, old_ps); |
4a6369e9 AD |
1699 | |
1700 | if (pi->dynamic_pcie_gen2) | |
c70d4553 | 1701 | rv6xx_set_safe_pcie_gen2(rdev, new_ps, old_ps); |
4a6369e9 AD |
1702 | |
1703 | if (pi->voltage_control) | |
1704 | rv6xx_enable_dynamic_voltage_control(rdev, false); | |
1705 | ||
1706 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) | |
1707 | rv6xx_enable_dynamic_backbias_control(rdev, false); | |
1708 | ||
1709 | if (pi->voltage_control) { | |
1710 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) | |
c70d4553 | 1711 | rv6xx_step_voltage_if_increasing(rdev, new_ps, old_ps); |
4a6369e9 AD |
1712 | msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000); |
1713 | } | |
1714 | ||
1715 | r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true); | |
1716 | r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false); | |
1717 | r600_wait_for_power_level_unequal(rdev, R600_POWER_LEVEL_LOW); | |
1718 | ||
c70d4553 | 1719 | rv6xx_generate_low_step(rdev, new_ps); |
4a6369e9 | 1720 | rv6xx_invalidate_intermediate_steps(rdev); |
c70d4553 | 1721 | rv6xx_calculate_stepping_parameters(rdev, new_ps); |
4a6369e9 AD |
1722 | rv6xx_program_stepping_parameters_lowest_entry(rdev); |
1723 | rv6xx_program_power_level_low_to_lowest_state(rdev); | |
1724 | ||
1725 | r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); | |
1726 | r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW); | |
1727 | r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); | |
1728 | ||
1729 | if (pi->voltage_control) { | |
ac0cdcb5 AD |
1730 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) { |
1731 | ret = rv6xx_step_voltage_if_decreasing(rdev, new_ps, old_ps); | |
1732 | if (ret) | |
1733 | return ret; | |
1734 | } | |
4a6369e9 AD |
1735 | rv6xx_enable_dynamic_voltage_control(rdev, true); |
1736 | } | |
1737 | ||
1738 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) | |
1739 | rv6xx_enable_dynamic_backbias_control(rdev, true); | |
1740 | ||
1741 | if (pi->dynamic_pcie_gen2) | |
c70d4553 | 1742 | rv6xx_enable_dynamic_pcie_gen2(rdev, new_ps, true); |
4a6369e9 AD |
1743 | |
1744 | rv6xx_reset_lvtm_data_sync(rdev); | |
1745 | ||
c70d4553 | 1746 | rv6xx_generate_stepping_table(rdev, new_ps); |
4a6369e9 AD |
1747 | rv6xx_program_stepping_parameters_except_lowest_entry(rdev); |
1748 | rv6xx_program_power_level_low(rdev); | |
1749 | rv6xx_program_power_level_medium(rdev); | |
1750 | rv6xx_program_power_level_high(rdev); | |
1751 | rv6xx_enable_medium(rdev); | |
1752 | rv6xx_enable_high(rdev); | |
1753 | ||
1754 | if (pi->thermal_protection) | |
1755 | rv6xx_enable_thermal_protection(rdev, true); | |
1756 | rv6xx_program_vc(rdev); | |
1757 | rv6xx_program_at(rdev); | |
1758 | ||
02478a10 AD |
1759 | rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); |
1760 | ||
f4f85a8c AD |
1761 | rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; |
1762 | ||
4a6369e9 AD |
1763 | return 0; |
1764 | } | |
1765 | ||
1766 | void rv6xx_setup_asic(struct radeon_device *rdev) | |
1767 | { | |
1768 | r600_enable_acpi_pm(rdev); | |
1769 | ||
1294d4a3 AD |
1770 | if (radeon_aspm != 0) { |
1771 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s) | |
1772 | rv6xx_enable_l0s(rdev); | |
1773 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1) | |
1774 | rv6xx_enable_l1(rdev); | |
1775 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1) | |
1776 | rv6xx_enable_pll_sleep_in_l1(rdev); | |
1777 | } | |
4a6369e9 AD |
1778 | } |
1779 | ||
1780 | void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev) | |
1781 | { | |
1782 | rv6xx_program_display_gap(rdev); | |
1783 | } | |
1784 | ||
1785 | union power_info { | |
1786 | struct _ATOM_POWERPLAY_INFO info; | |
1787 | struct _ATOM_POWERPLAY_INFO_V2 info_2; | |
1788 | struct _ATOM_POWERPLAY_INFO_V3 info_3; | |
1789 | struct _ATOM_PPLIB_POWERPLAYTABLE pplib; | |
1790 | struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; | |
1791 | struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; | |
1792 | }; | |
1793 | ||
1794 | union pplib_clock_info { | |
1795 | struct _ATOM_PPLIB_R600_CLOCK_INFO r600; | |
1796 | struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; | |
1797 | struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; | |
1798 | struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; | |
1799 | }; | |
1800 | ||
1801 | union pplib_power_state { | |
1802 | struct _ATOM_PPLIB_STATE v1; | |
1803 | struct _ATOM_PPLIB_STATE_V2 v2; | |
1804 | }; | |
1805 | ||
1806 | static void rv6xx_parse_pplib_non_clock_info(struct radeon_device *rdev, | |
1807 | struct radeon_ps *rps, | |
1808 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) | |
1809 | { | |
1810 | rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); | |
1811 | rps->class = le16_to_cpu(non_clock_info->usClassification); | |
1812 | rps->class2 = le16_to_cpu(non_clock_info->usClassification2); | |
1813 | ||
1814 | if (r600_is_uvd_state(rps->class, rps->class2)) { | |
1815 | rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; | |
1816 | rps->dclk = RV6XX_DEFAULT_DCLK_FREQ; | |
1817 | } else { | |
1818 | rps->vclk = 0; | |
1819 | rps->dclk = 0; | |
1820 | } | |
1821 | ||
1822 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) | |
1823 | rdev->pm.dpm.boot_ps = rps; | |
1824 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) | |
1825 | rdev->pm.dpm.uvd_ps = rps; | |
1826 | } | |
1827 | ||
1828 | static void rv6xx_parse_pplib_clock_info(struct radeon_device *rdev, | |
1829 | struct radeon_ps *rps, int index, | |
1830 | union pplib_clock_info *clock_info) | |
1831 | { | |
1832 | struct rv6xx_ps *ps = rv6xx_get_ps(rps); | |
1833 | u32 sclk, mclk; | |
1834 | u16 vddc; | |
1835 | struct rv6xx_pl *pl; | |
1836 | ||
1837 | switch (index) { | |
1838 | case 0: | |
1839 | pl = &ps->low; | |
1840 | break; | |
1841 | case 1: | |
1842 | pl = &ps->medium; | |
1843 | break; | |
1844 | case 2: | |
1845 | default: | |
1846 | pl = &ps->high; | |
1847 | break; | |
1848 | } | |
1849 | ||
1850 | sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); | |
1851 | sclk |= clock_info->r600.ucEngineClockHigh << 16; | |
1852 | mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); | |
1853 | mclk |= clock_info->r600.ucMemoryClockHigh << 16; | |
1854 | ||
1855 | pl->mclk = mclk; | |
1856 | pl->sclk = sclk; | |
1857 | pl->vddc = le16_to_cpu(clock_info->r600.usVDDC); | |
1858 | pl->flags = le32_to_cpu(clock_info->r600.ulFlags); | |
1859 | ||
1860 | /* patch up vddc if necessary */ | |
1861 | if (pl->vddc == 0xff01) { | |
1862 | if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc) == 0) | |
1863 | pl->vddc = vddc; | |
1864 | } | |
1865 | ||
1866 | /* fix up pcie gen2 */ | |
1867 | if (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) { | |
1868 | if ((rdev->family == CHIP_RV610) || (rdev->family == CHIP_RV630)) { | |
1869 | if (pl->vddc < 1100) | |
1870 | pl->flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2; | |
1871 | } | |
1872 | } | |
1873 | ||
1874 | /* patch up boot state */ | |
1875 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { | |
2abba66e AD |
1876 | u16 vddc, vddci, mvdd; |
1877 | radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); | |
4a6369e9 AD |
1878 | pl->mclk = rdev->clock.default_mclk; |
1879 | pl->sclk = rdev->clock.default_sclk; | |
1880 | pl->vddc = vddc; | |
1881 | } | |
1882 | } | |
1883 | ||
1884 | static int rv6xx_parse_power_table(struct radeon_device *rdev) | |
1885 | { | |
1886 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1887 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; | |
1888 | union pplib_power_state *power_state; | |
1889 | int i, j; | |
1890 | union pplib_clock_info *clock_info; | |
1891 | union power_info *power_info; | |
1892 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); | |
1893 | u16 data_offset; | |
1894 | u8 frev, crev; | |
1895 | struct rv6xx_ps *ps; | |
1896 | ||
1897 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, | |
1898 | &frev, &crev, &data_offset)) | |
1899 | return -EINVAL; | |
1900 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); | |
1901 | ||
1902 | rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * | |
1903 | power_info->pplib.ucNumStates, GFP_KERNEL); | |
1904 | if (!rdev->pm.dpm.ps) | |
1905 | return -ENOMEM; | |
1906 | rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); | |
1907 | rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); | |
1908 | rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); | |
1909 | ||
1910 | for (i = 0; i < power_info->pplib.ucNumStates; i++) { | |
1911 | power_state = (union pplib_power_state *) | |
1912 | (mode_info->atom_context->bios + data_offset + | |
1913 | le16_to_cpu(power_info->pplib.usStateArrayOffset) + | |
1914 | i * power_info->pplib.ucStateEntrySize); | |
1915 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) | |
1916 | (mode_info->atom_context->bios + data_offset + | |
1917 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + | |
1918 | (power_state->v1.ucNonClockStateIndex * | |
1919 | power_info->pplib.ucNonClockSize)); | |
1920 | if (power_info->pplib.ucStateEntrySize - 1) { | |
1921 | ps = kzalloc(sizeof(struct rv6xx_ps), GFP_KERNEL); | |
1922 | if (ps == NULL) { | |
1923 | kfree(rdev->pm.dpm.ps); | |
1924 | return -ENOMEM; | |
1925 | } | |
1926 | rdev->pm.dpm.ps[i].ps_priv = ps; | |
1927 | rv6xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], | |
1928 | non_clock_info); | |
1929 | for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { | |
1930 | clock_info = (union pplib_clock_info *) | |
1931 | (mode_info->atom_context->bios + data_offset + | |
1932 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + | |
1933 | (power_state->v1.ucClockStateIndices[j] * | |
1934 | power_info->pplib.ucClockInfoSize)); | |
1935 | rv6xx_parse_pplib_clock_info(rdev, | |
1936 | &rdev->pm.dpm.ps[i], j, | |
1937 | clock_info); | |
1938 | } | |
1939 | } | |
1940 | } | |
1941 | rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates; | |
1942 | return 0; | |
1943 | } | |
1944 | ||
1945 | int rv6xx_dpm_init(struct radeon_device *rdev) | |
1946 | { | |
1947 | int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); | |
1948 | uint16_t data_offset, size; | |
1949 | uint8_t frev, crev; | |
1950 | struct atom_clock_dividers dividers; | |
1951 | struct rv6xx_power_info *pi; | |
1952 | int ret; | |
1953 | ||
1954 | pi = kzalloc(sizeof(struct rv6xx_power_info), GFP_KERNEL); | |
1955 | if (pi == NULL) | |
1956 | return -ENOMEM; | |
1957 | rdev->pm.dpm.priv = pi; | |
1958 | ||
1959 | ret = rv6xx_parse_power_table(rdev); | |
1960 | if (ret) | |
1961 | return ret; | |
1962 | ||
1963 | if (rdev->pm.dpm.voltage_response_time == 0) | |
1964 | rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; | |
1965 | if (rdev->pm.dpm.backbias_response_time == 0) | |
1966 | rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; | |
1967 | ||
1968 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, | |
1969 | 0, false, ÷rs); | |
1970 | if (ret) | |
1971 | pi->spll_ref_div = dividers.ref_div + 1; | |
1972 | else | |
1973 | pi->spll_ref_div = R600_REFERENCEDIVIDER_DFLT; | |
1974 | ||
1975 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, | |
1976 | 0, false, ÷rs); | |
1977 | if (ret) | |
1978 | pi->mpll_ref_div = dividers.ref_div + 1; | |
1979 | else | |
1980 | pi->mpll_ref_div = R600_REFERENCEDIVIDER_DFLT; | |
1981 | ||
1982 | if (rdev->family >= CHIP_RV670) | |
1983 | pi->fb_div_scale = 1; | |
1984 | else | |
1985 | pi->fb_div_scale = 0; | |
1986 | ||
1987 | pi->voltage_control = | |
58653abd | 1988 | radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0); |
4a6369e9 AD |
1989 | |
1990 | pi->gfx_clock_gating = true; | |
1991 | ||
1992 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, | |
1993 | &frev, &crev, &data_offset)) { | |
1994 | pi->sclk_ss = true; | |
1995 | pi->mclk_ss = true; | |
1996 | pi->dynamic_ss = true; | |
1997 | } else { | |
1998 | pi->sclk_ss = false; | |
1999 | pi->mclk_ss = false; | |
2000 | pi->dynamic_ss = false; | |
2001 | } | |
2002 | ||
2003 | pi->dynamic_pcie_gen2 = true; | |
2004 | ||
2005 | if (pi->gfx_clock_gating && | |
2006 | (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)) | |
2007 | pi->thermal_protection = true; | |
2008 | else | |
2009 | pi->thermal_protection = false; | |
2010 | ||
2011 | pi->display_gap = true; | |
2012 | ||
2013 | return 0; | |
2014 | } | |
2015 | ||
2016 | void rv6xx_dpm_print_power_state(struct radeon_device *rdev, | |
2017 | struct radeon_ps *rps) | |
2018 | { | |
2019 | struct rv6xx_ps *ps = rv6xx_get_ps(rps); | |
2020 | struct rv6xx_pl *pl; | |
2021 | ||
2022 | r600_dpm_print_class_info(rps->class, rps->class2); | |
2023 | r600_dpm_print_cap_info(rps->caps); | |
2024 | printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); | |
2025 | pl = &ps->low; | |
2026 | printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u\n", | |
2027 | pl->sclk, pl->mclk, pl->vddc); | |
2028 | pl = &ps->medium; | |
2029 | printk("\t\tpower level 1 sclk: %u mclk: %u vddc: %u\n", | |
2030 | pl->sclk, pl->mclk, pl->vddc); | |
2031 | pl = &ps->high; | |
2032 | printk("\t\tpower level 2 sclk: %u mclk: %u vddc: %u\n", | |
2033 | pl->sclk, pl->mclk, pl->vddc); | |
2034 | r600_dpm_print_ps_status(rdev, rps); | |
2035 | } | |
2036 | ||
242916a5 AD |
2037 | void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
2038 | struct seq_file *m) | |
2039 | { | |
2040 | struct radeon_ps *rps = rdev->pm.dpm.current_ps; | |
2041 | struct rv6xx_ps *ps = rv6xx_get_ps(rps); | |
2042 | struct rv6xx_pl *pl; | |
2043 | u32 current_index = | |
2044 | (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> | |
2045 | CURRENT_PROFILE_INDEX_SHIFT; | |
2046 | ||
2047 | if (current_index > 2) { | |
2048 | seq_printf(m, "invalid dpm profile %d\n", current_index); | |
2049 | } else { | |
2050 | if (current_index == 0) | |
2051 | pl = &ps->low; | |
2052 | else if (current_index == 1) | |
2053 | pl = &ps->medium; | |
2054 | else /* current_index == 2 */ | |
2055 | pl = &ps->high; | |
2056 | seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); | |
2057 | seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u\n", | |
2058 | current_index, pl->sclk, pl->mclk, pl->vddc); | |
2059 | } | |
2060 | } | |
2061 | ||
4a6369e9 AD |
2062 | void rv6xx_dpm_fini(struct radeon_device *rdev) |
2063 | { | |
2064 | int i; | |
2065 | ||
2066 | for (i = 0; i < rdev->pm.dpm.num_ps; i++) { | |
2067 | kfree(rdev->pm.dpm.ps[i].ps_priv); | |
2068 | } | |
2069 | kfree(rdev->pm.dpm.ps); | |
2070 | kfree(rdev->pm.dpm.priv); | |
2071 | } | |
2072 | ||
2073 | u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low) | |
2074 | { | |
2075 | struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps); | |
2076 | ||
2077 | if (low) | |
2078 | return requested_state->low.sclk; | |
2079 | else | |
2080 | return requested_state->high.sclk; | |
2081 | } | |
2082 | ||
2083 | u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low) | |
2084 | { | |
2085 | struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps); | |
2086 | ||
2087 | if (low) | |
2088 | return requested_state->low.mclk; | |
2089 | else | |
2090 | return requested_state->high.mclk; | |
2091 | } | |
f4f85a8c AD |
2092 | |
2093 | int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, | |
2094 | enum radeon_dpm_forced_level level) | |
2095 | { | |
2096 | struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); | |
2097 | ||
2098 | if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { | |
2099 | pi->restricted_levels = 3; | |
2100 | } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { | |
2101 | pi->restricted_levels = 2; | |
2102 | } else { | |
2103 | pi->restricted_levels = 0; | |
2104 | } | |
2105 | ||
2106 | rv6xx_clear_vc(rdev); | |
2107 | r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); | |
2108 | r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF); | |
2109 | r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW); | |
2110 | r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false); | |
2111 | r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); | |
2112 | rv6xx_enable_medium(rdev); | |
2113 | rv6xx_enable_high(rdev); | |
2114 | if (pi->restricted_levels == 3) | |
2115 | r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false); | |
2116 | rv6xx_program_vc(rdev); | |
2117 | rv6xx_program_at(rdev); | |
2118 | ||
2119 | rdev->pm.dpm.forced_level = level; | |
2120 | ||
2121 | return 0; | |
2122 | } |