[linux-2.6-block.git] / drivers / gpu / drm / radeon / rv515.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include <linux/seq_file.h>
#include "drmP.h"
#include "radeon_reg.h"
#include "radeon.h"

/* rv515 depends on : */
void r100_hdp_reset(struct radeon_device *rdev);
int r100_cp_reset(struct radeon_device *rdev);
int r100_rb2d_reset(struct radeon_device *rdev);
int r100_gui_wait_for_idle(struct radeon_device *rdev);
int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
int rv370_pcie_gart_enable(struct radeon_device *rdev);
void rv370_pcie_gart_disable(struct radeon_device *rdev);
void r420_pipes_init(struct radeon_device *rdev);
void rs600_mc_disable_clients(struct radeon_device *rdev);
void rs600_disable_vga(struct radeon_device *rdev);

/* This files gather functions specifics to:
 * rv515
 *
 * Some of these functions might be used by newer ASICs.
 */
int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
void rv515_gpu_init(struct radeon_device *rdev);
int rv515_mc_wait_for_idle(struct radeon_device *rdev);


/*
 * MC
 */
int rv515_mc_init(struct radeon_device *rdev)
{
	uint32_t tmp;
	int r;

	if (r100_debugfs_rbbm_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
	}
	if (rv515_debugfs_pipes_info_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for pipes !\n");
	}
	if (rv515_debugfs_ga_info_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for pipes !\n");
	}

	rv515_gpu_init(rdev);
	rv370_pcie_gart_disable(rdev);

	/* Setup GPU memory space */
	rdev->mc.vram_location = 0xFFFFFFFFUL;
	rdev->mc.gtt_location = 0xFFFFFFFFUL;
	if (rdev->flags & RADEON_IS_AGP) {
		r = radeon_agp_init(rdev);
		if (r) {
			printk(KERN_WARNING "[drm] Disabling AGP\n");
			rdev->flags &= ~RADEON_IS_AGP;
			rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		} else {
			rdev->mc.gtt_location = rdev->mc.agp_base;
		}
	}
	r = radeon_mc_setup(rdev);
	if (r) {
		return r;
	}

	/* Program GPU memory space */
	rs600_mc_disable_clients(rdev);
	if (rv515_mc_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait MC idle while "
		       "programming pipes. Bad things might happen.\n");
	}
	/* Write VRAM size in case we are limiting it */
	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
	tmp = REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
	WREG32(0x134, tmp);
	tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
	tmp = REG_SET(RV515_MC_FB_TOP, tmp >> 16);
	tmp |= REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
	WREG32_MC(RV515_MC_FB_LOCATION, tmp);
	WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
	WREG32(0x310, rdev->mc.vram_location);
	if (rdev->flags & RADEON_IS_AGP) {
		tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
		tmp = REG_SET(RV515_MC_AGP_TOP, tmp >> 16);
		tmp |= REG_SET(RV515_MC_AGP_START, rdev->mc.gtt_location >> 16);
		WREG32_MC(RV515_MC_AGP_LOCATION, tmp);
		WREG32_MC(RV515_MC_AGP_BASE, rdev->mc.agp_base);
		WREG32_MC(RV515_MC_AGP_BASE_2, 0);
	} else {
		WREG32_MC(RV515_MC_AGP_LOCATION, 0x0FFFFFFF);
		WREG32_MC(RV515_MC_AGP_BASE, 0);
		WREG32_MC(RV515_MC_AGP_BASE_2, 0);
	}
	return 0;
}

void rv515_mc_fini(struct radeon_device *rdev)
{
	rv370_pcie_gart_disable(rdev);
	radeon_gart_table_vram_free(rdev);
	radeon_gart_fini(rdev);
}


/*
 * Global GPU functions
 */
void rv515_ring_start(struct radeon_device *rdev)
{
	unsigned gb_tile_config;
	int r;

	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
	gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16;
	switch (rdev->num_gb_pipes) {
	case 2:
		gb_tile_config |= R300_PIPE_COUNT_R300;
		break;
	case 3:
		gb_tile_config |= R300_PIPE_COUNT_R420_3P;
		break;
	case 4:
		gb_tile_config |= R300_PIPE_COUNT_R420;
		break;
	case 1:
	default:
		gb_tile_config |= R300_PIPE_COUNT_RV350;
		break;
	}

	r = radeon_ring_lock(rdev, 64);
	if (r) {
		return;
	}
	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
	radeon_ring_write(rdev,
			  RADEON_ISYNC_ANY2D_IDLE3D |
			  RADEON_ISYNC_ANY3D_IDLE2D |
			  RADEON_ISYNC_WAIT_IDLEGUI |
			  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
	radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
	radeon_ring_write(rdev, gb_tile_config);
	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
	radeon_ring_write(rdev,
			  RADEON_WAIT_2D_IDLECLEAN |
			  RADEON_WAIT_3D_IDLECLEAN);
	radeon_ring_write(rdev, PACKET0(0x170C, 0));
	radeon_ring_write(rdev, 1 << 31);
	radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
	radeon_ring_write(rdev, 0);
	radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
	radeon_ring_write(rdev, 0);
	radeon_ring_write(rdev, PACKET0(0x42C8, 0));
	radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
	radeon_ring_write(rdev, PACKET0(R500_VAP_INDEX_OFFSET, 0));
	radeon_ring_write(rdev, 0);
	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
	radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
	radeon_ring_write(rdev,
			  RADEON_WAIT_2D_IDLECLEAN |
			  RADEON_WAIT_3D_IDLECLEAN);
	radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
	radeon_ring_write(rdev, 0);
	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
	radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
	radeon_ring_write(rdev,
			  ((6 << R300_MS_X0_SHIFT) |
			   (6 << R300_MS_Y0_SHIFT) |
			   (6 << R300_MS_X1_SHIFT) |
			   (6 << R300_MS_Y1_SHIFT) |
			   (6 << R300_MS_X2_SHIFT) |
			   (6 << R300_MS_Y2_SHIFT) |
			   (6 << R300_MSBD0_Y_SHIFT) |
			   (6 << R300_MSBD0_X_SHIFT)));
	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
	radeon_ring_write(rdev,
			  ((6 << R300_MS_X3_SHIFT) |
			   (6 << R300_MS_Y3_SHIFT) |
			   (6 << R300_MS_X4_SHIFT) |
			   (6 << R300_MS_Y4_SHIFT) |
			   (6 << R300_MS_X5_SHIFT) |
			   (6 << R300_MS_Y5_SHIFT) |
			   (6 << R300_MSBD1_SHIFT)));
	radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
	radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
	radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
	radeon_ring_write(rdev,
			  R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
	radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
	radeon_ring_write(rdev,
			  R300_GEOMETRY_ROUND_NEAREST |
			  R300_COLOR_ROUND_NEAREST);
	radeon_ring_write(rdev, PACKET0(0x20C8, 0));
	radeon_ring_write(rdev, 0);
	radeon_ring_unlock_commit(rdev);
}

void rv515_errata(struct radeon_device *rdev)
{
	rdev->pll_errata = 0;
}

int rv515_mc_wait_for_idle(struct radeon_device *rdev)
{
	unsigned i;
	uint32_t tmp;

	for (i = 0; i < rdev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32_MC(RV515_MC_STATUS);
		if (tmp & RV515_MC_STATUS_IDLE) {
			return 0;
		}
		DRM_UDELAY(1);
	}
	return -1;
}

void rv515_gpu_init(struct radeon_device *rdev)
{
	unsigned pipe_select_current, gb_pipe_select, tmp;

	r100_hdp_reset(rdev);
	r100_rb2d_reset(rdev);

	if (r100_gui_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait GUI idle while "
		       "reseting GPU. Bad things might happen.\n");
	}

	rs600_disable_vga(rdev);

	r420_pipes_init(rdev);
	gb_pipe_select = RREG32(0x402C);
	tmp = RREG32(0x170C);
	pipe_select_current = (tmp >> 2) & 3;
	tmp = (1 << pipe_select_current) |
	      (((gb_pipe_select >> 8) & 0xF) << 4);
	WREG32_PLL(0x000D, tmp);
	if (r100_gui_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait GUI idle while "
		       "reseting GPU. Bad things might happen.\n");
	}
	if (rv515_mc_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait MC idle while "
		       "programming pipes. Bad things might happen.\n");
	}
}

int rv515_ga_reset(struct radeon_device *rdev)
{
	uint32_t tmp;
	bool reinit_cp;
	int i;

	reinit_cp = rdev->cp.ready;
	rdev->cp.ready = false;
	for (i = 0; i < rdev->usec_timeout; i++) {
		WREG32(RADEON_CP_CSQ_MODE, 0);
		WREG32(RADEON_CP_CSQ_CNTL, 0);
		WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
		(void)RREG32(RADEON_RBBM_SOFT_RESET);
		udelay(200);
		WREG32(RADEON_RBBM_SOFT_RESET, 0);
		/* Wait to prevent race in RBBM_STATUS */
		mdelay(1);
		tmp = RREG32(RADEON_RBBM_STATUS);
		if (tmp & ((1 << 20) | (1 << 26))) {
			DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
			/* GA still busy soft reset it */
			WREG32(0x429C, 0x200);
			WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
			WREG32(0x43E0, 0);
			WREG32(0x43E4, 0);
			WREG32(0x24AC, 0);
		}
		/* Wait to prevent race in RBBM_STATUS */
		mdelay(1);
		tmp = RREG32(RADEON_RBBM_STATUS);
		if (!(tmp & ((1 << 20) | (1 << 26)))) {
			break;
		}
	}
	for (i = 0; i < rdev->usec_timeout; i++) {
		tmp = RREG32(RADEON_RBBM_STATUS);
		if (!(tmp & ((1 << 20) | (1 << 26)))) {
			DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
				 tmp);
			DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
			DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
			DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
			if (reinit_cp) {
				return r100_cp_init(rdev, rdev->cp.ring_size);
			}
			return 0;
		}
		DRM_UDELAY(1);
	}
	tmp = RREG32(RADEON_RBBM_STATUS);
	DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
	return -1;
}

int rv515_gpu_reset(struct radeon_device *rdev)
{
	uint32_t status;

	/* reset order likely matter */
	status = RREG32(RADEON_RBBM_STATUS);
	/* reset HDP */
	r100_hdp_reset(rdev);
	/* reset rb2d */
	if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
		r100_rb2d_reset(rdev);
	}
	/* reset GA */
	if (status & ((1 << 20) | (1 << 26))) {
		rv515_ga_reset(rdev);
	}
	/* reset CP */
	status = RREG32(RADEON_RBBM_STATUS);
	if (status & (1 << 16)) {
		r100_cp_reset(rdev);
	}
	/* Check if GPU is idle */
	status = RREG32(RADEON_RBBM_STATUS);
	if (status & (1 << 31)) {
		DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
		return -1;
	}
	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
	return 0;
}


/*
 * VRAM info
 */
static void rv515_vram_get_type(struct radeon_device *rdev)
{
	uint32_t tmp;

	rdev->mc.vram_width = 128;
	rdev->mc.vram_is_ddr = true;
	tmp = RREG32_MC(RV515_MC_CNTL);
	tmp &= RV515_MEM_NUM_CHANNELS_MASK;
	switch (tmp) {
	case 0:
		rdev->mc.vram_width = 64;
		break;
	case 1:
		rdev->mc.vram_width = 128;
		break;
	default:
		rdev->mc.vram_width = 128;
		break;
	}
}

void rv515_vram_info(struct radeon_device *rdev)
{
	rv515_vram_get_type(rdev);
	
	r100_vram_init_sizes(rdev);
}


/*
 * Indirect registers accessor
 */
uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
{
	uint32_t r;

	WREG32(R520_MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
	r = RREG32(R520_MC_IND_DATA);
	WREG32(R520_MC_IND_INDEX, 0);
	return r;
}

void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	WREG32(R520_MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
	WREG32(R520_MC_IND_DATA, (v));
	WREG32(R520_MC_IND_INDEX, 0);
}

uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
{
	uint32_t r;

	WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
	(void)RREG32(RADEON_PCIE_INDEX);
	r = RREG32(RADEON_PCIE_DATA);
	return r;
}

void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
	(void)RREG32(RADEON_PCIE_INDEX);
	WREG32(RADEON_PCIE_DATA, (v));
	(void)RREG32(RADEON_PCIE_DATA);
}


/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)
static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t tmp;

	tmp = RREG32(R400_GB_PIPE_SELECT);
	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
	tmp = RREG32(R500_SU_REG_DEST);
	seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
	tmp = RREG32(R300_GB_TILE_CONFIG);
	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
	tmp = RREG32(R300_DST_PIPE_CONFIG);
	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
	return 0;
}

static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t tmp;

	tmp = RREG32(0x2140);
	seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
	radeon_gpu_reset(rdev);
	tmp = RREG32(0x425C);
	seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
	return 0;
}

static struct drm_info_list rv515_pipes_info_list[] = {
	{"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
};

static struct drm_info_list rv515_ga_info_list[] = {
	{"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
};
#endif

int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
#else
	return 0;
#endif
}

int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
#else
	return 0;
#endif
}


/*
 * Asic initialization
 */
static const unsigned r500_reg_safe_bm[219] = {
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
	0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
	0xF0000038, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0x1FFFFC78, 0xFFFFE000, 0xFFFFFFFE, 0xFFFFFFFF,
	0x38CF8F50, 0xFFF88082, 0xFF0000FC, 0xFAE009FF,
	0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
	0xFFFF8CFC, 0xFFFFC1FF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF,
	0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x0003FC01, 0x3FFFFCF8, 0xFE800B19, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
};

int rv515_init(struct radeon_device *rdev)
{
	rdev->config.r300.reg_safe_bm = r500_reg_safe_bm;
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm);
	return 0;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include <linux/seq_file.h>
	29	#include "drmP.h"
	30	#include "radeon_reg.h"
	31	#include "radeon.h"
	32
	33	/* rv515 depends on : */
	34	void r100_hdp_reset(struct radeon_device *rdev);
	35	int r100_cp_reset(struct radeon_device *rdev);
	36	int r100_rb2d_reset(struct radeon_device *rdev);
	37	int r100_gui_wait_for_idle(struct radeon_device *rdev);
	38	int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
	39	int rv370_pcie_gart_enable(struct radeon_device *rdev);
	40	void rv370_pcie_gart_disable(struct radeon_device *rdev);
	41	void r420_pipes_init(struct radeon_device *rdev);
	42	void rs600_mc_disable_clients(struct radeon_device *rdev);
	43	void rs600_disable_vga(struct radeon_device *rdev);
	44
	45	/* This files gather functions specifics to:
	46	* rv515
	47	*
	48	* Some of these functions might be used by newer ASICs.
	49	*/
	50	int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
	51	int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
	52	void rv515_gpu_init(struct radeon_device *rdev);
	53	int rv515_mc_wait_for_idle(struct radeon_device *rdev);
	54
	55
	56	/*
	57	* MC
	58	*/
	59	int rv515_mc_init(struct radeon_device *rdev)
	60	{
	61	uint32_t tmp;
	62	int r;
	63
	64	if (r100_debugfs_rbbm_init(rdev)) {
65	DRM_ERROR("Failed to register debugfs file for RBBM !\n");
66	}
67	if (rv515_debugfs_pipes_info_init(rdev)) {
68	DRM_ERROR("Failed to register debugfs file for pipes !\n");
69	}
70	if (rv515_debugfs_ga_info_init(rdev)) {
71	DRM_ERROR("Failed to register debugfs file for pipes !\n");
72	}
73
74	rv515_gpu_init(rdev);
75	rv370_pcie_gart_disable(rdev);
76
77	/* Setup GPU memory space */
78	rdev->mc.vram_location = 0xFFFFFFFFUL;
79	rdev->mc.gtt_location = 0xFFFFFFFFUL;
80	if (rdev->flags & RADEON_IS_AGP) {
81	r = radeon_agp_init(rdev);
82	if (r) {
83	printk(KERN_WARNING "[drm] Disabling AGP\n");
84	rdev->flags &= ~RADEON_IS_AGP;
85	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
86	} else {
87	rdev->mc.gtt_location = rdev->mc.agp_base;
88	}
89	}
90	r = radeon_mc_setup(rdev);
91	if (r) {
92	return r;
93	}
94
95	/* Program GPU memory space */
96	rs600_mc_disable_clients(rdev);
97	if (rv515_mc_wait_for_idle(rdev)) {
98	printk(KERN_WARNING "Failed to wait MC idle while "
99	"programming pipes. Bad things might happen.\n");
100	}
101	/* Write VRAM size in case we are limiting it */
102	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
103	tmp = REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
104	WREG32(0x134, tmp);
105	tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
106	tmp = REG_SET(RV515_MC_FB_TOP, tmp >> 16);
107	tmp \|= REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
108	WREG32_MC(RV515_MC_FB_LOCATION, tmp);
109	WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
110	WREG32(0x310, rdev->mc.vram_location);
111	if (rdev->flags & RADEON_IS_AGP) {
112	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
113	tmp = REG_SET(RV515_MC_AGP_TOP, tmp >> 16);
114	tmp \|= REG_SET(RV515_MC_AGP_START, rdev->mc.gtt_location >> 16);
115	WREG32_MC(RV515_MC_AGP_LOCATION, tmp);
116	WREG32_MC(RV515_MC_AGP_BASE, rdev->mc.agp_base);
117	WREG32_MC(RV515_MC_AGP_BASE_2, 0);
118	} else {
119	WREG32_MC(RV515_MC_AGP_LOCATION, 0x0FFFFFFF);
120	WREG32_MC(RV515_MC_AGP_BASE, 0);
121	WREG32_MC(RV515_MC_AGP_BASE_2, 0);
122	}
123	return 0;
124	}
125
126	void rv515_mc_fini(struct radeon_device *rdev)
127	{
128	rv370_pcie_gart_disable(rdev);
129	radeon_gart_table_vram_free(rdev);
130	radeon_gart_fini(rdev);
131	}
132
133
134	/*
135	* Global GPU functions
136	*/
137	void rv515_ring_start(struct radeon_device *rdev)
138	{
139	unsigned gb_tile_config;
140	int r;
141
142	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
143	gb_tile_config = R300_ENABLE_TILING \| R300_TILE_SIZE_16;
144	switch (rdev->num_gb_pipes) {
145	case 2:
146	gb_tile_config \|= R300_PIPE_COUNT_R300;
147	break;
148	case 3:
149	gb_tile_config \|= R300_PIPE_COUNT_R420_3P;
150	break;
151	case 4:
152	gb_tile_config \|= R300_PIPE_COUNT_R420;
153	break;
154	case 1:
155	default:
156	gb_tile_config \|= R300_PIPE_COUNT_RV350;
157	break;
158	}
159
160	r = radeon_ring_lock(rdev, 64);
161	if (r) {
162	return;
163	}
164	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
165	radeon_ring_write(rdev,
166	RADEON_ISYNC_ANY2D_IDLE3D \|
167	RADEON_ISYNC_ANY3D_IDLE2D \|
168	RADEON_ISYNC_WAIT_IDLEGUI \|
169	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
170	radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
171	radeon_ring_write(rdev, gb_tile_config);
172	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
173	radeon_ring_write(rdev,
174	RADEON_WAIT_2D_IDLECLEAN \|
175	RADEON_WAIT_3D_IDLECLEAN);
176	radeon_ring_write(rdev, PACKET0(0x170C, 0));
177	radeon_ring_write(rdev, 1 << 31);
178	radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
179	radeon_ring_write(rdev, 0);
180	radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
181	radeon_ring_write(rdev, 0);
182	radeon_ring_write(rdev, PACKET0(0x42C8, 0));
183	radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
184	radeon_ring_write(rdev, PACKET0(R500_VAP_INDEX_OFFSET, 0));
185	radeon_ring_write(rdev, 0);
186	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
187	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH \| R300_RB3D_DC_FREE);
188	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
189	radeon_ring_write(rdev, R300_ZC_FLUSH \| R300_ZC_FREE);
190	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
191	radeon_ring_write(rdev,
192	RADEON_WAIT_2D_IDLECLEAN \|
193	RADEON_WAIT_3D_IDLECLEAN);
194	radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
195	radeon_ring_write(rdev, 0);
196	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
197	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH \| R300_RB3D_DC_FREE);
198	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
199	radeon_ring_write(rdev, R300_ZC_FLUSH \| R300_ZC_FREE);
200	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
201	radeon_ring_write(rdev,
202	((6 << R300_MS_X0_SHIFT) \|
203	(6 << R300_MS_Y0_SHIFT) \|
204	(6 << R300_MS_X1_SHIFT) \|
205	(6 << R300_MS_Y1_SHIFT) \|
206	(6 << R300_MS_X2_SHIFT) \|
207	(6 << R300_MS_Y2_SHIFT) \|
208	(6 << R300_MSBD0_Y_SHIFT) \|
209	(6 << R300_MSBD0_X_SHIFT)));
210	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
211	radeon_ring_write(rdev,
212	((6 << R300_MS_X3_SHIFT) \|
213	(6 << R300_MS_Y3_SHIFT) \|
214	(6 << R300_MS_X4_SHIFT) \|
215	(6 << R300_MS_Y4_SHIFT) \|
216	(6 << R300_MS_X5_SHIFT) \|
217	(6 << R300_MS_Y5_SHIFT) \|
218	(6 << R300_MSBD1_SHIFT)));
219	radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
220	radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL \| R300_GA_FASTSYNC_CNTL);
221	radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
222	radeon_ring_write(rdev,
223	R300_FRONT_PTYPE_TRIANGE \| R300_BACK_PTYPE_TRIANGE);
224	radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
225	radeon_ring_write(rdev,
226	R300_GEOMETRY_ROUND_NEAREST \|
227	R300_COLOR_ROUND_NEAREST);
068a117c JG	228	radeon_ring_write(rdev, PACKET0(0x20C8, 0));
068a117c JG	229	radeon_ring_write(rdev, 0);
771fe6b9 JG	230	radeon_ring_unlock_commit(rdev);
	231	}
	232
	233	void rv515_errata(struct radeon_device *rdev)
	234	{
	235	rdev->pll_errata = 0;
	236	}
	237
	238	int rv515_mc_wait_for_idle(struct radeon_device *rdev)
	239	{
	240	unsigned i;
	241	uint32_t tmp;
	242
	243	for (i = 0; i < rdev->usec_timeout; i++) {
	244	/* read MC_STATUS */
	245	tmp = RREG32_MC(RV515_MC_STATUS);
	246	if (tmp & RV515_MC_STATUS_IDLE) {
	247	return 0;
	248	}
	249	DRM_UDELAY(1);
	250	}
	251	return -1;
	252	}
	253
	254	void rv515_gpu_init(struct radeon_device *rdev)
	255	{
	256	unsigned pipe_select_current, gb_pipe_select, tmp;
	257
	258	r100_hdp_reset(rdev);
	259	r100_rb2d_reset(rdev);
	260
	261	if (r100_gui_wait_for_idle(rdev)) {
	262	printk(KERN_WARNING "Failed to wait GUI idle while "
	263	"reseting GPU. Bad things might happen.\n");
	264	}
	265
	266	rs600_disable_vga(rdev);
	267
	268	r420_pipes_init(rdev);
	269	gb_pipe_select = RREG32(0x402C);
	270	tmp = RREG32(0x170C);
	271	pipe_select_current = (tmp >> 2) & 3;
	272	tmp = (1 << pipe_select_current) \|
	273	(((gb_pipe_select >> 8) & 0xF) << 4);
	274	WREG32_PLL(0x000D, tmp);
	275	if (r100_gui_wait_for_idle(rdev)) {
	276	printk(KERN_WARNING "Failed to wait GUI idle while "
	277	"reseting GPU. Bad things might happen.\n");
	278	}
	279	if (rv515_mc_wait_for_idle(rdev)) {
	280	printk(KERN_WARNING "Failed to wait MC idle while "
	281	"programming pipes. Bad things might happen.\n");
	282	}
	283	}
	284
	285	int rv515_ga_reset(struct radeon_device *rdev)
	286	{
	287	uint32_t tmp;
	288	bool reinit_cp;
	289	int i;
	290
	291	reinit_cp = rdev->cp.ready;
	292	rdev->cp.ready = false;
	293	for (i = 0; i < rdev->usec_timeout; i++) {
294	WREG32(RADEON_CP_CSQ_MODE, 0);
295	WREG32(RADEON_CP_CSQ_CNTL, 0);
296	WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
297	(void)RREG32(RADEON_RBBM_SOFT_RESET);
298	udelay(200);
299	WREG32(RADEON_RBBM_SOFT_RESET, 0);
300	/* Wait to prevent race in RBBM_STATUS */
301	mdelay(1);
302	tmp = RREG32(RADEON_RBBM_STATUS);
303	if (tmp & ((1 << 20) \| (1 << 26))) {
304	DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
305	/* GA still busy soft reset it */
306	WREG32(0x429C, 0x200);
307	WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
308	WREG32(0x43E0, 0);
309	WREG32(0x43E4, 0);
310	WREG32(0x24AC, 0);
311	}
312	/* Wait to prevent race in RBBM_STATUS */
313	mdelay(1);
314	tmp = RREG32(RADEON_RBBM_STATUS);
315	if (!(tmp & ((1 << 20) \| (1 << 26)))) {
316	break;
317	}
318	}
319	for (i = 0; i < rdev->usec_timeout; i++) {
320	tmp = RREG32(RADEON_RBBM_STATUS);
321	if (!(tmp & ((1 << 20) \| (1 << 26)))) {
322	DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
323	tmp);
324	DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
325	DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
326	DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
327	if (reinit_cp) {
328	return r100_cp_init(rdev, rdev->cp.ring_size);
329	}
330	return 0;
331	}
332	DRM_UDELAY(1);
333	}
334	tmp = RREG32(RADEON_RBBM_STATUS);
335	DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
336	return -1;
337	}
338
339	int rv515_gpu_reset(struct radeon_device *rdev)
340	{
341	uint32_t status;
342
343	/* reset order likely matter */
344	status = RREG32(RADEON_RBBM_STATUS);
345	/* reset HDP */
346	r100_hdp_reset(rdev);
347	/* reset rb2d */
348	if (status & ((1 << 17) \| (1 << 18) \| (1 << 27))) {
349	r100_rb2d_reset(rdev);
350	}
351	/* reset GA */
352	if (status & ((1 << 20) \| (1 << 26))) {
353	rv515_ga_reset(rdev);
354	}
355	/* reset CP */
356	status = RREG32(RADEON_RBBM_STATUS);
357	if (status & (1 << 16)) {
358	r100_cp_reset(rdev);
359	}
360	/* Check if GPU is idle */
361	status = RREG32(RADEON_RBBM_STATUS);
362	if (status & (1 << 31)) {
363	DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
364	return -1;
365	}
366	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
367	return 0;
368	}
369
370
371	/*
372	* VRAM info
373	*/
374	static void rv515_vram_get_type(struct radeon_device *rdev)
375	{
376	uint32_t tmp;
377
378	rdev->mc.vram_width = 128;
379	rdev->mc.vram_is_ddr = true;
380	tmp = RREG32_MC(RV515_MC_CNTL);
381	tmp &= RV515_MEM_NUM_CHANNELS_MASK;
382	switch (tmp) {
383	case 0:
384	rdev->mc.vram_width = 64;
385	break;
386	case 1:
387	rdev->mc.vram_width = 128;
388	break;
389	default:
390	rdev->mc.vram_width = 128;
391	break;
392	}
393	}
394
395	void rv515_vram_info(struct radeon_device *rdev)
396	{
397	rv515_vram_get_type(rdev);
2a0f8918 DA	398
2a0f8918 DA	399	r100_vram_init_sizes(rdev);
771fe6b9 JG	400	}
	401
	402
	403	/*
	404	* Indirect registers accessor
	405	*/
	406	uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
	407	{
	408	uint32_t r;
	409
	410	WREG32(R520_MC_IND_INDEX, 0x7f0000 \| (reg & 0xffff));
	411	r = RREG32(R520_MC_IND_DATA);
	412	WREG32(R520_MC_IND_INDEX, 0);
	413	return r;
	414	}
	415
	416	void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
	417	{
	418	WREG32(R520_MC_IND_INDEX, 0xff0000 \| ((reg) & 0xffff));
	419	WREG32(R520_MC_IND_DATA, (v));
	420	WREG32(R520_MC_IND_INDEX, 0);
	421	}
	422
	423	uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
	424	{
	425	uint32_t r;
	426
	427	WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
	428	(void)RREG32(RADEON_PCIE_INDEX);
	429	r = RREG32(RADEON_PCIE_DATA);
	430	return r;
	431	}
	432
	433	void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
	434	{
	435	WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
	436	(void)RREG32(RADEON_PCIE_INDEX);
	437	WREG32(RADEON_PCIE_DATA, (v));
	438	(void)RREG32(RADEON_PCIE_DATA);
	439	}
	440
	441
	442	/*
	443	* Debugfs info
	444	*/
	445	#if defined(CONFIG_DEBUG_FS)
	446	static int rv515_debugfs_pipes_info(struct seq_file m, void data)
	447	{
	448	struct drm_info_node node = (struct drm_info_node ) m->private;
	449	struct drm_device *dev = node->minor->dev;
	450	struct radeon_device *rdev = dev->dev_private;
	451	uint32_t tmp;
	452
	453	tmp = RREG32(R400_GB_PIPE_SELECT);
	454	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
	455	tmp = RREG32(R500_SU_REG_DEST);
	456	seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
	457	tmp = RREG32(R300_GB_TILE_CONFIG);
	458	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
	459	tmp = RREG32(R300_DST_PIPE_CONFIG);
	460	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
	461	return 0;
	462	}
	463
464	static int rv515_debugfs_ga_info(struct seq_file m, void data)
465	{
466	struct drm_info_node node = (struct drm_info_node ) m->private;
467	struct drm_device *dev = node->minor->dev;
468	struct radeon_device *rdev = dev->dev_private;
469	uint32_t tmp;
470
471	tmp = RREG32(0x2140);
472	seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
473	radeon_gpu_reset(rdev);
474	tmp = RREG32(0x425C);
475	seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
476	return 0;
477	}
478
479	static struct drm_info_list rv515_pipes_info_list[] = {
480	{"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
481	};
482
483	static struct drm_info_list rv515_ga_info_list[] = {
484	{"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
485	};
486	#endif
487
488	int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
489	{
490	#if defined(CONFIG_DEBUG_FS)
491	return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
492	#else
493	return 0;
494	#endif
495	}
496
497	int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
498	{
499	#if defined(CONFIG_DEBUG_FS)
500	return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
501	#else
502	return 0;
503	#endif
504	}
068a117c JG	505
	506
	507	/*
	508	* Asic initialization
	509	*/
531369e6 DA	510	static const unsigned r500_reg_safe_bm[219] = {
531369e6 DA	511	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
068a117c	512	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
068a117c JG	513	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	514	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	515	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	516	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	517	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	518	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	519	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	520	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	521	0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
	522	0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
	523	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	524	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	525	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
	526	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	527	0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
	528	0xF0000038, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
	529	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
	530	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	531	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	532	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	533	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	534	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	535	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	536	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	537	0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	538	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	539	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	540	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	541	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	542	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	543	0x1FFFFC78, 0xFFFFE000, 0xFFFFFFFE, 0xFFFFFFFF,
	544	0x38CF8F50, 0xFFF88082, 0xFF0000FC, 0xFAE009FF,
	545	0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
	546	0xFFFF8CFC, 0xFFFFC1FF, 0xFFFFFFFF, 0xFFFFFFFF,
	547	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	548	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF,
	549	0x00000000, 0x00000000, 0x00000000, 0x00000000,
531369e6 DA	550	0x0003FC01, 0x3FFFFCF8, 0xFE800B19, 0xFFFFFFFF,
	551	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	552	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	553	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	554	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	555	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	556	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	557	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	558	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	559	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	560	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	561	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	562	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	563	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	564	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	565	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
068a117c JG	566	};
068a117c JG	567
068a117c JG	568	int rv515_init(struct radeon_device *rdev)
	569	{
	570	rdev->config.r300.reg_safe_bm = r500_reg_safe_bm;
	571	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm);
	572	return 0;
	573	}