Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/seq_file.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
760285e7 | 30 | #include <drm/drmP.h> |
3ce0a23d | 31 | #include "rv515d.h" |
771fe6b9 | 32 | #include "radeon.h" |
e6990375 | 33 | #include "radeon_asic.h" |
d39c3b89 | 34 | #include "atom.h" |
50f15303 | 35 | #include "rv515_reg_safe.h" |
d39c3b89 JG |
36 | |
37 | /* This files gather functions specifics to: rv515 */ | |
1109ca09 LK |
38 | static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
39 | static int rv515_debugfs_ga_info_init(struct radeon_device *rdev); | |
40 | static void rv515_gpu_init(struct radeon_device *rdev); | |
771fe6b9 JG |
41 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
42 | ||
6253e4c7 AD |
43 | static const u32 crtc_offsets[2] = |
44 | { | |
45 | 0, | |
46 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL | |
47 | }; | |
48 | ||
f0ed1f65 | 49 | void rv515_debugfs(struct radeon_device *rdev) |
771fe6b9 | 50 | { |
771fe6b9 JG |
51 | if (r100_debugfs_rbbm_init(rdev)) { |
52 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); | |
53 | } | |
54 | if (rv515_debugfs_pipes_info_init(rdev)) { | |
55 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); | |
56 | } | |
57 | if (rv515_debugfs_ga_info_init(rdev)) { | |
58 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); | |
59 | } | |
771fe6b9 JG |
60 | } |
61 | ||
f712812e | 62 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 63 | { |
771fe6b9 JG |
64 | int r; |
65 | ||
e32eb50d | 66 | r = radeon_ring_lock(rdev, ring, 64); |
771fe6b9 JG |
67 | if (r) { |
68 | return; | |
69 | } | |
e32eb50d CK |
70 | radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); |
71 | radeon_ring_write(ring, | |
c93bb85b JG |
72 | ISYNC_ANY2D_IDLE3D | |
73 | ISYNC_ANY3D_IDLE2D | | |
74 | ISYNC_WAIT_IDLEGUI | | |
75 | ISYNC_CPSCRATCH_IDLEGUI); | |
e32eb50d CK |
76 | radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); |
77 | radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); | |
78 | radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); | |
79 | radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); | |
80 | radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); | |
81 | radeon_ring_write(ring, 0); | |
82 | radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); | |
83 | radeon_ring_write(ring, 0); | |
84 | radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); | |
85 | radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); | |
86 | radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); | |
87 | radeon_ring_write(ring, 0); | |
88 | radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); | |
89 | radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); | |
90 | radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); | |
91 | radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); | |
92 | radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); | |
93 | radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); | |
94 | radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); | |
95 | radeon_ring_write(ring, 0); | |
96 | radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); | |
97 | radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); | |
98 | radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); | |
99 | radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); | |
100 | radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); | |
101 | radeon_ring_write(ring, | |
c93bb85b JG |
102 | ((6 << MS_X0_SHIFT) | |
103 | (6 << MS_Y0_SHIFT) | | |
104 | (6 << MS_X1_SHIFT) | | |
105 | (6 << MS_Y1_SHIFT) | | |
106 | (6 << MS_X2_SHIFT) | | |
107 | (6 << MS_Y2_SHIFT) | | |
108 | (6 << MSBD0_Y_SHIFT) | | |
109 | (6 << MSBD0_X_SHIFT))); | |
e32eb50d CK |
110 | radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); |
111 | radeon_ring_write(ring, | |
c93bb85b JG |
112 | ((6 << MS_X3_SHIFT) | |
113 | (6 << MS_Y3_SHIFT) | | |
114 | (6 << MS_X4_SHIFT) | | |
115 | (6 << MS_Y4_SHIFT) | | |
116 | (6 << MS_X5_SHIFT) | | |
117 | (6 << MS_Y5_SHIFT) | | |
118 | (6 << MSBD1_SHIFT))); | |
e32eb50d CK |
119 | radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); |
120 | radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); | |
121 | radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); | |
122 | radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); | |
123 | radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); | |
124 | radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); | |
125 | radeon_ring_write(ring, PACKET0(0x20C8, 0)); | |
126 | radeon_ring_write(ring, 0); | |
127 | radeon_ring_unlock_commit(rdev, ring); | |
771fe6b9 JG |
128 | } |
129 | ||
771fe6b9 JG |
130 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
131 | { | |
132 | unsigned i; | |
133 | uint32_t tmp; | |
134 | ||
135 | for (i = 0; i < rdev->usec_timeout; i++) { | |
136 | /* read MC_STATUS */ | |
c93bb85b JG |
137 | tmp = RREG32_MC(MC_STATUS); |
138 | if (tmp & MC_STATUS_IDLE) { | |
771fe6b9 JG |
139 | return 0; |
140 | } | |
141 | DRM_UDELAY(1); | |
142 | } | |
143 | return -1; | |
144 | } | |
145 | ||
d39c3b89 JG |
146 | void rv515_vga_render_disable(struct radeon_device *rdev) |
147 | { | |
148 | WREG32(R_000300_VGA_RENDER_CONTROL, | |
149 | RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); | |
150 | } | |
151 | ||
1109ca09 | 152 | static void rv515_gpu_init(struct radeon_device *rdev) |
771fe6b9 JG |
153 | { |
154 | unsigned pipe_select_current, gb_pipe_select, tmp; | |
155 | ||
771fe6b9 JG |
156 | if (r100_gui_wait_for_idle(rdev)) { |
157 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
481e6283 | 158 | "resetting GPU. Bad things might happen.\n"); |
771fe6b9 | 159 | } |
d39c3b89 | 160 | rv515_vga_render_disable(rdev); |
771fe6b9 | 161 | r420_pipes_init(rdev); |
d75ee3be AD |
162 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
163 | tmp = RREG32(R300_DST_PIPE_CONFIG); | |
771fe6b9 JG |
164 | pipe_select_current = (tmp >> 2) & 3; |
165 | tmp = (1 << pipe_select_current) | | |
166 | (((gb_pipe_select >> 8) & 0xF) << 4); | |
167 | WREG32_PLL(0x000D, tmp); | |
168 | if (r100_gui_wait_for_idle(rdev)) { | |
169 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
481e6283 | 170 | "resetting GPU. Bad things might happen.\n"); |
771fe6b9 JG |
171 | } |
172 | if (rv515_mc_wait_for_idle(rdev)) { | |
173 | printk(KERN_WARNING "Failed to wait MC idle while " | |
174 | "programming pipes. Bad things might happen.\n"); | |
175 | } | |
176 | } | |
177 | ||
771fe6b9 JG |
178 | static void rv515_vram_get_type(struct radeon_device *rdev) |
179 | { | |
180 | uint32_t tmp; | |
181 | ||
182 | rdev->mc.vram_width = 128; | |
183 | rdev->mc.vram_is_ddr = true; | |
c93bb85b | 184 | tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; |
771fe6b9 JG |
185 | switch (tmp) { |
186 | case 0: | |
187 | rdev->mc.vram_width = 64; | |
188 | break; | |
189 | case 1: | |
190 | rdev->mc.vram_width = 128; | |
191 | break; | |
192 | default: | |
193 | rdev->mc.vram_width = 128; | |
194 | break; | |
195 | } | |
196 | } | |
197 | ||
1109ca09 | 198 | static void rv515_mc_init(struct radeon_device *rdev) |
771fe6b9 | 199 | { |
c93bb85b | 200 | |
771fe6b9 | 201 | rv515_vram_get_type(rdev); |
0924d942 | 202 | r100_vram_init_sizes(rdev); |
d594e46a | 203 | radeon_vram_location(rdev, &rdev->mc, 0); |
8d369bb1 | 204 | rdev->mc.gtt_base_align = 0; |
d594e46a JG |
205 | if (!(rdev->flags & RADEON_IS_AGP)) |
206 | radeon_gtt_location(rdev, &rdev->mc); | |
f47299c5 | 207 | radeon_update_bandwidth_info(rdev); |
771fe6b9 JG |
208 | } |
209 | ||
771fe6b9 JG |
210 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
211 | { | |
212 | uint32_t r; | |
213 | ||
c93bb85b JG |
214 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
215 | r = RREG32(MC_IND_DATA); | |
216 | WREG32(MC_IND_INDEX, 0); | |
771fe6b9 JG |
217 | return r; |
218 | } | |
219 | ||
220 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
221 | { | |
c93bb85b JG |
222 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
223 | WREG32(MC_IND_DATA, (v)); | |
224 | WREG32(MC_IND_INDEX, 0); | |
771fe6b9 JG |
225 | } |
226 | ||
771fe6b9 JG |
227 | #if defined(CONFIG_DEBUG_FS) |
228 | static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) | |
229 | { | |
230 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
231 | struct drm_device *dev = node->minor->dev; | |
232 | struct radeon_device *rdev = dev->dev_private; | |
233 | uint32_t tmp; | |
234 | ||
c93bb85b | 235 | tmp = RREG32(GB_PIPE_SELECT); |
771fe6b9 | 236 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
c93bb85b | 237 | tmp = RREG32(SU_REG_DEST); |
771fe6b9 | 238 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
c93bb85b | 239 | tmp = RREG32(GB_TILE_CONFIG); |
771fe6b9 | 240 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
c93bb85b | 241 | tmp = RREG32(DST_PIPE_CONFIG); |
771fe6b9 JG |
242 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
243 | return 0; | |
244 | } | |
245 | ||
246 | static int rv515_debugfs_ga_info(struct seq_file *m, void *data) | |
247 | { | |
248 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
249 | struct drm_device *dev = node->minor->dev; | |
250 | struct radeon_device *rdev = dev->dev_private; | |
251 | uint32_t tmp; | |
252 | ||
253 | tmp = RREG32(0x2140); | |
254 | seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); | |
a2d07b74 | 255 | radeon_asic_reset(rdev); |
771fe6b9 JG |
256 | tmp = RREG32(0x425C); |
257 | seq_printf(m, "GA_IDLE 0x%08x\n", tmp); | |
258 | return 0; | |
259 | } | |
260 | ||
261 | static struct drm_info_list rv515_pipes_info_list[] = { | |
262 | {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, | |
263 | }; | |
264 | ||
265 | static struct drm_info_list rv515_ga_info_list[] = { | |
266 | {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, | |
267 | }; | |
268 | #endif | |
269 | ||
1109ca09 | 270 | static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) |
771fe6b9 JG |
271 | { |
272 | #if defined(CONFIG_DEBUG_FS) | |
273 | return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); | |
274 | #else | |
275 | return 0; | |
276 | #endif | |
277 | } | |
278 | ||
1109ca09 | 279 | static int rv515_debugfs_ga_info_init(struct radeon_device *rdev) |
771fe6b9 JG |
280 | { |
281 | #if defined(CONFIG_DEBUG_FS) | |
282 | return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); | |
283 | #else | |
284 | return 0; | |
285 | #endif | |
286 | } | |
068a117c | 287 | |
d39c3b89 JG |
288 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) |
289 | { | |
6253e4c7 AD |
290 | u32 crtc_enabled, tmp, frame_count, blackout; |
291 | int i, j; | |
292 | ||
d39c3b89 JG |
293 | save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); |
294 | save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); | |
d39c3b89 | 295 | |
6253e4c7 | 296 | /* disable VGA render */ |
d39c3b89 | 297 | WREG32(R_000300_VGA_RENDER_CONTROL, 0); |
6253e4c7 AD |
298 | /* blank the display controllers */ |
299 | for (i = 0; i < rdev->num_crtc; i++) { | |
300 | crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; | |
301 | if (crtc_enabled) { | |
302 | save->crtc_enabled[i] = true; | |
303 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); | |
304 | if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { | |
305 | radeon_wait_for_vblank(rdev, i); | |
e884fc64 | 306 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
6253e4c7 AD |
307 | tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
308 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); | |
e884fc64 | 309 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
6253e4c7 AD |
310 | } |
311 | /* wait for the next frame */ | |
312 | frame_count = radeon_get_vblank_counter(rdev, i); | |
313 | for (j = 0; j < rdev->usec_timeout; j++) { | |
314 | if (radeon_get_vblank_counter(rdev, i) != frame_count) | |
315 | break; | |
316 | udelay(1); | |
317 | } | |
e884fc64 AD |
318 | |
319 | /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ | |
320 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); | |
321 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); | |
322 | tmp &= ~AVIVO_CRTC_EN; | |
323 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); | |
324 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); | |
325 | save->crtc_enabled[i] = false; | |
326 | /* ***** */ | |
6253e4c7 AD |
327 | } else { |
328 | save->crtc_enabled[i] = false; | |
329 | } | |
330 | } | |
331 | ||
332 | radeon_mc_wait_for_idle(rdev); | |
333 | ||
334 | if (rdev->family >= CHIP_R600) { | |
335 | if (rdev->family >= CHIP_RV770) | |
336 | blackout = RREG32(R700_MC_CITF_CNTL); | |
337 | else | |
338 | blackout = RREG32(R600_CITF_CNTL); | |
339 | if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) { | |
340 | /* Block CPU access */ | |
341 | WREG32(R600_BIF_FB_EN, 0); | |
342 | /* blackout the MC */ | |
343 | blackout |= R600_BLACKOUT_MASK; | |
344 | if (rdev->family >= CHIP_RV770) | |
345 | WREG32(R700_MC_CITF_CNTL, blackout); | |
346 | else | |
347 | WREG32(R600_CITF_CNTL, blackout); | |
348 | } | |
349 | } | |
39dc9aab AD |
350 | /* wait for the MC to settle */ |
351 | udelay(100); | |
2f86e2ed AD |
352 | |
353 | /* lock double buffered regs */ | |
354 | for (i = 0; i < rdev->num_crtc; i++) { | |
355 | if (save->crtc_enabled[i]) { | |
356 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); | |
357 | if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) { | |
358 | tmp |= AVIVO_D1GRPH_UPDATE_LOCK; | |
359 | WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); | |
360 | } | |
361 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); | |
362 | if (!(tmp & 1)) { | |
363 | tmp |= 1; | |
364 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); | |
365 | } | |
366 | } | |
367 | } | |
d39c3b89 JG |
368 | } |
369 | ||
370 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) | |
371 | { | |
6253e4c7 AD |
372 | u32 tmp, frame_count; |
373 | int i, j; | |
374 | ||
375 | /* update crtc base addresses */ | |
376 | for (i = 0; i < rdev->num_crtc; i++) { | |
377 | if (rdev->family >= CHIP_RV770) { | |
367cbe2f | 378 | if (i == 0) { |
6253e4c7 AD |
379 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, |
380 | upper_32_bits(rdev->mc.vram_start)); | |
381 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, | |
382 | upper_32_bits(rdev->mc.vram_start)); | |
383 | } else { | |
384 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, | |
385 | upper_32_bits(rdev->mc.vram_start)); | |
386 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, | |
387 | upper_32_bits(rdev->mc.vram_start)); | |
388 | } | |
389 | } | |
390 | WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], | |
391 | (u32)rdev->mc.vram_start); | |
392 | WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], | |
393 | (u32)rdev->mc.vram_start); | |
394 | } | |
395 | WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); | |
396 | ||
2f86e2ed AD |
397 | /* unlock regs and wait for update */ |
398 | for (i = 0; i < rdev->num_crtc; i++) { | |
399 | if (save->crtc_enabled[i]) { | |
400 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); | |
401 | if ((tmp & 0x3) != 0) { | |
402 | tmp &= ~0x3; | |
403 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); | |
404 | } | |
405 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); | |
406 | if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { | |
407 | tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; | |
408 | WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); | |
409 | } | |
410 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); | |
411 | if (tmp & 1) { | |
412 | tmp &= ~1; | |
413 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); | |
414 | } | |
415 | for (j = 0; j < rdev->usec_timeout; j++) { | |
416 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); | |
417 | if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) | |
418 | break; | |
419 | udelay(1); | |
420 | } | |
421 | } | |
422 | } | |
423 | ||
6253e4c7 AD |
424 | if (rdev->family >= CHIP_R600) { |
425 | /* unblackout the MC */ | |
426 | if (rdev->family >= CHIP_RV770) | |
427 | tmp = RREG32(R700_MC_CITF_CNTL); | |
428 | else | |
429 | tmp = RREG32(R600_CITF_CNTL); | |
430 | tmp &= ~R600_BLACKOUT_MASK; | |
431 | if (rdev->family >= CHIP_RV770) | |
432 | WREG32(R700_MC_CITF_CNTL, tmp); | |
433 | else | |
434 | WREG32(R600_CITF_CNTL, tmp); | |
435 | /* allow CPU access */ | |
436 | WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); | |
437 | } | |
438 | ||
439 | for (i = 0; i < rdev->num_crtc; i++) { | |
440 | if (save->crtc_enabled[i]) { | |
441 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); | |
442 | tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; | |
443 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); | |
444 | /* wait for the next frame */ | |
445 | frame_count = radeon_get_vblank_counter(rdev, i); | |
446 | for (j = 0; j < rdev->usec_timeout; j++) { | |
447 | if (radeon_get_vblank_counter(rdev, i) != frame_count) | |
448 | break; | |
449 | udelay(1); | |
450 | } | |
451 | } | |
452 | } | |
453 | /* Unlock vga access */ | |
d39c3b89 JG |
454 | WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); |
455 | mdelay(1); | |
d39c3b89 JG |
456 | WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); |
457 | } | |
458 | ||
1109ca09 | 459 | static void rv515_mc_program(struct radeon_device *rdev) |
d39c3b89 JG |
460 | { |
461 | struct rv515_mc_save save; | |
462 | ||
463 | /* Stops all mc clients */ | |
464 | rv515_mc_stop(rdev, &save); | |
465 | ||
466 | /* Wait for mc idle */ | |
467 | if (rv515_mc_wait_for_idle(rdev)) | |
468 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
469 | /* Write VRAM size in case we are limiting it */ | |
470 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | |
471 | /* Program MC, should be a 32bits limited address space */ | |
472 | WREG32_MC(R_000001_MC_FB_LOCATION, | |
473 | S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | | |
474 | S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
475 | WREG32(R_000134_HDP_FB_LOCATION, | |
476 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); | |
477 | if (rdev->flags & RADEON_IS_AGP) { | |
478 | WREG32_MC(R_000002_MC_AGP_LOCATION, | |
479 | S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | | |
480 | S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); | |
481 | WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); | |
482 | WREG32_MC(R_000004_MC_AGP_BASE_2, | |
483 | S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); | |
484 | } else { | |
485 | WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); | |
486 | WREG32_MC(R_000003_MC_AGP_BASE, 0); | |
487 | WREG32_MC(R_000004_MC_AGP_BASE_2, 0); | |
488 | } | |
489 | ||
490 | rv515_mc_resume(rdev, &save); | |
491 | } | |
492 | ||
493 | void rv515_clock_startup(struct radeon_device *rdev) | |
494 | { | |
495 | if (radeon_dynclks != -1 && radeon_dynclks) | |
496 | radeon_atom_set_clock_gating(rdev, 1); | |
497 | /* We need to force on some of the block */ | |
498 | WREG32_PLL(R_00000F_CP_DYN_CNTL, | |
499 | RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); | |
500 | WREG32_PLL(R_000011_E2_DYN_CNTL, | |
501 | RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); | |
502 | WREG32_PLL(R_000013_IDCT_DYN_CNTL, | |
503 | RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); | |
504 | } | |
505 | ||
506 | static int rv515_startup(struct radeon_device *rdev) | |
507 | { | |
508 | int r; | |
509 | ||
510 | rv515_mc_program(rdev); | |
511 | /* Resume clock */ | |
512 | rv515_clock_startup(rdev); | |
513 | /* Initialize GPU configuration (# pipes, ...) */ | |
514 | rv515_gpu_init(rdev); | |
515 | /* Initialize GART (initialize after TTM so we can allocate | |
516 | * memory through TTM but finalize after TTM) */ | |
517 | if (rdev->flags & RADEON_IS_PCIE) { | |
518 | r = rv370_pcie_gart_enable(rdev); | |
519 | if (r) | |
520 | return r; | |
521 | } | |
724c80e1 AD |
522 | |
523 | /* allocate wb buffer */ | |
524 | r = radeon_wb_init(rdev); | |
525 | if (r) | |
526 | return r; | |
527 | ||
30eb77f4 JG |
528 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
529 | if (r) { | |
530 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
531 | return r; | |
532 | } | |
533 | ||
d39c3b89 | 534 | /* Enable IRQ */ |
ac447df4 | 535 | rs600_irq_set(rdev); |
cafe6609 | 536 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
d39c3b89 JG |
537 | /* 1M ring buffer */ |
538 | r = r100_cp_init(rdev, 1024 * 1024); | |
539 | if (r) { | |
ec4f2ac4 | 540 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
d39c3b89 JG |
541 | return r; |
542 | } | |
b15ba512 | 543 | |
2898c348 CK |
544 | r = radeon_ib_pool_init(rdev); |
545 | if (r) { | |
546 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | |
b15ba512 | 547 | return r; |
2898c348 | 548 | } |
b15ba512 | 549 | |
d39c3b89 JG |
550 | return 0; |
551 | } | |
552 | ||
553 | int rv515_resume(struct radeon_device *rdev) | |
554 | { | |
6b7746e8 JG |
555 | int r; |
556 | ||
d39c3b89 JG |
557 | /* Make sur GART are not working */ |
558 | if (rdev->flags & RADEON_IS_PCIE) | |
559 | rv370_pcie_gart_disable(rdev); | |
560 | /* Resume clock before doing reset */ | |
561 | rv515_clock_startup(rdev); | |
562 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 563 | if (radeon_asic_reset(rdev)) { |
d39c3b89 JG |
564 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
565 | RREG32(R_000E40_RBBM_STATUS), | |
566 | RREG32(R_0007C0_CP_STAT)); | |
567 | } | |
568 | /* post */ | |
569 | atom_asic_init(rdev->mode_info.atom_context); | |
570 | /* Resume clock after posting */ | |
571 | rv515_clock_startup(rdev); | |
550e2d92 DA |
572 | /* Initialize surface registers */ |
573 | radeon_surface_init(rdev); | |
b15ba512 JG |
574 | |
575 | rdev->accel_working = true; | |
6b7746e8 JG |
576 | r = rv515_startup(rdev); |
577 | if (r) { | |
578 | rdev->accel_working = false; | |
579 | } | |
580 | return r; | |
d39c3b89 JG |
581 | } |
582 | ||
583 | int rv515_suspend(struct radeon_device *rdev) | |
584 | { | |
585 | r100_cp_disable(rdev); | |
724c80e1 | 586 | radeon_wb_disable(rdev); |
ac447df4 | 587 | rs600_irq_disable(rdev); |
d39c3b89 JG |
588 | if (rdev->flags & RADEON_IS_PCIE) |
589 | rv370_pcie_gart_disable(rdev); | |
590 | return 0; | |
591 | } | |
592 | ||
593 | void rv515_set_safe_registers(struct radeon_device *rdev) | |
068a117c | 594 | { |
50f15303 DA |
595 | rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; |
596 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); | |
d39c3b89 JG |
597 | } |
598 | ||
599 | void rv515_fini(struct radeon_device *rdev) | |
600 | { | |
d39c3b89 | 601 | r100_cp_fini(rdev); |
724c80e1 | 602 | radeon_wb_fini(rdev); |
2898c348 | 603 | radeon_ib_pool_fini(rdev); |
d39c3b89 | 604 | radeon_gem_fini(rdev); |
4c788679 | 605 | rv370_pcie_gart_fini(rdev); |
d39c3b89 JG |
606 | radeon_agp_fini(rdev); |
607 | radeon_irq_kms_fini(rdev); | |
608 | radeon_fence_driver_fini(rdev); | |
4c788679 | 609 | radeon_bo_fini(rdev); |
d39c3b89 JG |
610 | radeon_atombios_fini(rdev); |
611 | kfree(rdev->bios); | |
612 | rdev->bios = NULL; | |
613 | } | |
614 | ||
615 | int rv515_init(struct radeon_device *rdev) | |
616 | { | |
617 | int r; | |
618 | ||
d39c3b89 JG |
619 | /* Initialize scratch registers */ |
620 | radeon_scratch_init(rdev); | |
621 | /* Initialize surface registers */ | |
622 | radeon_surface_init(rdev); | |
623 | /* TODO: disable VGA need to use VGA request */ | |
4c712e6c DA |
624 | /* restore some register to sane defaults */ |
625 | r100_restore_sanity(rdev); | |
d39c3b89 JG |
626 | /* BIOS*/ |
627 | if (!radeon_get_bios(rdev)) { | |
628 | if (ASIC_IS_AVIVO(rdev)) | |
629 | return -EINVAL; | |
630 | } | |
631 | if (rdev->is_atom_bios) { | |
632 | r = radeon_atombios_init(rdev); | |
633 | if (r) | |
634 | return r; | |
635 | } else { | |
636 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); | |
637 | return -EINVAL; | |
638 | } | |
639 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 640 | if (radeon_asic_reset(rdev)) { |
d39c3b89 JG |
641 | dev_warn(rdev->dev, |
642 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
643 | RREG32(R_000E40_RBBM_STATUS), | |
644 | RREG32(R_0007C0_CP_STAT)); | |
645 | } | |
646 | /* check if cards are posted or not */ | |
72542d77 DA |
647 | if (radeon_boot_test_post_card(rdev) == false) |
648 | return -EINVAL; | |
d39c3b89 JG |
649 | /* Initialize clocks */ |
650 | radeon_get_clock_info(rdev->ddev); | |
d594e46a JG |
651 | /* initialize AGP */ |
652 | if (rdev->flags & RADEON_IS_AGP) { | |
653 | r = radeon_agp_init(rdev); | |
654 | if (r) { | |
655 | radeon_agp_disable(rdev); | |
656 | } | |
657 | } | |
658 | /* initialize memory controller */ | |
659 | rv515_mc_init(rdev); | |
d39c3b89 JG |
660 | rv515_debugfs(rdev); |
661 | /* Fence driver */ | |
30eb77f4 | 662 | r = radeon_fence_driver_init(rdev); |
d39c3b89 JG |
663 | if (r) |
664 | return r; | |
665 | r = radeon_irq_kms_init(rdev); | |
666 | if (r) | |
667 | return r; | |
668 | /* Memory manager */ | |
4c788679 | 669 | r = radeon_bo_init(rdev); |
d39c3b89 JG |
670 | if (r) |
671 | return r; | |
672 | r = rv370_pcie_gart_init(rdev); | |
673 | if (r) | |
674 | return r; | |
675 | rv515_set_safe_registers(rdev); | |
b15ba512 | 676 | |
d39c3b89 JG |
677 | rdev->accel_working = true; |
678 | r = rv515_startup(rdev); | |
679 | if (r) { | |
680 | /* Somethings want wront with the accel init stop accel */ | |
681 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
d39c3b89 | 682 | r100_cp_fini(rdev); |
724c80e1 | 683 | radeon_wb_fini(rdev); |
2898c348 | 684 | radeon_ib_pool_fini(rdev); |
655efd3d | 685 | radeon_irq_kms_fini(rdev); |
d39c3b89 JG |
686 | rv370_pcie_gart_fini(rdev); |
687 | radeon_agp_fini(rdev); | |
d39c3b89 JG |
688 | rdev->accel_working = false; |
689 | } | |
068a117c JG |
690 | return 0; |
691 | } | |
c93bb85b | 692 | |
4ce001ab | 693 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) |
c93bb85b | 694 | { |
4ce001ab DA |
695 | int index_reg = 0x6578 + crtc->crtc_offset; |
696 | int data_reg = 0x657c + crtc->crtc_offset; | |
697 | ||
698 | WREG32(0x659C + crtc->crtc_offset, 0x0); | |
699 | WREG32(0x6594 + crtc->crtc_offset, 0x705); | |
700 | WREG32(0x65A4 + crtc->crtc_offset, 0x10001); | |
701 | WREG32(0x65D8 + crtc->crtc_offset, 0x0); | |
702 | WREG32(0x65B0 + crtc->crtc_offset, 0x0); | |
703 | WREG32(0x65C0 + crtc->crtc_offset, 0x0); | |
704 | WREG32(0x65D4 + crtc->crtc_offset, 0x0); | |
705 | WREG32(index_reg, 0x0); | |
706 | WREG32(data_reg, 0x841880A8); | |
707 | WREG32(index_reg, 0x1); | |
708 | WREG32(data_reg, 0x84208680); | |
709 | WREG32(index_reg, 0x2); | |
710 | WREG32(data_reg, 0xBFF880B0); | |
711 | WREG32(index_reg, 0x100); | |
712 | WREG32(data_reg, 0x83D88088); | |
713 | WREG32(index_reg, 0x101); | |
714 | WREG32(data_reg, 0x84608680); | |
715 | WREG32(index_reg, 0x102); | |
716 | WREG32(data_reg, 0xBFF080D0); | |
717 | WREG32(index_reg, 0x200); | |
718 | WREG32(data_reg, 0x83988068); | |
719 | WREG32(index_reg, 0x201); | |
720 | WREG32(data_reg, 0x84A08680); | |
721 | WREG32(index_reg, 0x202); | |
722 | WREG32(data_reg, 0xBFF080F8); | |
723 | WREG32(index_reg, 0x300); | |
724 | WREG32(data_reg, 0x83588058); | |
725 | WREG32(index_reg, 0x301); | |
726 | WREG32(data_reg, 0x84E08660); | |
727 | WREG32(index_reg, 0x302); | |
728 | WREG32(data_reg, 0xBFF88120); | |
729 | WREG32(index_reg, 0x400); | |
730 | WREG32(data_reg, 0x83188040); | |
731 | WREG32(index_reg, 0x401); | |
732 | WREG32(data_reg, 0x85008660); | |
733 | WREG32(index_reg, 0x402); | |
734 | WREG32(data_reg, 0xBFF88150); | |
735 | WREG32(index_reg, 0x500); | |
736 | WREG32(data_reg, 0x82D88030); | |
737 | WREG32(index_reg, 0x501); | |
738 | WREG32(data_reg, 0x85408640); | |
739 | WREG32(index_reg, 0x502); | |
740 | WREG32(data_reg, 0xBFF88180); | |
741 | WREG32(index_reg, 0x600); | |
742 | WREG32(data_reg, 0x82A08018); | |
743 | WREG32(index_reg, 0x601); | |
744 | WREG32(data_reg, 0x85808620); | |
745 | WREG32(index_reg, 0x602); | |
746 | WREG32(data_reg, 0xBFF081B8); | |
747 | WREG32(index_reg, 0x700); | |
748 | WREG32(data_reg, 0x82608010); | |
749 | WREG32(index_reg, 0x701); | |
750 | WREG32(data_reg, 0x85A08600); | |
751 | WREG32(index_reg, 0x702); | |
752 | WREG32(data_reg, 0x800081F0); | |
753 | WREG32(index_reg, 0x800); | |
754 | WREG32(data_reg, 0x8228BFF8); | |
755 | WREG32(index_reg, 0x801); | |
756 | WREG32(data_reg, 0x85E085E0); | |
757 | WREG32(index_reg, 0x802); | |
758 | WREG32(data_reg, 0xBFF88228); | |
759 | WREG32(index_reg, 0x10000); | |
760 | WREG32(data_reg, 0x82A8BF00); | |
761 | WREG32(index_reg, 0x10001); | |
762 | WREG32(data_reg, 0x82A08CC0); | |
763 | WREG32(index_reg, 0x10002); | |
764 | WREG32(data_reg, 0x8008BEF8); | |
765 | WREG32(index_reg, 0x10100); | |
766 | WREG32(data_reg, 0x81F0BF28); | |
767 | WREG32(index_reg, 0x10101); | |
768 | WREG32(data_reg, 0x83608CA0); | |
769 | WREG32(index_reg, 0x10102); | |
770 | WREG32(data_reg, 0x8018BED0); | |
771 | WREG32(index_reg, 0x10200); | |
772 | WREG32(data_reg, 0x8148BF38); | |
773 | WREG32(index_reg, 0x10201); | |
774 | WREG32(data_reg, 0x84408C80); | |
775 | WREG32(index_reg, 0x10202); | |
776 | WREG32(data_reg, 0x8008BEB8); | |
777 | WREG32(index_reg, 0x10300); | |
778 | WREG32(data_reg, 0x80B0BF78); | |
779 | WREG32(index_reg, 0x10301); | |
780 | WREG32(data_reg, 0x85008C20); | |
781 | WREG32(index_reg, 0x10302); | |
782 | WREG32(data_reg, 0x8020BEA0); | |
783 | WREG32(index_reg, 0x10400); | |
784 | WREG32(data_reg, 0x8028BF90); | |
785 | WREG32(index_reg, 0x10401); | |
786 | WREG32(data_reg, 0x85E08BC0); | |
787 | WREG32(index_reg, 0x10402); | |
788 | WREG32(data_reg, 0x8018BE90); | |
789 | WREG32(index_reg, 0x10500); | |
790 | WREG32(data_reg, 0xBFB8BFB0); | |
791 | WREG32(index_reg, 0x10501); | |
792 | WREG32(data_reg, 0x86C08B40); | |
793 | WREG32(index_reg, 0x10502); | |
794 | WREG32(data_reg, 0x8010BE90); | |
795 | WREG32(index_reg, 0x10600); | |
796 | WREG32(data_reg, 0xBF58BFC8); | |
797 | WREG32(index_reg, 0x10601); | |
798 | WREG32(data_reg, 0x87A08AA0); | |
799 | WREG32(index_reg, 0x10602); | |
800 | WREG32(data_reg, 0x8010BE98); | |
801 | WREG32(index_reg, 0x10700); | |
802 | WREG32(data_reg, 0xBF10BFF0); | |
803 | WREG32(index_reg, 0x10701); | |
804 | WREG32(data_reg, 0x886089E0); | |
805 | WREG32(index_reg, 0x10702); | |
806 | WREG32(data_reg, 0x8018BEB0); | |
807 | WREG32(index_reg, 0x10800); | |
808 | WREG32(data_reg, 0xBED8BFE8); | |
809 | WREG32(index_reg, 0x10801); | |
810 | WREG32(data_reg, 0x89408940); | |
811 | WREG32(index_reg, 0x10802); | |
812 | WREG32(data_reg, 0xBFE8BED8); | |
813 | WREG32(index_reg, 0x20000); | |
814 | WREG32(data_reg, 0x80008000); | |
815 | WREG32(index_reg, 0x20001); | |
816 | WREG32(data_reg, 0x90008000); | |
817 | WREG32(index_reg, 0x20002); | |
818 | WREG32(data_reg, 0x80008000); | |
819 | WREG32(index_reg, 0x20003); | |
820 | WREG32(data_reg, 0x80008000); | |
821 | WREG32(index_reg, 0x20100); | |
822 | WREG32(data_reg, 0x80108000); | |
823 | WREG32(index_reg, 0x20101); | |
824 | WREG32(data_reg, 0x8FE0BF70); | |
825 | WREG32(index_reg, 0x20102); | |
826 | WREG32(data_reg, 0xBFE880C0); | |
827 | WREG32(index_reg, 0x20103); | |
828 | WREG32(data_reg, 0x80008000); | |
829 | WREG32(index_reg, 0x20200); | |
830 | WREG32(data_reg, 0x8018BFF8); | |
831 | WREG32(index_reg, 0x20201); | |
832 | WREG32(data_reg, 0x8F80BF08); | |
833 | WREG32(index_reg, 0x20202); | |
834 | WREG32(data_reg, 0xBFD081A0); | |
835 | WREG32(index_reg, 0x20203); | |
836 | WREG32(data_reg, 0xBFF88000); | |
837 | WREG32(index_reg, 0x20300); | |
838 | WREG32(data_reg, 0x80188000); | |
839 | WREG32(index_reg, 0x20301); | |
840 | WREG32(data_reg, 0x8EE0BEC0); | |
841 | WREG32(index_reg, 0x20302); | |
842 | WREG32(data_reg, 0xBFB082A0); | |
843 | WREG32(index_reg, 0x20303); | |
844 | WREG32(data_reg, 0x80008000); | |
845 | WREG32(index_reg, 0x20400); | |
846 | WREG32(data_reg, 0x80188000); | |
847 | WREG32(index_reg, 0x20401); | |
848 | WREG32(data_reg, 0x8E00BEA0); | |
849 | WREG32(index_reg, 0x20402); | |
850 | WREG32(data_reg, 0xBF8883C0); | |
851 | WREG32(index_reg, 0x20403); | |
852 | WREG32(data_reg, 0x80008000); | |
853 | WREG32(index_reg, 0x20500); | |
854 | WREG32(data_reg, 0x80188000); | |
855 | WREG32(index_reg, 0x20501); | |
856 | WREG32(data_reg, 0x8D00BE90); | |
857 | WREG32(index_reg, 0x20502); | |
858 | WREG32(data_reg, 0xBF588500); | |
859 | WREG32(index_reg, 0x20503); | |
860 | WREG32(data_reg, 0x80008008); | |
861 | WREG32(index_reg, 0x20600); | |
862 | WREG32(data_reg, 0x80188000); | |
863 | WREG32(index_reg, 0x20601); | |
864 | WREG32(data_reg, 0x8BC0BE98); | |
865 | WREG32(index_reg, 0x20602); | |
866 | WREG32(data_reg, 0xBF308660); | |
867 | WREG32(index_reg, 0x20603); | |
868 | WREG32(data_reg, 0x80008008); | |
869 | WREG32(index_reg, 0x20700); | |
870 | WREG32(data_reg, 0x80108000); | |
871 | WREG32(index_reg, 0x20701); | |
872 | WREG32(data_reg, 0x8A80BEB0); | |
873 | WREG32(index_reg, 0x20702); | |
874 | WREG32(data_reg, 0xBF0087C0); | |
875 | WREG32(index_reg, 0x20703); | |
876 | WREG32(data_reg, 0x80008008); | |
877 | WREG32(index_reg, 0x20800); | |
878 | WREG32(data_reg, 0x80108000); | |
879 | WREG32(index_reg, 0x20801); | |
880 | WREG32(data_reg, 0x8920BED0); | |
881 | WREG32(index_reg, 0x20802); | |
882 | WREG32(data_reg, 0xBED08920); | |
883 | WREG32(index_reg, 0x20803); | |
884 | WREG32(data_reg, 0x80008010); | |
885 | WREG32(index_reg, 0x30000); | |
886 | WREG32(data_reg, 0x90008000); | |
887 | WREG32(index_reg, 0x30001); | |
888 | WREG32(data_reg, 0x80008000); | |
889 | WREG32(index_reg, 0x30100); | |
890 | WREG32(data_reg, 0x8FE0BF90); | |
891 | WREG32(index_reg, 0x30101); | |
892 | WREG32(data_reg, 0xBFF880A0); | |
893 | WREG32(index_reg, 0x30200); | |
894 | WREG32(data_reg, 0x8F60BF40); | |
895 | WREG32(index_reg, 0x30201); | |
896 | WREG32(data_reg, 0xBFE88180); | |
897 | WREG32(index_reg, 0x30300); | |
898 | WREG32(data_reg, 0x8EC0BF00); | |
899 | WREG32(index_reg, 0x30301); | |
900 | WREG32(data_reg, 0xBFC88280); | |
901 | WREG32(index_reg, 0x30400); | |
902 | WREG32(data_reg, 0x8DE0BEE0); | |
903 | WREG32(index_reg, 0x30401); | |
904 | WREG32(data_reg, 0xBFA083A0); | |
905 | WREG32(index_reg, 0x30500); | |
906 | WREG32(data_reg, 0x8CE0BED0); | |
907 | WREG32(index_reg, 0x30501); | |
908 | WREG32(data_reg, 0xBF7884E0); | |
909 | WREG32(index_reg, 0x30600); | |
910 | WREG32(data_reg, 0x8BA0BED8); | |
911 | WREG32(index_reg, 0x30601); | |
912 | WREG32(data_reg, 0xBF508640); | |
913 | WREG32(index_reg, 0x30700); | |
914 | WREG32(data_reg, 0x8A60BEE8); | |
915 | WREG32(index_reg, 0x30701); | |
916 | WREG32(data_reg, 0xBF2087A0); | |
917 | WREG32(index_reg, 0x30800); | |
918 | WREG32(data_reg, 0x8900BF00); | |
919 | WREG32(index_reg, 0x30801); | |
920 | WREG32(data_reg, 0xBF008900); | |
c93bb85b JG |
921 | } |
922 | ||
923 | struct rv515_watermark { | |
924 | u32 lb_request_fifo_depth; | |
925 | fixed20_12 num_line_pair; | |
926 | fixed20_12 estimated_width; | |
927 | fixed20_12 worst_case_latency; | |
928 | fixed20_12 consumption_rate; | |
929 | fixed20_12 active_time; | |
930 | fixed20_12 dbpp; | |
931 | fixed20_12 priority_mark_max; | |
932 | fixed20_12 priority_mark; | |
933 | fixed20_12 sclk; | |
934 | }; | |
935 | ||
1109ca09 | 936 | static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, |
c93bb85b JG |
937 | struct radeon_crtc *crtc, |
938 | struct rv515_watermark *wm) | |
939 | { | |
940 | struct drm_display_mode *mode = &crtc->base.mode; | |
941 | fixed20_12 a, b, c; | |
942 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; | |
943 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; | |
944 | ||
945 | if (!crtc->base.enabled) { | |
946 | /* FIXME: wouldn't it better to set priority mark to maximum */ | |
947 | wm->lb_request_fifo_depth = 4; | |
948 | return; | |
949 | } | |
950 | ||
68adac5e BS |
951 | if (crtc->vsc.full > dfixed_const(2)) |
952 | wm->num_line_pair.full = dfixed_const(2); | |
c93bb85b | 953 | else |
68adac5e | 954 | wm->num_line_pair.full = dfixed_const(1); |
c93bb85b | 955 | |
68adac5e BS |
956 | b.full = dfixed_const(mode->crtc_hdisplay); |
957 | c.full = dfixed_const(256); | |
958 | a.full = dfixed_div(b, c); | |
959 | request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); | |
960 | request_fifo_depth.full = dfixed_ceil(request_fifo_depth); | |
961 | if (a.full < dfixed_const(4)) { | |
c93bb85b JG |
962 | wm->lb_request_fifo_depth = 4; |
963 | } else { | |
68adac5e | 964 | wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); |
c93bb85b JG |
965 | } |
966 | ||
967 | /* Determine consumption rate | |
968 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) | |
969 | * vtaps = number of vertical taps, | |
970 | * vsc = vertical scaling ratio, defined as source/destination | |
971 | * hsc = horizontal scaling ration, defined as source/destination | |
972 | */ | |
68adac5e BS |
973 | a.full = dfixed_const(mode->clock); |
974 | b.full = dfixed_const(1000); | |
975 | a.full = dfixed_div(a, b); | |
976 | pclk.full = dfixed_div(b, a); | |
c93bb85b | 977 | if (crtc->rmx_type != RMX_OFF) { |
68adac5e | 978 | b.full = dfixed_const(2); |
c93bb85b JG |
979 | if (crtc->vsc.full > b.full) |
980 | b.full = crtc->vsc.full; | |
68adac5e BS |
981 | b.full = dfixed_mul(b, crtc->hsc); |
982 | c.full = dfixed_const(2); | |
983 | b.full = dfixed_div(b, c); | |
984 | consumption_time.full = dfixed_div(pclk, b); | |
c93bb85b JG |
985 | } else { |
986 | consumption_time.full = pclk.full; | |
987 | } | |
68adac5e BS |
988 | a.full = dfixed_const(1); |
989 | wm->consumption_rate.full = dfixed_div(a, consumption_time); | |
c93bb85b JG |
990 | |
991 | ||
992 | /* Determine line time | |
993 | * LineTime = total time for one line of displayhtotal | |
994 | * LineTime = total number of horizontal pixels | |
995 | * pclk = pixel clock period(ns) | |
996 | */ | |
68adac5e BS |
997 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
998 | line_time.full = dfixed_mul(a, pclk); | |
c93bb85b JG |
999 | |
1000 | /* Determine active time | |
1001 | * ActiveTime = time of active region of display within one line, | |
1002 | * hactive = total number of horizontal active pixels | |
1003 | * htotal = total number of horizontal pixels | |
1004 | */ | |
68adac5e BS |
1005 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
1006 | b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); | |
1007 | wm->active_time.full = dfixed_mul(line_time, b); | |
1008 | wm->active_time.full = dfixed_div(wm->active_time, a); | |
c93bb85b JG |
1009 | |
1010 | /* Determine chunk time | |
1011 | * ChunkTime = the time it takes the DCP to send one chunk of data | |
1012 | * to the LB which consists of pipeline delay and inter chunk gap | |
1013 | * sclk = system clock(Mhz) | |
1014 | */ | |
68adac5e BS |
1015 | a.full = dfixed_const(600 * 1000); |
1016 | chunk_time.full = dfixed_div(a, rdev->pm.sclk); | |
1017 | read_delay_latency.full = dfixed_const(1000); | |
c93bb85b JG |
1018 | |
1019 | /* Determine the worst case latency | |
1020 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) | |
1021 | * WorstCaseLatency = worst case time from urgent to when the MC starts | |
1022 | * to return data | |
1023 | * READ_DELAY_IDLE_MAX = constant of 1us | |
1024 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB | |
1025 | * which consists of pipeline delay and inter chunk gap | |
1026 | */ | |
68adac5e BS |
1027 | if (dfixed_trunc(wm->num_line_pair) > 1) { |
1028 | a.full = dfixed_const(3); | |
1029 | wm->worst_case_latency.full = dfixed_mul(a, chunk_time); | |
c93bb85b JG |
1030 | wm->worst_case_latency.full += read_delay_latency.full; |
1031 | } else { | |
1032 | wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; | |
1033 | } | |
1034 | ||
1035 | /* Determine the tolerable latency | |
1036 | * TolerableLatency = Any given request has only 1 line time | |
1037 | * for the data to be returned | |
1038 | * LBRequestFifoDepth = Number of chunk requests the LB can | |
1039 | * put into the request FIFO for a display | |
1040 | * LineTime = total time for one line of display | |
1041 | * ChunkTime = the time it takes the DCP to send one chunk | |
1042 | * of data to the LB which consists of | |
1043 | * pipeline delay and inter chunk gap | |
1044 | */ | |
68adac5e | 1045 | if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { |
c93bb85b JG |
1046 | tolerable_latency.full = line_time.full; |
1047 | } else { | |
68adac5e | 1048 | tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); |
c93bb85b | 1049 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
68adac5e | 1050 | tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); |
c93bb85b JG |
1051 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
1052 | } | |
1053 | /* We assume worst case 32bits (4 bytes) */ | |
68adac5e | 1054 | wm->dbpp.full = dfixed_const(2 * 16); |
c93bb85b JG |
1055 | |
1056 | /* Determine the maximum priority mark | |
1057 | * width = viewport width in pixels | |
1058 | */ | |
68adac5e BS |
1059 | a.full = dfixed_const(16); |
1060 | wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); | |
1061 | wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); | |
1062 | wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); | |
c93bb85b JG |
1063 | |
1064 | /* Determine estimated width */ | |
1065 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; | |
68adac5e BS |
1066 | estimated_width.full = dfixed_div(estimated_width, consumption_time); |
1067 | if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { | |
69b3b5e5 | 1068 | wm->priority_mark.full = wm->priority_mark_max.full; |
c93bb85b | 1069 | } else { |
68adac5e BS |
1070 | a.full = dfixed_const(16); |
1071 | wm->priority_mark.full = dfixed_div(estimated_width, a); | |
1072 | wm->priority_mark.full = dfixed_ceil(wm->priority_mark); | |
c93bb85b JG |
1073 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
1074 | } | |
1075 | } | |
1076 | ||
1077 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) | |
1078 | { | |
1079 | struct drm_display_mode *mode0 = NULL; | |
1080 | struct drm_display_mode *mode1 = NULL; | |
1081 | struct rv515_watermark wm0; | |
1082 | struct rv515_watermark wm1; | |
e06b14ee AD |
1083 | u32 tmp; |
1084 | u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF; | |
1085 | u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF; | |
c93bb85b JG |
1086 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
1087 | fixed20_12 a, b; | |
1088 | ||
1089 | if (rdev->mode_info.crtcs[0]->base.enabled) | |
1090 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; | |
1091 | if (rdev->mode_info.crtcs[1]->base.enabled) | |
1092 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; | |
1093 | rs690_line_buffer_adjust(rdev, mode0, mode1); | |
1094 | ||
1095 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); | |
1096 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); | |
1097 | ||
1098 | tmp = wm0.lb_request_fifo_depth; | |
1099 | tmp |= wm1.lb_request_fifo_depth << 16; | |
1100 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); | |
1101 | ||
1102 | if (mode0 && mode1) { | |
68adac5e BS |
1103 | if (dfixed_trunc(wm0.dbpp) > 64) |
1104 | a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); | |
c93bb85b JG |
1105 | else |
1106 | a.full = wm0.num_line_pair.full; | |
68adac5e BS |
1107 | if (dfixed_trunc(wm1.dbpp) > 64) |
1108 | b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); | |
c93bb85b JG |
1109 | else |
1110 | b.full = wm1.num_line_pair.full; | |
1111 | a.full += b.full; | |
68adac5e | 1112 | fill_rate.full = dfixed_div(wm0.sclk, a); |
c93bb85b JG |
1113 | if (wm0.consumption_rate.full > fill_rate.full) { |
1114 | b.full = wm0.consumption_rate.full - fill_rate.full; | |
68adac5e BS |
1115 | b.full = dfixed_mul(b, wm0.active_time); |
1116 | a.full = dfixed_const(16); | |
1117 | b.full = dfixed_div(b, a); | |
1118 | a.full = dfixed_mul(wm0.worst_case_latency, | |
c93bb85b JG |
1119 | wm0.consumption_rate); |
1120 | priority_mark02.full = a.full + b.full; | |
1121 | } else { | |
68adac5e | 1122 | a.full = dfixed_mul(wm0.worst_case_latency, |
c93bb85b | 1123 | wm0.consumption_rate); |
68adac5e BS |
1124 | b.full = dfixed_const(16 * 1000); |
1125 | priority_mark02.full = dfixed_div(a, b); | |
c93bb85b JG |
1126 | } |
1127 | if (wm1.consumption_rate.full > fill_rate.full) { | |
1128 | b.full = wm1.consumption_rate.full - fill_rate.full; | |
68adac5e BS |
1129 | b.full = dfixed_mul(b, wm1.active_time); |
1130 | a.full = dfixed_const(16); | |
1131 | b.full = dfixed_div(b, a); | |
1132 | a.full = dfixed_mul(wm1.worst_case_latency, | |
c93bb85b JG |
1133 | wm1.consumption_rate); |
1134 | priority_mark12.full = a.full + b.full; | |
1135 | } else { | |
68adac5e | 1136 | a.full = dfixed_mul(wm1.worst_case_latency, |
c93bb85b | 1137 | wm1.consumption_rate); |
68adac5e BS |
1138 | b.full = dfixed_const(16 * 1000); |
1139 | priority_mark12.full = dfixed_div(a, b); | |
c93bb85b JG |
1140 | } |
1141 | if (wm0.priority_mark.full > priority_mark02.full) | |
1142 | priority_mark02.full = wm0.priority_mark.full; | |
68adac5e | 1143 | if (dfixed_trunc(priority_mark02) < 0) |
c93bb85b JG |
1144 | priority_mark02.full = 0; |
1145 | if (wm0.priority_mark_max.full > priority_mark02.full) | |
1146 | priority_mark02.full = wm0.priority_mark_max.full; | |
1147 | if (wm1.priority_mark.full > priority_mark12.full) | |
1148 | priority_mark12.full = wm1.priority_mark.full; | |
68adac5e | 1149 | if (dfixed_trunc(priority_mark12) < 0) |
c93bb85b JG |
1150 | priority_mark12.full = 0; |
1151 | if (wm1.priority_mark_max.full > priority_mark12.full) | |
1152 | priority_mark12.full = wm1.priority_mark_max.full; | |
68adac5e BS |
1153 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
1154 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); | |
f46c0120 AD |
1155 | if (rdev->disp_priority == 2) { |
1156 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | |
1157 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | |
1158 | } | |
c93bb85b | 1159 | } else if (mode0) { |
68adac5e BS |
1160 | if (dfixed_trunc(wm0.dbpp) > 64) |
1161 | a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); | |
c93bb85b JG |
1162 | else |
1163 | a.full = wm0.num_line_pair.full; | |
68adac5e | 1164 | fill_rate.full = dfixed_div(wm0.sclk, a); |
c93bb85b JG |
1165 | if (wm0.consumption_rate.full > fill_rate.full) { |
1166 | b.full = wm0.consumption_rate.full - fill_rate.full; | |
68adac5e BS |
1167 | b.full = dfixed_mul(b, wm0.active_time); |
1168 | a.full = dfixed_const(16); | |
1169 | b.full = dfixed_div(b, a); | |
1170 | a.full = dfixed_mul(wm0.worst_case_latency, | |
c93bb85b JG |
1171 | wm0.consumption_rate); |
1172 | priority_mark02.full = a.full + b.full; | |
1173 | } else { | |
68adac5e | 1174 | a.full = dfixed_mul(wm0.worst_case_latency, |
c93bb85b | 1175 | wm0.consumption_rate); |
68adac5e BS |
1176 | b.full = dfixed_const(16); |
1177 | priority_mark02.full = dfixed_div(a, b); | |
c93bb85b JG |
1178 | } |
1179 | if (wm0.priority_mark.full > priority_mark02.full) | |
1180 | priority_mark02.full = wm0.priority_mark.full; | |
68adac5e | 1181 | if (dfixed_trunc(priority_mark02) < 0) |
c93bb85b JG |
1182 | priority_mark02.full = 0; |
1183 | if (wm0.priority_mark_max.full > priority_mark02.full) | |
1184 | priority_mark02.full = wm0.priority_mark_max.full; | |
68adac5e | 1185 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
f46c0120 AD |
1186 | if (rdev->disp_priority == 2) |
1187 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | |
e06b14ee | 1188 | } else if (mode1) { |
68adac5e BS |
1189 | if (dfixed_trunc(wm1.dbpp) > 64) |
1190 | a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); | |
c93bb85b JG |
1191 | else |
1192 | a.full = wm1.num_line_pair.full; | |
68adac5e | 1193 | fill_rate.full = dfixed_div(wm1.sclk, a); |
c93bb85b JG |
1194 | if (wm1.consumption_rate.full > fill_rate.full) { |
1195 | b.full = wm1.consumption_rate.full - fill_rate.full; | |
68adac5e BS |
1196 | b.full = dfixed_mul(b, wm1.active_time); |
1197 | a.full = dfixed_const(16); | |
1198 | b.full = dfixed_div(b, a); | |
1199 | a.full = dfixed_mul(wm1.worst_case_latency, | |
c93bb85b JG |
1200 | wm1.consumption_rate); |
1201 | priority_mark12.full = a.full + b.full; | |
1202 | } else { | |
68adac5e | 1203 | a.full = dfixed_mul(wm1.worst_case_latency, |
c93bb85b | 1204 | wm1.consumption_rate); |
68adac5e BS |
1205 | b.full = dfixed_const(16 * 1000); |
1206 | priority_mark12.full = dfixed_div(a, b); | |
c93bb85b JG |
1207 | } |
1208 | if (wm1.priority_mark.full > priority_mark12.full) | |
1209 | priority_mark12.full = wm1.priority_mark.full; | |
68adac5e | 1210 | if (dfixed_trunc(priority_mark12) < 0) |
c93bb85b JG |
1211 | priority_mark12.full = 0; |
1212 | if (wm1.priority_mark_max.full > priority_mark12.full) | |
1213 | priority_mark12.full = wm1.priority_mark_max.full; | |
68adac5e | 1214 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
f46c0120 AD |
1215 | if (rdev->disp_priority == 2) |
1216 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | |
c93bb85b | 1217 | } |
e06b14ee AD |
1218 | |
1219 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | |
1220 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | |
1221 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); | |
1222 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | |
c93bb85b JG |
1223 | } |
1224 | ||
1225 | void rv515_bandwidth_update(struct radeon_device *rdev) | |
1226 | { | |
1227 | uint32_t tmp; | |
1228 | struct drm_display_mode *mode0 = NULL; | |
1229 | struct drm_display_mode *mode1 = NULL; | |
1230 | ||
f46c0120 AD |
1231 | radeon_update_display_priority(rdev); |
1232 | ||
c93bb85b JG |
1233 | if (rdev->mode_info.crtcs[0]->base.enabled) |
1234 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; | |
1235 | if (rdev->mode_info.crtcs[1]->base.enabled) | |
1236 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; | |
1237 | /* | |
1238 | * Set display0/1 priority up in the memory controller for | |
1239 | * modes if the user specifies HIGH for displaypriority | |
1240 | * option. | |
1241 | */ | |
f46c0120 AD |
1242 | if ((rdev->disp_priority == 2) && |
1243 | (rdev->family == CHIP_RV515)) { | |
c93bb85b JG |
1244 | tmp = RREG32_MC(MC_MISC_LAT_TIMER); |
1245 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; | |
1246 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; | |
1247 | if (mode1) | |
1248 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); | |
1249 | if (mode0) | |
1250 | tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); | |
1251 | WREG32_MC(MC_MISC_LAT_TIMER, tmp); | |
1252 | } | |
1253 | rv515_bandwidth_avivo_update(rdev); | |
1254 | } |