Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
c010f800 JG |
28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
29 | * | |
30 | * This file gather function specific to RS600 which is the IGP of | |
31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 | |
32 | * is the X1250/X1270 supporting AMD CPU). The display engine are | |
33 | * the avivo one, bios is an atombios, 3D block are the one of the | |
34 | * R4XX family. The GART is different from the RS400 one and is very | |
35 | * close to the one of the R600 family (R600 likely being an evolution | |
36 | * of the RS600 GART block). | |
37 | */ | |
760285e7 | 38 | #include <drm/drmP.h> |
771fe6b9 | 39 | #include "radeon.h" |
e6990375 | 40 | #include "radeon_asic.h" |
c010f800 JG |
41 | #include "atom.h" |
42 | #include "rs600d.h" | |
771fe6b9 | 43 | |
3f7dc91a DA |
44 | #include "rs600_reg_safe.h" |
45 | ||
1109ca09 | 46 | static void rs600_gpu_init(struct radeon_device *rdev); |
771fe6b9 | 47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
771fe6b9 | 48 | |
75104fa4 AD |
49 | static const u32 crtc_offsets[2] = |
50 | { | |
51 | 0, | |
52 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL | |
53 | }; | |
54 | ||
bea5497b AD |
55 | static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) |
56 | { | |
57 | if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) | |
58 | return true; | |
59 | else | |
60 | return false; | |
61 | } | |
62 | ||
63 | static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) | |
64 | { | |
65 | u32 pos1, pos2; | |
66 | ||
67 | pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); | |
68 | pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); | |
69 | ||
70 | if (pos1 != pos2) | |
71 | return true; | |
72 | else | |
73 | return false; | |
74 | } | |
75 | ||
76 | /** | |
77 | * avivo_wait_for_vblank - vblank wait asic callback. | |
78 | * | |
79 | * @rdev: radeon_device pointer | |
80 | * @crtc: crtc to wait for vblank on | |
81 | * | |
82 | * Wait for vblank on the requested crtc (r5xx-r7xx). | |
83 | */ | |
3ae19b75 AD |
84 | void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) |
85 | { | |
bea5497b | 86 | unsigned i = 0; |
3ae19b75 | 87 | |
75104fa4 AD |
88 | if (crtc >= rdev->num_crtc) |
89 | return; | |
90 | ||
bea5497b AD |
91 | if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) |
92 | return; | |
93 | ||
94 | /* depending on when we hit vblank, we may be close to active; if so, | |
95 | * wait for another frame. | |
96 | */ | |
97 | while (avivo_is_in_vblank(rdev, crtc)) { | |
98 | if (i++ % 100 == 0) { | |
99 | if (!avivo_is_counter_moving(rdev, crtc)) | |
3ae19b75 | 100 | break; |
3ae19b75 | 101 | } |
bea5497b AD |
102 | } |
103 | ||
104 | while (!avivo_is_in_vblank(rdev, crtc)) { | |
105 | if (i++ % 100 == 0) { | |
106 | if (!avivo_is_counter_moving(rdev, crtc)) | |
3ae19b75 | 107 | break; |
3ae19b75 AD |
108 | } |
109 | } | |
110 | } | |
111 | ||
6f34be50 AD |
112 | void rs600_pre_page_flip(struct radeon_device *rdev, int crtc) |
113 | { | |
6f34be50 AD |
114 | /* enable the pflip int */ |
115 | radeon_irq_kms_pflip_irq_get(rdev, crtc); | |
116 | } | |
117 | ||
118 | void rs600_post_page_flip(struct radeon_device *rdev, int crtc) | |
119 | { | |
120 | /* disable the pflip int */ | |
121 | radeon_irq_kms_pflip_irq_put(rdev, crtc); | |
122 | } | |
123 | ||
124 | u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) | |
125 | { | |
126 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
127 | u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); | |
f6496479 | 128 | int i; |
6f34be50 AD |
129 | |
130 | /* Lock the graphics update lock */ | |
131 | tmp |= AVIVO_D1GRPH_UPDATE_LOCK; | |
132 | WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); | |
133 | ||
134 | /* update the scanout addresses */ | |
135 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | |
136 | (u32)crtc_base); | |
137 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | |
138 | (u32)crtc_base); | |
139 | ||
140 | /* Wait for update_pending to go high. */ | |
f6496479 AD |
141 | for (i = 0; i < rdev->usec_timeout; i++) { |
142 | if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) | |
143 | break; | |
144 | udelay(1); | |
145 | } | |
6f34be50 AD |
146 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
147 | ||
148 | /* Unlock the lock, so double-buffering can take place inside vblank */ | |
149 | tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; | |
150 | WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); | |
151 | ||
152 | /* Return current update_pending status: */ | |
153 | return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; | |
154 | } | |
155 | ||
134b480f AD |
156 | void avivo_program_fmt(struct drm_encoder *encoder) |
157 | { | |
158 | struct drm_device *dev = encoder->dev; | |
159 | struct radeon_device *rdev = dev->dev_private; | |
160 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
161 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | |
162 | int bpc = 0; | |
163 | u32 tmp = 0; | |
6214bb74 | 164 | enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; |
134b480f | 165 | |
6214bb74 AD |
166 | if (connector) { |
167 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
134b480f | 168 | bpc = radeon_get_monitor_bpc(connector); |
6214bb74 AD |
169 | dither = radeon_connector->dither; |
170 | } | |
134b480f AD |
171 | |
172 | /* LVDS FMT is set up by atom */ | |
173 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) | |
174 | return; | |
175 | ||
176 | if (bpc == 0) | |
177 | return; | |
178 | ||
179 | switch (bpc) { | |
180 | case 6: | |
6214bb74 | 181 | if (dither == RADEON_FMT_DITHER_ENABLE) |
134b480f AD |
182 | /* XXX sort out optimal dither settings */ |
183 | tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; | |
184 | else | |
185 | tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN; | |
186 | break; | |
187 | case 8: | |
6214bb74 | 188 | if (dither == RADEON_FMT_DITHER_ENABLE) |
134b480f AD |
189 | /* XXX sort out optimal dither settings */ |
190 | tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN | | |
191 | AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH); | |
192 | else | |
193 | tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN | | |
194 | AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH); | |
195 | break; | |
196 | case 10: | |
197 | default: | |
198 | /* not needed */ | |
199 | break; | |
200 | } | |
201 | ||
202 | switch (radeon_encoder->encoder_id) { | |
203 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
204 | WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp); | |
205 | break; | |
206 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
207 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp); | |
208 | break; | |
209 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
210 | WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp); | |
211 | break; | |
212 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
213 | WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp); | |
214 | break; | |
215 | default: | |
216 | break; | |
217 | } | |
218 | } | |
219 | ||
49e02b73 AD |
220 | void rs600_pm_misc(struct radeon_device *rdev) |
221 | { | |
49e02b73 AD |
222 | int requested_index = rdev->pm.requested_power_state_index; |
223 | struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; | |
224 | struct radeon_voltage *voltage = &ps->clock_info[0].voltage; | |
225 | u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; | |
536fcd51 | 226 | u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; |
49e02b73 AD |
227 | |
228 | if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { | |
229 | if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { | |
230 | tmp = RREG32(voltage->gpio.reg); | |
231 | if (voltage->active_high) | |
232 | tmp |= voltage->gpio.mask; | |
233 | else | |
234 | tmp &= ~(voltage->gpio.mask); | |
235 | WREG32(voltage->gpio.reg, tmp); | |
236 | if (voltage->delay) | |
237 | udelay(voltage->delay); | |
238 | } else { | |
239 | tmp = RREG32(voltage->gpio.reg); | |
240 | if (voltage->active_high) | |
241 | tmp &= ~voltage->gpio.mask; | |
242 | else | |
243 | tmp |= voltage->gpio.mask; | |
244 | WREG32(voltage->gpio.reg, tmp); | |
245 | if (voltage->delay) | |
246 | udelay(voltage->delay); | |
247 | } | |
7ac9aa5a | 248 | } else if (voltage->type == VOLTAGE_VDDC) |
8a83ec5e | 249 | radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); |
49e02b73 AD |
250 | |
251 | dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); | |
252 | dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); | |
253 | dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); | |
254 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { | |
255 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { | |
256 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); | |
257 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); | |
258 | } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { | |
259 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); | |
260 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); | |
261 | } | |
262 | } else { | |
263 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); | |
264 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); | |
265 | } | |
266 | WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); | |
267 | ||
268 | dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); | |
269 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { | |
270 | dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; | |
271 | if (voltage->delay) { | |
272 | dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; | |
273 | dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); | |
274 | } else | |
275 | dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; | |
276 | } else | |
277 | dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; | |
278 | WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); | |
279 | ||
280 | hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); | |
281 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) | |
282 | hdp_dyn_cntl &= ~HDP_FORCEON; | |
283 | else | |
284 | hdp_dyn_cntl |= HDP_FORCEON; | |
285 | WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); | |
536fcd51 AD |
286 | #if 0 |
287 | /* mc_host_dyn seems to cause hangs from time to time */ | |
49e02b73 AD |
288 | mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); |
289 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) | |
290 | mc_host_dyn_cntl &= ~MC_HOST_FORCEON; | |
291 | else | |
292 | mc_host_dyn_cntl |= MC_HOST_FORCEON; | |
293 | WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); | |
536fcd51 AD |
294 | #endif |
295 | dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); | |
296 | if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) | |
297 | dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; | |
298 | else | |
299 | dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; | |
300 | WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); | |
49e02b73 AD |
301 | |
302 | /* set pcie lanes */ | |
303 | if ((rdev->flags & RADEON_IS_PCIE) && | |
304 | !(rdev->flags & RADEON_IS_IGP) && | |
798bcf73 | 305 | rdev->asic->pm.set_pcie_lanes && |
49e02b73 AD |
306 | (ps->pcie_lanes != |
307 | rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { | |
308 | radeon_set_pcie_lanes(rdev, | |
309 | ps->pcie_lanes); | |
ce8a3eb2 | 310 | DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); |
49e02b73 | 311 | } |
49e02b73 AD |
312 | } |
313 | ||
314 | void rs600_pm_prepare(struct radeon_device *rdev) | |
315 | { | |
316 | struct drm_device *ddev = rdev->ddev; | |
317 | struct drm_crtc *crtc; | |
318 | struct radeon_crtc *radeon_crtc; | |
319 | u32 tmp; | |
320 | ||
321 | /* disable any active CRTCs */ | |
322 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { | |
323 | radeon_crtc = to_radeon_crtc(crtc); | |
324 | if (radeon_crtc->enabled) { | |
325 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); | |
326 | tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; | |
327 | WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); | |
328 | } | |
329 | } | |
330 | } | |
331 | ||
332 | void rs600_pm_finish(struct radeon_device *rdev) | |
333 | { | |
334 | struct drm_device *ddev = rdev->ddev; | |
335 | struct drm_crtc *crtc; | |
336 | struct radeon_crtc *radeon_crtc; | |
337 | u32 tmp; | |
338 | ||
339 | /* enable any active CRTCs */ | |
340 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { | |
341 | radeon_crtc = to_radeon_crtc(crtc); | |
342 | if (radeon_crtc->enabled) { | |
343 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); | |
344 | tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; | |
345 | WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); | |
346 | } | |
347 | } | |
348 | } | |
349 | ||
dcfdd408 AD |
350 | /* hpd for digital panel detect/disconnect */ |
351 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) | |
352 | { | |
353 | u32 tmp; | |
354 | bool connected = false; | |
355 | ||
356 | switch (hpd) { | |
357 | case RADEON_HPD_1: | |
358 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); | |
359 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) | |
360 | connected = true; | |
361 | break; | |
362 | case RADEON_HPD_2: | |
363 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); | |
364 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) | |
365 | connected = true; | |
366 | break; | |
367 | default: | |
368 | break; | |
369 | } | |
370 | return connected; | |
371 | } | |
372 | ||
373 | void rs600_hpd_set_polarity(struct radeon_device *rdev, | |
374 | enum radeon_hpd_id hpd) | |
375 | { | |
376 | u32 tmp; | |
377 | bool connected = rs600_hpd_sense(rdev, hpd); | |
378 | ||
379 | switch (hpd) { | |
380 | case RADEON_HPD_1: | |
381 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
382 | if (connected) | |
383 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); | |
384 | else | |
385 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); | |
386 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
387 | break; | |
388 | case RADEON_HPD_2: | |
389 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
390 | if (connected) | |
391 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); | |
392 | else | |
393 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); | |
394 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
395 | break; | |
396 | default: | |
397 | break; | |
398 | } | |
399 | } | |
400 | ||
401 | void rs600_hpd_init(struct radeon_device *rdev) | |
402 | { | |
403 | struct drm_device *dev = rdev->ddev; | |
404 | struct drm_connector *connector; | |
fb98257a | 405 | unsigned enable = 0; |
dcfdd408 AD |
406 | |
407 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
408 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
409 | switch (radeon_connector->hpd.hpd) { | |
410 | case RADEON_HPD_1: | |
411 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, | |
412 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); | |
dcfdd408 AD |
413 | break; |
414 | case RADEON_HPD_2: | |
415 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, | |
416 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); | |
dcfdd408 AD |
417 | break; |
418 | default: | |
419 | break; | |
420 | } | |
fb98257a | 421 | enable |= 1 << radeon_connector->hpd.hpd; |
64912e99 | 422 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
dcfdd408 | 423 | } |
fb98257a | 424 | radeon_irq_kms_enable_hpd(rdev, enable); |
dcfdd408 AD |
425 | } |
426 | ||
427 | void rs600_hpd_fini(struct radeon_device *rdev) | |
428 | { | |
429 | struct drm_device *dev = rdev->ddev; | |
430 | struct drm_connector *connector; | |
fb98257a | 431 | unsigned disable = 0; |
dcfdd408 AD |
432 | |
433 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
434 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
435 | switch (radeon_connector->hpd.hpd) { | |
436 | case RADEON_HPD_1: | |
437 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, | |
438 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); | |
dcfdd408 AD |
439 | break; |
440 | case RADEON_HPD_2: | |
441 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, | |
442 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); | |
dcfdd408 AD |
443 | break; |
444 | default: | |
445 | break; | |
446 | } | |
fb98257a | 447 | disable |= 1 << radeon_connector->hpd.hpd; |
dcfdd408 | 448 | } |
fb98257a | 449 | radeon_irq_kms_disable_hpd(rdev, disable); |
dcfdd408 AD |
450 | } |
451 | ||
90aca4d2 JG |
452 | int rs600_asic_reset(struct radeon_device *rdev) |
453 | { | |
90aca4d2 | 454 | struct rv515_mc_save save; |
25b2ec5b AD |
455 | u32 status, tmp; |
456 | int ret = 0; | |
90aca4d2 | 457 | |
90aca4d2 JG |
458 | status = RREG32(R_000E40_RBBM_STATUS); |
459 | if (!G_000E40_GUI_ACTIVE(status)) { | |
460 | return 0; | |
461 | } | |
25b2ec5b AD |
462 | /* Stops all mc clients */ |
463 | rv515_mc_stop(rdev, &save); | |
90aca4d2 JG |
464 | status = RREG32(R_000E40_RBBM_STATUS); |
465 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
466 | /* stop CP */ | |
467 | WREG32(RADEON_CP_CSQ_CNTL, 0); | |
468 | tmp = RREG32(RADEON_CP_RB_CNTL); | |
469 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); | |
470 | WREG32(RADEON_CP_RB_RPTR_WR, 0); | |
471 | WREG32(RADEON_CP_RB_WPTR, 0); | |
472 | WREG32(RADEON_CP_RB_CNTL, tmp); | |
473 | pci_save_state(rdev->pdev); | |
474 | /* disable bus mastering */ | |
642ce525 MD |
475 | pci_clear_master(rdev->pdev); |
476 | mdelay(1); | |
90aca4d2 JG |
477 | /* reset GA+VAP */ |
478 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | | |
479 | S_0000F0_SOFT_RESET_GA(1)); | |
480 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
481 | mdelay(500); | |
482 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
483 | mdelay(1); | |
484 | status = RREG32(R_000E40_RBBM_STATUS); | |
485 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
486 | /* reset CP */ | |
487 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); | |
488 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
489 | mdelay(500); | |
490 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
491 | mdelay(1); | |
492 | status = RREG32(R_000E40_RBBM_STATUS); | |
493 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
494 | /* reset MC */ | |
495 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); | |
496 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
497 | mdelay(500); | |
498 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
499 | mdelay(1); | |
500 | status = RREG32(R_000E40_RBBM_STATUS); | |
501 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
502 | /* restore PCI & busmastering */ | |
503 | pci_restore_state(rdev->pdev); | |
504 | /* Check if GPU is idle */ | |
505 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { | |
506 | dev_err(rdev->dev, "failed to reset GPU\n"); | |
25b2ec5b AD |
507 | ret = -1; |
508 | } else | |
509 | dev_info(rdev->dev, "GPU reset succeed\n"); | |
90aca4d2 | 510 | rv515_mc_resume(rdev, &save); |
25b2ec5b | 511 | return ret; |
90aca4d2 JG |
512 | } |
513 | ||
771fe6b9 JG |
514 | /* |
515 | * GART. | |
516 | */ | |
517 | void rs600_gart_tlb_flush(struct radeon_device *rdev) | |
518 | { | |
519 | uint32_t tmp; | |
520 | ||
c010f800 JG |
521 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
522 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; | |
523 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); | |
771fe6b9 | 524 | |
c010f800 | 525 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
30f69f3f | 526 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); |
c010f800 | 527 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
771fe6b9 | 528 | |
c010f800 JG |
529 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
530 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; | |
531 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); | |
532 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); | |
771fe6b9 JG |
533 | } |
534 | ||
1109ca09 | 535 | static int rs600_gart_init(struct radeon_device *rdev) |
771fe6b9 | 536 | { |
771fe6b9 JG |
537 | int r; |
538 | ||
c9a1be96 | 539 | if (rdev->gart.robj) { |
fce7d61b | 540 | WARN(1, "RS600 GART already initialized\n"); |
4aac0473 JG |
541 | return 0; |
542 | } | |
771fe6b9 JG |
543 | /* Initialize common gart structure */ |
544 | r = radeon_gart_init(rdev); | |
545 | if (r) { | |
546 | return r; | |
547 | } | |
548 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; | |
4aac0473 JG |
549 | return radeon_gart_table_vram_alloc(rdev); |
550 | } | |
551 | ||
e22e6d20 | 552 | static int rs600_gart_enable(struct radeon_device *rdev) |
4aac0473 | 553 | { |
c010f800 | 554 | u32 tmp; |
4aac0473 JG |
555 | int r, i; |
556 | ||
c9a1be96 | 557 | if (rdev->gart.robj == NULL) { |
4aac0473 JG |
558 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
559 | return -EINVAL; | |
771fe6b9 | 560 | } |
4aac0473 JG |
561 | r = radeon_gart_table_vram_pin(rdev); |
562 | if (r) | |
563 | return r; | |
82568565 | 564 | radeon_gart_restore(rdev); |
c010f800 | 565 | /* Enable bus master */ |
e22e6d20 AD |
566 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
567 | WREG32(RADEON_BUS_CNTL, tmp); | |
771fe6b9 | 568 | /* FIXME: setup default page */ |
c010f800 | 569 | WREG32_MC(R_000100_MC_PT0_CNTL, |
4f15d24a AD |
570 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
571 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); | |
572 | ||
771fe6b9 | 573 | for (i = 0; i < 19; i++) { |
c010f800 | 574 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
4f15d24a AD |
575 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
576 | S_00016C_SYSTEM_ACCESS_MODE_MASK( | |
577 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | | |
578 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( | |
579 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | | |
580 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | | |
581 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | | |
582 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); | |
771fe6b9 | 583 | } |
771fe6b9 | 584 | /* enable first context */ |
c010f800 | 585 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
4f15d24a AD |
586 | S_000102_ENABLE_PAGE_TABLE(1) | |
587 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); | |
588 | ||
771fe6b9 | 589 | /* disable all other contexts */ |
4f15d24a | 590 | for (i = 1; i < 8; i++) |
c010f800 | 591 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
771fe6b9 JG |
592 | |
593 | /* setup the page table */ | |
c010f800 | 594 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
4f15d24a AD |
595 | rdev->gart.table_addr); |
596 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); | |
597 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); | |
c010f800 | 598 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
771fe6b9 | 599 | |
4f15d24a AD |
600 | /* System context maps to VRAM space */ |
601 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); | |
602 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); | |
603 | ||
771fe6b9 | 604 | /* enable page tables */ |
c010f800 JG |
605 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
606 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); | |
607 | tmp = RREG32_MC(R_000009_MC_CNTL1); | |
608 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); | |
771fe6b9 | 609 | rs600_gart_tlb_flush(rdev); |
fcf4de5a TV |
610 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
611 | (unsigned)(rdev->mc.gtt_size >> 20), | |
612 | (unsigned long long)rdev->gart.table_addr); | |
771fe6b9 JG |
613 | rdev->gart.ready = true; |
614 | return 0; | |
615 | } | |
616 | ||
1109ca09 | 617 | static void rs600_gart_disable(struct radeon_device *rdev) |
771fe6b9 | 618 | { |
4c788679 | 619 | u32 tmp; |
771fe6b9 JG |
620 | |
621 | /* FIXME: disable out of gart access */ | |
c010f800 JG |
622 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
623 | tmp = RREG32_MC(R_000009_MC_CNTL1); | |
624 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); | |
c9a1be96 | 625 | radeon_gart_table_vram_unpin(rdev); |
4aac0473 JG |
626 | } |
627 | ||
1109ca09 | 628 | static void rs600_gart_fini(struct radeon_device *rdev) |
4aac0473 | 629 | { |
f9274562 | 630 | radeon_gart_fini(rdev); |
4aac0473 JG |
631 | rs600_gart_disable(rdev); |
632 | radeon_gart_table_vram_free(rdev); | |
771fe6b9 JG |
633 | } |
634 | ||
635 | #define R600_PTE_VALID (1 << 0) | |
636 | #define R600_PTE_SYSTEM (1 << 1) | |
637 | #define R600_PTE_SNOOPED (1 << 2) | |
638 | #define R600_PTE_READABLE (1 << 5) | |
639 | #define R600_PTE_WRITEABLE (1 << 6) | |
640 | ||
641 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |
642 | { | |
c9a1be96 | 643 | void __iomem *ptr = (void *)rdev->gart.ptr; |
771fe6b9 JG |
644 | |
645 | if (i < 0 || i > rdev->gart.num_gpu_pages) { | |
646 | return -EINVAL; | |
647 | } | |
648 | addr = addr & 0xFFFFFFFFFFFFF000ULL; | |
649 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; | |
650 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; | |
a0533fbf | 651 | writeq(addr, ptr + (i * 8)); |
771fe6b9 JG |
652 | return 0; |
653 | } | |
654 | ||
7ed220d7 MD |
655 | int rs600_irq_set(struct radeon_device *rdev) |
656 | { | |
657 | uint32_t tmp = 0; | |
658 | uint32_t mode_int = 0; | |
dcfdd408 AD |
659 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
660 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); | |
661 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & | |
662 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); | |
f122c610 AD |
663 | u32 hdmi0; |
664 | if (ASIC_IS_DCE2(rdev)) | |
665 | hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & | |
666 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); | |
667 | else | |
668 | hdmi0 = 0; | |
7ed220d7 | 669 | |
003e69f9 | 670 | if (!rdev->irq.installed) { |
fce7d61b | 671 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
003e69f9 JG |
672 | WREG32(R_000040_GEN_INT_CNTL, 0); |
673 | return -EINVAL; | |
674 | } | |
736fc37f | 675 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
c010f800 | 676 | tmp |= S_000040_SW_INT_EN(1); |
7ed220d7 | 677 | } |
6f34be50 | 678 | if (rdev->irq.crtc_vblank_int[0] || |
736fc37f | 679 | atomic_read(&rdev->irq.pflip[0])) { |
c010f800 | 680 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
7ed220d7 | 681 | } |
6f34be50 | 682 | if (rdev->irq.crtc_vblank_int[1] || |
736fc37f | 683 | atomic_read(&rdev->irq.pflip[1])) { |
c010f800 | 684 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
7ed220d7 | 685 | } |
dcfdd408 AD |
686 | if (rdev->irq.hpd[0]) { |
687 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); | |
688 | } | |
689 | if (rdev->irq.hpd[1]) { | |
690 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); | |
691 | } | |
f122c610 AD |
692 | if (rdev->irq.afmt[0]) { |
693 | hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); | |
694 | } | |
c010f800 JG |
695 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
696 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); | |
dcfdd408 AD |
697 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
698 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); | |
f122c610 AD |
699 | if (ASIC_IS_DCE2(rdev)) |
700 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); | |
7ed220d7 MD |
701 | return 0; |
702 | } | |
703 | ||
6f34be50 | 704 | static inline u32 rs600_irq_ack(struct radeon_device *rdev) |
7ed220d7 | 705 | { |
01ceae8e | 706 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
2031f77c | 707 | uint32_t irq_mask = S_000044_SW_INT(1); |
dcfdd408 | 708 | u32 tmp; |
c010f800 | 709 | |
01ceae8e | 710 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
6f34be50 AD |
711 | rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
712 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { | |
c010f800 JG |
713 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
714 | S_006534_D1MODE_VBLANK_ACK(1)); | |
7ed220d7 | 715 | } |
6f34be50 | 716 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
c010f800 JG |
717 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
718 | S_006D34_D2MODE_VBLANK_ACK(1)); | |
7ed220d7 | 719 | } |
6f34be50 | 720 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
dcfdd408 AD |
721 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
722 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); | |
723 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
724 | } | |
6f34be50 | 725 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
dcfdd408 AD |
726 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
727 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); | |
728 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
729 | } | |
7ed220d7 | 730 | } else { |
6f34be50 | 731 | rdev->irq.stat_regs.r500.disp_int = 0; |
7ed220d7 MD |
732 | } |
733 | ||
f122c610 AD |
734 | if (ASIC_IS_DCE2(rdev)) { |
735 | rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & | |
736 | S_007404_HDMI0_AZ_FORMAT_WTRIG(1); | |
737 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { | |
738 | tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); | |
739 | tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); | |
740 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); | |
741 | } | |
742 | } else | |
743 | rdev->irq.stat_regs.r500.hdmi0_status = 0; | |
744 | ||
7ed220d7 | 745 | if (irqs) { |
01ceae8e | 746 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
7ed220d7 MD |
747 | } |
748 | return irqs & irq_mask; | |
749 | } | |
750 | ||
ac447df4 JG |
751 | void rs600_irq_disable(struct radeon_device *rdev) |
752 | { | |
f122c610 AD |
753 | u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
754 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); | |
755 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); | |
ac447df4 JG |
756 | WREG32(R_000040_GEN_INT_CNTL, 0); |
757 | WREG32(R_006540_DxMODE_INT_MASK, 0); | |
758 | /* Wait and acknowledge irq */ | |
759 | mdelay(1); | |
6f34be50 | 760 | rs600_irq_ack(rdev); |
ac447df4 JG |
761 | } |
762 | ||
7ed220d7 MD |
763 | int rs600_irq_process(struct radeon_device *rdev) |
764 | { | |
6f34be50 | 765 | u32 status, msi_rearm; |
d4877cf2 | 766 | bool queue_hotplug = false; |
f122c610 | 767 | bool queue_hdmi = false; |
7ed220d7 | 768 | |
6f34be50 | 769 | status = rs600_irq_ack(rdev); |
f122c610 AD |
770 | if (!status && |
771 | !rdev->irq.stat_regs.r500.disp_int && | |
772 | !rdev->irq.stat_regs.r500.hdmi0_status) { | |
7ed220d7 MD |
773 | return IRQ_NONE; |
774 | } | |
f122c610 AD |
775 | while (status || |
776 | rdev->irq.stat_regs.r500.disp_int || | |
777 | rdev->irq.stat_regs.r500.hdmi0_status) { | |
7ed220d7 | 778 | /* SW interrupt */ |
6f34be50 | 779 | if (G_000044_SW_INT(status)) { |
7465280c | 780 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
6f34be50 | 781 | } |
7ed220d7 | 782 | /* Vertical blank interrupts */ |
6f34be50 | 783 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
6f34be50 AD |
784 | if (rdev->irq.crtc_vblank_int[0]) { |
785 | drm_handle_vblank(rdev->ddev, 0); | |
786 | rdev->pm.vblank_sync = true; | |
787 | wake_up(&rdev->irq.vblank_queue); | |
788 | } | |
736fc37f | 789 | if (atomic_read(&rdev->irq.pflip[0])) |
3e4ea742 | 790 | radeon_crtc_handle_flip(rdev, 0); |
c913e23a | 791 | } |
6f34be50 | 792 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
6f34be50 AD |
793 | if (rdev->irq.crtc_vblank_int[1]) { |
794 | drm_handle_vblank(rdev->ddev, 1); | |
795 | rdev->pm.vblank_sync = true; | |
796 | wake_up(&rdev->irq.vblank_queue); | |
797 | } | |
736fc37f | 798 | if (atomic_read(&rdev->irq.pflip[1])) |
3e4ea742 | 799 | radeon_crtc_handle_flip(rdev, 1); |
c913e23a | 800 | } |
6f34be50 | 801 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
d4877cf2 AD |
802 | queue_hotplug = true; |
803 | DRM_DEBUG("HPD1\n"); | |
dcfdd408 | 804 | } |
6f34be50 | 805 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
d4877cf2 AD |
806 | queue_hotplug = true; |
807 | DRM_DEBUG("HPD2\n"); | |
dcfdd408 | 808 | } |
f122c610 AD |
809 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
810 | queue_hdmi = true; | |
811 | DRM_DEBUG("HDMI0\n"); | |
812 | } | |
6f34be50 | 813 | status = rs600_irq_ack(rdev); |
7ed220d7 | 814 | } |
d4877cf2 | 815 | if (queue_hotplug) |
32c87fca | 816 | schedule_work(&rdev->hotplug_work); |
f122c610 AD |
817 | if (queue_hdmi) |
818 | schedule_work(&rdev->audio_work); | |
3e5cb98d AD |
819 | if (rdev->msi_enabled) { |
820 | switch (rdev->family) { | |
821 | case CHIP_RS600: | |
822 | case CHIP_RS690: | |
823 | case CHIP_RS740: | |
824 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; | |
825 | WREG32(RADEON_BUS_CNTL, msi_rearm); | |
826 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); | |
827 | break; | |
828 | default: | |
b7f5b7de | 829 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
3e5cb98d AD |
830 | break; |
831 | } | |
832 | } | |
7ed220d7 MD |
833 | return IRQ_HANDLED; |
834 | } | |
835 | ||
836 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) | |
837 | { | |
838 | if (crtc == 0) | |
c010f800 | 839 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
7ed220d7 | 840 | else |
c010f800 | 841 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
7ed220d7 MD |
842 | } |
843 | ||
771fe6b9 JG |
844 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
845 | { | |
846 | unsigned i; | |
771fe6b9 JG |
847 | |
848 | for (i = 0; i < rdev->usec_timeout; i++) { | |
c010f800 | 849 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
771fe6b9 | 850 | return 0; |
c010f800 | 851 | udelay(1); |
771fe6b9 JG |
852 | } |
853 | return -1; | |
854 | } | |
855 | ||
1109ca09 | 856 | static void rs600_gpu_init(struct radeon_device *rdev) |
771fe6b9 | 857 | { |
771fe6b9 | 858 | r420_pipes_init(rdev); |
c010f800 JG |
859 | /* Wait for mc idle */ |
860 | if (rs600_mc_wait_for_idle(rdev)) | |
861 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
771fe6b9 JG |
862 | } |
863 | ||
1109ca09 | 864 | static void rs600_mc_init(struct radeon_device *rdev) |
771fe6b9 | 865 | { |
d594e46a JG |
866 | u64 base; |
867 | ||
01d73a69 JC |
868 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
869 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | |
771fe6b9 JG |
870 | rdev->mc.vram_is_ddr = true; |
871 | rdev->mc.vram_width = 128; | |
722f2943 AD |
872 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
873 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | |
51e5fcd3 | 874 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
d594e46a JG |
875 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
876 | base = RREG32_MC(R_000004_MC_FB_LOCATION); | |
877 | base = G_000004_MC_FB_START(base) << 16; | |
878 | radeon_vram_location(rdev, &rdev->mc, base); | |
8d369bb1 | 879 | rdev->mc.gtt_base_align = 0; |
d594e46a | 880 | radeon_gtt_location(rdev, &rdev->mc); |
f47299c5 | 881 | radeon_update_bandwidth_info(rdev); |
771fe6b9 JG |
882 | } |
883 | ||
c93bb85b JG |
884 | void rs600_bandwidth_update(struct radeon_device *rdev) |
885 | { | |
f46c0120 AD |
886 | struct drm_display_mode *mode0 = NULL; |
887 | struct drm_display_mode *mode1 = NULL; | |
888 | u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; | |
889 | /* FIXME: implement full support */ | |
890 | ||
891 | radeon_update_display_priority(rdev); | |
892 | ||
893 | if (rdev->mode_info.crtcs[0]->base.enabled) | |
894 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; | |
895 | if (rdev->mode_info.crtcs[1]->base.enabled) | |
896 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; | |
897 | ||
898 | rs690_line_buffer_adjust(rdev, mode0, mode1); | |
899 | ||
900 | if (rdev->disp_priority == 2) { | |
901 | d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); | |
902 | d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); | |
903 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); | |
904 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); | |
905 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | |
906 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | |
907 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); | |
908 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | |
909 | } | |
c93bb85b JG |
910 | } |
911 | ||
771fe6b9 JG |
912 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
913 | { | |
0a5b7b0b AD |
914 | unsigned long flags; |
915 | u32 r; | |
916 | ||
917 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); | |
c010f800 JG |
918 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
919 | S_000070_MC_IND_CITF_ARB0(1)); | |
0a5b7b0b AD |
920 | r = RREG32(R_000074_MC_IND_DATA); |
921 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); | |
922 | return r; | |
771fe6b9 JG |
923 | } |
924 | ||
925 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
926 | { | |
0a5b7b0b AD |
927 | unsigned long flags; |
928 | ||
929 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); | |
c010f800 JG |
930 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
931 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); | |
932 | WREG32(R_000074_MC_IND_DATA, v); | |
0a5b7b0b | 933 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
c010f800 JG |
934 | } |
935 | ||
1109ca09 | 936 | static void rs600_debugfs(struct radeon_device *rdev) |
c010f800 JG |
937 | { |
938 | if (r100_debugfs_rbbm_init(rdev)) | |
939 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); | |
771fe6b9 | 940 | } |
3f7dc91a | 941 | |
3bc68535 | 942 | void rs600_set_safe_registers(struct radeon_device *rdev) |
3f7dc91a DA |
943 | { |
944 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; | |
945 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); | |
3bc68535 JG |
946 | } |
947 | ||
c010f800 JG |
948 | static void rs600_mc_program(struct radeon_device *rdev) |
949 | { | |
950 | struct rv515_mc_save save; | |
951 | ||
952 | /* Stops all mc clients */ | |
953 | rv515_mc_stop(rdev, &save); | |
954 | ||
955 | /* Wait for mc idle */ | |
956 | if (rs600_mc_wait_for_idle(rdev)) | |
957 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
958 | ||
959 | /* FIXME: What does AGP means for such chipset ? */ | |
960 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); | |
961 | WREG32_MC(R_000006_AGP_BASE, 0); | |
962 | WREG32_MC(R_000007_AGP_BASE_2, 0); | |
963 | /* Program MC */ | |
964 | WREG32_MC(R_000004_MC_FB_LOCATION, | |
965 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | | |
966 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
967 | WREG32(R_000134_HDP_FB_LOCATION, | |
968 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); | |
969 | ||
970 | rv515_mc_resume(rdev, &save); | |
971 | } | |
972 | ||
973 | static int rs600_startup(struct radeon_device *rdev) | |
974 | { | |
975 | int r; | |
976 | ||
977 | rs600_mc_program(rdev); | |
978 | /* Resume clock */ | |
979 | rv515_clock_startup(rdev); | |
980 | /* Initialize GPU configuration (# pipes, ...) */ | |
981 | rs600_gpu_init(rdev); | |
982 | /* Initialize GART (initialize after TTM so we can allocate | |
983 | * memory through TTM but finalize after TTM) */ | |
984 | r = rs600_gart_enable(rdev); | |
985 | if (r) | |
986 | return r; | |
724c80e1 AD |
987 | |
988 | /* allocate wb buffer */ | |
989 | r = radeon_wb_init(rdev); | |
990 | if (r) | |
991 | return r; | |
992 | ||
30eb77f4 JG |
993 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
994 | if (r) { | |
995 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
996 | return r; | |
997 | } | |
998 | ||
c010f800 | 999 | /* Enable IRQ */ |
e49f3959 AH |
1000 | if (!rdev->irq.installed) { |
1001 | r = radeon_irq_kms_init(rdev); | |
1002 | if (r) | |
1003 | return r; | |
1004 | } | |
1005 | ||
c010f800 | 1006 | rs600_irq_set(rdev); |
cafe6609 | 1007 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
c010f800 JG |
1008 | /* 1M ring buffer */ |
1009 | r = r100_cp_init(rdev, 1024 * 1024); | |
1010 | if (r) { | |
ec4f2ac4 | 1011 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
c010f800 JG |
1012 | return r; |
1013 | } | |
b15ba512 | 1014 | |
2898c348 CK |
1015 | r = radeon_ib_pool_init(rdev); |
1016 | if (r) { | |
1017 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | |
b15ba512 | 1018 | return r; |
2898c348 | 1019 | } |
b15ba512 | 1020 | |
d4e30ef0 AD |
1021 | r = r600_audio_init(rdev); |
1022 | if (r) { | |
1023 | dev_err(rdev->dev, "failed initializing audio\n"); | |
1024 | return r; | |
1025 | } | |
1026 | ||
c010f800 JG |
1027 | return 0; |
1028 | } | |
1029 | ||
1030 | int rs600_resume(struct radeon_device *rdev) | |
1031 | { | |
6b7746e8 JG |
1032 | int r; |
1033 | ||
c010f800 JG |
1034 | /* Make sur GART are not working */ |
1035 | rs600_gart_disable(rdev); | |
1036 | /* Resume clock before doing reset */ | |
1037 | rv515_clock_startup(rdev); | |
1038 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 1039 | if (radeon_asic_reset(rdev)) { |
c010f800 JG |
1040 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
1041 | RREG32(R_000E40_RBBM_STATUS), | |
1042 | RREG32(R_0007C0_CP_STAT)); | |
1043 | } | |
1044 | /* post */ | |
1045 | atom_asic_init(rdev->mode_info.atom_context); | |
1046 | /* Resume clock after posting */ | |
1047 | rv515_clock_startup(rdev); | |
550e2d92 DA |
1048 | /* Initialize surface registers */ |
1049 | radeon_surface_init(rdev); | |
b15ba512 JG |
1050 | |
1051 | rdev->accel_working = true; | |
6b7746e8 JG |
1052 | r = rs600_startup(rdev); |
1053 | if (r) { | |
1054 | rdev->accel_working = false; | |
1055 | } | |
1056 | return r; | |
c010f800 JG |
1057 | } |
1058 | ||
1059 | int rs600_suspend(struct radeon_device *rdev) | |
1060 | { | |
6c7bccea | 1061 | radeon_pm_suspend(rdev); |
fe50ac78 | 1062 | r600_audio_fini(rdev); |
c010f800 | 1063 | r100_cp_disable(rdev); |
724c80e1 | 1064 | radeon_wb_disable(rdev); |
ac447df4 | 1065 | rs600_irq_disable(rdev); |
c010f800 JG |
1066 | rs600_gart_disable(rdev); |
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | void rs600_fini(struct radeon_device *rdev) | |
1071 | { | |
6c7bccea | 1072 | radeon_pm_fini(rdev); |
fe50ac78 | 1073 | r600_audio_fini(rdev); |
c010f800 | 1074 | r100_cp_fini(rdev); |
724c80e1 | 1075 | radeon_wb_fini(rdev); |
2898c348 | 1076 | radeon_ib_pool_fini(rdev); |
c010f800 JG |
1077 | radeon_gem_fini(rdev); |
1078 | rs600_gart_fini(rdev); | |
1079 | radeon_irq_kms_fini(rdev); | |
1080 | radeon_fence_driver_fini(rdev); | |
4c788679 | 1081 | radeon_bo_fini(rdev); |
c010f800 JG |
1082 | radeon_atombios_fini(rdev); |
1083 | kfree(rdev->bios); | |
1084 | rdev->bios = NULL; | |
1085 | } | |
1086 | ||
3bc68535 JG |
1087 | int rs600_init(struct radeon_device *rdev) |
1088 | { | |
c010f800 JG |
1089 | int r; |
1090 | ||
c010f800 JG |
1091 | /* Disable VGA */ |
1092 | rv515_vga_render_disable(rdev); | |
1093 | /* Initialize scratch registers */ | |
1094 | radeon_scratch_init(rdev); | |
1095 | /* Initialize surface registers */ | |
1096 | radeon_surface_init(rdev); | |
4c712e6c DA |
1097 | /* restore some register to sane defaults */ |
1098 | r100_restore_sanity(rdev); | |
c010f800 JG |
1099 | /* BIOS */ |
1100 | if (!radeon_get_bios(rdev)) { | |
1101 | if (ASIC_IS_AVIVO(rdev)) | |
1102 | return -EINVAL; | |
1103 | } | |
1104 | if (rdev->is_atom_bios) { | |
1105 | r = radeon_atombios_init(rdev); | |
1106 | if (r) | |
1107 | return r; | |
1108 | } else { | |
1109 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); | |
1110 | return -EINVAL; | |
1111 | } | |
1112 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 1113 | if (radeon_asic_reset(rdev)) { |
c010f800 JG |
1114 | dev_warn(rdev->dev, |
1115 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
1116 | RREG32(R_000E40_RBBM_STATUS), | |
1117 | RREG32(R_0007C0_CP_STAT)); | |
1118 | } | |
1119 | /* check if cards are posted or not */ | |
72542d77 DA |
1120 | if (radeon_boot_test_post_card(rdev) == false) |
1121 | return -EINVAL; | |
1122 | ||
c010f800 JG |
1123 | /* Initialize clocks */ |
1124 | radeon_get_clock_info(rdev->ddev); | |
d594e46a JG |
1125 | /* initialize memory controller */ |
1126 | rs600_mc_init(rdev); | |
c010f800 JG |
1127 | rs600_debugfs(rdev); |
1128 | /* Fence driver */ | |
30eb77f4 | 1129 | r = radeon_fence_driver_init(rdev); |
c010f800 JG |
1130 | if (r) |
1131 | return r; | |
1132 | /* Memory manager */ | |
4c788679 | 1133 | r = radeon_bo_init(rdev); |
c010f800 JG |
1134 | if (r) |
1135 | return r; | |
1136 | r = rs600_gart_init(rdev); | |
1137 | if (r) | |
1138 | return r; | |
1139 | rs600_set_safe_registers(rdev); | |
b15ba512 | 1140 | |
6c7bccea AD |
1141 | /* Initialize power management */ |
1142 | radeon_pm_init(rdev); | |
1143 | ||
c010f800 JG |
1144 | rdev->accel_working = true; |
1145 | r = rs600_startup(rdev); | |
1146 | if (r) { | |
1147 | /* Somethings want wront with the accel init stop accel */ | |
1148 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
c010f800 | 1149 | r100_cp_fini(rdev); |
724c80e1 | 1150 | radeon_wb_fini(rdev); |
2898c348 | 1151 | radeon_ib_pool_fini(rdev); |
c010f800 JG |
1152 | rs600_gart_fini(rdev); |
1153 | radeon_irq_kms_fini(rdev); | |
1154 | rdev->accel_working = false; | |
1155 | } | |
3f7dc91a DA |
1156 | return 0; |
1157 | } |