projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-3.10/drivers' of git://git.kernel.dk/linux-block
[linux-2.6-block.git] / drivers / gpu / drm / radeon / rs600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
c010f800
JG		 28/* RS600 / Radeon X1250/X1270 integrated GPU
29 *
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
37 */
760285e7 38#include <drm/drmP.h>
771fe6b9 39#include "radeon.h"
e6990375 40#include "radeon_asic.h"
c010f800
JG		 41#include "atom.h"
42#include "rs600d.h"
771fe6b9 43
3f7dc91a
DA		 44#include "rs600_reg_safe.h"
45
1109ca09 46static void rs600_gpu_init(struct radeon_device *rdev);
771fe6b9 47int rs600_mc_wait_for_idle(struct radeon_device *rdev);
771fe6b9 48
75104fa4
AD		 49static const u32 crtc_offsets[2] =
50{
51 0,
52 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
53};
54
bea5497b
AD		 55static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
56{
57 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
58 return true;
59 else
60 return false;
61}
62
63static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
64{
65 u32 pos1, pos2;
66
67 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
68 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
69
70 if (pos1 != pos2)
71 return true;
72 else
73 return false;
74}
75
76/**
77 * avivo_wait_for_vblank - vblank wait asic callback.
78 *
79 * @rdev: radeon_device pointer
80 * @crtc: crtc to wait for vblank on
81 *
82 * Wait for vblank on the requested crtc (r5xx-r7xx).
83 */
3ae19b75
AD		 84void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
85{
bea5497b 86 unsigned i = 0;
3ae19b75 87
75104fa4
AD		 88 if (crtc >= rdev->num_crtc)
89 return;
90
bea5497b
AD		 91 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
92 return;
93
94 /* depending on when we hit vblank, we may be close to active; if so,
95 * wait for another frame.
96 */
97 while (avivo_is_in_vblank(rdev, crtc)) {
98 if (i++ % 100 == 0) {
99 if (!avivo_is_counter_moving(rdev, crtc))
3ae19b75 100 break;
3ae19b75 101 }
bea5497b
AD		 102 }
103
104 while (!avivo_is_in_vblank(rdev, crtc)) {
105 if (i++ % 100 == 0) {
106 if (!avivo_is_counter_moving(rdev, crtc))
3ae19b75 107 break;
3ae19b75
AD		 108 }
109 }
110}
111
6f34be50
AD		 112void rs600_pre_page_flip(struct radeon_device *rdev, int crtc)
113{
6f34be50
AD		 114 /* enable the pflip int */
115 radeon_irq_kms_pflip_irq_get(rdev, crtc);
116}
117
118void rs600_post_page_flip(struct radeon_device *rdev, int crtc)
119{
120 /* disable the pflip int */
121 radeon_irq_kms_pflip_irq_put(rdev, crtc);
122}
123
124u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
125{
126 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
127 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
f6496479 128 int i;
6f34be50
AD		 129
130 /* Lock the graphics update lock */
131 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
132 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
133
134 /* update the scanout addresses */
135 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
136 (u32)crtc_base);
137 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
138 (u32)crtc_base);
139
140 /* Wait for update_pending to go high. */
f6496479
AD		 141 for (i = 0; i < rdev->usec_timeout; i++) {
142 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
143 break;
144 udelay(1);
145 }
6f34be50
AD		 146 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
147
148 /* Unlock the lock, so double-buffering can take place inside vblank */
149 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
150 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
151
152 /* Return current update_pending status: */
153 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
154}
155
49e02b73
AD		 156void rs600_pm_misc(struct radeon_device *rdev)
157{
49e02b73
AD		 158 int requested_index = rdev->pm.requested_power_state_index;
159 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
160 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
161 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
536fcd51 162 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
49e02b73
AD		 163
164 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
165 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
166 tmp = RREG32(voltage->gpio.reg);
167 if (voltage->active_high)
168 tmp |= voltage->gpio.mask;
169 else
170 tmp &= ~(voltage->gpio.mask);
171 WREG32(voltage->gpio.reg, tmp);
172 if (voltage->delay)
173 udelay(voltage->delay);
174 } else {
175 tmp = RREG32(voltage->gpio.reg);
176 if (voltage->active_high)
177 tmp &= ~voltage->gpio.mask;
178 else
179 tmp |= voltage->gpio.mask;
180 WREG32(voltage->gpio.reg, tmp);
181 if (voltage->delay)
182 udelay(voltage->delay);
183 }
7ac9aa5a 184 } else if (voltage->type == VOLTAGE_VDDC)
8a83ec5e 185 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
49e02b73
AD		 186
187 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
188 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
189 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
190 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
191 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
192 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
193 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
194 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
195 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
196 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
197 }
198 } else {
199 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
200 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
201 }
202 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
203
204 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
205 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
206 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
207 if (voltage->delay) {
208 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
209 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
210 } else
211 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
212 } else
213 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
214 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
215
216 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
217 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
218 hdp_dyn_cntl &= ~HDP_FORCEON;
219 else
220 hdp_dyn_cntl |= HDP_FORCEON;
221 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
536fcd51
AD		 222#if 0
223 /* mc_host_dyn seems to cause hangs from time to time */
49e02b73
AD		 224 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
225 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
226 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
227 else
228 mc_host_dyn_cntl |= MC_HOST_FORCEON;
229 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
536fcd51
AD		 230#endif
231 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
232 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
233 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
234 else
235 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
236 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
49e02b73
AD		 237
238 /* set pcie lanes */
239 if ((rdev->flags & RADEON_IS_PCIE) &&
240 !(rdev->flags & RADEON_IS_IGP) &&
798bcf73 241 rdev->asic->pm.set_pcie_lanes &&
49e02b73
AD		 242 (ps->pcie_lanes !=
243 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
244 radeon_set_pcie_lanes(rdev,
245 ps->pcie_lanes);
ce8a3eb2 246 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 247 }
49e02b73
AD		 248}
249
250void rs600_pm_prepare(struct radeon_device *rdev)
251{
252 struct drm_device *ddev = rdev->ddev;
253 struct drm_crtc *crtc;
254 struct radeon_crtc *radeon_crtc;
255 u32 tmp;
256
257 /* disable any active CRTCs */
258 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
259 radeon_crtc = to_radeon_crtc(crtc);
260 if (radeon_crtc->enabled) {
261 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
262 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
263 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
264 }
265 }
266}
267
268void rs600_pm_finish(struct radeon_device *rdev)
269{
270 struct drm_device *ddev = rdev->ddev;
271 struct drm_crtc *crtc;
272 struct radeon_crtc *radeon_crtc;
273 u32 tmp;
274
275 /* enable any active CRTCs */
276 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
277 radeon_crtc = to_radeon_crtc(crtc);
278 if (radeon_crtc->enabled) {
279 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
280 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
281 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
282 }
283 }
284}
285
dcfdd408
AD		 286/* hpd for digital panel detect/disconnect */
287bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
288{
289 u32 tmp;
290 bool connected = false;
291
292 switch (hpd) {
293 case RADEON_HPD_1:
294 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
295 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
296 connected = true;
297 break;
298 case RADEON_HPD_2:
299 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
300 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
301 connected = true;
302 break;
303 default:
304 break;
305 }
306 return connected;
307}
308
309void rs600_hpd_set_polarity(struct radeon_device *rdev,
310 enum radeon_hpd_id hpd)
311{
312 u32 tmp;
313 bool connected = rs600_hpd_sense(rdev, hpd);
314
315 switch (hpd) {
316 case RADEON_HPD_1:
317 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
318 if (connected)
319 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
320 else
321 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
322 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
323 break;
324 case RADEON_HPD_2:
325 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
326 if (connected)
327 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
328 else
329 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
330 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
331 break;
332 default:
333 break;
334 }
335}
336
337void rs600_hpd_init(struct radeon_device *rdev)
338{
339 struct drm_device *dev = rdev->ddev;
340 struct drm_connector *connector;
fb98257a 341 unsigned enable = 0;
dcfdd408
AD		 342
343 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
344 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
345 switch (radeon_connector->hpd.hpd) {
346 case RADEON_HPD_1:
347 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
348 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
dcfdd408
AD		 349 break;
350 case RADEON_HPD_2:
351 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
352 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
dcfdd408
AD		 353 break;
354 default:
355 break;
356 }
fb98257a 357 enable |= 1 << radeon_connector->hpd.hpd;
64912e99 358 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
dcfdd408 359 }
fb98257a 360 radeon_irq_kms_enable_hpd(rdev, enable);
dcfdd408
AD		 361}
362
363void rs600_hpd_fini(struct radeon_device *rdev)
364{
365 struct drm_device *dev = rdev->ddev;
366 struct drm_connector *connector;
fb98257a 367 unsigned disable = 0;
dcfdd408
AD		 368
369 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
370 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
371 switch (radeon_connector->hpd.hpd) {
372 case RADEON_HPD_1:
373 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
374 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
dcfdd408
AD		 375 break;
376 case RADEON_HPD_2:
377 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
378 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
dcfdd408
AD		 379 break;
380 default:
381 break;
382 }
fb98257a 383 disable |= 1 << radeon_connector->hpd.hpd;
dcfdd408 384 }
fb98257a 385 radeon_irq_kms_disable_hpd(rdev, disable);
dcfdd408
AD		 386}
387
90aca4d2
JG		 388int rs600_asic_reset(struct radeon_device *rdev)
389{
90aca4d2 390 struct rv515_mc_save save;
25b2ec5b
AD		 391 u32 status, tmp;
392 int ret = 0;
90aca4d2 393
90aca4d2
JG		 394 status = RREG32(R_000E40_RBBM_STATUS);
395 if (!G_000E40_GUI_ACTIVE(status)) {
396 return 0;
397 }
25b2ec5b
AD		 398 /* Stops all mc clients */
399 rv515_mc_stop(rdev, &save);
90aca4d2
JG		 400 status = RREG32(R_000E40_RBBM_STATUS);
401 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
402 /* stop CP */
403 WREG32(RADEON_CP_CSQ_CNTL, 0);
404 tmp = RREG32(RADEON_CP_RB_CNTL);
405 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
406 WREG32(RADEON_CP_RB_RPTR_WR, 0);
407 WREG32(RADEON_CP_RB_WPTR, 0);
408 WREG32(RADEON_CP_RB_CNTL, tmp);
409 pci_save_state(rdev->pdev);
410 /* disable bus mastering */
642ce525
MD		 411 pci_clear_master(rdev->pdev);
412 mdelay(1);
90aca4d2
JG		 413 /* reset GA+VAP */
414 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
415 S_0000F0_SOFT_RESET_GA(1));
416 RREG32(R_0000F0_RBBM_SOFT_RESET);
417 mdelay(500);
418 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
419 mdelay(1);
420 status = RREG32(R_000E40_RBBM_STATUS);
421 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
422 /* reset CP */
423 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
424 RREG32(R_0000F0_RBBM_SOFT_RESET);
425 mdelay(500);
426 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
427 mdelay(1);
428 status = RREG32(R_000E40_RBBM_STATUS);
429 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
430 /* reset MC */
431 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
432 RREG32(R_0000F0_RBBM_SOFT_RESET);
433 mdelay(500);
434 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
435 mdelay(1);
436 status = RREG32(R_000E40_RBBM_STATUS);
437 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
438 /* restore PCI & busmastering */
439 pci_restore_state(rdev->pdev);
440 /* Check if GPU is idle */
441 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
442 dev_err(rdev->dev, "failed to reset GPU\n");
25b2ec5b
AD		 443 ret = -1;
444 } else
445 dev_info(rdev->dev, "GPU reset succeed\n");
90aca4d2 446 rv515_mc_resume(rdev, &save);
25b2ec5b 447 return ret;
90aca4d2
JG		 448}
449
771fe6b9
JG		 450/*
451 * GART.
452 */
453void rs600_gart_tlb_flush(struct radeon_device *rdev)
454{
455 uint32_t tmp;
456
c010f800
JG		 457 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
458 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
459 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9 460
c010f800 461 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
30f69f3f 462 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
c010f800 463 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9 464
c010f800
JG		 465 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
466 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
467 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
468 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
771fe6b9
JG		 469}
470
1109ca09 471static int rs600_gart_init(struct radeon_device *rdev)
771fe6b9 472{
771fe6b9
JG		 473 int r;
474
c9a1be96 475 if (rdev->gart.robj) {
fce7d61b 476 WARN(1, "RS600 GART already initialized\n");
4aac0473
JG		 477 return 0;
478 }
771fe6b9
JG		 479 /* Initialize common gart structure */
480 r = radeon_gart_init(rdev);
481 if (r) {
482 return r;
483 }
484 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 485 return radeon_gart_table_vram_alloc(rdev);
486}
487
e22e6d20 488static int rs600_gart_enable(struct radeon_device *rdev)
4aac0473 489{
c010f800 490 u32 tmp;
4aac0473
JG		 491 int r, i;
492
c9a1be96 493 if (rdev->gart.robj == NULL) {
4aac0473
JG		 494 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
495 return -EINVAL;
771fe6b9 496 }
4aac0473
JG		 497 r = radeon_gart_table_vram_pin(rdev);
498 if (r)
499 return r;
82568565 500 radeon_gart_restore(rdev);
c010f800 501 /* Enable bus master */
e22e6d20
AD		 502 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
503 WREG32(RADEON_BUS_CNTL, tmp);
771fe6b9 504 /* FIXME: setup default page */
c010f800 505 WREG32_MC(R_000100_MC_PT0_CNTL,
4f15d24a
AD		 506 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
507 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
508
771fe6b9 509 for (i = 0; i < 19; i++) {
c010f800 510 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
4f15d24a
AD		 511 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
512 S_00016C_SYSTEM_ACCESS_MODE_MASK(
513 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
514 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
515 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
516 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
517 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
518 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
771fe6b9 519 }
771fe6b9 520 /* enable first context */
c010f800 521 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
4f15d24a
AD		 522 S_000102_ENABLE_PAGE_TABLE(1) |
523 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
524
771fe6b9 525 /* disable all other contexts */
4f15d24a 526 for (i = 1; i < 8; i++)
c010f800 527 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
771fe6b9
JG		 528
529 /* setup the page table */
c010f800 530 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
4f15d24a
AD		 531 rdev->gart.table_addr);
532 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
533 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
c010f800 534 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
771fe6b9 535
4f15d24a
AD		 536 /* System context maps to VRAM space */
537 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
538 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
539
771fe6b9 540 /* enable page tables */
c010f800
JG		 541 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
542 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
543 tmp = RREG32_MC(R_000009_MC_CNTL1);
544 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
771fe6b9 545 rs600_gart_tlb_flush(rdev);
fcf4de5a
TV		 546 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
547 (unsigned)(rdev->mc.gtt_size >> 20),
548 (unsigned long long)rdev->gart.table_addr);
771fe6b9
JG		 549 rdev->gart.ready = true;
550 return 0;
551}
552
1109ca09 553static void rs600_gart_disable(struct radeon_device *rdev)
771fe6b9 554{
4c788679 555 u32 tmp;
771fe6b9
JG		 556
557 /* FIXME: disable out of gart access */
c010f800
JG		 558 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
559 tmp = RREG32_MC(R_000009_MC_CNTL1);
560 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
c9a1be96 561 radeon_gart_table_vram_unpin(rdev);
4aac0473
JG		 562}
563
1109ca09 564static void rs600_gart_fini(struct radeon_device *rdev)
4aac0473 565{
f9274562 566 radeon_gart_fini(rdev);
4aac0473
JG		 567 rs600_gart_disable(rdev);
568 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 569}
570
571#define R600_PTE_VALID (1 << 0)
572#define R600_PTE_SYSTEM (1 << 1)
573#define R600_PTE_SNOOPED (1 << 2)
574#define R600_PTE_READABLE (1 << 5)
575#define R600_PTE_WRITEABLE (1 << 6)
576
577int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
578{
c9a1be96 579 void __iomem *ptr = (void *)rdev->gart.ptr;
771fe6b9
JG		 580
581 if (i < 0 || i > rdev->gart.num_gpu_pages) {
582 return -EINVAL;
583 }
584 addr = addr & 0xFFFFFFFFFFFFF000ULL;
585 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
586 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
a0533fbf 587 writeq(addr, ptr + (i * 8));
771fe6b9
JG		 588 return 0;
589}
590
7ed220d7
MD		 591int rs600_irq_set(struct radeon_device *rdev)
592{
593 uint32_t tmp = 0;
594 uint32_t mode_int = 0;
dcfdd408
AD		 595 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
596 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
597 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
598 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
f122c610
AD		 599 u32 hdmi0;
600 if (ASIC_IS_DCE2(rdev))
601 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
602 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
603 else
604 hdmi0 = 0;
7ed220d7 605
003e69f9 606 if (!rdev->irq.installed) {
fce7d61b 607 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 608 WREG32(R_000040_GEN_INT_CNTL, 0);
609 return -EINVAL;
610 }
736fc37f 611 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
c010f800 612 tmp |= S_000040_SW_INT_EN(1);
7ed220d7 613 }
6f34be50 614 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 615 atomic_read(&rdev->irq.pflip[0])) {
c010f800 616 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
7ed220d7 617 }
6f34be50 618 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 619 atomic_read(&rdev->irq.pflip[1])) {
c010f800 620 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
7ed220d7 621 }
dcfdd408
AD		 622 if (rdev->irq.hpd[0]) {
623 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
624 }
625 if (rdev->irq.hpd[1]) {
626 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
627 }
f122c610
AD		 628 if (rdev->irq.afmt[0]) {
629 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
630 }
c010f800
JG		 631 WREG32(R_000040_GEN_INT_CNTL, tmp);
632 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
dcfdd408
AD		 633 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
634 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
f122c610
AD		 635 if (ASIC_IS_DCE2(rdev))
636 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
7ed220d7
MD		 637 return 0;
638}
639
6f34be50 640static inline u32 rs600_irq_ack(struct radeon_device *rdev)
7ed220d7 641{
01ceae8e 642 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
2031f77c 643 uint32_t irq_mask = S_000044_SW_INT(1);
dcfdd408 644 u32 tmp;
c010f800 645
01ceae8e 646 if (G_000044_DISPLAY_INT_STAT(irqs)) {
6f34be50
AD		 647 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
648 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
c010f800
JG		 649 WREG32(R_006534_D1MODE_VBLANK_STATUS,
650 S_006534_D1MODE_VBLANK_ACK(1));
7ed220d7 651 }
6f34be50 652 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
c010f800
JG		 653 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
654 S_006D34_D2MODE_VBLANK_ACK(1));
7ed220d7 655 }
6f34be50 656 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
dcfdd408
AD		 657 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
658 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
659 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
660 }
6f34be50 661 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
dcfdd408
AD		 662 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
663 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
664 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
665 }
7ed220d7 666 } else {
6f34be50 667 rdev->irq.stat_regs.r500.disp_int = 0;
7ed220d7
MD		 668 }
669
f122c610
AD		 670 if (ASIC_IS_DCE2(rdev)) {
671 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
672 S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
673 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
674 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
675 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
676 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
677 }
678 } else
679 rdev->irq.stat_regs.r500.hdmi0_status = 0;
680
7ed220d7 681 if (irqs) {
01ceae8e 682 WREG32(R_000044_GEN_INT_STATUS, irqs);
7ed220d7
MD		 683 }
684 return irqs & irq_mask;
685}
686
ac447df4
JG		 687void rs600_irq_disable(struct radeon_device *rdev)
688{
f122c610
AD		 689 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
690 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
691 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
ac447df4
JG		 692 WREG32(R_000040_GEN_INT_CNTL, 0);
693 WREG32(R_006540_DxMODE_INT_MASK, 0);
694 /* Wait and acknowledge irq */
695 mdelay(1);
6f34be50 696 rs600_irq_ack(rdev);
ac447df4
JG		 697}
698
7ed220d7
MD		 699int rs600_irq_process(struct radeon_device *rdev)
700{
6f34be50 701 u32 status, msi_rearm;
d4877cf2 702 bool queue_hotplug = false;
f122c610 703 bool queue_hdmi = false;
7ed220d7 704
6f34be50 705 status = rs600_irq_ack(rdev);
f122c610
AD		 706 if (!status &&
707 !rdev->irq.stat_regs.r500.disp_int &&
708 !rdev->irq.stat_regs.r500.hdmi0_status) {
7ed220d7
MD		 709 return IRQ_NONE;
710 }
f122c610
AD		 711 while (status ||
712 rdev->irq.stat_regs.r500.disp_int ||
713 rdev->irq.stat_regs.r500.hdmi0_status) {
7ed220d7 714 /* SW interrupt */
6f34be50 715 if (G_000044_SW_INT(status)) {
7465280c 716 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
6f34be50 717 }
7ed220d7 718 /* Vertical blank interrupts */
6f34be50 719 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
6f34be50
AD		 720 if (rdev->irq.crtc_vblank_int[0]) {
721 drm_handle_vblank(rdev->ddev, 0);
722 rdev->pm.vblank_sync = true;
723 wake_up(&rdev->irq.vblank_queue);
724 }
736fc37f 725 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 726 radeon_crtc_handle_flip(rdev, 0);
c913e23a 727 }
6f34be50 728 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
6f34be50
AD		 729 if (rdev->irq.crtc_vblank_int[1]) {
730 drm_handle_vblank(rdev->ddev, 1);
731 rdev->pm.vblank_sync = true;
732 wake_up(&rdev->irq.vblank_queue);
733 }
736fc37f 734 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 735 radeon_crtc_handle_flip(rdev, 1);
c913e23a 736 }
6f34be50 737 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
d4877cf2
AD		 738 queue_hotplug = true;
739 DRM_DEBUG("HPD1\n");
dcfdd408 740 }
6f34be50 741 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
d4877cf2
AD		 742 queue_hotplug = true;
743 DRM_DEBUG("HPD2\n");
dcfdd408 744 }
f122c610
AD		 745 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
746 queue_hdmi = true;
747 DRM_DEBUG("HDMI0\n");
748 }
6f34be50 749 status = rs600_irq_ack(rdev);
7ed220d7 750 }
d4877cf2 751 if (queue_hotplug)
32c87fca 752 schedule_work(&rdev->hotplug_work);
f122c610
AD		 753 if (queue_hdmi)
754 schedule_work(&rdev->audio_work);
3e5cb98d
AD		 755 if (rdev->msi_enabled) {
756 switch (rdev->family) {
757 case CHIP_RS600:
758 case CHIP_RS690:
759 case CHIP_RS740:
760 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
761 WREG32(RADEON_BUS_CNTL, msi_rearm);
762 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
763 break;
764 default:
b7f5b7de 765 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
3e5cb98d
AD		 766 break;
767 }
768 }
7ed220d7
MD		 769 return IRQ_HANDLED;
770}
771
772u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
773{
774 if (crtc == 0)
c010f800 775 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
7ed220d7 776 else
c010f800 777 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
7ed220d7
MD		 778}
779
771fe6b9
JG		 780int rs600_mc_wait_for_idle(struct radeon_device *rdev)
781{
782 unsigned i;
771fe6b9
JG		 783
784 for (i = 0; i < rdev->usec_timeout; i++) {
c010f800 785 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
771fe6b9 786 return 0;
c010f800 787 udelay(1);
771fe6b9
JG		 788 }
789 return -1;
790}
791
1109ca09 792static void rs600_gpu_init(struct radeon_device *rdev)
771fe6b9 793{
771fe6b9 794 r420_pipes_init(rdev);
c010f800
JG		 795 /* Wait for mc idle */
796 if (rs600_mc_wait_for_idle(rdev))
797 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
771fe6b9
JG		 798}
799
1109ca09 800static void rs600_mc_init(struct radeon_device *rdev)
771fe6b9 801{
d594e46a
JG		 802 u64 base;
803
01d73a69
JC		 804 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
805 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
771fe6b9
JG		 806 rdev->mc.vram_is_ddr = true;
807 rdev->mc.vram_width = 128;
722f2943
AD		 808 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
809 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
51e5fcd3 810 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a
JG		 811 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
812 base = RREG32_MC(R_000004_MC_FB_LOCATION);
813 base = G_000004_MC_FB_START(base) << 16;
814 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 815 rdev->mc.gtt_base_align = 0;
d594e46a 816 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 817 radeon_update_bandwidth_info(rdev);
771fe6b9
JG		 818}
819
c93bb85b
JG		 820void rs600_bandwidth_update(struct radeon_device *rdev)
821{
f46c0120
AD		 822 struct drm_display_mode *mode0 = NULL;
823 struct drm_display_mode *mode1 = NULL;
824 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
825 /* FIXME: implement full support */
826
827 radeon_update_display_priority(rdev);
828
829 if (rdev->mode_info.crtcs[0]->base.enabled)
830 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
831 if (rdev->mode_info.crtcs[1]->base.enabled)
832 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
833
834 rs690_line_buffer_adjust(rdev, mode0, mode1);
835
836 if (rdev->disp_priority == 2) {
837 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
838 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
839 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
840 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
841 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
842 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
843 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
844 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
845 }
c93bb85b
JG		 846}
847
771fe6b9
JG		 848uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
849{
c010f800
JG		 850 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
851 S_000070_MC_IND_CITF_ARB0(1));
852 return RREG32(R_000074_MC_IND_DATA);
771fe6b9
JG		 853}
854
855void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
856{
c010f800
JG		 857 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
858 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
859 WREG32(R_000074_MC_IND_DATA, v);
860}
861
1109ca09 862static void rs600_debugfs(struct radeon_device *rdev)
c010f800
JG		 863{
864 if (r100_debugfs_rbbm_init(rdev))
865 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
771fe6b9 866}
3f7dc91a 867
3bc68535 868void rs600_set_safe_registers(struct radeon_device *rdev)
3f7dc91a
DA		 869{
870 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
871 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
3bc68535
JG		 872}
873
c010f800
JG		 874static void rs600_mc_program(struct radeon_device *rdev)
875{
876 struct rv515_mc_save save;
877
878 /* Stops all mc clients */
879 rv515_mc_stop(rdev, &save);
880
881 /* Wait for mc idle */
882 if (rs600_mc_wait_for_idle(rdev))
883 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
884
885 /* FIXME: What does AGP means for such chipset ? */
886 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
887 WREG32_MC(R_000006_AGP_BASE, 0);
888 WREG32_MC(R_000007_AGP_BASE_2, 0);
889 /* Program MC */
890 WREG32_MC(R_000004_MC_FB_LOCATION,
891 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
892 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
893 WREG32(R_000134_HDP_FB_LOCATION,
894 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
895
896 rv515_mc_resume(rdev, &save);
897}
898
899static int rs600_startup(struct radeon_device *rdev)
900{
901 int r;
902
903 rs600_mc_program(rdev);
904 /* Resume clock */
905 rv515_clock_startup(rdev);
906 /* Initialize GPU configuration (# pipes, ...) */
907 rs600_gpu_init(rdev);
908 /* Initialize GART (initialize after TTM so we can allocate
909 * memory through TTM but finalize after TTM) */
910 r = rs600_gart_enable(rdev);
911 if (r)
912 return r;
724c80e1
AD		 913
914 /* allocate wb buffer */
915 r = radeon_wb_init(rdev);
916 if (r)
917 return r;
918
30eb77f4
JG		 919 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
920 if (r) {
921 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
922 return r;
923 }
924
c010f800 925 /* Enable IRQ */
c010f800 926 rs600_irq_set(rdev);
cafe6609 927 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
c010f800
JG		 928 /* 1M ring buffer */
929 r = r100_cp_init(rdev, 1024 * 1024);
930 if (r) {
ec4f2ac4 931 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
c010f800
JG		 932 return r;
933 }
b15ba512 934
2898c348
CK		 935 r = radeon_ib_pool_init(rdev);
936 if (r) {
937 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 938 return r;
2898c348 939 }
b15ba512 940
d4e30ef0
AD		 941 r = r600_audio_init(rdev);
942 if (r) {
943 dev_err(rdev->dev, "failed initializing audio\n");
944 return r;
945 }
946
c010f800
JG		 947 return 0;
948}
949
950int rs600_resume(struct radeon_device *rdev)
951{
6b7746e8
JG		 952 int r;
953
c010f800
JG		 954 /* Make sur GART are not working */
955 rs600_gart_disable(rdev);
956 /* Resume clock before doing reset */
957 rv515_clock_startup(rdev);
958 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 959 if (radeon_asic_reset(rdev)) {
c010f800
JG		 960 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
961 RREG32(R_000E40_RBBM_STATUS),
962 RREG32(R_0007C0_CP_STAT));
963 }
964 /* post */
965 atom_asic_init(rdev->mode_info.atom_context);
966 /* Resume clock after posting */
967 rv515_clock_startup(rdev);
550e2d92
DA		 968 /* Initialize surface registers */
969 radeon_surface_init(rdev);
b15ba512
JG		 970
971 rdev->accel_working = true;
6b7746e8
JG		 972 r = rs600_startup(rdev);
973 if (r) {
974 rdev->accel_working = false;
975 }
976 return r;
c010f800
JG		 977}
978
979int rs600_suspend(struct radeon_device *rdev)
980{
fe50ac78 981 r600_audio_fini(rdev);
c010f800 982 r100_cp_disable(rdev);
724c80e1 983 radeon_wb_disable(rdev);
ac447df4 984 rs600_irq_disable(rdev);
c010f800
JG		 985 rs600_gart_disable(rdev);
986 return 0;
987}
988
989void rs600_fini(struct radeon_device *rdev)
990{
fe50ac78 991 r600_audio_fini(rdev);
c010f800 992 r100_cp_fini(rdev);
724c80e1 993 radeon_wb_fini(rdev);
2898c348 994 radeon_ib_pool_fini(rdev);
c010f800
JG		 995 radeon_gem_fini(rdev);
996 rs600_gart_fini(rdev);
997 radeon_irq_kms_fini(rdev);
998 radeon_fence_driver_fini(rdev);
4c788679 999 radeon_bo_fini(rdev);
c010f800
JG		 1000 radeon_atombios_fini(rdev);
1001 kfree(rdev->bios);
1002 rdev->bios = NULL;
1003}
1004
3bc68535
JG		 1005int rs600_init(struct radeon_device *rdev)
1006{
c010f800
JG		 1007 int r;
1008
c010f800
JG		 1009 /* Disable VGA */
1010 rv515_vga_render_disable(rdev);
1011 /* Initialize scratch registers */
1012 radeon_scratch_init(rdev);
1013 /* Initialize surface registers */
1014 radeon_surface_init(rdev);
4c712e6c
DA		 1015 /* restore some register to sane defaults */
1016 r100_restore_sanity(rdev);
c010f800
JG		 1017 /* BIOS */
1018 if (!radeon_get_bios(rdev)) {
1019 if (ASIC_IS_AVIVO(rdev))
1020 return -EINVAL;
1021 }
1022 if (rdev->is_atom_bios) {
1023 r = radeon_atombios_init(rdev);
1024 if (r)
1025 return r;
1026 } else {
1027 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1028 return -EINVAL;
1029 }
1030 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 1031 if (radeon_asic_reset(rdev)) {
c010f800
JG		 1032 dev_warn(rdev->dev,
1033 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1034 RREG32(R_000E40_RBBM_STATUS),
1035 RREG32(R_0007C0_CP_STAT));
1036 }
1037 /* check if cards are posted or not */
72542d77
DA		 1038 if (radeon_boot_test_post_card(rdev) == false)
1039 return -EINVAL;
1040
c010f800
JG		 1041 /* Initialize clocks */
1042 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 1043 /* initialize memory controller */
1044 rs600_mc_init(rdev);
c010f800
JG		 1045 rs600_debugfs(rdev);
1046 /* Fence driver */
30eb77f4 1047 r = radeon_fence_driver_init(rdev);
c010f800
JG		 1048 if (r)
1049 return r;
1050 r = radeon_irq_kms_init(rdev);
1051 if (r)
1052 return r;
1053 /* Memory manager */
4c788679 1054 r = radeon_bo_init(rdev);
c010f800
JG		 1055 if (r)
1056 return r;
1057 r = rs600_gart_init(rdev);
1058 if (r)
1059 return r;
1060 rs600_set_safe_registers(rdev);
b15ba512 1061
c010f800
JG		 1062 rdev->accel_working = true;
1063 r = rs600_startup(rdev);
1064 if (r) {
1065 /* Somethings want wront with the accel init stop accel */
1066 dev_err(rdev->dev, "Disabling GPU acceleration\n");
c010f800 1067 r100_cp_fini(rdev);
724c80e1 1068 radeon_wb_fini(rdev);
2898c348 1069 radeon_ib_pool_fini(rdev);
c010f800
JG		 1070 rs600_gart_fini(rdev);
1071 radeon_irq_kms_fini(rdev);
1072 rdev->accel_working = false;
1073 }
3f7dc91a
DA		 1074 return 0;
1075}
Linux 6.x block layer and io_uring tree(s)