Commit | Line | Data |
---|---|---|
ecc0b326 MD |
1 | /* |
2 | * Copyright 2009 VMware, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Michel Dänzer | |
23 | */ | |
24 | #include <drm/drmP.h> | |
25 | #include <drm/radeon_drm.h> | |
26 | #include "radeon_reg.h" | |
27 | #include "radeon.h" | |
28 | ||
29 | ||
30 | /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */ | |
31 | void radeon_test_moves(struct radeon_device *rdev) | |
32 | { | |
4c788679 JG |
33 | struct radeon_bo *vram_obj = NULL; |
34 | struct radeon_bo **gtt_obj = NULL; | |
ecc0b326 MD |
35 | struct radeon_fence *fence = NULL; |
36 | uint64_t gtt_addr, vram_addr; | |
37 | unsigned i, n, size; | |
38 | int r; | |
39 | ||
40 | size = 1024 * 1024; | |
41 | ||
42 | /* Number of tests = | |
24cae9e7 | 43 | * (Total GTT - IB pool - writeback page - ring buffers) / test size |
ecc0b326 | 44 | */ |
7b1f2485 | 45 | n = rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024; |
bf852799 | 46 | for (i = 0; i < RADEON_NUM_RINGS; ++i) |
e32eb50d | 47 | n -= rdev->ring[i].ring_size; |
24cae9e7 MD |
48 | if (rdev->wb.wb_obj) |
49 | n -= RADEON_GPU_PAGE_SIZE; | |
50 | if (rdev->ih.ring_obj) | |
51 | n -= rdev->ih.ring_size; | |
52 | n /= size; | |
ecc0b326 MD |
53 | |
54 | gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL); | |
55 | if (!gtt_obj) { | |
56 | DRM_ERROR("Failed to allocate %d pointers\n", n); | |
57 | r = 1; | |
58 | goto out_cleanup; | |
59 | } | |
60 | ||
441921d5 | 61 | r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
40f5cf99 | 62 | NULL, &vram_obj); |
ecc0b326 MD |
63 | if (r) { |
64 | DRM_ERROR("Failed to create VRAM object\n"); | |
65 | goto out_cleanup; | |
66 | } | |
4c788679 JG |
67 | r = radeon_bo_reserve(vram_obj, false); |
68 | if (unlikely(r != 0)) | |
69 | goto out_cleanup; | |
70 | r = radeon_bo_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr); | |
ecc0b326 MD |
71 | if (r) { |
72 | DRM_ERROR("Failed to pin VRAM object\n"); | |
73 | goto out_cleanup; | |
74 | } | |
ecc0b326 MD |
75 | for (i = 0; i < n; i++) { |
76 | void *gtt_map, *vram_map; | |
77 | void **gtt_start, **gtt_end; | |
78 | void **vram_start, **vram_end; | |
79 | ||
441921d5 | 80 | r = radeon_bo_create(rdev, size, PAGE_SIZE, true, |
40f5cf99 | 81 | RADEON_GEM_DOMAIN_GTT, NULL, gtt_obj + i); |
ecc0b326 MD |
82 | if (r) { |
83 | DRM_ERROR("Failed to create GTT object %d\n", i); | |
84 | goto out_cleanup; | |
85 | } | |
86 | ||
4c788679 JG |
87 | r = radeon_bo_reserve(gtt_obj[i], false); |
88 | if (unlikely(r != 0)) | |
89 | goto out_cleanup; | |
90 | r = radeon_bo_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, >t_addr); | |
ecc0b326 MD |
91 | if (r) { |
92 | DRM_ERROR("Failed to pin GTT object %d\n", i); | |
93 | goto out_cleanup; | |
94 | } | |
95 | ||
4c788679 | 96 | r = radeon_bo_kmap(gtt_obj[i], >t_map); |
ecc0b326 MD |
97 | if (r) { |
98 | DRM_ERROR("Failed to map GTT object %d\n", i); | |
99 | goto out_cleanup; | |
100 | } | |
101 | ||
102 | for (gtt_start = gtt_map, gtt_end = gtt_map + size; | |
103 | gtt_start < gtt_end; | |
104 | gtt_start++) | |
105 | *gtt_start = gtt_start; | |
106 | ||
4c788679 | 107 | radeon_bo_kunmap(gtt_obj[i]); |
ecc0b326 | 108 | |
876dc9f3 | 109 | r = radeon_copy(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, &fence); |
ecc0b326 MD |
110 | if (r) { |
111 | DRM_ERROR("Failed GTT->VRAM copy %d\n", i); | |
112 | goto out_cleanup; | |
113 | } | |
114 | ||
115 | r = radeon_fence_wait(fence, false); | |
116 | if (r) { | |
117 | DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i); | |
118 | goto out_cleanup; | |
119 | } | |
120 | ||
121 | radeon_fence_unref(&fence); | |
122 | ||
4c788679 | 123 | r = radeon_bo_kmap(vram_obj, &vram_map); |
ecc0b326 MD |
124 | if (r) { |
125 | DRM_ERROR("Failed to map VRAM object after copy %d\n", i); | |
126 | goto out_cleanup; | |
127 | } | |
128 | ||
129 | for (gtt_start = gtt_map, gtt_end = gtt_map + size, | |
130 | vram_start = vram_map, vram_end = vram_map + size; | |
131 | vram_start < vram_end; | |
132 | gtt_start++, vram_start++) { | |
133 | if (*vram_start != gtt_start) { | |
134 | DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, " | |
4fb1a35c MD |
135 | "expected 0x%p (GTT/VRAM offset " |
136 | "0x%16llx/0x%16llx)\n", | |
137 | i, *vram_start, gtt_start, | |
138 | (unsigned long long) | |
139 | (gtt_addr - rdev->mc.gtt_start + | |
140 | (void*)gtt_start - gtt_map), | |
141 | (unsigned long long) | |
142 | (vram_addr - rdev->mc.vram_start + | |
143 | (void*)gtt_start - gtt_map)); | |
4c788679 | 144 | radeon_bo_kunmap(vram_obj); |
ecc0b326 MD |
145 | goto out_cleanup; |
146 | } | |
147 | *vram_start = vram_start; | |
148 | } | |
149 | ||
4c788679 | 150 | radeon_bo_kunmap(vram_obj); |
ecc0b326 | 151 | |
876dc9f3 | 152 | r = radeon_copy(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, &fence); |
ecc0b326 MD |
153 | if (r) { |
154 | DRM_ERROR("Failed VRAM->GTT copy %d\n", i); | |
155 | goto out_cleanup; | |
156 | } | |
157 | ||
158 | r = radeon_fence_wait(fence, false); | |
159 | if (r) { | |
160 | DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i); | |
161 | goto out_cleanup; | |
162 | } | |
163 | ||
164 | radeon_fence_unref(&fence); | |
165 | ||
4c788679 | 166 | r = radeon_bo_kmap(gtt_obj[i], >t_map); |
ecc0b326 MD |
167 | if (r) { |
168 | DRM_ERROR("Failed to map GTT object after copy %d\n", i); | |
169 | goto out_cleanup; | |
170 | } | |
171 | ||
172 | for (gtt_start = gtt_map, gtt_end = gtt_map + size, | |
173 | vram_start = vram_map, vram_end = vram_map + size; | |
174 | gtt_start < gtt_end; | |
175 | gtt_start++, vram_start++) { | |
176 | if (*gtt_start != vram_start) { | |
177 | DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, " | |
4fb1a35c MD |
178 | "expected 0x%p (VRAM/GTT offset " |
179 | "0x%16llx/0x%16llx)\n", | |
180 | i, *gtt_start, vram_start, | |
181 | (unsigned long long) | |
182 | (vram_addr - rdev->mc.vram_start + | |
183 | (void*)vram_start - vram_map), | |
184 | (unsigned long long) | |
185 | (gtt_addr - rdev->mc.gtt_start + | |
186 | (void*)vram_start - vram_map)); | |
4c788679 | 187 | radeon_bo_kunmap(gtt_obj[i]); |
ecc0b326 MD |
188 | goto out_cleanup; |
189 | } | |
190 | } | |
191 | ||
4c788679 | 192 | radeon_bo_kunmap(gtt_obj[i]); |
ecc0b326 MD |
193 | |
194 | DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n", | |
d594e46a | 195 | gtt_addr - rdev->mc.gtt_start); |
ecc0b326 MD |
196 | } |
197 | ||
198 | out_cleanup: | |
199 | if (vram_obj) { | |
4c788679 JG |
200 | if (radeon_bo_is_reserved(vram_obj)) { |
201 | radeon_bo_unpin(vram_obj); | |
202 | radeon_bo_unreserve(vram_obj); | |
203 | } | |
204 | radeon_bo_unref(&vram_obj); | |
ecc0b326 MD |
205 | } |
206 | if (gtt_obj) { | |
207 | for (i = 0; i < n; i++) { | |
208 | if (gtt_obj[i]) { | |
4c788679 JG |
209 | if (radeon_bo_is_reserved(gtt_obj[i])) { |
210 | radeon_bo_unpin(gtt_obj[i]); | |
211 | radeon_bo_unreserve(gtt_obj[i]); | |
212 | } | |
213 | radeon_bo_unref(>t_obj[i]); | |
ecc0b326 MD |
214 | } |
215 | } | |
216 | kfree(gtt_obj); | |
217 | } | |
218 | if (fence) { | |
219 | radeon_fence_unref(&fence); | |
220 | } | |
221 | if (r) { | |
222 | printk(KERN_WARNING "Error while testing BO move.\n"); | |
223 | } | |
224 | } | |
60a7e396 CK |
225 | |
226 | void radeon_test_ring_sync(struct radeon_device *rdev, | |
e32eb50d CK |
227 | struct radeon_ring *ringA, |
228 | struct radeon_ring *ringB) | |
60a7e396 | 229 | { |
ce954884 | 230 | struct radeon_fence *fence1 = NULL, *fence2 = NULL; |
60a7e396 | 231 | struct radeon_semaphore *semaphore = NULL; |
e32eb50d CK |
232 | int ridxA = radeon_ring_index(rdev, ringA); |
233 | int ridxB = radeon_ring_index(rdev, ringB); | |
60a7e396 CK |
234 | int r; |
235 | ||
60a7e396 CK |
236 | r = radeon_semaphore_create(rdev, &semaphore); |
237 | if (r) { | |
238 | DRM_ERROR("Failed to create semaphore\n"); | |
239 | goto out_cleanup; | |
240 | } | |
241 | ||
e32eb50d | 242 | r = radeon_ring_lock(rdev, ringA, 64); |
60a7e396 | 243 | if (r) { |
e32eb50d | 244 | DRM_ERROR("Failed to lock ring A %d\n", ridxA); |
60a7e396 CK |
245 | goto out_cleanup; |
246 | } | |
e32eb50d | 247 | radeon_semaphore_emit_wait(rdev, ridxA, semaphore); |
876dc9f3 CK |
248 | r = radeon_fence_emit(rdev, &fence1, ridxA); |
249 | if (r) { | |
250 | DRM_ERROR("Failed to emit fence 1\n"); | |
251 | radeon_ring_unlock_undo(rdev, ringA); | |
252 | goto out_cleanup; | |
253 | } | |
ce954884 | 254 | radeon_semaphore_emit_wait(rdev, ridxA, semaphore); |
876dc9f3 CK |
255 | r = radeon_fence_emit(rdev, &fence2, ridxA); |
256 | if (r) { | |
257 | DRM_ERROR("Failed to emit fence 2\n"); | |
258 | radeon_ring_unlock_undo(rdev, ringA); | |
259 | goto out_cleanup; | |
260 | } | |
e32eb50d | 261 | radeon_ring_unlock_commit(rdev, ringA); |
60a7e396 CK |
262 | |
263 | mdelay(1000); | |
264 | ||
ce954884 CK |
265 | if (radeon_fence_signaled(fence1)) { |
266 | DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n"); | |
60a7e396 CK |
267 | goto out_cleanup; |
268 | } | |
269 | ||
e32eb50d | 270 | r = radeon_ring_lock(rdev, ringB, 64); |
60a7e396 | 271 | if (r) { |
e32eb50d | 272 | DRM_ERROR("Failed to lock ring B %p\n", ringB); |
60a7e396 CK |
273 | goto out_cleanup; |
274 | } | |
e32eb50d CK |
275 | radeon_semaphore_emit_signal(rdev, ridxB, semaphore); |
276 | radeon_ring_unlock_commit(rdev, ringB); | |
60a7e396 | 277 | |
ce954884 CK |
278 | r = radeon_fence_wait(fence1, false); |
279 | if (r) { | |
280 | DRM_ERROR("Failed to wait for sync fence 1\n"); | |
281 | goto out_cleanup; | |
282 | } | |
283 | ||
284 | mdelay(1000); | |
285 | ||
286 | if (radeon_fence_signaled(fence2)) { | |
287 | DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n"); | |
288 | goto out_cleanup; | |
289 | } | |
290 | ||
291 | r = radeon_ring_lock(rdev, ringB, 64); | |
60a7e396 | 292 | if (r) { |
ce954884 | 293 | DRM_ERROR("Failed to lock ring B %p\n", ringB); |
60a7e396 CK |
294 | goto out_cleanup; |
295 | } | |
ce954884 CK |
296 | radeon_semaphore_emit_signal(rdev, ridxB, semaphore); |
297 | radeon_ring_unlock_commit(rdev, ringB); | |
60a7e396 | 298 | |
ce954884 CK |
299 | r = radeon_fence_wait(fence2, false); |
300 | if (r) { | |
301 | DRM_ERROR("Failed to wait for sync fence 1\n"); | |
302 | goto out_cleanup; | |
303 | } | |
60a7e396 CK |
304 | |
305 | out_cleanup: | |
306 | if (semaphore) | |
a8c05940 | 307 | radeon_semaphore_free(rdev, semaphore, NULL); |
60a7e396 | 308 | |
ce954884 CK |
309 | if (fence1) |
310 | radeon_fence_unref(&fence1); | |
311 | ||
312 | if (fence2) | |
313 | radeon_fence_unref(&fence2); | |
314 | ||
315 | if (r) | |
316 | printk(KERN_WARNING "Error while testing ring sync (%d).\n", r); | |
317 | } | |
318 | ||
319 | void radeon_test_ring_sync2(struct radeon_device *rdev, | |
320 | struct radeon_ring *ringA, | |
321 | struct radeon_ring *ringB, | |
322 | struct radeon_ring *ringC) | |
323 | { | |
324 | struct radeon_fence *fenceA = NULL, *fenceB = NULL; | |
325 | struct radeon_semaphore *semaphore = NULL; | |
326 | int ridxA = radeon_ring_index(rdev, ringA); | |
327 | int ridxB = radeon_ring_index(rdev, ringB); | |
328 | int ridxC = radeon_ring_index(rdev, ringC); | |
329 | bool sigA, sigB; | |
330 | int i, r; | |
331 | ||
ce954884 CK |
332 | r = radeon_semaphore_create(rdev, &semaphore); |
333 | if (r) { | |
334 | DRM_ERROR("Failed to create semaphore\n"); | |
335 | goto out_cleanup; | |
336 | } | |
337 | ||
338 | r = radeon_ring_lock(rdev, ringA, 64); | |
339 | if (r) { | |
340 | DRM_ERROR("Failed to lock ring A %d\n", ridxA); | |
341 | goto out_cleanup; | |
342 | } | |
343 | radeon_semaphore_emit_wait(rdev, ridxA, semaphore); | |
876dc9f3 CK |
344 | r = radeon_fence_emit(rdev, &fenceA, ridxA); |
345 | if (r) { | |
346 | DRM_ERROR("Failed to emit sync fence 1\n"); | |
347 | radeon_ring_unlock_undo(rdev, ringA); | |
348 | goto out_cleanup; | |
349 | } | |
ce954884 CK |
350 | radeon_ring_unlock_commit(rdev, ringA); |
351 | ||
352 | r = radeon_ring_lock(rdev, ringB, 64); | |
353 | if (r) { | |
354 | DRM_ERROR("Failed to lock ring B %d\n", ridxB); | |
355 | goto out_cleanup; | |
356 | } | |
357 | radeon_semaphore_emit_wait(rdev, ridxB, semaphore); | |
876dc9f3 CK |
358 | r = radeon_fence_emit(rdev, &fenceB, ridxB); |
359 | if (r) { | |
360 | DRM_ERROR("Failed to create sync fence 2\n"); | |
361 | radeon_ring_unlock_undo(rdev, ringB); | |
362 | goto out_cleanup; | |
363 | } | |
ce954884 CK |
364 | radeon_ring_unlock_commit(rdev, ringB); |
365 | ||
366 | mdelay(1000); | |
367 | ||
368 | if (radeon_fence_signaled(fenceA)) { | |
369 | DRM_ERROR("Fence A signaled without waiting for semaphore.\n"); | |
370 | goto out_cleanup; | |
371 | } | |
372 | if (radeon_fence_signaled(fenceB)) { | |
373 | DRM_ERROR("Fence A signaled without waiting for semaphore.\n"); | |
374 | goto out_cleanup; | |
375 | } | |
376 | ||
377 | r = radeon_ring_lock(rdev, ringC, 64); | |
378 | if (r) { | |
379 | DRM_ERROR("Failed to lock ring B %p\n", ringC); | |
380 | goto out_cleanup; | |
381 | } | |
382 | radeon_semaphore_emit_signal(rdev, ridxC, semaphore); | |
383 | radeon_ring_unlock_commit(rdev, ringC); | |
384 | ||
385 | for (i = 0; i < 30; ++i) { | |
386 | mdelay(100); | |
387 | sigA = radeon_fence_signaled(fenceA); | |
388 | sigB = radeon_fence_signaled(fenceB); | |
389 | if (sigA || sigB) | |
390 | break; | |
391 | } | |
392 | ||
393 | if (!sigA && !sigB) { | |
394 | DRM_ERROR("Neither fence A nor B has been signaled\n"); | |
395 | goto out_cleanup; | |
396 | } else if (sigA && sigB) { | |
397 | DRM_ERROR("Both fence A and B has been signaled\n"); | |
398 | goto out_cleanup; | |
399 | } | |
400 | ||
401 | DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B'); | |
402 | ||
403 | r = radeon_ring_lock(rdev, ringC, 64); | |
404 | if (r) { | |
405 | DRM_ERROR("Failed to lock ring B %p\n", ringC); | |
406 | goto out_cleanup; | |
407 | } | |
408 | radeon_semaphore_emit_signal(rdev, ridxC, semaphore); | |
409 | radeon_ring_unlock_commit(rdev, ringC); | |
410 | ||
411 | mdelay(1000); | |
412 | ||
413 | r = radeon_fence_wait(fenceA, false); | |
414 | if (r) { | |
415 | DRM_ERROR("Failed to wait for sync fence A\n"); | |
416 | goto out_cleanup; | |
417 | } | |
418 | r = radeon_fence_wait(fenceB, false); | |
419 | if (r) { | |
420 | DRM_ERROR("Failed to wait for sync fence B\n"); | |
421 | goto out_cleanup; | |
422 | } | |
423 | ||
424 | out_cleanup: | |
425 | if (semaphore) | |
a8c05940 | 426 | radeon_semaphore_free(rdev, semaphore, NULL); |
ce954884 CK |
427 | |
428 | if (fenceA) | |
429 | radeon_fence_unref(&fenceA); | |
430 | ||
431 | if (fenceB) | |
432 | radeon_fence_unref(&fenceB); | |
60a7e396 CK |
433 | |
434 | if (r) | |
435 | printk(KERN_WARNING "Error while testing ring sync (%d).\n", r); | |
436 | } | |
437 | ||
438 | void radeon_test_syncing(struct radeon_device *rdev) | |
439 | { | |
ce954884 | 440 | int i, j, k; |
60a7e396 CK |
441 | |
442 | for (i = 1; i < RADEON_NUM_RINGS; ++i) { | |
e32eb50d CK |
443 | struct radeon_ring *ringA = &rdev->ring[i]; |
444 | if (!ringA->ready) | |
60a7e396 CK |
445 | continue; |
446 | ||
447 | for (j = 0; j < i; ++j) { | |
e32eb50d CK |
448 | struct radeon_ring *ringB = &rdev->ring[j]; |
449 | if (!ringB->ready) | |
60a7e396 CK |
450 | continue; |
451 | ||
ce954884 | 452 | DRM_INFO("Testing syncing between rings %d and %d...\n", i, j); |
e32eb50d | 453 | radeon_test_ring_sync(rdev, ringA, ringB); |
60a7e396 | 454 | |
ce954884 | 455 | DRM_INFO("Testing syncing between rings %d and %d...\n", j, i); |
e32eb50d | 456 | radeon_test_ring_sync(rdev, ringB, ringA); |
ce954884 CK |
457 | |
458 | for (k = 0; k < j; ++k) { | |
459 | struct radeon_ring *ringC = &rdev->ring[k]; | |
1f2e124d AD |
460 | if (!ringC->ready) |
461 | continue; | |
ce954884 CK |
462 | |
463 | DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k); | |
464 | radeon_test_ring_sync2(rdev, ringA, ringB, ringC); | |
465 | ||
466 | DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j); | |
467 | radeon_test_ring_sync2(rdev, ringA, ringC, ringB); | |
468 | ||
469 | DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k); | |
470 | radeon_test_ring_sync2(rdev, ringB, ringA, ringC); | |
471 | ||
472 | DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i); | |
473 | radeon_test_ring_sync2(rdev, ringB, ringC, ringA); | |
474 | ||
475 | DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j); | |
476 | radeon_test_ring_sync2(rdev, ringC, ringA, ringB); | |
477 | ||
478 | DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i); | |
479 | radeon_test_ring_sync2(rdev, ringC, ringB, ringA); | |
480 | } | |
60a7e396 CK |
481 | } |
482 | } | |
483 | } |