[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_ring.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 *          Christian König
 */

#include <linux/debugfs.h>

#include <drm/drm_device.h>
#include <drm/drm_file.h>

#include "radeon.h"

/*
 * Rings
 * Most engines on the GPU are fed via ring buffers.  Ring
 * buffers are areas of GPU accessible memory that the host
 * writes commands into and the GPU reads commands out of.
 * There is a rptr (read pointer) that determines where the
 * GPU is currently reading, and a wptr (write pointer)
 * which determines where the host has written.  When the
 * pointers are equal, the ring is idle.  When the host
 * writes commands to the ring buffer, it increments the
 * wptr.  The GPU then starts fetching commands and executes
 * them until the pointers are equal again.
 */
static void radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);

/**
 * radeon_ring_supports_scratch_reg - check if the ring supports
 * writing to scratch registers
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 *
 * Check if a specific ring supports writing to scratch registers (all asics).
 * Returns true if the ring supports writing to scratch regs, false if not.
 */
bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
				      struct radeon_ring *ring)
{
	switch (ring->idx) {
	case RADEON_RING_TYPE_GFX_INDEX:
	case CAYMAN_RING_TYPE_CP1_INDEX:
	case CAYMAN_RING_TYPE_CP2_INDEX:
		return true;
	default:
		return false;
	}
}

/**
 * radeon_ring_free_size - update the free size
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 *
 * Update the free dw slots in the ring buffer (all asics).
 */
void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
{
	uint32_t rptr = radeon_ring_get_rptr(rdev, ring);

	/* This works because ring_size is a power of 2 */
	ring->ring_free_dw = rptr + (ring->ring_size / 4);
	ring->ring_free_dw -= ring->wptr;
	ring->ring_free_dw &= ring->ptr_mask;
	if (!ring->ring_free_dw) {
		/* this is an empty ring */
		ring->ring_free_dw = ring->ring_size / 4;
		/*  update lockup info to avoid false positive */
		radeon_ring_lockup_update(rdev, ring);
	}
}

/**
 * radeon_ring_alloc - allocate space on the ring buffer
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 * @ndw: number of dwords to allocate in the ring buffer
 *
 * Allocate @ndw dwords in the ring buffer (all asics).
 * Returns 0 on success, error on failure.
 */
int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
{
	int r;

	/* make sure we aren't trying to allocate more space than there is on the ring */
	if (ndw > (ring->ring_size / 4))
		return -ENOMEM;
	/* Align requested size with padding so unlock_commit can
	 * pad safely */
	radeon_ring_free_size(rdev, ring);
	ndw = (ndw + ring->align_mask) & ~ring->align_mask;
	while (ndw > (ring->ring_free_dw - 1)) {
		radeon_ring_free_size(rdev, ring);
		if (ndw < ring->ring_free_dw) {
			break;
		}
		r = radeon_fence_wait_next(rdev, ring->idx);
		if (r)
			return r;
	}
	ring->count_dw = ndw;
	ring->wptr_old = ring->wptr;
	return 0;
}

/**
 * radeon_ring_lock - lock the ring and allocate space on it
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 * @ndw: number of dwords to allocate in the ring buffer
 *
 * Lock the ring and allocate @ndw dwords in the ring buffer
 * (all asics).
 * Returns 0 on success, error on failure.
 */
int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
{
	int r;

	mutex_lock(&rdev->ring_lock);
	r = radeon_ring_alloc(rdev, ring, ndw);
	if (r) {
		mutex_unlock(&rdev->ring_lock);
		return r;
	}
	return 0;
}

/**
 * radeon_ring_commit - tell the GPU to execute the new
 * commands on the ring buffer
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 * @hdp_flush: Whether or not to perform an HDP cache flush
 *
 * Update the wptr (write pointer) to tell the GPU to
 * execute new commands on the ring buffer (all asics).
 */
void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring,
			bool hdp_flush)
{
	/* If we are emitting the HDP flush via the ring buffer, we need to
	 * do it before padding.
	 */
	if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush)
		rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring);
	/* We pad to match fetch size */
	while (ring->wptr & ring->align_mask) {
		radeon_ring_write(ring, ring->nop);
	}
	mb();
	/* If we are emitting the HDP flush via MMIO, we need to do it after
	 * all CPU writes to VRAM finished.
	 */
	if (hdp_flush && rdev->asic->mmio_hdp_flush)
		rdev->asic->mmio_hdp_flush(rdev);
	radeon_ring_set_wptr(rdev, ring);
}

/**
 * radeon_ring_unlock_commit - tell the GPU to execute the new
 * commands on the ring buffer and unlock it
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 * @hdp_flush: Whether or not to perform an HDP cache flush
 *
 * Call radeon_ring_commit() then unlock the ring (all asics).
 */
void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring,
			       bool hdp_flush)
{
	radeon_ring_commit(rdev, ring, hdp_flush);
	mutex_unlock(&rdev->ring_lock);
}

/**
 * radeon_ring_undo - reset the wptr
 *
 * @ring: radeon_ring structure holding ring information
 *
 * Reset the driver's copy of the wptr (all asics).
 */
void radeon_ring_undo(struct radeon_ring *ring)
{
	ring->wptr = ring->wptr_old;
}

/**
 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
 *
 * @rdev:       radeon device structure
 * @ring: radeon_ring structure holding ring information
 *
 * Call radeon_ring_undo() then unlock the ring (all asics).
 */
void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
{
	radeon_ring_undo(ring);
	mutex_unlock(&rdev->ring_lock);
}

/**
 * radeon_ring_lockup_update - update lockup variables
 *
 * @rdev:       radeon device structure
 * @ring: radeon_ring structure holding ring information
 *
 * Update the last rptr value and timestamp (all asics).
 */
void radeon_ring_lockup_update(struct radeon_device *rdev,
			       struct radeon_ring *ring)
{
	atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring));
	atomic64_set(&ring->last_activity, jiffies_64);
}

/**
 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
 * @rdev:       radeon device structure
 * @ring:       radeon_ring structure holding ring information
 *
 */
bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
{
	uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
	uint64_t last = atomic64_read(&ring->last_activity);
	uint64_t elapsed;

	if (rptr != atomic_read(&ring->last_rptr)) {
		/* ring is still working, no lockup */
		radeon_ring_lockup_update(rdev, ring);
		return false;
	}

	elapsed = jiffies_to_msecs(jiffies_64 - last);
	if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
		dev_err(rdev->dev, "ring %d stalled for more than %llumsec\n",
			ring->idx, elapsed);
		return true;
	}
	/* give a chance to the GPU ... */
	return false;
}

/**
 * radeon_ring_backup - Back up the content of a ring
 *
 * @rdev: radeon_device pointer
 * @ring: the ring we want to back up
 * @data: placeholder for returned commit data
 *
 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
 */
unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
			    uint32_t **data)
{
	unsigned size, ptr, i;

	/* just in case lock the ring */
	mutex_lock(&rdev->ring_lock);
	*data = NULL;

	if (ring->ring_obj == NULL) {
		mutex_unlock(&rdev->ring_lock);
		return 0;
	}

	/* it doesn't make sense to save anything if all fences are signaled */
	if (!radeon_fence_count_emitted(rdev, ring->idx)) {
		mutex_unlock(&rdev->ring_lock);
		return 0;
	}

	/* calculate the number of dw on the ring */
	if (ring->rptr_save_reg)
		ptr = RREG32(ring->rptr_save_reg);
	else if (rdev->wb.enabled)
		ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
	else {
		/* no way to read back the next rptr */
		mutex_unlock(&rdev->ring_lock);
		return 0;
	}

	size = ring->wptr + (ring->ring_size / 4);
	size -= ptr;
	size &= ring->ptr_mask;
	if (size == 0) {
		mutex_unlock(&rdev->ring_lock);
		return 0;
	}

	/* and then save the content of the ring */
	*data = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
	if (!*data) {
		mutex_unlock(&rdev->ring_lock);
		return 0;
	}
	for (i = 0; i < size; ++i) {
		(*data)[i] = ring->ring[ptr++];
		ptr &= ring->ptr_mask;
	}

	mutex_unlock(&rdev->ring_lock);
	return size;
}

/**
 * radeon_ring_restore - append saved commands to the ring again
 *
 * @rdev: radeon_device pointer
 * @ring: ring to append commands to
 * @size: number of dwords we want to write
 * @data: saved commands
 *
 * Allocates space on the ring and restore the previously saved commands.
 */
int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
			unsigned size, uint32_t *data)
{
	int i, r;

	if (!size || !data)
		return 0;

	/* restore the saved ring content */
	r = radeon_ring_lock(rdev, ring, size);
	if (r)
		return r;

	for (i = 0; i < size; ++i) {
		radeon_ring_write(ring, data[i]);
	}

	radeon_ring_unlock_commit(rdev, ring, false);
	kvfree(data);
	return 0;
}

/**
 * radeon_ring_init - init driver ring struct.
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 * @ring_size: size of the ring
 * @rptr_offs: offset of the rptr writeback location in the WB buffer
 * @nop: nop packet for this ring
 *
 * Initialize the driver information for the selected ring (all asics).
 * Returns 0 on success, error on failure.
 */
int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
		     unsigned rptr_offs, u32 nop)
{
	int r;

	ring->ring_size = ring_size;
	ring->rptr_offs = rptr_offs;
	ring->nop = nop;
	ring->rdev = rdev;
	/* Allocate ring buffer */
	if (ring->ring_obj == NULL) {
		r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
				     RADEON_GEM_DOMAIN_GTT, 0, NULL,
				     NULL, &ring->ring_obj);
		if (r) {
			dev_err(rdev->dev, "(%d) ring create failed\n", r);
			return r;
		}
		r = radeon_bo_reserve(ring->ring_obj, false);
		if (unlikely(r != 0))
			return r;
		r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
					&ring->gpu_addr);
		if (r) {
			radeon_bo_unreserve(ring->ring_obj);
			dev_err(rdev->dev, "(%d) ring pin failed\n", r);
			return r;
		}
		r = radeon_bo_kmap(ring->ring_obj,
				       (void **)&ring->ring);
		radeon_bo_unreserve(ring->ring_obj);
		if (r) {
			dev_err(rdev->dev, "(%d) ring map failed\n", r);
			return r;
		}
		radeon_debugfs_ring_init(rdev, ring);
	}
	ring->ptr_mask = (ring->ring_size / 4) - 1;
	ring->ring_free_dw = ring->ring_size / 4;
	if (rdev->wb.enabled) {
		u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
		ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
		ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
	}
	radeon_ring_lockup_update(rdev, ring);
	return 0;
}

/**
 * radeon_ring_fini - tear down the driver ring struct.
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 *
 * Tear down the driver information for the selected ring (all asics).
 */
void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
{
	int r;
	struct radeon_bo *ring_obj;

	mutex_lock(&rdev->ring_lock);
	ring_obj = ring->ring_obj;
	ring->ready = false;
	ring->ring = NULL;
	ring->ring_obj = NULL;
	mutex_unlock(&rdev->ring_lock);

	if (ring_obj) {
		r = radeon_bo_reserve(ring_obj, false);
		if (likely(r == 0)) {
			radeon_bo_kunmap(ring_obj);
			radeon_bo_unpin(ring_obj);
			radeon_bo_unreserve(ring_obj);
		}
		radeon_bo_unref(&ring_obj);
	}
}

/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)

static int radeon_debugfs_ring_info_show(struct seq_file *m, void *unused)
{
	struct radeon_ring *ring = m->private;
	struct radeon_device *rdev = ring->rdev;

	uint32_t rptr, wptr, rptr_next;
	unsigned count, i, j;

	radeon_ring_free_size(rdev, ring);
	count = (ring->ring_size / 4) - ring->ring_free_dw;

	wptr = radeon_ring_get_wptr(rdev, ring);
	seq_printf(m, "wptr: 0x%08x [%5d]\n",
		   wptr, wptr);

	rptr = radeon_ring_get_rptr(rdev, ring);
	seq_printf(m, "rptr: 0x%08x [%5d]\n",
		   rptr, rptr);

	if (ring->rptr_save_reg) {
		rptr_next = RREG32(ring->rptr_save_reg);
		seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n",
			   ring->rptr_save_reg, rptr_next, rptr_next);
	} else
		rptr_next = ~0;

	seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
		   ring->wptr, ring->wptr);
	seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
		   ring->last_semaphore_signal_addr);
	seq_printf(m, "last semaphore wait addr   : 0x%016llx\n",
		   ring->last_semaphore_wait_addr);
	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
	seq_printf(m, "%u dwords in ring\n", count);

	if (!ring->ring)
		return 0;

	/* print 8 dw before current rptr as often it's the last executed
	 * packet that is the root issue
	 */
	i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
	for (j = 0; j <= (count + 32); j++) {
		seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
		if (rptr == i)
			seq_puts(m, " *");
		if (rptr_next == i)
			seq_puts(m, " #");
		seq_puts(m, "\n");
		i = (i + 1) & ring->ptr_mask;
	}
	return 0;
}

DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_ring_info);

static const char *radeon_debugfs_ring_idx_to_name(uint32_t ridx)
{
	switch (ridx) {
	case RADEON_RING_TYPE_GFX_INDEX:
		return "radeon_ring_gfx";
	case CAYMAN_RING_TYPE_CP1_INDEX:
		return "radeon_ring_cp1";
	case CAYMAN_RING_TYPE_CP2_INDEX:
		return "radeon_ring_cp2";
	case R600_RING_TYPE_DMA_INDEX:
		return "radeon_ring_dma1";
	case CAYMAN_RING_TYPE_DMA1_INDEX:
		return "radeon_ring_dma2";
	case R600_RING_TYPE_UVD_INDEX:
		return "radeon_ring_uvd";
	case TN_RING_TYPE_VCE1_INDEX:
		return "radeon_ring_vce1";
	case TN_RING_TYPE_VCE2_INDEX:
		return "radeon_ring_vce2";
	default:
		return NULL;

	}
}
#endif

static void radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
{
#if defined(CONFIG_DEBUG_FS)
	const char *ring_name = radeon_debugfs_ring_idx_to_name(ring->idx);
	struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root;

	if (ring_name)
		debugfs_create_file(ring_name, 0444, root, ring,
				    &radeon_debugfs_ring_info_fops);

#endif
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
c507f7ef	27	* Christian König
771fe6b9	28	*/
f9183127	29
33d5ae6c JN	30	#include <linux/debugfs.h>
33d5ae6c JN	31
f9183127 SR	32	#include <drm/drm_device.h>
	33	#include <drm/drm_file.h>
	34
771fe6b9	35	#include "radeon.h"
7bd560e8	36
771fe6b9	37	/*
75923280 AD	38	* Rings
	39	* Most engines on the GPU are fed via ring buffers. Ring
	40	* buffers are areas of GPU accessible memory that the host
	41	* writes commands into and the GPU reads commands out of.
	42	* There is a rptr (read pointer) that determines where the
	43	* GPU is currently reading, and a wptr (write pointer)
	44	* which determines where the host has written. When the
	45	* pointers are equal, the ring is idle. When the host
	46	* writes commands to the ring buffer, it increments the
	47	* wptr. The GPU then starts fetching commands and executes
	48	* them until the pointers are equal again.
771fe6b9	49	*/
5b54d679	50	static void radeon_debugfs_ring_init(struct radeon_device rdev, struct radeon_ring ring);
c507f7ef	51
75923280 AD	52	/**
	53	* radeon_ring_supports_scratch_reg - check if the ring supports
	54	* writing to scratch registers
	55	*
	56	* @rdev: radeon_device pointer
	57	* @ring: radeon_ring structure holding ring information
	58	*
	59	* Check if a specific ring supports writing to scratch registers (all asics).
	60	* Returns true if the ring supports writing to scratch regs, false if not.
	61	*/
89d35807 AD	62	bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
	63	struct radeon_ring *ring)
	64	{
	65	switch (ring->idx) {
	66	case RADEON_RING_TYPE_GFX_INDEX:
	67	case CAYMAN_RING_TYPE_CP1_INDEX:
	68	case CAYMAN_RING_TYPE_CP2_INDEX:
	69	return true;
	70	default:
	71	return false;
	72	}
	73	}
	74
75923280 AD	75	/**
	76	* radeon_ring_free_size - update the free size
	77	*
	78	* @rdev: radeon_device pointer
	79	* @ring: radeon_ring structure holding ring information
	80	*
	81	* Update the free dw slots in the ring buffer (all asics).
	82	*/
e32eb50d	83	void radeon_ring_free_size(struct radeon_device rdev, struct radeon_ring ring)
771fe6b9	84	{
ff212f25 CK	85	uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
ff212f25 CK	86
771fe6b9	87	/* This works because ring_size is a power of 2 */
ff212f25	88	ring->ring_free_dw = rptr + (ring->ring_size / 4);
e32eb50d CK	89	ring->ring_free_dw -= ring->wptr;
	90	ring->ring_free_dw &= ring->ptr_mask;
	91	if (!ring->ring_free_dw) {
82dc62a3	92	/* this is an empty ring */
e32eb50d	93	ring->ring_free_dw = ring->ring_size / 4;
82dc62a3 CK	94	/* update lockup info to avoid false positive */
82dc62a3 CK	95	radeon_ring_lockup_update(rdev, ring);
771fe6b9 JG	96	}
	97	}
	98
75923280 AD	99	/**
	100	* radeon_ring_alloc - allocate space on the ring buffer
	101	*
	102	* @rdev: radeon_device pointer
	103	* @ring: radeon_ring structure holding ring information
	104	* @ndw: number of dwords to allocate in the ring buffer
	105	*
	106	* Allocate @ndw dwords in the ring buffer (all asics).
	107	* Returns 0 on success, error on failure.
	108	*/
e32eb50d	109	int radeon_ring_alloc(struct radeon_device rdev, struct radeon_ring ring, unsigned ndw)
771fe6b9 JG	110	{
	111	int r;
	112
fd5d93a0 AD	113	/* make sure we aren't trying to allocate more space than there is on the ring */
	114	if (ndw > (ring->ring_size / 4))
	115	return -ENOMEM;
771fe6b9 JG	116	/* Align requested size with padding so unlock_commit can
771fe6b9 JG	117	* pad safely */
8444d5c6	118	radeon_ring_free_size(rdev, ring);
e32eb50d CK	119	ndw = (ndw + ring->align_mask) & ~ring->align_mask;
	120	while (ndw > (ring->ring_free_dw - 1)) {
	121	radeon_ring_free_size(rdev, ring);
	122	if (ndw < ring->ring_free_dw) {
771fe6b9 JG	123	break;
771fe6b9 JG	124	}
37615527	125	r = radeon_fence_wait_next(rdev, ring->idx);
91700f3c	126	if (r)
771fe6b9	127	return r;
771fe6b9	128	}
e32eb50d CK	129	ring->count_dw = ndw;
e32eb50d CK	130	ring->wptr_old = ring->wptr;
771fe6b9 JG	131	return 0;
	132	}
	133
75923280 AD	134	/**
	135	* radeon_ring_lock - lock the ring and allocate space on it
	136	*
	137	* @rdev: radeon_device pointer
	138	* @ring: radeon_ring structure holding ring information
	139	* @ndw: number of dwords to allocate in the ring buffer
	140	*
	141	* Lock the ring and allocate @ndw dwords in the ring buffer
	142	* (all asics).
	143	* Returns 0 on success, error on failure.
	144	*/
e32eb50d	145	int radeon_ring_lock(struct radeon_device rdev, struct radeon_ring ring, unsigned ndw)
91700f3c MG	146	{
	147	int r;
	148
d6999bc7	149	mutex_lock(&rdev->ring_lock);
e32eb50d	150	r = radeon_ring_alloc(rdev, ring, ndw);
91700f3c	151	if (r) {
d6999bc7	152	mutex_unlock(&rdev->ring_lock);
91700f3c MG	153	return r;
	154	}
	155	return 0;
	156	}
	157
75923280 AD	158	/**
	159	* radeon_ring_commit - tell the GPU to execute the new
	160	* commands on the ring buffer
	161	*
	162	* @rdev: radeon_device pointer
	163	* @ring: radeon_ring structure holding ring information
1538a9e0	164	* @hdp_flush: Whether or not to perform an HDP cache flush
75923280 AD	165	*
	166	* Update the wptr (write pointer) to tell the GPU to
	167	* execute new commands on the ring buffer (all asics).
	168	*/
1538a9e0 MD	169	void radeon_ring_commit(struct radeon_device rdev, struct radeon_ring ring,
1538a9e0 MD	170	bool hdp_flush)
771fe6b9	171	{
72a9987e MD	172	/* If we are emitting the HDP flush via the ring buffer, we need to
	173	* do it before padding.
	174	*/
1538a9e0	175	if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush)
72a9987e	176	rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring);
771fe6b9	177	/* We pad to match fetch size */
07a71330	178	while (ring->wptr & ring->align_mask) {
78c5560a	179	radeon_ring_write(ring, ring->nop);
771fe6b9	180	}
85b2331b	181	mb();
72a9987e MD	182	/* If we are emitting the HDP flush via MMIO, we need to do it after
	183	* all CPU writes to VRAM finished.
	184	*/
1538a9e0	185	if (hdp_flush && rdev->asic->mmio_hdp_flush)
72a9987e	186	rdev->asic->mmio_hdp_flush(rdev);
f93bdefe	187	radeon_ring_set_wptr(rdev, ring);
91700f3c MG	188	}
91700f3c MG	189
75923280 AD	190	/**
	191	* radeon_ring_unlock_commit - tell the GPU to execute the new
	192	* commands on the ring buffer and unlock it
	193	*
	194	* @rdev: radeon_device pointer
	195	* @ring: radeon_ring structure holding ring information
1538a9e0	196	* @hdp_flush: Whether or not to perform an HDP cache flush
75923280 AD	197	*
	198	* Call radeon_ring_commit() then unlock the ring (all asics).
	199	*/
1538a9e0 MD	200	void radeon_ring_unlock_commit(struct radeon_device rdev, struct radeon_ring ring,
1538a9e0 MD	201	bool hdp_flush)
91700f3c	202	{
1538a9e0	203	radeon_ring_commit(rdev, ring, hdp_flush);
d6999bc7	204	mutex_unlock(&rdev->ring_lock);
771fe6b9 JG	205	}
771fe6b9 JG	206
75923280 AD	207	/**
	208	* radeon_ring_undo - reset the wptr
	209	*
	210	* @ring: radeon_ring structure holding ring information
	211	*
501f9d4c	212	* Reset the driver's copy of the wptr (all asics).
75923280	213	*/
d6999bc7	214	void radeon_ring_undo(struct radeon_ring *ring)
771fe6b9	215	{
e32eb50d	216	ring->wptr = ring->wptr_old;
d6999bc7 CK	217	}
d6999bc7 CK	218
75923280 AD	219	/**
	220	* radeon_ring_unlock_undo - reset the wptr and unlock the ring
	221	*
b4391459	222	* @rdev: radeon device structure
75923280 AD	223	* @ring: radeon_ring structure holding ring information
	224	*
	225	* Call radeon_ring_undo() then unlock the ring (all asics).
	226	*/
d6999bc7 CK	227	void radeon_ring_unlock_undo(struct radeon_device rdev, struct radeon_ring ring)
	228	{
	229	radeon_ring_undo(ring);
	230	mutex_unlock(&rdev->ring_lock);
771fe6b9 JG	231	}
771fe6b9 JG	232
75923280	233	/**
501f9d4c	234	* radeon_ring_lockup_update - update lockup variables
75923280	235	*
b4391459	236	* @rdev: radeon device structure
75923280 AD	237	* @ring: radeon_ring structure holding ring information
	238	*
	239	* Update the last rptr value and timestamp (all asics).
	240	*/
ff212f25 CK	241	void radeon_ring_lockup_update(struct radeon_device *rdev,
ff212f25 CK	242	struct radeon_ring *ring)
069211e5	243	{
aee4aa73 CK	244	atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring));
aee4aa73 CK	245	atomic64_set(&ring->last_activity, jiffies_64);
069211e5 CK	246	}
	247
	248	/**
	249	* radeon_ring_test_lockup() - check if ring is lockedup by recording information
	250	* @rdev: radeon device structure
	251	* @ring: radeon_ring structure holding ring information
	252	*
2d2fe3f9	253	*/
069211e5 CK	254	bool radeon_ring_test_lockup(struct radeon_device rdev, struct radeon_ring ring)
069211e5 CK	255	{
ff212f25	256	uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
aee4aa73 CK	257	uint64_t last = atomic64_read(&ring->last_activity);
aee4aa73 CK	258	uint64_t elapsed;
069211e5	259
aee4aa73 CK	260	if (rptr != atomic_read(&ring->last_rptr)) {
aee4aa73 CK	261	/* ring is still working, no lockup */
ff212f25	262	radeon_ring_lockup_update(rdev, ring);
069211e5 CK	263	return false;
069211e5 CK	264	}
aee4aa73 CK	265
aee4aa73 CK	266	elapsed = jiffies_to_msecs(jiffies_64 - last);
3368ff0c	267	if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
aee4aa73 CK	268	dev_err(rdev->dev, "ring %d stalled for more than %llumsec\n",
aee4aa73 CK	269	ring->idx, elapsed);
069211e5 CK	270	return true;
	271	}
	272	/* give a chance to the GPU ... */
	273	return false;
	274	}
	275
55d7c221 CK	276	/**
	277	* radeon_ring_backup - Back up the content of a ring
	278	*
	279	* @rdev: radeon_device pointer
	280	* @ring: the ring we want to back up
b4391459	281	* @data: placeholder for returned commit data
55d7c221 CK	282	*
	283	* Saves all unprocessed commits from a ring, returns the number of dwords saved.
	284	*/
	285	unsigned radeon_ring_backup(struct radeon_device rdev, struct radeon_ring ring,
	286	uint32_t **data)
	287	{
	288	unsigned size, ptr, i;
55d7c221 CK	289
	290	/* just in case lock the ring */
	291	mutex_lock(&rdev->ring_lock);
	292	*data = NULL;
	293
89d35807	294	if (ring->ring_obj == NULL) {
55d7c221 CK	295	mutex_unlock(&rdev->ring_lock);
	296	return 0;
	297	}
	298
	299	/* it doesn't make sense to save anything if all fences are signaled */
8b25ed34	300	if (!radeon_fence_count_emitted(rdev, ring->idx)) {
55d7c221 CK	301	mutex_unlock(&rdev->ring_lock);
	302	return 0;
	303	}
	304
	305	/* calculate the number of dw on the ring */
89d35807 AD	306	if (ring->rptr_save_reg)
	307	ptr = RREG32(ring->rptr_save_reg);
	308	else if (rdev->wb.enabled)
	309	ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
	310	else {
	311	/* no way to read back the next rptr */
	312	mutex_unlock(&rdev->ring_lock);
	313	return 0;
	314	}
	315
55d7c221 CK	316	size = ring->wptr + (ring->ring_size / 4);
	317	size -= ptr;
	318	size &= ring->ptr_mask;
	319	if (size == 0) {
	320	mutex_unlock(&rdev->ring_lock);
	321	return 0;
	322	}
	323
	324	/* and then save the content of the ring */
2098105e	325	*data = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
1e179d4e DC	326	if (!*data) {
	327	mutex_unlock(&rdev->ring_lock);
	328	return 0;
	329	}
55d7c221 CK	330	for (i = 0; i < size; ++i) {
	331	(*data)[i] = ring->ring[ptr++];
	332	ptr &= ring->ptr_mask;
	333	}
	334
	335	mutex_unlock(&rdev->ring_lock);
	336	return size;
	337	}
	338
	339	/**
	340	* radeon_ring_restore - append saved commands to the ring again
	341	*
	342	* @rdev: radeon_device pointer
	343	* @ring: ring to append commands to
	344	* @size: number of dwords we want to write
	345	* @data: saved commands
	346	*
	347	* Allocates space on the ring and restore the previously saved commands.
	348	*/
	349	int radeon_ring_restore(struct radeon_device rdev, struct radeon_ring ring,
	350	unsigned size, uint32_t *data)
	351	{
	352	int i, r;
	353
	354	if (!size \|\| !data)
	355	return 0;
	356
	357	/* restore the saved ring content */
	358	r = radeon_ring_lock(rdev, ring, size);
	359	if (r)
	360	return r;
	361
	362	for (i = 0; i < size; ++i) {
	363	radeon_ring_write(ring, data[i]);
	364	}
	365
1538a9e0	366	radeon_ring_unlock_commit(rdev, ring, false);
2098105e	367	kvfree(data);
55d7c221 CK	368	return 0;
	369	}
	370
75923280 AD	371	/**
	372	* radeon_ring_init - init driver ring struct.
	373	*
	374	* @rdev: radeon_device pointer
	375	* @ring: radeon_ring structure holding ring information
	376	* @ring_size: size of the ring
	377	* @rptr_offs: offset of the rptr writeback location in the WB buffer
75923280 AD	378	* @nop: nop packet for this ring
	379	*
	380	* Initialize the driver information for the selected ring (all asics).
	381	* Returns 0 on success, error on failure.
	382	*/
e32eb50d	383	int radeon_ring_init(struct radeon_device rdev, struct radeon_ring ring, unsigned ring_size,
ea31bf69	384	unsigned rptr_offs, u32 nop)
771fe6b9 JG	385	{
	386	int r;
	387
e32eb50d CK	388	ring->ring_size = ring_size;
e32eb50d CK	389	ring->rptr_offs = rptr_offs;
78c5560a	390	ring->nop = nop;
e7fa81bb	391	ring->rdev = rdev;
771fe6b9	392	/* Allocate ring buffer */
e32eb50d CK	393	if (ring->ring_obj == NULL) {
e32eb50d CK	394	r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
831b6966	395	RADEON_GEM_DOMAIN_GTT, 0, NULL,
40f5cf99	396	NULL, &ring->ring_obj);
771fe6b9	397	if (r) {
4c788679	398	dev_err(rdev->dev, "(%d) ring create failed\n", r);
771fe6b9 JG	399	return r;
771fe6b9 JG	400	}
e32eb50d	401	r = radeon_bo_reserve(ring->ring_obj, false);
4c788679 JG	402	if (unlikely(r != 0))
4c788679 JG	403	return r;
e32eb50d CK	404	r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
e32eb50d CK	405	&ring->gpu_addr);
771fe6b9	406	if (r) {
e32eb50d	407	radeon_bo_unreserve(ring->ring_obj);
4c788679	408	dev_err(rdev->dev, "(%d) ring pin failed\n", r);
771fe6b9 JG	409	return r;
771fe6b9 JG	410	}
e32eb50d CK	411	r = radeon_bo_kmap(ring->ring_obj,
	412	(void **)&ring->ring);
	413	radeon_bo_unreserve(ring->ring_obj);
771fe6b9	414	if (r) {
4c788679	415	dev_err(rdev->dev, "(%d) ring map failed\n", r);
771fe6b9 JG	416	return r;
771fe6b9 JG	417	}
69a83fd3	418	radeon_debugfs_ring_init(rdev, ring);
771fe6b9	419	}
e32eb50d CK	420	ring->ptr_mask = (ring->ring_size / 4) - 1;
e32eb50d CK	421	ring->ring_free_dw = ring->ring_size / 4;
89d35807 AD	422	if (rdev->wb.enabled) {
	423	u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
	424	ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
	425	ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
	426	}
ff212f25	427	radeon_ring_lockup_update(rdev, ring);
771fe6b9 JG	428	return 0;
	429	}
	430
75923280 AD	431	/**
	432	* radeon_ring_fini - tear down the driver ring struct.
	433	*
	434	* @rdev: radeon_device pointer
	435	* @ring: radeon_ring structure holding ring information
	436	*
	437	* Tear down the driver information for the selected ring (all asics).
	438	*/
e32eb50d	439	void radeon_ring_fini(struct radeon_device rdev, struct radeon_ring ring)
771fe6b9	440	{
4c788679	441	int r;
ca2af923	442	struct radeon_bo *ring_obj;
4c788679	443
d6999bc7	444	mutex_lock(&rdev->ring_lock);
e32eb50d	445	ring_obj = ring->ring_obj;
d6999bc7	446	ring->ready = false;
e32eb50d CK	447	ring->ring = NULL;
e32eb50d CK	448	ring->ring_obj = NULL;
d6999bc7	449	mutex_unlock(&rdev->ring_lock);
ca2af923 AD	450
	451	if (ring_obj) {
	452	r = radeon_bo_reserve(ring_obj, false);
4c788679	453	if (likely(r == 0)) {
ca2af923 AD	454	radeon_bo_kunmap(ring_obj);
	455	radeon_bo_unpin(ring_obj);
	456	radeon_bo_unreserve(ring_obj);
4c788679	457	}
ca2af923	458	radeon_bo_unref(&ring_obj);
771fe6b9	459	}
771fe6b9 JG	460	}
771fe6b9 JG	461
771fe6b9 JG	462	/*
	463	* Debugfs info
	464	*/
	465	#if defined(CONFIG_DEBUG_FS)
af9720f4	466
5b54d679	467	static int radeon_debugfs_ring_info_show(struct seq_file m, void unused)
af9720f4	468	{
6091ede9	469	struct radeon_ring *ring = m->private;
5b54d679	470	struct radeon_device *rdev = ring->rdev;
df893a25 CK	471
df893a25 CK	472	uint32_t rptr, wptr, rptr_next;
af9720f4 CK	473	unsigned count, i, j;
	474
	475	radeon_ring_free_size(rdev, ring);
	476	count = (ring->ring_size / 4) - ring->ring_free_dw;
df893a25 CK	477
df893a25 CK	478	wptr = radeon_ring_get_wptr(rdev, ring);
ea31bf69 AD	479	seq_printf(m, "wptr: 0x%08x [%5d]\n",
ea31bf69 AD	480	wptr, wptr);
df893a25 CK	481
df893a25 CK	482	rptr = radeon_ring_get_rptr(rdev, ring);
ea31bf69 AD	483	seq_printf(m, "rptr: 0x%08x [%5d]\n",
ea31bf69 AD	484	rptr, rptr);
df893a25	485
45df6803	486	if (ring->rptr_save_reg) {
df893a25 CK	487	rptr_next = RREG32(ring->rptr_save_reg);
	488	seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n",
	489	ring->rptr_save_reg, rptr_next, rptr_next);
	490	} else
	491	rptr_next = ~0;
	492
	493	seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
	494	ring->wptr, ring->wptr);
df893a25 CK	495	seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
	496	ring->last_semaphore_signal_addr);
	497	seq_printf(m, "last semaphore wait addr : 0x%016llx\n",
	498	ring->last_semaphore_wait_addr);
af9720f4 CK	499	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
af9720f4 CK	500	seq_printf(m, "%u dwords in ring\n", count);
df893a25	501
1b01fc34	502	if (!ring->ring)
df893a25 CK	503	return 0;
df893a25 CK	504
4d009190 JG	505	/* print 8 dw before current rptr as often it's the last executed
	506	* packet that is the root issue
	507	*/
df893a25 CK	508	i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
	509	for (j = 0; j <= (count + 32); j++) {
	510	seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
	511	if (rptr == i)
	512	seq_puts(m, " *");
	513	if (rptr_next == i)
	514	seq_puts(m, " #");
	515	seq_puts(m, "\n");
	516	i = (i + 1) & ring->ptr_mask;
af9720f4 CK	517	}
	518	return 0;
	519	}
	520
5b54d679 ND	521	DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_ring_info);
	522
	523	static const char *radeon_debugfs_ring_idx_to_name(uint32_t ridx)
	524	{
	525	switch (ridx) {
	526	case RADEON_RING_TYPE_GFX_INDEX:
	527	return "radeon_ring_gfx";
	528	case CAYMAN_RING_TYPE_CP1_INDEX:
	529	return "radeon_ring_cp1";
	530	case CAYMAN_RING_TYPE_CP2_INDEX:
	531	return "radeon_ring_cp2";
	532	case R600_RING_TYPE_DMA_INDEX:
	533	return "radeon_ring_dma1";
	534	case CAYMAN_RING_TYPE_DMA1_INDEX:
	535	return "radeon_ring_dma2";
	536	case R600_RING_TYPE_UVD_INDEX:
	537	return "radeon_ring_uvd";
	538	case TN_RING_TYPE_VCE1_INDEX:
	539	return "radeon_ring_vce1";
	540	case TN_RING_TYPE_VCE2_INDEX:
	541	return "radeon_ring_vce2";
	542	default:
	543	return NULL;
af9720f4	544
5b54d679 ND	545	}
5b54d679 ND	546	}
771fe6b9 JG	547	#endif
771fe6b9 JG	548
5b54d679	549	static void radeon_debugfs_ring_init(struct radeon_device rdev, struct radeon_ring ring)
af9720f4 CK	550	{
af9720f4 CK	551	#if defined(CONFIG_DEBUG_FS)
5b54d679	552	const char *ring_name = radeon_debugfs_ring_idx_to_name(ring->idx);
fb1b5e1d	553	struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root;
ec1a6cce	554
5b54d679 ND	555	if (ring_name)
	556	debugfs_create_file(ring_name, 0444, root, ring,
	557	&radeon_debugfs_ring_info_fops);
ec1a6cce	558
af9720f4 CK	559	#endif
af9720f4 CK	560	}