Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
c507f7ef | 27 | * Christian König |
771fe6b9 JG |
28 | */ |
29 | #include <linux/seq_file.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
33 | #include "radeon_reg.h" |
34 | #include "radeon.h" | |
35 | #include "atom.h" | |
36 | ||
c507f7ef | 37 | /* |
75923280 AD |
38 | * IB |
39 | * IBs (Indirect Buffers) and areas of GPU accessible memory where | |
40 | * commands are stored. You can put a pointer to the IB in the | |
41 | * command ring and the hw will fetch the commands from the IB | |
42 | * and execute them. Generally userspace acceleration drivers | |
43 | * produce command buffers which are send to the kernel and | |
44 | * put in IBs for execution by the requested ring. | |
c507f7ef | 45 | */ |
1109ca09 | 46 | static int radeon_debugfs_sa_init(struct radeon_device *rdev); |
771fe6b9 | 47 | |
75923280 AD |
48 | /** |
49 | * radeon_ib_get - request an IB (Indirect Buffer) | |
50 | * | |
51 | * @rdev: radeon_device pointer | |
52 | * @ring: ring index the IB is associated with | |
53 | * @ib: IB object returned | |
54 | * @size: requested IB size | |
55 | * | |
56 | * Request an IB (all asics). IBs are allocated using the | |
57 | * suballocator. | |
58 | * Returns 0 on success, error on failure. | |
59 | */ | |
69e130a6 | 60 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
4bf3dd92 CK |
61 | struct radeon_ib *ib, struct radeon_vm *vm, |
62 | unsigned size) | |
771fe6b9 | 63 | { |
1654b817 | 64 | int r; |
b15ba512 | 65 | |
f2e39221 | 66 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true); |
c507f7ef JG |
67 | if (r) { |
68 | dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); | |
c507f7ef | 69 | return r; |
b15ba512 | 70 | } |
c507f7ef | 71 | |
220907d9 CK |
72 | r = radeon_semaphore_create(rdev, &ib->semaphore); |
73 | if (r) { | |
74 | return r; | |
75 | } | |
76 | ||
876dc9f3 CK |
77 | ib->ring = ring; |
78 | ib->fence = NULL; | |
f2e39221 | 79 | ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); |
4bf3dd92 CK |
80 | ib->vm = vm; |
81 | if (vm) { | |
ca19f21e CK |
82 | /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address |
83 | * space and soffset is the offset inside the pool bo | |
4bf3dd92 | 84 | */ |
ca19f21e | 85 | ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET; |
4bf3dd92 CK |
86 | } else { |
87 | ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); | |
88 | } | |
f2e39221 | 89 | ib->is_const_ib = false; |
c507f7ef JG |
90 | |
91 | return 0; | |
771fe6b9 JG |
92 | } |
93 | ||
75923280 AD |
94 | /** |
95 | * radeon_ib_free - free an IB (Indirect Buffer) | |
96 | * | |
97 | * @rdev: radeon_device pointer | |
98 | * @ib: IB object to free | |
99 | * | |
100 | * Free an IB (all asics). | |
101 | */ | |
f2e39221 | 102 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) |
771fe6b9 | 103 | { |
220907d9 | 104 | radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); |
f2e39221 JG |
105 | radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); |
106 | radeon_fence_unref(&ib->fence); | |
771fe6b9 JG |
107 | } |
108 | ||
75923280 AD |
109 | /** |
110 | * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring | |
111 | * | |
112 | * @rdev: radeon_device pointer | |
113 | * @ib: IB object to schedule | |
114 | * @const_ib: Const IB to schedule (SI only) | |
115 | * | |
116 | * Schedule an IB on the associated ring (all asics). | |
117 | * Returns 0 on success, error on failure. | |
118 | * | |
119 | * On SI, there are two parallel engines fed from the primary ring, | |
120 | * the CE (Constant Engine) and the DE (Drawing Engine). Since | |
121 | * resource descriptors have moved to memory, the CE allows you to | |
122 | * prime the caches while the DE is updating register state so that | |
123 | * the resource descriptors will be already in cache when the draw is | |
124 | * processed. To accomplish this, the userspace driver submits two | |
125 | * IBs, one for the CE and one for the DE. If there is a CE IB (called | |
126 | * a CONST_IB), it will be put on the ring prior to the DE IB. Prior | |
127 | * to SI there was just a DE IB. | |
128 | */ | |
4ef72566 CK |
129 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
130 | struct radeon_ib *const_ib) | |
771fe6b9 | 131 | { |
876dc9f3 | 132 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
1654b817 | 133 | int r = 0; |
771fe6b9 | 134 | |
e32eb50d | 135 | if (!ib->length_dw || !ring->ready) { |
771fe6b9 | 136 | /* TODO: Nothings in the ib we should report. */ |
c507f7ef | 137 | dev_err(rdev->dev, "couldn't schedule ib\n"); |
771fe6b9 JG |
138 | return -EINVAL; |
139 | } | |
ecb114a1 | 140 | |
6cdf6585 | 141 | /* 64 dwords should be enough for fence too */ |
220907d9 | 142 | r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); |
771fe6b9 | 143 | if (r) { |
c507f7ef | 144 | dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); |
771fe6b9 JG |
145 | return r; |
146 | } | |
1654b817 CK |
147 | |
148 | /* sync with other rings */ | |
149 | r = radeon_semaphore_sync_rings(rdev, ib->semaphore, ib->ring); | |
150 | if (r) { | |
151 | dev_err(rdev->dev, "failed to sync rings (%d)\n", r); | |
152 | radeon_ring_unlock_undo(rdev, ring); | |
153 | return r; | |
220907d9 | 154 | } |
1654b817 | 155 | |
9b40e5d8 | 156 | /* if we can't remember our last VM flush then flush now! */ |
466476df JG |
157 | /* XXX figure out why we have to flush for every IB */ |
158 | if (ib->vm /*&& !ib->vm->last_flush*/) { | |
498522b4 | 159 | radeon_ring_vm_flush(rdev, ib->ring, ib->vm); |
9b40e5d8 | 160 | } |
4ef72566 CK |
161 | if (const_ib) { |
162 | radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); | |
163 | radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); | |
164 | } | |
876dc9f3 CK |
165 | radeon_ring_ib_execute(rdev, ib->ring, ib); |
166 | r = radeon_fence_emit(rdev, &ib->fence, ib->ring); | |
167 | if (r) { | |
168 | dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); | |
169 | radeon_ring_unlock_undo(rdev, ring); | |
170 | return r; | |
171 | } | |
4ef72566 CK |
172 | if (const_ib) { |
173 | const_ib->fence = radeon_fence_ref(ib->fence); | |
174 | } | |
9b40e5d8 CK |
175 | /* we just flushed the VM, remember that */ |
176 | if (ib->vm && !ib->vm->last_flush) { | |
177 | ib->vm->last_flush = radeon_fence_ref(ib->fence); | |
178 | } | |
e32eb50d | 179 | radeon_ring_unlock_commit(rdev, ring); |
771fe6b9 JG |
180 | return 0; |
181 | } | |
182 | ||
75923280 AD |
183 | /** |
184 | * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool | |
185 | * | |
186 | * @rdev: radeon_device pointer | |
187 | * | |
188 | * Initialize the suballocator to manage a pool of memory | |
189 | * for use as IBs (all asics). | |
190 | * Returns 0 on success, error on failure. | |
191 | */ | |
771fe6b9 JG |
192 | int radeon_ib_pool_init(struct radeon_device *rdev) |
193 | { | |
c507f7ef | 194 | int r; |
771fe6b9 | 195 | |
c507f7ef | 196 | if (rdev->ib_pool_ready) { |
d54fbd49 JG |
197 | return 0; |
198 | } | |
c507f7ef | 199 | r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, |
c3b7fe8b | 200 | RADEON_IB_POOL_SIZE*64*1024, |
6c4f978b | 201 | RADEON_GPU_PAGE_SIZE, |
c3b7fe8b CK |
202 | RADEON_GEM_DOMAIN_GTT); |
203 | if (r) { | |
c3b7fe8b CK |
204 | return r; |
205 | } | |
2898c348 CK |
206 | |
207 | r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); | |
208 | if (r) { | |
209 | return r; | |
210 | } | |
211 | ||
c507f7ef JG |
212 | rdev->ib_pool_ready = true; |
213 | if (radeon_debugfs_sa_init(rdev)) { | |
214 | dev_err(rdev->dev, "failed to register debugfs file for SA\n"); | |
771fe6b9 | 215 | } |
b15ba512 | 216 | return 0; |
771fe6b9 JG |
217 | } |
218 | ||
75923280 AD |
219 | /** |
220 | * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool | |
221 | * | |
222 | * @rdev: radeon_device pointer | |
223 | * | |
224 | * Tear down the suballocator managing the pool of memory | |
225 | * for use as IBs (all asics). | |
226 | */ | |
771fe6b9 JG |
227 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
228 | { | |
c507f7ef | 229 | if (rdev->ib_pool_ready) { |
2898c348 | 230 | radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); |
c507f7ef JG |
231 | radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); |
232 | rdev->ib_pool_ready = false; | |
771fe6b9 | 233 | } |
771fe6b9 JG |
234 | } |
235 | ||
75923280 AD |
236 | /** |
237 | * radeon_ib_ring_tests - test IBs on the rings | |
238 | * | |
239 | * @rdev: radeon_device pointer | |
240 | * | |
241 | * Test an IB (Indirect Buffer) on each ring. | |
242 | * If the test fails, disable the ring. | |
243 | * Returns 0 on success, error if the primary GFX ring | |
244 | * IB test fails. | |
245 | */ | |
7bd560e8 CK |
246 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
247 | { | |
248 | unsigned i; | |
249 | int r; | |
250 | ||
251 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | |
252 | struct radeon_ring *ring = &rdev->ring[i]; | |
253 | ||
254 | if (!ring->ready) | |
255 | continue; | |
256 | ||
257 | r = radeon_ib_test(rdev, i, ring); | |
258 | if (r) { | |
259 | ring->ready = false; | |
260 | ||
261 | if (i == RADEON_RING_TYPE_GFX_INDEX) { | |
262 | /* oh, oh, that's really bad */ | |
263 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); | |
264 | rdev->accel_working = false; | |
265 | return r; | |
266 | ||
267 | } else { | |
268 | /* still not good, but we can live with it */ | |
269 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); | |
270 | } | |
271 | } | |
272 | } | |
273 | return 0; | |
274 | } | |
275 | ||
771fe6b9 | 276 | /* |
75923280 AD |
277 | * Rings |
278 | * Most engines on the GPU are fed via ring buffers. Ring | |
279 | * buffers are areas of GPU accessible memory that the host | |
280 | * writes commands into and the GPU reads commands out of. | |
281 | * There is a rptr (read pointer) that determines where the | |
282 | * GPU is currently reading, and a wptr (write pointer) | |
283 | * which determines where the host has written. When the | |
284 | * pointers are equal, the ring is idle. When the host | |
285 | * writes commands to the ring buffer, it increments the | |
286 | * wptr. The GPU then starts fetching commands and executes | |
287 | * them until the pointers are equal again. | |
771fe6b9 | 288 | */ |
1109ca09 | 289 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
c507f7ef | 290 | |
75923280 AD |
291 | /** |
292 | * radeon_ring_write - write a value to the ring | |
293 | * | |
294 | * @ring: radeon_ring structure holding ring information | |
295 | * @v: dword (dw) value to write | |
296 | * | |
297 | * Write a value to the requested ring buffer (all asics). | |
298 | */ | |
c507f7ef JG |
299 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
300 | { | |
301 | #if DRM_DEBUG_CODE | |
302 | if (ring->count_dw <= 0) { | |
8ad33cdf | 303 | DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); |
c507f7ef JG |
304 | } |
305 | #endif | |
306 | ring->ring[ring->wptr++] = v; | |
307 | ring->wptr &= ring->ptr_mask; | |
308 | ring->count_dw--; | |
309 | ring->ring_free_dw--; | |
310 | } | |
311 | ||
75923280 AD |
312 | /** |
313 | * radeon_ring_supports_scratch_reg - check if the ring supports | |
314 | * writing to scratch registers | |
315 | * | |
316 | * @rdev: radeon_device pointer | |
317 | * @ring: radeon_ring structure holding ring information | |
318 | * | |
319 | * Check if a specific ring supports writing to scratch registers (all asics). | |
320 | * Returns true if the ring supports writing to scratch regs, false if not. | |
321 | */ | |
89d35807 AD |
322 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
323 | struct radeon_ring *ring) | |
324 | { | |
325 | switch (ring->idx) { | |
326 | case RADEON_RING_TYPE_GFX_INDEX: | |
327 | case CAYMAN_RING_TYPE_CP1_INDEX: | |
328 | case CAYMAN_RING_TYPE_CP2_INDEX: | |
329 | return true; | |
330 | default: | |
331 | return false; | |
332 | } | |
333 | } | |
334 | ||
f93bdefe AD |
335 | u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev, |
336 | struct radeon_ring *ring) | |
337 | { | |
338 | u32 rptr; | |
339 | ||
02c9f7fa | 340 | if (rdev->wb.enabled) |
f93bdefe AD |
341 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); |
342 | else | |
343 | rptr = RREG32(ring->rptr_reg); | |
f93bdefe AD |
344 | |
345 | return rptr; | |
346 | } | |
347 | ||
348 | u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev, | |
349 | struct radeon_ring *ring) | |
350 | { | |
351 | u32 wptr; | |
352 | ||
353 | wptr = RREG32(ring->wptr_reg); | |
f93bdefe AD |
354 | |
355 | return wptr; | |
356 | } | |
357 | ||
358 | void radeon_ring_generic_set_wptr(struct radeon_device *rdev, | |
359 | struct radeon_ring *ring) | |
360 | { | |
2e1e6dad | 361 | WREG32(ring->wptr_reg, ring->wptr); |
f93bdefe AD |
362 | (void)RREG32(ring->wptr_reg); |
363 | } | |
364 | ||
75923280 AD |
365 | /** |
366 | * radeon_ring_free_size - update the free size | |
367 | * | |
368 | * @rdev: radeon_device pointer | |
369 | * @ring: radeon_ring structure holding ring information | |
370 | * | |
371 | * Update the free dw slots in the ring buffer (all asics). | |
372 | */ | |
e32eb50d | 373 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 374 | { |
f93bdefe | 375 | ring->rptr = radeon_ring_get_rptr(rdev, ring); |
771fe6b9 | 376 | /* This works because ring_size is a power of 2 */ |
e32eb50d CK |
377 | ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); |
378 | ring->ring_free_dw -= ring->wptr; | |
379 | ring->ring_free_dw &= ring->ptr_mask; | |
380 | if (!ring->ring_free_dw) { | |
381 | ring->ring_free_dw = ring->ring_size / 4; | |
771fe6b9 JG |
382 | } |
383 | } | |
384 | ||
75923280 AD |
385 | /** |
386 | * radeon_ring_alloc - allocate space on the ring buffer | |
387 | * | |
388 | * @rdev: radeon_device pointer | |
389 | * @ring: radeon_ring structure holding ring information | |
390 | * @ndw: number of dwords to allocate in the ring buffer | |
391 | * | |
392 | * Allocate @ndw dwords in the ring buffer (all asics). | |
393 | * Returns 0 on success, error on failure. | |
394 | */ | |
e32eb50d | 395 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
771fe6b9 JG |
396 | { |
397 | int r; | |
398 | ||
fd5d93a0 AD |
399 | /* make sure we aren't trying to allocate more space than there is on the ring */ |
400 | if (ndw > (ring->ring_size / 4)) | |
401 | return -ENOMEM; | |
771fe6b9 JG |
402 | /* Align requested size with padding so unlock_commit can |
403 | * pad safely */ | |
8444d5c6 JG |
404 | radeon_ring_free_size(rdev, ring); |
405 | if (ring->ring_free_dw == (ring->ring_size / 4)) { | |
406 | /* This is an empty ring update lockup info to avoid | |
407 | * false positive. | |
408 | */ | |
409 | radeon_ring_lockup_update(ring); | |
410 | } | |
e32eb50d CK |
411 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
412 | while (ndw > (ring->ring_free_dw - 1)) { | |
413 | radeon_ring_free_size(rdev, ring); | |
414 | if (ndw < ring->ring_free_dw) { | |
771fe6b9 JG |
415 | break; |
416 | } | |
8b25ed34 | 417 | r = radeon_fence_wait_next_locked(rdev, ring->idx); |
91700f3c | 418 | if (r) |
771fe6b9 | 419 | return r; |
771fe6b9 | 420 | } |
e32eb50d CK |
421 | ring->count_dw = ndw; |
422 | ring->wptr_old = ring->wptr; | |
771fe6b9 JG |
423 | return 0; |
424 | } | |
425 | ||
75923280 AD |
426 | /** |
427 | * radeon_ring_lock - lock the ring and allocate space on it | |
428 | * | |
429 | * @rdev: radeon_device pointer | |
430 | * @ring: radeon_ring structure holding ring information | |
431 | * @ndw: number of dwords to allocate in the ring buffer | |
432 | * | |
433 | * Lock the ring and allocate @ndw dwords in the ring buffer | |
434 | * (all asics). | |
435 | * Returns 0 on success, error on failure. | |
436 | */ | |
e32eb50d | 437 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
91700f3c MG |
438 | { |
439 | int r; | |
440 | ||
d6999bc7 | 441 | mutex_lock(&rdev->ring_lock); |
e32eb50d | 442 | r = radeon_ring_alloc(rdev, ring, ndw); |
91700f3c | 443 | if (r) { |
d6999bc7 | 444 | mutex_unlock(&rdev->ring_lock); |
91700f3c MG |
445 | return r; |
446 | } | |
447 | return 0; | |
448 | } | |
449 | ||
75923280 AD |
450 | /** |
451 | * radeon_ring_commit - tell the GPU to execute the new | |
452 | * commands on the ring buffer | |
453 | * | |
454 | * @rdev: radeon_device pointer | |
455 | * @ring: radeon_ring structure holding ring information | |
456 | * | |
457 | * Update the wptr (write pointer) to tell the GPU to | |
458 | * execute new commands on the ring buffer (all asics). | |
459 | */ | |
e32eb50d | 460 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 461 | { |
771fe6b9 | 462 | /* We pad to match fetch size */ |
07a71330 | 463 | while (ring->wptr & ring->align_mask) { |
78c5560a | 464 | radeon_ring_write(ring, ring->nop); |
771fe6b9 | 465 | } |
85b2331b | 466 | mb(); |
f93bdefe | 467 | radeon_ring_set_wptr(rdev, ring); |
91700f3c MG |
468 | } |
469 | ||
75923280 AD |
470 | /** |
471 | * radeon_ring_unlock_commit - tell the GPU to execute the new | |
472 | * commands on the ring buffer and unlock it | |
473 | * | |
474 | * @rdev: radeon_device pointer | |
475 | * @ring: radeon_ring structure holding ring information | |
476 | * | |
477 | * Call radeon_ring_commit() then unlock the ring (all asics). | |
478 | */ | |
e32eb50d | 479 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
91700f3c | 480 | { |
e32eb50d | 481 | radeon_ring_commit(rdev, ring); |
d6999bc7 | 482 | mutex_unlock(&rdev->ring_lock); |
771fe6b9 JG |
483 | } |
484 | ||
75923280 AD |
485 | /** |
486 | * radeon_ring_undo - reset the wptr | |
487 | * | |
488 | * @ring: radeon_ring structure holding ring information | |
489 | * | |
501f9d4c | 490 | * Reset the driver's copy of the wptr (all asics). |
75923280 | 491 | */ |
d6999bc7 | 492 | void radeon_ring_undo(struct radeon_ring *ring) |
771fe6b9 | 493 | { |
e32eb50d | 494 | ring->wptr = ring->wptr_old; |
d6999bc7 CK |
495 | } |
496 | ||
75923280 AD |
497 | /** |
498 | * radeon_ring_unlock_undo - reset the wptr and unlock the ring | |
499 | * | |
500 | * @ring: radeon_ring structure holding ring information | |
501 | * | |
502 | * Call radeon_ring_undo() then unlock the ring (all asics). | |
503 | */ | |
d6999bc7 CK |
504 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
505 | { | |
506 | radeon_ring_undo(ring); | |
507 | mutex_unlock(&rdev->ring_lock); | |
771fe6b9 JG |
508 | } |
509 | ||
75923280 AD |
510 | /** |
511 | * radeon_ring_force_activity - add some nop packets to the ring | |
512 | * | |
513 | * @rdev: radeon_device pointer | |
514 | * @ring: radeon_ring structure holding ring information | |
515 | * | |
516 | * Add some nop packets to the ring to force activity (all asics). | |
517 | * Used for lockup detection to see if the rptr is advancing. | |
518 | */ | |
7b9ef16b CK |
519 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring) |
520 | { | |
521 | int r; | |
522 | ||
7b9ef16b CK |
523 | radeon_ring_free_size(rdev, ring); |
524 | if (ring->rptr == ring->wptr) { | |
525 | r = radeon_ring_alloc(rdev, ring, 1); | |
526 | if (!r) { | |
527 | radeon_ring_write(ring, ring->nop); | |
528 | radeon_ring_commit(rdev, ring); | |
529 | } | |
530 | } | |
7b9ef16b CK |
531 | } |
532 | ||
75923280 | 533 | /** |
501f9d4c | 534 | * radeon_ring_lockup_update - update lockup variables |
75923280 AD |
535 | * |
536 | * @ring: radeon_ring structure holding ring information | |
537 | * | |
538 | * Update the last rptr value and timestamp (all asics). | |
539 | */ | |
069211e5 CK |
540 | void radeon_ring_lockup_update(struct radeon_ring *ring) |
541 | { | |
542 | ring->last_rptr = ring->rptr; | |
543 | ring->last_activity = jiffies; | |
544 | } | |
545 | ||
546 | /** | |
547 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information | |
548 | * @rdev: radeon device structure | |
549 | * @ring: radeon_ring structure holding ring information | |
550 | * | |
551 | * We don't need to initialize the lockup tracking information as we will either | |
552 | * have CP rptr to a different value of jiffies wrap around which will force | |
553 | * initialization of the lockup tracking informations. | |
554 | * | |
555 | * A possible false positivie is if we get call after while and last_cp_rptr == | |
556 | * the current CP rptr, even if it's unlikely it might happen. To avoid this | |
557 | * if the elapsed time since last call is bigger than 2 second than we return | |
558 | * false and update the tracking information. Due to this the caller must call | |
559 | * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported | |
560 | * the fencing code should be cautious about that. | |
561 | * | |
562 | * Caller should write to the ring to force CP to do something so we don't get | |
563 | * false positive when CP is just gived nothing to do. | |
564 | * | |
565 | **/ | |
566 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) | |
567 | { | |
568 | unsigned long cjiffies, elapsed; | |
069211e5 CK |
569 | |
570 | cjiffies = jiffies; | |
571 | if (!time_after(cjiffies, ring->last_activity)) { | |
572 | /* likely a wrap around */ | |
573 | radeon_ring_lockup_update(ring); | |
574 | return false; | |
575 | } | |
f93bdefe | 576 | ring->rptr = radeon_ring_get_rptr(rdev, ring); |
069211e5 CK |
577 | if (ring->rptr != ring->last_rptr) { |
578 | /* CP is still working no lockup */ | |
579 | radeon_ring_lockup_update(ring); | |
580 | return false; | |
581 | } | |
582 | elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); | |
3368ff0c | 583 | if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { |
069211e5 CK |
584 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
585 | return true; | |
586 | } | |
587 | /* give a chance to the GPU ... */ | |
588 | return false; | |
589 | } | |
590 | ||
55d7c221 CK |
591 | /** |
592 | * radeon_ring_backup - Back up the content of a ring | |
593 | * | |
594 | * @rdev: radeon_device pointer | |
595 | * @ring: the ring we want to back up | |
596 | * | |
597 | * Saves all unprocessed commits from a ring, returns the number of dwords saved. | |
598 | */ | |
599 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, | |
600 | uint32_t **data) | |
601 | { | |
602 | unsigned size, ptr, i; | |
55d7c221 CK |
603 | |
604 | /* just in case lock the ring */ | |
605 | mutex_lock(&rdev->ring_lock); | |
606 | *data = NULL; | |
607 | ||
89d35807 | 608 | if (ring->ring_obj == NULL) { |
55d7c221 CK |
609 | mutex_unlock(&rdev->ring_lock); |
610 | return 0; | |
611 | } | |
612 | ||
613 | /* it doesn't make sense to save anything if all fences are signaled */ | |
8b25ed34 | 614 | if (!radeon_fence_count_emitted(rdev, ring->idx)) { |
55d7c221 CK |
615 | mutex_unlock(&rdev->ring_lock); |
616 | return 0; | |
617 | } | |
618 | ||
619 | /* calculate the number of dw on the ring */ | |
89d35807 AD |
620 | if (ring->rptr_save_reg) |
621 | ptr = RREG32(ring->rptr_save_reg); | |
622 | else if (rdev->wb.enabled) | |
623 | ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); | |
624 | else { | |
625 | /* no way to read back the next rptr */ | |
626 | mutex_unlock(&rdev->ring_lock); | |
627 | return 0; | |
628 | } | |
629 | ||
55d7c221 CK |
630 | size = ring->wptr + (ring->ring_size / 4); |
631 | size -= ptr; | |
632 | size &= ring->ptr_mask; | |
633 | if (size == 0) { | |
634 | mutex_unlock(&rdev->ring_lock); | |
635 | return 0; | |
636 | } | |
637 | ||
638 | /* and then save the content of the ring */ | |
1e179d4e DC |
639 | *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); |
640 | if (!*data) { | |
641 | mutex_unlock(&rdev->ring_lock); | |
642 | return 0; | |
643 | } | |
55d7c221 CK |
644 | for (i = 0; i < size; ++i) { |
645 | (*data)[i] = ring->ring[ptr++]; | |
646 | ptr &= ring->ptr_mask; | |
647 | } | |
648 | ||
649 | mutex_unlock(&rdev->ring_lock); | |
650 | return size; | |
651 | } | |
652 | ||
653 | /** | |
654 | * radeon_ring_restore - append saved commands to the ring again | |
655 | * | |
656 | * @rdev: radeon_device pointer | |
657 | * @ring: ring to append commands to | |
658 | * @size: number of dwords we want to write | |
659 | * @data: saved commands | |
660 | * | |
661 | * Allocates space on the ring and restore the previously saved commands. | |
662 | */ | |
663 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |
664 | unsigned size, uint32_t *data) | |
665 | { | |
666 | int i, r; | |
667 | ||
668 | if (!size || !data) | |
669 | return 0; | |
670 | ||
671 | /* restore the saved ring content */ | |
672 | r = radeon_ring_lock(rdev, ring, size); | |
673 | if (r) | |
674 | return r; | |
675 | ||
676 | for (i = 0; i < size; ++i) { | |
677 | radeon_ring_write(ring, data[i]); | |
678 | } | |
679 | ||
680 | radeon_ring_unlock_commit(rdev, ring); | |
681 | kfree(data); | |
682 | return 0; | |
683 | } | |
684 | ||
75923280 AD |
685 | /** |
686 | * radeon_ring_init - init driver ring struct. | |
687 | * | |
688 | * @rdev: radeon_device pointer | |
689 | * @ring: radeon_ring structure holding ring information | |
690 | * @ring_size: size of the ring | |
691 | * @rptr_offs: offset of the rptr writeback location in the WB buffer | |
692 | * @rptr_reg: MMIO offset of the rptr register | |
693 | * @wptr_reg: MMIO offset of the wptr register | |
75923280 AD |
694 | * @nop: nop packet for this ring |
695 | * | |
696 | * Initialize the driver information for the selected ring (all asics). | |
697 | * Returns 0 on success, error on failure. | |
698 | */ | |
e32eb50d | 699 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
2e1e6dad | 700 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop) |
771fe6b9 JG |
701 | { |
702 | int r; | |
703 | ||
e32eb50d CK |
704 | ring->ring_size = ring_size; |
705 | ring->rptr_offs = rptr_offs; | |
706 | ring->rptr_reg = rptr_reg; | |
707 | ring->wptr_reg = wptr_reg; | |
78c5560a | 708 | ring->nop = nop; |
771fe6b9 | 709 | /* Allocate ring buffer */ |
e32eb50d CK |
710 | if (ring->ring_obj == NULL) { |
711 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, | |
40f5cf99 AD |
712 | RADEON_GEM_DOMAIN_GTT, |
713 | NULL, &ring->ring_obj); | |
771fe6b9 | 714 | if (r) { |
4c788679 | 715 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
771fe6b9 JG |
716 | return r; |
717 | } | |
e32eb50d | 718 | r = radeon_bo_reserve(ring->ring_obj, false); |
4c788679 JG |
719 | if (unlikely(r != 0)) |
720 | return r; | |
e32eb50d CK |
721 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
722 | &ring->gpu_addr); | |
771fe6b9 | 723 | if (r) { |
e32eb50d | 724 | radeon_bo_unreserve(ring->ring_obj); |
4c788679 | 725 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
771fe6b9 JG |
726 | return r; |
727 | } | |
e32eb50d CK |
728 | r = radeon_bo_kmap(ring->ring_obj, |
729 | (void **)&ring->ring); | |
730 | radeon_bo_unreserve(ring->ring_obj); | |
771fe6b9 | 731 | if (r) { |
4c788679 | 732 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
771fe6b9 JG |
733 | return r; |
734 | } | |
735 | } | |
e32eb50d CK |
736 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
737 | ring->ring_free_dw = ring->ring_size / 4; | |
89d35807 AD |
738 | if (rdev->wb.enabled) { |
739 | u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); | |
740 | ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; | |
741 | ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; | |
742 | } | |
ec1a6cce CK |
743 | if (radeon_debugfs_ring_init(rdev, ring)) { |
744 | DRM_ERROR("Failed to register debugfs file for rings !\n"); | |
745 | } | |
48c0ac99 | 746 | radeon_ring_lockup_update(ring); |
771fe6b9 JG |
747 | return 0; |
748 | } | |
749 | ||
75923280 AD |
750 | /** |
751 | * radeon_ring_fini - tear down the driver ring struct. | |
752 | * | |
753 | * @rdev: radeon_device pointer | |
754 | * @ring: radeon_ring structure holding ring information | |
755 | * | |
756 | * Tear down the driver information for the selected ring (all asics). | |
757 | */ | |
e32eb50d | 758 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 759 | { |
4c788679 | 760 | int r; |
ca2af923 | 761 | struct radeon_bo *ring_obj; |
4c788679 | 762 | |
d6999bc7 | 763 | mutex_lock(&rdev->ring_lock); |
e32eb50d | 764 | ring_obj = ring->ring_obj; |
d6999bc7 | 765 | ring->ready = false; |
e32eb50d CK |
766 | ring->ring = NULL; |
767 | ring->ring_obj = NULL; | |
d6999bc7 | 768 | mutex_unlock(&rdev->ring_lock); |
ca2af923 AD |
769 | |
770 | if (ring_obj) { | |
771 | r = radeon_bo_reserve(ring_obj, false); | |
4c788679 | 772 | if (likely(r == 0)) { |
ca2af923 AD |
773 | radeon_bo_kunmap(ring_obj); |
774 | radeon_bo_unpin(ring_obj); | |
775 | radeon_bo_unreserve(ring_obj); | |
4c788679 | 776 | } |
ca2af923 | 777 | radeon_bo_unref(&ring_obj); |
771fe6b9 | 778 | } |
771fe6b9 JG |
779 | } |
780 | ||
771fe6b9 JG |
781 | /* |
782 | * Debugfs info | |
783 | */ | |
784 | #if defined(CONFIG_DEBUG_FS) | |
af9720f4 CK |
785 | |
786 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) | |
787 | { | |
788 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
789 | struct drm_device *dev = node->minor->dev; | |
790 | struct radeon_device *rdev = dev->dev_private; | |
791 | int ridx = *(int*)node->info_ent->data; | |
792 | struct radeon_ring *ring = &rdev->ring[ridx]; | |
df893a25 CK |
793 | |
794 | uint32_t rptr, wptr, rptr_next; | |
af9720f4 CK |
795 | unsigned count, i, j; |
796 | ||
797 | radeon_ring_free_size(rdev, ring); | |
798 | count = (ring->ring_size / 4) - ring->ring_free_dw; | |
df893a25 CK |
799 | |
800 | wptr = radeon_ring_get_wptr(rdev, ring); | |
801 | seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", | |
802 | ring->wptr_reg, wptr, wptr); | |
803 | ||
804 | rptr = radeon_ring_get_rptr(rdev, ring); | |
805 | seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", | |
806 | ring->rptr_reg, rptr, rptr); | |
807 | ||
45df6803 | 808 | if (ring->rptr_save_reg) { |
df893a25 CK |
809 | rptr_next = RREG32(ring->rptr_save_reg); |
810 | seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n", | |
811 | ring->rptr_save_reg, rptr_next, rptr_next); | |
812 | } else | |
813 | rptr_next = ~0; | |
814 | ||
815 | seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", | |
816 | ring->wptr, ring->wptr); | |
817 | seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", | |
818 | ring->rptr, ring->rptr); | |
819 | seq_printf(m, "last semaphore signal addr : 0x%016llx\n", | |
820 | ring->last_semaphore_signal_addr); | |
821 | seq_printf(m, "last semaphore wait addr : 0x%016llx\n", | |
822 | ring->last_semaphore_wait_addr); | |
af9720f4 CK |
823 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
824 | seq_printf(m, "%u dwords in ring\n", count); | |
df893a25 CK |
825 | |
826 | if (!ring->ready) | |
827 | return 0; | |
828 | ||
4d009190 JG |
829 | /* print 8 dw before current rptr as often it's the last executed |
830 | * packet that is the root issue | |
831 | */ | |
df893a25 CK |
832 | i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; |
833 | for (j = 0; j <= (count + 32); j++) { | |
834 | seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]); | |
835 | if (rptr == i) | |
836 | seq_puts(m, " *"); | |
837 | if (rptr_next == i) | |
838 | seq_puts(m, " #"); | |
839 | seq_puts(m, "\n"); | |
840 | i = (i + 1) & ring->ptr_mask; | |
af9720f4 CK |
841 | } |
842 | return 0; | |
843 | } | |
844 | ||
f2ba57b5 CK |
845 | static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX; |
846 | static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; | |
847 | static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; | |
848 | static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX; | |
849 | static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; | |
850 | static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX; | |
af9720f4 CK |
851 | |
852 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { | |
f2ba57b5 CK |
853 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index}, |
854 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index}, | |
855 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index}, | |
856 | {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index}, | |
857 | {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index}, | |
858 | {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index}, | |
af9720f4 CK |
859 | }; |
860 | ||
711a9729 CK |
861 | static int radeon_debugfs_sa_info(struct seq_file *m, void *data) |
862 | { | |
863 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
864 | struct drm_device *dev = node->minor->dev; | |
865 | struct radeon_device *rdev = dev->dev_private; | |
866 | ||
c507f7ef | 867 | radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); |
711a9729 CK |
868 | |
869 | return 0; | |
870 | ||
871 | } | |
872 | ||
873 | static struct drm_info_list radeon_debugfs_sa_list[] = { | |
874 | {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, | |
875 | }; | |
876 | ||
771fe6b9 JG |
877 | #endif |
878 | ||
1109ca09 | 879 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
af9720f4 CK |
880 | { |
881 | #if defined(CONFIG_DEBUG_FS) | |
ec1a6cce CK |
882 | unsigned i; |
883 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { | |
884 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; | |
885 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; | |
886 | unsigned r; | |
887 | ||
888 | if (&rdev->ring[ridx] != ring) | |
889 | continue; | |
890 | ||
891 | r = radeon_debugfs_add_files(rdev, info, 1); | |
892 | if (r) | |
893 | return r; | |
894 | } | |
af9720f4 | 895 | #endif |
ec1a6cce | 896 | return 0; |
af9720f4 CK |
897 | } |
898 | ||
1109ca09 | 899 | static int radeon_debugfs_sa_init(struct radeon_device *rdev) |
771fe6b9 JG |
900 | { |
901 | #if defined(CONFIG_DEBUG_FS) | |
c507f7ef | 902 | return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); |
771fe6b9 JG |
903 | #else |
904 | return 0; | |
905 | #endif | |
906 | } |