[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_ring.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include <linux/seq_file.h>
#include <linux/slab.h>
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon_reg.h"
#include "radeon.h"
#include "atom.h"

int radeon_debugfs_ib_init(struct radeon_device *rdev);
int radeon_debugfs_ring_init(struct radeon_device *rdev);

u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
{
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	u32 pg_idx, pg_offset;
	u32 idx_value = 0;
	int new_page;

	pg_idx = (idx * 4) / PAGE_SIZE;
	pg_offset = (idx * 4) % PAGE_SIZE;

	if (ibc->kpage_idx[0] == pg_idx)
		return ibc->kpage[0][pg_offset/4];
	if (ibc->kpage_idx[1] == pg_idx)
		return ibc->kpage[1][pg_offset/4];

	new_page = radeon_cs_update_pages(p, pg_idx);
	if (new_page < 0) {
		p->parser_error = new_page;
		return 0;
	}

	idx_value = ibc->kpage[new_page][pg_offset/4];
	return idx_value;
}

void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
{
#if DRM_DEBUG_CODE
	if (ring->count_dw <= 0) {
		DRM_ERROR("radeon: writting more dword to ring than expected !\n");
	}
#endif
	ring->ring[ring->wptr++] = v;
	ring->wptr &= ring->ptr_mask;
	ring->count_dw--;
	ring->ring_free_dw--;
}

/*
 * IB.
 */
bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib)
{
	bool done = false;

	/* only free ib which have been emited */
	if (ib->fence && ib->fence->emitted) {
		if (radeon_fence_signaled(ib->fence)) {
			radeon_fence_unref(&ib->fence);
			radeon_sa_bo_free(rdev, &ib->sa_bo);
			done = true;
		}
	}
	return done;
}

int radeon_ib_get(struct radeon_device *rdev, int ring,
		  struct radeon_ib **ib, unsigned size)
{
	struct radeon_fence *fence;
	unsigned cretry = 0;
	int r = 0, i, idx;

	*ib = NULL;
	/* align size on 256 bytes */
	size = ALIGN(size, 256);

	r = radeon_fence_create(rdev, &fence, ring);
	if (r) {
		dev_err(rdev->dev, "failed to create fence for new IB\n");
		return r;
	}

	radeon_mutex_lock(&rdev->ib_pool.mutex);
	idx = rdev->ib_pool.head_id;
retry:
	if (cretry > 5) {
		dev_err(rdev->dev, "failed to get an ib after 5 retry\n");
		radeon_mutex_unlock(&rdev->ib_pool.mutex);
		radeon_fence_unref(&fence);
		return -ENOMEM;
	}
	cretry++;
	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
		radeon_ib_try_free(rdev, &rdev->ib_pool.ibs[idx]);
		if (rdev->ib_pool.ibs[idx].fence == NULL) {
			r = radeon_sa_bo_new(rdev, &rdev->ib_pool.sa_manager,
					     &rdev->ib_pool.ibs[idx].sa_bo,
					     size, 256);
			if (!r) {
				*ib = &rdev->ib_pool.ibs[idx];
				(*ib)->ptr = rdev->ib_pool.sa_manager.cpu_ptr;
				(*ib)->ptr += ((*ib)->sa_bo.offset >> 2);
				(*ib)->gpu_addr = rdev->ib_pool.sa_manager.gpu_addr;
				(*ib)->gpu_addr += (*ib)->sa_bo.offset;
				(*ib)->fence = fence;
				(*ib)->vm_id = 0;
				/* ib are most likely to be allocated in a ring fashion
				 * thus rdev->ib_pool.head_id should be the id of the
				 * oldest ib
				 */
				rdev->ib_pool.head_id = (1 + idx);
				rdev->ib_pool.head_id &= (RADEON_IB_POOL_SIZE - 1);
				radeon_mutex_unlock(&rdev->ib_pool.mutex);
				return 0;
			}
		}
		idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1);
	}
	/* this should be rare event, ie all ib scheduled none signaled yet.
	 */
	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
		if (rdev->ib_pool.ibs[idx].fence && rdev->ib_pool.ibs[idx].fence->emitted) {
			r = radeon_fence_wait(rdev->ib_pool.ibs[idx].fence, false);
			if (!r) {
				goto retry;
			}
			/* an error happened */
			break;
		}
		idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1);
	}
	radeon_mutex_unlock(&rdev->ib_pool.mutex);
	radeon_fence_unref(&fence);
	return r;
}

void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
{
	struct radeon_ib *tmp = *ib;

	*ib = NULL;
	if (tmp == NULL) {
		return;
	}
	radeon_mutex_lock(&rdev->ib_pool.mutex);
	if (tmp->fence && !tmp->fence->emitted) {
		radeon_sa_bo_free(rdev, &tmp->sa_bo);
		radeon_fence_unref(&tmp->fence);
	}
	radeon_mutex_unlock(&rdev->ib_pool.mutex);
}

int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
{
	struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
	int r = 0;

	if (!ib->length_dw || !ring->ready) {
		/* TODO: Nothings in the ib we should report. */
		DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
		return -EINVAL;
	}

	/* 64 dwords should be enough for fence too */
	r = radeon_ring_lock(rdev, ring, 64);
	if (r) {
		DRM_ERROR("radeon: scheduling IB failed (%d).\n", r);
		return r;
	}
	radeon_ring_ib_execute(rdev, ib->fence->ring, ib);
	radeon_fence_emit(rdev, ib->fence);
	radeon_ring_unlock_commit(rdev, ring);
	return 0;
}

int radeon_ib_pool_init(struct radeon_device *rdev)
{
	struct radeon_sa_manager tmp;
	int i, r;

	r = radeon_sa_bo_manager_init(rdev, &tmp,
				      RADEON_IB_POOL_SIZE*64*1024,
				      RADEON_GEM_DOMAIN_GTT);
	if (r) {
		return r;
	}

	radeon_mutex_lock(&rdev->ib_pool.mutex);
	if (rdev->ib_pool.ready) {
		radeon_mutex_unlock(&rdev->ib_pool.mutex);
		radeon_sa_bo_manager_fini(rdev, &tmp);
		return 0;
	}

	rdev->ib_pool.sa_manager = tmp;
	INIT_LIST_HEAD(&rdev->ib_pool.sa_manager.sa_bo);
	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
		rdev->ib_pool.ibs[i].fence = NULL;
		rdev->ib_pool.ibs[i].idx = i;
		rdev->ib_pool.ibs[i].length_dw = 0;
		INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].sa_bo.list);
	}
	rdev->ib_pool.head_id = 0;
	rdev->ib_pool.ready = true;
	DRM_INFO("radeon: ib pool ready.\n");

	if (radeon_debugfs_ib_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for IB !\n");
	}
	if (radeon_debugfs_ring_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for rings !\n");
	}
	radeon_mutex_unlock(&rdev->ib_pool.mutex);
	return 0;
}

void radeon_ib_pool_fini(struct radeon_device *rdev)
{
	unsigned i;

	radeon_mutex_lock(&rdev->ib_pool.mutex);
	if (rdev->ib_pool.ready) {
		for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
			radeon_sa_bo_free(rdev, &rdev->ib_pool.ibs[i].sa_bo);
			radeon_fence_unref(&rdev->ib_pool.ibs[i].fence);
		}
		radeon_sa_bo_manager_fini(rdev, &rdev->ib_pool.sa_manager);
		rdev->ib_pool.ready = false;
	}
	radeon_mutex_unlock(&rdev->ib_pool.mutex);
}

int radeon_ib_pool_start(struct radeon_device *rdev)
{
	return radeon_sa_bo_manager_start(rdev, &rdev->ib_pool.sa_manager);
}

int radeon_ib_pool_suspend(struct radeon_device *rdev)
{
	return radeon_sa_bo_manager_suspend(rdev, &rdev->ib_pool.sa_manager);
}

/*
 * Ring.
 */
int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *ring)
{
	/* r1xx-r5xx only has CP ring */
	if (rdev->family < CHIP_R600)
		return RADEON_RING_TYPE_GFX_INDEX;

	if (rdev->family >= CHIP_CAYMAN) {
		if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX])
			return CAYMAN_RING_TYPE_CP1_INDEX;
		else if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX])
			return CAYMAN_RING_TYPE_CP2_INDEX;
	}
	return RADEON_RING_TYPE_GFX_INDEX;
}

void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
{
	u32 rptr;

	if (rdev->wb.enabled)
		rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
	else
		rptr = RREG32(ring->rptr_reg);
	ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
	/* This works because ring_size is a power of 2 */
	ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
	ring->ring_free_dw -= ring->wptr;
	ring->ring_free_dw &= ring->ptr_mask;
	if (!ring->ring_free_dw) {
		ring->ring_free_dw = ring->ring_size / 4;
	}
}


int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
{
	int r;

	/* Align requested size with padding so unlock_commit can
	 * pad safely */
	ndw = (ndw + ring->align_mask) & ~ring->align_mask;
	while (ndw > (ring->ring_free_dw - 1)) {
		radeon_ring_free_size(rdev, ring);
		if (ndw < ring->ring_free_dw) {
			break;
		}
		r = radeon_fence_wait_next(rdev, radeon_ring_index(rdev, ring));
		if (r)
			return r;
	}
	ring->count_dw = ndw;
	ring->wptr_old = ring->wptr;
	return 0;
}

int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
{
	int r;

	mutex_lock(&ring->mutex);
	r = radeon_ring_alloc(rdev, ring, ndw);
	if (r) {
		mutex_unlock(&ring->mutex);
		return r;
	}
	return 0;
}

void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
{
	unsigned count_dw_pad;
	unsigned i;

	/* We pad to match fetch size */
	count_dw_pad = (ring->align_mask + 1) -
		       (ring->wptr & ring->align_mask);
	for (i = 0; i < count_dw_pad; i++) {
		radeon_ring_write(ring, ring->nop);
	}
	DRM_MEMORYBARRIER();
	WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
	(void)RREG32(ring->wptr_reg);
}

void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
{
	radeon_ring_commit(rdev, ring);
	mutex_unlock(&ring->mutex);
}

void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
{
	ring->wptr = ring->wptr_old;
	mutex_unlock(&ring->mutex);
}

int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
		     unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
		     u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop)
{
	int r;

	ring->ring_size = ring_size;
	ring->rptr_offs = rptr_offs;
	ring->rptr_reg = rptr_reg;
	ring->wptr_reg = wptr_reg;
	ring->ptr_reg_shift = ptr_reg_shift;
	ring->ptr_reg_mask = ptr_reg_mask;
	ring->nop = nop;
	/* Allocate ring buffer */
	if (ring->ring_obj == NULL) {
		r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
					RADEON_GEM_DOMAIN_GTT,
					&ring->ring_obj);
		if (r) {
			dev_err(rdev->dev, "(%d) ring create failed\n", r);
			return r;
		}
		r = radeon_bo_reserve(ring->ring_obj, false);
		if (unlikely(r != 0))
			return r;
		r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
					&ring->gpu_addr);
		if (r) {
			radeon_bo_unreserve(ring->ring_obj);
			dev_err(rdev->dev, "(%d) ring pin failed\n", r);
			return r;
		}
		r = radeon_bo_kmap(ring->ring_obj,
				       (void **)&ring->ring);
		radeon_bo_unreserve(ring->ring_obj);
		if (r) {
			dev_err(rdev->dev, "(%d) ring map failed\n", r);
			return r;
		}
	}
	ring->ptr_mask = (ring->ring_size / 4) - 1;
	ring->ring_free_dw = ring->ring_size / 4;
	return 0;
}

void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
{
	int r;
	struct radeon_bo *ring_obj;

	mutex_lock(&ring->mutex);
	ring_obj = ring->ring_obj;
	ring->ring = NULL;
	ring->ring_obj = NULL;
	mutex_unlock(&ring->mutex);

	if (ring_obj) {
		r = radeon_bo_reserve(ring_obj, false);
		if (likely(r == 0)) {
			radeon_bo_kunmap(ring_obj);
			radeon_bo_unpin(ring_obj);
			radeon_bo_unreserve(ring_obj);
		}
		radeon_bo_unref(&ring_obj);
	}
}

/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)

static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
	int ridx = *(int*)node->info_ent->data;
	struct radeon_ring *ring = &rdev->ring[ridx];
	unsigned count, i, j;

	radeon_ring_free_size(rdev, ring);
	count = (ring->ring_size / 4) - ring->ring_free_dw;
	seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg));
	seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg));
	seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr);
	seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr);
	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
	seq_printf(m, "%u dwords in ring\n", count);
	i = ring->rptr;
	for (j = 0; j <= count; j++) {
		seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
		i = (i + 1) & ring->ptr_mask;
	}
	return 0;
}

static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;

static struct drm_info_list radeon_debugfs_ring_info_list[] = {
	{"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},
	{"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},
	{"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},
};

static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct radeon_ib *ib = node->info_ent->data;
	unsigned i;

	if (ib == NULL) {
		return 0;
	}
	seq_printf(m, "IB %04u\n", ib->idx);
	seq_printf(m, "IB fence %p\n", ib->fence);
	seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
	for (i = 0; i < ib->length_dw; i++) {
		seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
	}
	return 0;
}

static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
#endif

int radeon_debugfs_ring_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, radeon_debugfs_ring_info_list,
					ARRAY_SIZE(radeon_debugfs_ring_info_list));
#else
	return 0;
#endif
}

int radeon_debugfs_ib_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	unsigned i;

	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
		sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
		radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
		radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
		radeon_debugfs_ib_list[i].driver_features = 0;
		radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
	}
	return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
					RADEON_IB_POOL_SIZE);
#else
	return 0;
#endif
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include <linux/seq_file.h>
5a0e3ad6	29	#include <linux/slab.h>
771fe6b9 JG	30	#include "drmP.h"
	31	#include "radeon_drm.h"
	32	#include "radeon_reg.h"
	33	#include "radeon.h"
	34	#include "atom.h"
	35
	36	int radeon_debugfs_ib_init(struct radeon_device *rdev);
af9720f4	37	int radeon_debugfs_ring_init(struct radeon_device *rdev);
771fe6b9	38
ce580fab AK	39	u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
	40	{
	41	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	42	u32 pg_idx, pg_offset;
	43	u32 idx_value = 0;
	44	int new_page;
	45
	46	pg_idx = (idx * 4) / PAGE_SIZE;
	47	pg_offset = (idx * 4) % PAGE_SIZE;
	48
	49	if (ibc->kpage_idx[0] == pg_idx)
	50	return ibc->kpage[0][pg_offset/4];
	51	if (ibc->kpage_idx[1] == pg_idx)
	52	return ibc->kpage[1][pg_offset/4];
	53
	54	new_page = radeon_cs_update_pages(p, pg_idx);
	55	if (new_page < 0) {
	56	p->parser_error = new_page;
	57	return 0;
	58	}
	59
	60	idx_value = ibc->kpage[new_page][pg_offset/4];
	61	return idx_value;
	62	}
	63
e32eb50d	64	void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
ce580fab AK	65	{
ce580fab AK	66	#if DRM_DEBUG_CODE
e32eb50d	67	if (ring->count_dw <= 0) {
ce580fab AK	68	DRM_ERROR("radeon: writting more dword to ring than expected !\n");
	69	}
	70	#endif
e32eb50d CK	71	ring->ring[ring->wptr++] = v;
	72	ring->wptr &= ring->ptr_mask;
	73	ring->count_dw--;
	74	ring->ring_free_dw--;
ce580fab AK	75	}
ce580fab AK	76
b15ba512 JG	77	/*
	78	* IB.
	79	*/
c1341e52	80	bool radeon_ib_try_free(struct radeon_device rdev, struct radeon_ib ib)
9f93ed39	81	{
b15ba512 JG	82	bool done = false;
	83
	84	/* only free ib which have been emited */
	85	if (ib->fence && ib->fence->emitted) {
	86	if (radeon_fence_signaled(ib->fence)) {
	87	radeon_fence_unref(&ib->fence);
	88	radeon_sa_bo_free(rdev, &ib->sa_bo);
	89	done = true;
	90	}
9f93ed39	91	}
b15ba512	92	return done;
9f93ed39 JG	93	}
9f93ed39 JG	94
69e130a6 JG	95	int radeon_ib_get(struct radeon_device *rdev, int ring,
69e130a6 JG	96	struct radeon_ib **ib, unsigned size)
771fe6b9 JG	97	{
771fe6b9 JG	98	struct radeon_fence *fence;
b15ba512 JG	99	unsigned cretry = 0;
b15ba512 JG	100	int r = 0, i, idx;
771fe6b9 JG	101
771fe6b9 JG	102	*ib = NULL;
69e130a6 JG	103	/* align size on 256 bytes */
69e130a6 JG	104	size = ALIGN(size, 256);
b15ba512	105
7b1f2485	106	r = radeon_fence_create(rdev, &fence, ring);
771fe6b9	107	if (r) {
91cb91be	108	dev_err(rdev->dev, "failed to create fence for new IB\n");
771fe6b9 JG	109	return r;
771fe6b9 JG	110	}
b15ba512	111
9fc04b50	112	radeon_mutex_lock(&rdev->ib_pool.mutex);
b15ba512 JG	113	idx = rdev->ib_pool.head_id;
	114	retry:
	115	if (cretry > 5) {
	116	dev_err(rdev->dev, "failed to get an ib after 5 retry\n");
9fc04b50	117	radeon_mutex_unlock(&rdev->ib_pool.mutex);
91cb91be	118	radeon_fence_unref(&fence);
b15ba512	119	return -ENOMEM;
771fe6b9	120	}
b15ba512 JG	121	cretry++;
	122	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
	123	radeon_ib_try_free(rdev, &rdev->ib_pool.ibs[idx]);
	124	if (rdev->ib_pool.ibs[idx].fence == NULL) {
	125	r = radeon_sa_bo_new(rdev, &rdev->ib_pool.sa_manager,
	126	&rdev->ib_pool.ibs[idx].sa_bo,
69e130a6	127	size, 256);
b15ba512 JG	128	if (!r) {
	129	*ib = &rdev->ib_pool.ibs[idx];
	130	(*ib)->ptr = rdev->ib_pool.sa_manager.cpu_ptr;
	131	(ib)->ptr += ((ib)->sa_bo.offset >> 2);
	132	(*ib)->gpu_addr = rdev->ib_pool.sa_manager.gpu_addr;
	133	(ib)->gpu_addr += (ib)->sa_bo.offset;
	134	(*ib)->fence = fence;
721604a1	135	(*ib)->vm_id = 0;
b15ba512 JG	136	/* ib are most likely to be allocated in a ring fashion
	137	* thus rdev->ib_pool.head_id should be the id of the
	138	* oldest ib
	139	*/
	140	rdev->ib_pool.head_id = (1 + idx);
	141	rdev->ib_pool.head_id &= (RADEON_IB_POOL_SIZE - 1);
9fc04b50	142	radeon_mutex_unlock(&rdev->ib_pool.mutex);
b15ba512 JG	143	return 0;
b15ba512 JG	144	}
91cb91be	145	}
b15ba512 JG	146	idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1);
	147	}
	148	/* this should be rare event, ie all ib scheduled none signaled yet.
	149	*/
	150	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
c1341e52	151	if (rdev->ib_pool.ibs[idx].fence && rdev->ib_pool.ibs[idx].fence->emitted) {
b15ba512 JG	152	r = radeon_fence_wait(rdev->ib_pool.ibs[idx].fence, false);
	153	if (!r) {
	154	goto retry;
	155	}
	156	/* an error happened */
	157	break;
	158	}
	159	idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1);
771fe6b9	160	}
9fc04b50	161	radeon_mutex_unlock(&rdev->ib_pool.mutex);
b15ba512 JG	162	radeon_fence_unref(&fence);
b15ba512 JG	163	return r;
771fe6b9 JG	164	}
	165
	166	void radeon_ib_free(struct radeon_device rdev, struct radeon_ib *ib)
	167	{
	168	struct radeon_ib tmp = ib;
	169
	170	*ib = NULL;
	171	if (tmp == NULL) {
	172	return;
	173	}
9fc04b50	174	radeon_mutex_lock(&rdev->ib_pool.mutex);
b15ba512 JG	175	if (tmp->fence && !tmp->fence->emitted) {
	176	radeon_sa_bo_free(rdev, &tmp->sa_bo);
	177	radeon_fence_unref(&tmp->fence);
	178	}
9fc04b50	179	radeon_mutex_unlock(&rdev->ib_pool.mutex);
771fe6b9 JG	180	}
771fe6b9 JG	181
771fe6b9 JG	182	int radeon_ib_schedule(struct radeon_device rdev, struct radeon_ib ib)
771fe6b9 JG	183	{
e32eb50d	184	struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
771fe6b9 JG	185	int r = 0;
771fe6b9 JG	186
e32eb50d	187	if (!ib->length_dw \|\| !ring->ready) {
771fe6b9	188	/* TODO: Nothings in the ib we should report. */
91cb91be	189	DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
771fe6b9 JG	190	return -EINVAL;
771fe6b9 JG	191	}
ecb114a1	192
6cdf6585	193	/* 64 dwords should be enough for fence too */
e32eb50d	194	r = radeon_ring_lock(rdev, ring, 64);
771fe6b9	195	if (r) {
ec4f2ac4	196	DRM_ERROR("radeon: scheduling IB failed (%d).\n", r);
771fe6b9 JG	197	return r;
771fe6b9 JG	198	}
4c87bc26	199	radeon_ring_ib_execute(rdev, ib->fence->ring, ib);
771fe6b9	200	radeon_fence_emit(rdev, ib->fence);
e32eb50d	201	radeon_ring_unlock_commit(rdev, ring);
771fe6b9 JG	202	return 0;
	203	}
	204
	205	int radeon_ib_pool_init(struct radeon_device *rdev)
	206	{
d54fbd49	207	struct radeon_sa_manager tmp;
b15ba512	208	int i, r;
771fe6b9	209
d54fbd49	210	r = radeon_sa_bo_manager_init(rdev, &tmp,
b15ba512 JG	211	RADEON_IB_POOL_SIZE641024,
b15ba512 JG	212	RADEON_GEM_DOMAIN_GTT);
771fe6b9	213	if (r) {
771fe6b9 JG	214	return r;
771fe6b9 JG	215	}
771fe6b9	216
9fc04b50	217	radeon_mutex_lock(&rdev->ib_pool.mutex);
d54fbd49	218	if (rdev->ib_pool.ready) {
9fc04b50	219	radeon_mutex_unlock(&rdev->ib_pool.mutex);
d54fbd49 JG	220	radeon_sa_bo_manager_fini(rdev, &tmp);
	221	return 0;
	222	}
	223
	224	rdev->ib_pool.sa_manager = tmp;
	225	INIT_LIST_HEAD(&rdev->ib_pool.sa_manager.sa_bo);
b15ba512 JG	226	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
b15ba512 JG	227	rdev->ib_pool.ibs[i].fence = NULL;
771fe6b9 JG	228	rdev->ib_pool.ibs[i].idx = i;
771fe6b9 JG	229	rdev->ib_pool.ibs[i].length_dw = 0;
b15ba512	230	INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].sa_bo.list);
771fe6b9	231	}
91cb91be	232	rdev->ib_pool.head_id = 0;
771fe6b9 JG	233	rdev->ib_pool.ready = true;
771fe6b9 JG	234	DRM_INFO("radeon: ib pool ready.\n");
b15ba512	235
771fe6b9 JG	236	if (radeon_debugfs_ib_init(rdev)) {
	237	DRM_ERROR("Failed to register debugfs file for IB !\n");
	238	}
af9720f4 CK	239	if (radeon_debugfs_ring_init(rdev)) {
	240	DRM_ERROR("Failed to register debugfs file for rings !\n");
	241	}
9fc04b50	242	radeon_mutex_unlock(&rdev->ib_pool.mutex);
b15ba512	243	return 0;
771fe6b9 JG	244	}
	245
	246	void radeon_ib_pool_fini(struct radeon_device *rdev)
	247	{
b15ba512	248	unsigned i;
4c788679	249
9fc04b50	250	radeon_mutex_lock(&rdev->ib_pool.mutex);
b15ba512 JG	251	if (rdev->ib_pool.ready) {
	252	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
	253	radeon_sa_bo_free(rdev, &rdev->ib_pool.ibs[i].sa_bo);
	254	radeon_fence_unref(&rdev->ib_pool.ibs[i].fence);
4c788679	255	}
b15ba512 JG	256	radeon_sa_bo_manager_fini(rdev, &rdev->ib_pool.sa_manager);
b15ba512 JG	257	rdev->ib_pool.ready = false;
771fe6b9	258	}
9fc04b50	259	radeon_mutex_unlock(&rdev->ib_pool.mutex);
771fe6b9 JG	260	}
771fe6b9 JG	261
b15ba512 JG	262	int radeon_ib_pool_start(struct radeon_device *rdev)
	263	{
	264	return radeon_sa_bo_manager_start(rdev, &rdev->ib_pool.sa_manager);
	265	}
	266
	267	int radeon_ib_pool_suspend(struct radeon_device *rdev)
	268	{
	269	return radeon_sa_bo_manager_suspend(rdev, &rdev->ib_pool.sa_manager);
	270	}
771fe6b9 JG	271
	272	/*
	273	* Ring.
	274	*/
e32eb50d	275	int radeon_ring_index(struct radeon_device rdev, struct radeon_ring ring)
bf852799 CK	276	{
	277	/* r1xx-r5xx only has CP ring */
	278	if (rdev->family < CHIP_R600)
	279	return RADEON_RING_TYPE_GFX_INDEX;
	280
	281	if (rdev->family >= CHIP_CAYMAN) {
e32eb50d	282	if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX])
bf852799	283	return CAYMAN_RING_TYPE_CP1_INDEX;
e32eb50d	284	else if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX])
bf852799 CK	285	return CAYMAN_RING_TYPE_CP2_INDEX;
	286	}
	287	return RADEON_RING_TYPE_GFX_INDEX;
	288	}
	289
e32eb50d	290	void radeon_ring_free_size(struct radeon_device rdev, struct radeon_ring ring)
771fe6b9	291	{
78c5560a AD	292	u32 rptr;
78c5560a AD	293
724c80e1	294	if (rdev->wb.enabled)
78c5560a	295	rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
5596a9db	296	else
78c5560a AD	297	rptr = RREG32(ring->rptr_reg);
78c5560a AD	298	ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
771fe6b9	299	/* This works because ring_size is a power of 2 */
e32eb50d CK	300	ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
	301	ring->ring_free_dw -= ring->wptr;
	302	ring->ring_free_dw &= ring->ptr_mask;
	303	if (!ring->ring_free_dw) {
	304	ring->ring_free_dw = ring->ring_size / 4;
771fe6b9 JG	305	}
	306	}
	307
7b1f2485	308
e32eb50d	309	int radeon_ring_alloc(struct radeon_device rdev, struct radeon_ring ring, unsigned ndw)
771fe6b9 JG	310	{
	311	int r;
	312
	313	/* Align requested size with padding so unlock_commit can
	314	* pad safely */
e32eb50d CK	315	ndw = (ndw + ring->align_mask) & ~ring->align_mask;
	316	while (ndw > (ring->ring_free_dw - 1)) {
	317	radeon_ring_free_size(rdev, ring);
	318	if (ndw < ring->ring_free_dw) {
771fe6b9 JG	319	break;
771fe6b9 JG	320	}
e32eb50d	321	r = radeon_fence_wait_next(rdev, radeon_ring_index(rdev, ring));
91700f3c	322	if (r)
771fe6b9	323	return r;
771fe6b9	324	}
e32eb50d CK	325	ring->count_dw = ndw;
e32eb50d CK	326	ring->wptr_old = ring->wptr;
771fe6b9 JG	327	return 0;
	328	}
	329
e32eb50d	330	int radeon_ring_lock(struct radeon_device rdev, struct radeon_ring ring, unsigned ndw)
91700f3c MG	331	{
	332	int r;
	333
e32eb50d CK	334	mutex_lock(&ring->mutex);
e32eb50d CK	335	r = radeon_ring_alloc(rdev, ring, ndw);
91700f3c	336	if (r) {
e32eb50d	337	mutex_unlock(&ring->mutex);
91700f3c MG	338	return r;
	339	}
	340	return 0;
	341	}
	342
e32eb50d	343	void radeon_ring_commit(struct radeon_device rdev, struct radeon_ring ring)
771fe6b9 JG	344	{
	345	unsigned count_dw_pad;
	346	unsigned i;
	347
	348	/* We pad to match fetch size */
e32eb50d CK	349	count_dw_pad = (ring->align_mask + 1) -
e32eb50d CK	350	(ring->wptr & ring->align_mask);
771fe6b9	351	for (i = 0; i < count_dw_pad; i++) {
78c5560a	352	radeon_ring_write(ring, ring->nop);
771fe6b9 JG	353	}
771fe6b9 JG	354	DRM_MEMORYBARRIER();
78c5560a	355	WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
e32eb50d	356	(void)RREG32(ring->wptr_reg);
91700f3c MG	357	}
91700f3c MG	358
e32eb50d	359	void radeon_ring_unlock_commit(struct radeon_device rdev, struct radeon_ring ring)
91700f3c	360	{
e32eb50d CK	361	radeon_ring_commit(rdev, ring);
e32eb50d CK	362	mutex_unlock(&ring->mutex);
771fe6b9 JG	363	}
771fe6b9 JG	364
e32eb50d	365	void radeon_ring_unlock_undo(struct radeon_device rdev, struct radeon_ring ring)
771fe6b9	366	{
e32eb50d CK	367	ring->wptr = ring->wptr_old;
e32eb50d CK	368	mutex_unlock(&ring->mutex);
771fe6b9 JG	369	}
771fe6b9 JG	370
e32eb50d	371	int radeon_ring_init(struct radeon_device rdev, struct radeon_ring ring, unsigned ring_size,
78c5560a AD	372	unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
78c5560a AD	373	u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop)
771fe6b9 JG	374	{
	375	int r;
	376
e32eb50d CK	377	ring->ring_size = ring_size;
	378	ring->rptr_offs = rptr_offs;
	379	ring->rptr_reg = rptr_reg;
	380	ring->wptr_reg = wptr_reg;
78c5560a AD	381	ring->ptr_reg_shift = ptr_reg_shift;
	382	ring->ptr_reg_mask = ptr_reg_mask;
	383	ring->nop = nop;
771fe6b9	384	/* Allocate ring buffer */
e32eb50d CK	385	if (ring->ring_obj == NULL) {
e32eb50d CK	386	r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
4c788679	387	RADEON_GEM_DOMAIN_GTT,
e32eb50d	388	&ring->ring_obj);
771fe6b9	389	if (r) {
4c788679	390	dev_err(rdev->dev, "(%d) ring create failed\n", r);
771fe6b9 JG	391	return r;
771fe6b9 JG	392	}
e32eb50d	393	r = radeon_bo_reserve(ring->ring_obj, false);
4c788679 JG	394	if (unlikely(r != 0))
4c788679 JG	395	return r;
e32eb50d CK	396	r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
e32eb50d CK	397	&ring->gpu_addr);
771fe6b9	398	if (r) {
e32eb50d	399	radeon_bo_unreserve(ring->ring_obj);
4c788679	400	dev_err(rdev->dev, "(%d) ring pin failed\n", r);
771fe6b9 JG	401	return r;
771fe6b9 JG	402	}
e32eb50d CK	403	r = radeon_bo_kmap(ring->ring_obj,
	404	(void **)&ring->ring);
	405	radeon_bo_unreserve(ring->ring_obj);
771fe6b9	406	if (r) {
4c788679	407	dev_err(rdev->dev, "(%d) ring map failed\n", r);
771fe6b9 JG	408	return r;
	409	}
	410	}
e32eb50d CK	411	ring->ptr_mask = (ring->ring_size / 4) - 1;
e32eb50d CK	412	ring->ring_free_dw = ring->ring_size / 4;
771fe6b9 JG	413	return 0;
	414	}
	415
e32eb50d	416	void radeon_ring_fini(struct radeon_device rdev, struct radeon_ring ring)
771fe6b9	417	{
4c788679	418	int r;
ca2af923	419	struct radeon_bo *ring_obj;
4c788679	420
e32eb50d CK	421	mutex_lock(&ring->mutex);
	422	ring_obj = ring->ring_obj;
	423	ring->ring = NULL;
	424	ring->ring_obj = NULL;
	425	mutex_unlock(&ring->mutex);
ca2af923 AD	426
	427	if (ring_obj) {
	428	r = radeon_bo_reserve(ring_obj, false);
4c788679	429	if (likely(r == 0)) {
ca2af923 AD	430	radeon_bo_kunmap(ring_obj);
	431	radeon_bo_unpin(ring_obj);
	432	radeon_bo_unreserve(ring_obj);
4c788679	433	}
ca2af923	434	radeon_bo_unref(&ring_obj);
771fe6b9	435	}
771fe6b9 JG	436	}
771fe6b9 JG	437
771fe6b9 JG	438	/*
	439	* Debugfs info
	440	*/
	441	#if defined(CONFIG_DEBUG_FS)
af9720f4 CK	442
	443	static int radeon_debugfs_ring_info(struct seq_file m, void data)
	444	{
	445	struct drm_info_node node = (struct drm_info_node ) m->private;
	446	struct drm_device *dev = node->minor->dev;
	447	struct radeon_device *rdev = dev->dev_private;
	448	int ridx = (int)node->info_ent->data;
	449	struct radeon_ring *ring = &rdev->ring[ridx];
	450	unsigned count, i, j;
	451
	452	radeon_ring_free_size(rdev, ring);
	453	count = (ring->ring_size / 4) - ring->ring_free_dw;
	454	seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg));
	455	seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg));
	456	seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr);
	457	seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr);
	458	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
	459	seq_printf(m, "%u dwords in ring\n", count);
	460	i = ring->rptr;
	461	for (j = 0; j <= count; j++) {
	462	seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
	463	i = (i + 1) & ring->ptr_mask;
	464	}
	465	return 0;
	466	}
	467
	468	static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
	469	static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
	470	static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
	471
	472	static struct drm_info_list radeon_debugfs_ring_info_list[] = {
	473	{"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},
	474	{"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},
	475	{"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},
	476	};
	477
771fe6b9 JG	478	static int radeon_debugfs_ib_info(struct seq_file m, void data)
	479	{
	480	struct drm_info_node node = (struct drm_info_node ) m->private;
	481	struct radeon_ib *ib = node->info_ent->data;
	482	unsigned i;
	483
	484	if (ib == NULL) {
	485	return 0;
	486	}
91cb91be	487	seq_printf(m, "IB %04u\n", ib->idx);
771fe6b9 JG	488	seq_printf(m, "IB fence %p\n", ib->fence);
	489	seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
	490	for (i = 0; i < ib->length_dw; i++) {
	491	seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
	492	}
	493	return 0;
	494	}
	495
	496	static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
	497	static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
	498	#endif
	499
af9720f4 CK	500	int radeon_debugfs_ring_init(struct radeon_device *rdev)
	501	{
	502	#if defined(CONFIG_DEBUG_FS)
	503	return radeon_debugfs_add_files(rdev, radeon_debugfs_ring_info_list,
	504	ARRAY_SIZE(radeon_debugfs_ring_info_list));
	505	#else
	506	return 0;
	507	#endif
	508	}
	509
771fe6b9 JG	510	int radeon_debugfs_ib_init(struct radeon_device *rdev)
	511	{
	512	#if defined(CONFIG_DEBUG_FS)
	513	unsigned i;
	514
	515	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
	516	sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
	517	radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
	518	radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
	519	radeon_debugfs_ib_list[i].driver_features = 0;
	520	radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
	521	}
	522	return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
	523	RADEON_IB_POOL_SIZE);
	524	#else
	525	return 0;
	526	#endif
	527	}