[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_ring.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 *          Christian König
 */
#include <drm/drmP.h>
#include "radeon.h"

/*
 * Rings
 * Most engines on the GPU are fed via ring buffers.  Ring
 * buffers are areas of GPU accessible memory that the host
 * writes commands into and the GPU reads commands out of.
 * There is a rptr (read pointer) that determines where the
 * GPU is currently reading, and a wptr (write pointer)
 * which determines where the host has written.  When the
 * pointers are equal, the ring is idle.  When the host
 * writes commands to the ring buffer, it increments the
 * wptr.  The GPU then starts fetching commands and executes
 * them until the pointers are equal again.
 */
static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);

/**
 * radeon_ring_supports_scratch_reg - check if the ring supports
 * writing to scratch registers
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 *
 * Check if a specific ring supports writing to scratch registers (all asics).
 * Returns true if the ring supports writing to scratch regs, false if not.
 */
bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
				      struct radeon_ring *ring)
{
	switch (ring->idx) {
	case RADEON_RING_TYPE_GFX_INDEX:
	case CAYMAN_RING_TYPE_CP1_INDEX:
	case CAYMAN_RING_TYPE_CP2_INDEX:
		return true;
	default:
		return false;
	}
}

/**
 * radeon_ring_free_size - update the free size
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 *
 * Update the free dw slots in the ring buffer (all asics).
 */
void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
{
	uint32_t rptr = radeon_ring_get_rptr(rdev, ring);

	/* This works because ring_size is a power of 2 */
	ring->ring_free_dw = rptr + (ring->ring_size / 4);
	ring->ring_free_dw -= ring->wptr;
	ring->ring_free_dw &= ring->ptr_mask;
	if (!ring->ring_free_dw) {
		/* this is an empty ring */
		ring->ring_free_dw = ring->ring_size / 4;
		/*  update lockup info to avoid false positive */
		radeon_ring_lockup_update(rdev, ring);
	}
}

/**
 * radeon_ring_alloc - allocate space on the ring buffer
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 * @ndw: number of dwords to allocate in the ring buffer
 *
 * Allocate @ndw dwords in the ring buffer (all asics).
 * Returns 0 on success, error on failure.
 */
int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
{
	int r;

	/* make sure we aren't trying to allocate more space than there is on the ring */
	if (ndw > (ring->ring_size / 4))
		return -ENOMEM;
	/* Align requested size with padding so unlock_commit can
	 * pad safely */
	radeon_ring_free_size(rdev, ring);
	ndw = (ndw + ring->align_mask) & ~ring->align_mask;
	while (ndw > (ring->ring_free_dw - 1)) {
		radeon_ring_free_size(rdev, ring);
		if (ndw < ring->ring_free_dw) {
			break;
		}
		r = radeon_fence_wait_next(rdev, ring->idx);
		if (r)
			return r;
	}
	ring->count_dw = ndw;
	ring->wptr_old = ring->wptr;
	return 0;
}

/**
 * radeon_ring_lock - lock the ring and allocate space on it
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 * @ndw: number of dwords to allocate in the ring buffer
 *
 * Lock the ring and allocate @ndw dwords in the ring buffer
 * (all asics).
 * Returns 0 on success, error on failure.
 */
int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
{
	int r;

	mutex_lock(&rdev->ring_lock);
	r = radeon_ring_alloc(rdev, ring, ndw);
	if (r) {
		mutex_unlock(&rdev->ring_lock);
		return r;
	}
	return 0;
}

/**
 * radeon_ring_commit - tell the GPU to execute the new
 * commands on the ring buffer
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 * @hdp_flush: Whether or not to perform an HDP cache flush
 *
 * Update the wptr (write pointer) to tell the GPU to
 * execute new commands on the ring buffer (all asics).
 */
void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring,
			bool hdp_flush)
{
	/* If we are emitting the HDP flush via the ring buffer, we need to
	 * do it before padding.
	 */
	if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush)
		rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring);
	/* We pad to match fetch size */
	while (ring->wptr & ring->align_mask) {
		radeon_ring_write(ring, ring->nop);
	}
	mb();
	/* If we are emitting the HDP flush via MMIO, we need to do it after
	 * all CPU writes to VRAM finished.
	 */
	if (hdp_flush && rdev->asic->mmio_hdp_flush)
		rdev->asic->mmio_hdp_flush(rdev);
	radeon_ring_set_wptr(rdev, ring);
}

/**
 * radeon_ring_unlock_commit - tell the GPU to execute the new
 * commands on the ring buffer and unlock it
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 * @hdp_flush: Whether or not to perform an HDP cache flush
 *
 * Call radeon_ring_commit() then unlock the ring (all asics).
 */
void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring,
			       bool hdp_flush)
{
	radeon_ring_commit(rdev, ring, hdp_flush);
	mutex_unlock(&rdev->ring_lock);
}

/**
 * radeon_ring_undo - reset the wptr
 *
 * @ring: radeon_ring structure holding ring information
 *
 * Reset the driver's copy of the wptr (all asics).
 */
void radeon_ring_undo(struct radeon_ring *ring)
{
	ring->wptr = ring->wptr_old;
}

/**
 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
 *
 * @ring: radeon_ring structure holding ring information
 *
 * Call radeon_ring_undo() then unlock the ring (all asics).
 */
void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
{
	radeon_ring_undo(ring);
	mutex_unlock(&rdev->ring_lock);
}

/**
 * radeon_ring_lockup_update - update lockup variables
 *
 * @ring: radeon_ring structure holding ring information
 *
 * Update the last rptr value and timestamp (all asics).
 */
void radeon_ring_lockup_update(struct radeon_device *rdev,
			       struct radeon_ring *ring)
{
	atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring));
	atomic64_set(&ring->last_activity, jiffies_64);
}

/**
 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
 * @rdev:       radeon device structure
 * @ring:       radeon_ring structure holding ring information
 *
 */
bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
{
	uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
	uint64_t last = atomic64_read(&ring->last_activity);
	uint64_t elapsed;

	if (rptr != atomic_read(&ring->last_rptr)) {
		/* ring is still working, no lockup */
		radeon_ring_lockup_update(rdev, ring);
		return false;
	}

	elapsed = jiffies_to_msecs(jiffies_64 - last);
	if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
		dev_err(rdev->dev, "ring %d stalled for more than %llumsec\n",
			ring->idx, elapsed);
		return true;
	}
	/* give a chance to the GPU ... */
	return false;
}

/**
 * radeon_ring_backup - Back up the content of a ring
 *
 * @rdev: radeon_device pointer
 * @ring: the ring we want to back up
 *
 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
 */
unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
			    uint32_t **data)
{
	unsigned size, ptr, i;

	/* just in case lock the ring */
	mutex_lock(&rdev->ring_lock);
	*data = NULL;

	if (ring->ring_obj == NULL) {
		mutex_unlock(&rdev->ring_lock);
		return 0;
	}

	/* it doesn't make sense to save anything if all fences are signaled */
	if (!radeon_fence_count_emitted(rdev, ring->idx)) {
		mutex_unlock(&rdev->ring_lock);
		return 0;
	}

	/* calculate the number of dw on the ring */
	if (ring->rptr_save_reg)
		ptr = RREG32(ring->rptr_save_reg);
	else if (rdev->wb.enabled)
		ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
	else {
		/* no way to read back the next rptr */
		mutex_unlock(&rdev->ring_lock);
		return 0;
	}

	size = ring->wptr + (ring->ring_size / 4);
	size -= ptr;
	size &= ring->ptr_mask;
	if (size == 0) {
		mutex_unlock(&rdev->ring_lock);
		return 0;
	}

	/* and then save the content of the ring */
	*data = drm_malloc_ab(size, sizeof(uint32_t));
	if (!*data) {
		mutex_unlock(&rdev->ring_lock);
		return 0;
	}
	for (i = 0; i < size; ++i) {
		(*data)[i] = ring->ring[ptr++];
		ptr &= ring->ptr_mask;
	}

	mutex_unlock(&rdev->ring_lock);
	return size;
}

/**
 * radeon_ring_restore - append saved commands to the ring again
 *
 * @rdev: radeon_device pointer
 * @ring: ring to append commands to
 * @size: number of dwords we want to write
 * @data: saved commands
 *
 * Allocates space on the ring and restore the previously saved commands.
 */
int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
			unsigned size, uint32_t *data)
{
	int i, r;

	if (!size || !data)
		return 0;

	/* restore the saved ring content */
	r = radeon_ring_lock(rdev, ring, size);
	if (r)
		return r;

	for (i = 0; i < size; ++i) {
		radeon_ring_write(ring, data[i]);
	}

	radeon_ring_unlock_commit(rdev, ring, false);
	drm_free_large(data);
	return 0;
}

/**
 * radeon_ring_init - init driver ring struct.
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 * @ring_size: size of the ring
 * @rptr_offs: offset of the rptr writeback location in the WB buffer
 * @nop: nop packet for this ring
 *
 * Initialize the driver information for the selected ring (all asics).
 * Returns 0 on success, error on failure.
 */
int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
		     unsigned rptr_offs, u32 nop)
{
	int r;

	ring->ring_size = ring_size;
	ring->rptr_offs = rptr_offs;
	ring->nop = nop;
	/* Allocate ring buffer */
	if (ring->ring_obj == NULL) {
		r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
				     RADEON_GEM_DOMAIN_GTT, 0, NULL,
				     NULL, &ring->ring_obj);
		if (r) {
			dev_err(rdev->dev, "(%d) ring create failed\n", r);
			return r;
		}
		r = radeon_bo_reserve(ring->ring_obj, false);
		if (unlikely(r != 0))
			return r;
		r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
					&ring->gpu_addr);
		if (r) {
			radeon_bo_unreserve(ring->ring_obj);
			dev_err(rdev->dev, "(%d) ring pin failed\n", r);
			return r;
		}
		r = radeon_bo_kmap(ring->ring_obj,
				       (void **)&ring->ring);
		radeon_bo_unreserve(ring->ring_obj);
		if (r) {
			dev_err(rdev->dev, "(%d) ring map failed\n", r);
			return r;
		}
	}
	ring->ptr_mask = (ring->ring_size / 4) - 1;
	ring->ring_free_dw = ring->ring_size / 4;
	if (rdev->wb.enabled) {
		u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
		ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
		ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
	}
	if (radeon_debugfs_ring_init(rdev, ring)) {
		DRM_ERROR("Failed to register debugfs file for rings !\n");
	}
	radeon_ring_lockup_update(rdev, ring);
	return 0;
}

/**
 * radeon_ring_fini - tear down the driver ring struct.
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 *
 * Tear down the driver information for the selected ring (all asics).
 */
void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
{
	int r;
	struct radeon_bo *ring_obj;

	mutex_lock(&rdev->ring_lock);
	ring_obj = ring->ring_obj;
	ring->ready = false;
	ring->ring = NULL;
	ring->ring_obj = NULL;
	mutex_unlock(&rdev->ring_lock);

	if (ring_obj) {
		r = radeon_bo_reserve(ring_obj, false);
		if (likely(r == 0)) {
			radeon_bo_kunmap(ring_obj);
			radeon_bo_unpin(ring_obj);
			radeon_bo_unreserve(ring_obj);
		}
		radeon_bo_unref(&ring_obj);
	}
}

/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)

static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
	int ridx = *(int*)node->info_ent->data;
	struct radeon_ring *ring = &rdev->ring[ridx];

	uint32_t rptr, wptr, rptr_next;
	unsigned count, i, j;

	radeon_ring_free_size(rdev, ring);
	count = (ring->ring_size / 4) - ring->ring_free_dw;

	wptr = radeon_ring_get_wptr(rdev, ring);
	seq_printf(m, "wptr: 0x%08x [%5d]\n",
		   wptr, wptr);

	rptr = radeon_ring_get_rptr(rdev, ring);
	seq_printf(m, "rptr: 0x%08x [%5d]\n",
		   rptr, rptr);

	if (ring->rptr_save_reg) {
		rptr_next = RREG32(ring->rptr_save_reg);
		seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n",
			   ring->rptr_save_reg, rptr_next, rptr_next);
	} else
		rptr_next = ~0;

	seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
		   ring->wptr, ring->wptr);
	seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
		   ring->last_semaphore_signal_addr);
	seq_printf(m, "last semaphore wait addr   : 0x%016llx\n",
		   ring->last_semaphore_wait_addr);
	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
	seq_printf(m, "%u dwords in ring\n", count);

	if (!ring->ring)
		return 0;

	/* print 8 dw before current rptr as often it's the last executed
	 * packet that is the root issue
	 */
	i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
	for (j = 0; j <= (count + 32); j++) {
		seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
		if (rptr == i)
			seq_puts(m, " *");
		if (rptr_next == i)
			seq_puts(m, " #");
		seq_puts(m, "\n");
		i = (i + 1) & ring->ptr_mask;
	}
	return 0;
}

static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX;
static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX;

static struct drm_info_list radeon_debugfs_ring_info_list[] = {
	{"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
	{"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index},
	{"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index},
	{"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
	{"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
	{"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
	{"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index},
	{"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index},
};

#endif

static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
{
#if defined(CONFIG_DEBUG_FS)
	unsigned i;
	for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
		struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
		int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
		unsigned r;

		if (&rdev->ring[ridx] != ring)
			continue;

		r = radeon_debugfs_add_files(rdev, info, 1);
		if (r)
			return r;
	}
#endif
	return 0;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
c507f7ef	27	* Christian König
771fe6b9	28	*/
760285e7	29	#include <drm/drmP.h>
771fe6b9	30	#include "radeon.h"
7bd560e8	31
771fe6b9	32	/*
75923280 AD	33	* Rings
	34	* Most engines on the GPU are fed via ring buffers. Ring
	35	* buffers are areas of GPU accessible memory that the host
	36	* writes commands into and the GPU reads commands out of.
	37	* There is a rptr (read pointer) that determines where the
	38	* GPU is currently reading, and a wptr (write pointer)
	39	* which determines where the host has written. When the
	40	* pointers are equal, the ring is idle. When the host
	41	* writes commands to the ring buffer, it increments the
	42	* wptr. The GPU then starts fetching commands and executes
	43	* them until the pointers are equal again.
771fe6b9	44	*/
1109ca09	45	static int radeon_debugfs_ring_init(struct radeon_device rdev, struct radeon_ring ring);
c507f7ef	46
75923280 AD	47	/**
	48	* radeon_ring_supports_scratch_reg - check if the ring supports
	49	* writing to scratch registers
	50	*
	51	* @rdev: radeon_device pointer
	52	* @ring: radeon_ring structure holding ring information
	53	*
	54	* Check if a specific ring supports writing to scratch registers (all asics).
	55	* Returns true if the ring supports writing to scratch regs, false if not.
	56	*/
89d35807 AD	57	bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
	58	struct radeon_ring *ring)
	59	{
	60	switch (ring->idx) {
	61	case RADEON_RING_TYPE_GFX_INDEX:
	62	case CAYMAN_RING_TYPE_CP1_INDEX:
	63	case CAYMAN_RING_TYPE_CP2_INDEX:
	64	return true;
	65	default:
	66	return false;
	67	}
	68	}
	69
75923280 AD	70	/**
	71	* radeon_ring_free_size - update the free size
	72	*
	73	* @rdev: radeon_device pointer
	74	* @ring: radeon_ring structure holding ring information
	75	*
	76	* Update the free dw slots in the ring buffer (all asics).
	77	*/
e32eb50d	78	void radeon_ring_free_size(struct radeon_device rdev, struct radeon_ring ring)
771fe6b9	79	{
ff212f25 CK	80	uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
ff212f25 CK	81
771fe6b9	82	/* This works because ring_size is a power of 2 */
ff212f25	83	ring->ring_free_dw = rptr + (ring->ring_size / 4);
e32eb50d CK	84	ring->ring_free_dw -= ring->wptr;
	85	ring->ring_free_dw &= ring->ptr_mask;
	86	if (!ring->ring_free_dw) {
82dc62a3	87	/* this is an empty ring */
e32eb50d	88	ring->ring_free_dw = ring->ring_size / 4;
82dc62a3 CK	89	/* update lockup info to avoid false positive */
82dc62a3 CK	90	radeon_ring_lockup_update(rdev, ring);
771fe6b9 JG	91	}
	92	}
	93
75923280 AD	94	/**
	95	* radeon_ring_alloc - allocate space on the ring buffer
	96	*
	97	* @rdev: radeon_device pointer
	98	* @ring: radeon_ring structure holding ring information
	99	* @ndw: number of dwords to allocate in the ring buffer
	100	*
	101	* Allocate @ndw dwords in the ring buffer (all asics).
	102	* Returns 0 on success, error on failure.
	103	*/
e32eb50d	104	int radeon_ring_alloc(struct radeon_device rdev, struct radeon_ring ring, unsigned ndw)
771fe6b9 JG	105	{
	106	int r;
	107
fd5d93a0 AD	108	/* make sure we aren't trying to allocate more space than there is on the ring */
	109	if (ndw > (ring->ring_size / 4))
	110	return -ENOMEM;
771fe6b9 JG	111	/* Align requested size with padding so unlock_commit can
771fe6b9 JG	112	* pad safely */
8444d5c6	113	radeon_ring_free_size(rdev, ring);
e32eb50d CK	114	ndw = (ndw + ring->align_mask) & ~ring->align_mask;
	115	while (ndw > (ring->ring_free_dw - 1)) {
	116	radeon_ring_free_size(rdev, ring);
	117	if (ndw < ring->ring_free_dw) {
771fe6b9 JG	118	break;
771fe6b9 JG	119	}
37615527	120	r = radeon_fence_wait_next(rdev, ring->idx);
91700f3c	121	if (r)
771fe6b9	122	return r;
771fe6b9	123	}
e32eb50d CK	124	ring->count_dw = ndw;
e32eb50d CK	125	ring->wptr_old = ring->wptr;
771fe6b9 JG	126	return 0;
	127	}
	128
75923280 AD	129	/**
	130	* radeon_ring_lock - lock the ring and allocate space on it
	131	*
	132	* @rdev: radeon_device pointer
	133	* @ring: radeon_ring structure holding ring information
	134	* @ndw: number of dwords to allocate in the ring buffer
	135	*
	136	* Lock the ring and allocate @ndw dwords in the ring buffer
	137	* (all asics).
	138	* Returns 0 on success, error on failure.
	139	*/
e32eb50d	140	int radeon_ring_lock(struct radeon_device rdev, struct radeon_ring ring, unsigned ndw)
91700f3c MG	141	{
	142	int r;
	143
d6999bc7	144	mutex_lock(&rdev->ring_lock);
e32eb50d	145	r = radeon_ring_alloc(rdev, ring, ndw);
91700f3c	146	if (r) {
d6999bc7	147	mutex_unlock(&rdev->ring_lock);
91700f3c MG	148	return r;
	149	}
	150	return 0;
	151	}
	152
75923280 AD	153	/**
	154	* radeon_ring_commit - tell the GPU to execute the new
	155	* commands on the ring buffer
	156	*
	157	* @rdev: radeon_device pointer
	158	* @ring: radeon_ring structure holding ring information
1538a9e0	159	* @hdp_flush: Whether or not to perform an HDP cache flush
75923280 AD	160	*
	161	* Update the wptr (write pointer) to tell the GPU to
	162	* execute new commands on the ring buffer (all asics).
	163	*/
1538a9e0 MD	164	void radeon_ring_commit(struct radeon_device rdev, struct radeon_ring ring,
1538a9e0 MD	165	bool hdp_flush)
771fe6b9	166	{
72a9987e MD	167	/* If we are emitting the HDP flush via the ring buffer, we need to
	168	* do it before padding.
	169	*/
1538a9e0	170	if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush)
72a9987e	171	rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring);
771fe6b9	172	/* We pad to match fetch size */
07a71330	173	while (ring->wptr & ring->align_mask) {
78c5560a	174	radeon_ring_write(ring, ring->nop);
771fe6b9	175	}
85b2331b	176	mb();
72a9987e MD	177	/* If we are emitting the HDP flush via MMIO, we need to do it after
	178	* all CPU writes to VRAM finished.
	179	*/
1538a9e0	180	if (hdp_flush && rdev->asic->mmio_hdp_flush)
72a9987e	181	rdev->asic->mmio_hdp_flush(rdev);
f93bdefe	182	radeon_ring_set_wptr(rdev, ring);
91700f3c MG	183	}
91700f3c MG	184
75923280 AD	185	/**
	186	* radeon_ring_unlock_commit - tell the GPU to execute the new
	187	* commands on the ring buffer and unlock it
	188	*
	189	* @rdev: radeon_device pointer
	190	* @ring: radeon_ring structure holding ring information
1538a9e0	191	* @hdp_flush: Whether or not to perform an HDP cache flush
75923280 AD	192	*
	193	* Call radeon_ring_commit() then unlock the ring (all asics).
	194	*/
1538a9e0 MD	195	void radeon_ring_unlock_commit(struct radeon_device rdev, struct radeon_ring ring,
1538a9e0 MD	196	bool hdp_flush)
91700f3c	197	{
1538a9e0	198	radeon_ring_commit(rdev, ring, hdp_flush);
d6999bc7	199	mutex_unlock(&rdev->ring_lock);
771fe6b9 JG	200	}
771fe6b9 JG	201
75923280 AD	202	/**
	203	* radeon_ring_undo - reset the wptr
	204	*
	205	* @ring: radeon_ring structure holding ring information
	206	*
501f9d4c	207	* Reset the driver's copy of the wptr (all asics).
75923280	208	*/
d6999bc7	209	void radeon_ring_undo(struct radeon_ring *ring)
771fe6b9	210	{
e32eb50d	211	ring->wptr = ring->wptr_old;
d6999bc7 CK	212	}
d6999bc7 CK	213
75923280 AD	214	/**
	215	* radeon_ring_unlock_undo - reset the wptr and unlock the ring
	216	*
	217	* @ring: radeon_ring structure holding ring information
	218	*
	219	* Call radeon_ring_undo() then unlock the ring (all asics).
	220	*/
d6999bc7 CK	221	void radeon_ring_unlock_undo(struct radeon_device rdev, struct radeon_ring ring)
	222	{
	223	radeon_ring_undo(ring);
	224	mutex_unlock(&rdev->ring_lock);
771fe6b9 JG	225	}
771fe6b9 JG	226
75923280	227	/**
501f9d4c	228	* radeon_ring_lockup_update - update lockup variables
75923280 AD	229	*
	230	* @ring: radeon_ring structure holding ring information
	231	*
	232	* Update the last rptr value and timestamp (all asics).
	233	*/
ff212f25 CK	234	void radeon_ring_lockup_update(struct radeon_device *rdev,
ff212f25 CK	235	struct radeon_ring *ring)
069211e5	236	{
aee4aa73 CK	237	atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring));
aee4aa73 CK	238	atomic64_set(&ring->last_activity, jiffies_64);
069211e5 CK	239	}
	240
	241	/**
	242	* radeon_ring_test_lockup() - check if ring is lockedup by recording information
	243	* @rdev: radeon device structure
	244	* @ring: radeon_ring structure holding ring information
	245	*
2d2fe3f9	246	*/
069211e5 CK	247	bool radeon_ring_test_lockup(struct radeon_device rdev, struct radeon_ring ring)
069211e5 CK	248	{
ff212f25	249	uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
aee4aa73 CK	250	uint64_t last = atomic64_read(&ring->last_activity);
aee4aa73 CK	251	uint64_t elapsed;
069211e5	252
aee4aa73 CK	253	if (rptr != atomic_read(&ring->last_rptr)) {
aee4aa73 CK	254	/* ring is still working, no lockup */
ff212f25	255	radeon_ring_lockup_update(rdev, ring);
069211e5 CK	256	return false;
069211e5 CK	257	}
aee4aa73 CK	258
aee4aa73 CK	259	elapsed = jiffies_to_msecs(jiffies_64 - last);
3368ff0c	260	if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
aee4aa73 CK	261	dev_err(rdev->dev, "ring %d stalled for more than %llumsec\n",
aee4aa73 CK	262	ring->idx, elapsed);
069211e5 CK	263	return true;
	264	}
	265	/* give a chance to the GPU ... */
	266	return false;
	267	}
	268
55d7c221 CK	269	/**
	270	* radeon_ring_backup - Back up the content of a ring
	271	*
	272	* @rdev: radeon_device pointer
	273	* @ring: the ring we want to back up
	274	*
	275	* Saves all unprocessed commits from a ring, returns the number of dwords saved.
	276	*/
	277	unsigned radeon_ring_backup(struct radeon_device rdev, struct radeon_ring ring,
	278	uint32_t **data)
	279	{
	280	unsigned size, ptr, i;
55d7c221 CK	281
	282	/* just in case lock the ring */
	283	mutex_lock(&rdev->ring_lock);
	284	*data = NULL;
	285
89d35807	286	if (ring->ring_obj == NULL) {
55d7c221 CK	287	mutex_unlock(&rdev->ring_lock);
	288	return 0;
	289	}
	290
	291	/* it doesn't make sense to save anything if all fences are signaled */
8b25ed34	292	if (!radeon_fence_count_emitted(rdev, ring->idx)) {
55d7c221 CK	293	mutex_unlock(&rdev->ring_lock);
	294	return 0;
	295	}
	296
	297	/* calculate the number of dw on the ring */
89d35807 AD	298	if (ring->rptr_save_reg)
	299	ptr = RREG32(ring->rptr_save_reg);
	300	else if (rdev->wb.enabled)
	301	ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
	302	else {
	303	/* no way to read back the next rptr */
	304	mutex_unlock(&rdev->ring_lock);
	305	return 0;
	306	}
	307
55d7c221 CK	308	size = ring->wptr + (ring->ring_size / 4);
	309	size -= ptr;
	310	size &= ring->ptr_mask;
	311	if (size == 0) {
	312	mutex_unlock(&rdev->ring_lock);
	313	return 0;
	314	}
	315
	316	/* and then save the content of the ring */
e5a5fd4d	317	*data = drm_malloc_ab(size, sizeof(uint32_t));
1e179d4e DC	318	if (!*data) {
	319	mutex_unlock(&rdev->ring_lock);
	320	return 0;
	321	}
55d7c221 CK	322	for (i = 0; i < size; ++i) {
	323	(*data)[i] = ring->ring[ptr++];
	324	ptr &= ring->ptr_mask;
	325	}
	326
	327	mutex_unlock(&rdev->ring_lock);
	328	return size;
	329	}
	330
	331	/**
	332	* radeon_ring_restore - append saved commands to the ring again
	333	*
	334	* @rdev: radeon_device pointer
	335	* @ring: ring to append commands to
	336	* @size: number of dwords we want to write
	337	* @data: saved commands
	338	*
	339	* Allocates space on the ring and restore the previously saved commands.
	340	*/
	341	int radeon_ring_restore(struct radeon_device rdev, struct radeon_ring ring,
	342	unsigned size, uint32_t *data)
	343	{
	344	int i, r;
	345
	346	if (!size \|\| !data)
	347	return 0;
	348
	349	/* restore the saved ring content */
	350	r = radeon_ring_lock(rdev, ring, size);
	351	if (r)
	352	return r;
	353
	354	for (i = 0; i < size; ++i) {
	355	radeon_ring_write(ring, data[i]);
	356	}
	357
1538a9e0	358	radeon_ring_unlock_commit(rdev, ring, false);
e5a5fd4d	359	drm_free_large(data);
55d7c221 CK	360	return 0;
	361	}
	362
75923280 AD	363	/**
	364	* radeon_ring_init - init driver ring struct.
	365	*
	366	* @rdev: radeon_device pointer
	367	* @ring: radeon_ring structure holding ring information
	368	* @ring_size: size of the ring
	369	* @rptr_offs: offset of the rptr writeback location in the WB buffer
75923280 AD	370	* @nop: nop packet for this ring
	371	*
	372	* Initialize the driver information for the selected ring (all asics).
	373	* Returns 0 on success, error on failure.
	374	*/
e32eb50d	375	int radeon_ring_init(struct radeon_device rdev, struct radeon_ring ring, unsigned ring_size,
ea31bf69	376	unsigned rptr_offs, u32 nop)
771fe6b9 JG	377	{
	378	int r;
	379
e32eb50d CK	380	ring->ring_size = ring_size;
e32eb50d CK	381	ring->rptr_offs = rptr_offs;
78c5560a	382	ring->nop = nop;
771fe6b9	383	/* Allocate ring buffer */
e32eb50d CK	384	if (ring->ring_obj == NULL) {
e32eb50d CK	385	r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
831b6966	386	RADEON_GEM_DOMAIN_GTT, 0, NULL,
40f5cf99	387	NULL, &ring->ring_obj);
771fe6b9	388	if (r) {
4c788679	389	dev_err(rdev->dev, "(%d) ring create failed\n", r);
771fe6b9 JG	390	return r;
771fe6b9 JG	391	}
e32eb50d	392	r = radeon_bo_reserve(ring->ring_obj, false);
4c788679 JG	393	if (unlikely(r != 0))
4c788679 JG	394	return r;
e32eb50d CK	395	r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
e32eb50d CK	396	&ring->gpu_addr);
771fe6b9	397	if (r) {
e32eb50d	398	radeon_bo_unreserve(ring->ring_obj);
4c788679	399	dev_err(rdev->dev, "(%d) ring pin failed\n", r);
771fe6b9 JG	400	return r;
771fe6b9 JG	401	}
e32eb50d CK	402	r = radeon_bo_kmap(ring->ring_obj,
	403	(void **)&ring->ring);
	404	radeon_bo_unreserve(ring->ring_obj);
771fe6b9	405	if (r) {
4c788679	406	dev_err(rdev->dev, "(%d) ring map failed\n", r);
771fe6b9 JG	407	return r;
	408	}
	409	}
e32eb50d CK	410	ring->ptr_mask = (ring->ring_size / 4) - 1;
e32eb50d CK	411	ring->ring_free_dw = ring->ring_size / 4;
89d35807 AD	412	if (rdev->wb.enabled) {
	413	u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
	414	ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
	415	ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
	416	}
ec1a6cce CK	417	if (radeon_debugfs_ring_init(rdev, ring)) {
	418	DRM_ERROR("Failed to register debugfs file for rings !\n");
	419	}
ff212f25	420	radeon_ring_lockup_update(rdev, ring);
771fe6b9 JG	421	return 0;
	422	}
	423
75923280 AD	424	/**
	425	* radeon_ring_fini - tear down the driver ring struct.
	426	*
	427	* @rdev: radeon_device pointer
	428	* @ring: radeon_ring structure holding ring information
	429	*
	430	* Tear down the driver information for the selected ring (all asics).
	431	*/
e32eb50d	432	void radeon_ring_fini(struct radeon_device rdev, struct radeon_ring ring)
771fe6b9	433	{
4c788679	434	int r;
ca2af923	435	struct radeon_bo *ring_obj;
4c788679	436
d6999bc7	437	mutex_lock(&rdev->ring_lock);
e32eb50d	438	ring_obj = ring->ring_obj;
d6999bc7	439	ring->ready = false;
e32eb50d CK	440	ring->ring = NULL;
e32eb50d CK	441	ring->ring_obj = NULL;
d6999bc7	442	mutex_unlock(&rdev->ring_lock);
ca2af923 AD	443
	444	if (ring_obj) {
	445	r = radeon_bo_reserve(ring_obj, false);
4c788679	446	if (likely(r == 0)) {
ca2af923 AD	447	radeon_bo_kunmap(ring_obj);
	448	radeon_bo_unpin(ring_obj);
	449	radeon_bo_unreserve(ring_obj);
4c788679	450	}
ca2af923	451	radeon_bo_unref(&ring_obj);
771fe6b9	452	}
771fe6b9 JG	453	}
771fe6b9 JG	454
771fe6b9 JG	455	/*
	456	* Debugfs info
	457	*/
	458	#if defined(CONFIG_DEBUG_FS)
af9720f4 CK	459
	460	static int radeon_debugfs_ring_info(struct seq_file m, void data)
	461	{
	462	struct drm_info_node node = (struct drm_info_node ) m->private;
	463	struct drm_device *dev = node->minor->dev;
	464	struct radeon_device *rdev = dev->dev_private;
	465	int ridx = (int)node->info_ent->data;
	466	struct radeon_ring *ring = &rdev->ring[ridx];
df893a25 CK	467
df893a25 CK	468	uint32_t rptr, wptr, rptr_next;
af9720f4 CK	469	unsigned count, i, j;
	470
	471	radeon_ring_free_size(rdev, ring);
	472	count = (ring->ring_size / 4) - ring->ring_free_dw;
df893a25 CK	473
df893a25 CK	474	wptr = radeon_ring_get_wptr(rdev, ring);
ea31bf69 AD	475	seq_printf(m, "wptr: 0x%08x [%5d]\n",
ea31bf69 AD	476	wptr, wptr);
df893a25 CK	477
df893a25 CK	478	rptr = radeon_ring_get_rptr(rdev, ring);
ea31bf69 AD	479	seq_printf(m, "rptr: 0x%08x [%5d]\n",
ea31bf69 AD	480	rptr, rptr);
df893a25	481
45df6803	482	if (ring->rptr_save_reg) {
df893a25 CK	483	rptr_next = RREG32(ring->rptr_save_reg);
	484	seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n",
	485	ring->rptr_save_reg, rptr_next, rptr_next);
	486	} else
	487	rptr_next = ~0;
	488
	489	seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
	490	ring->wptr, ring->wptr);
df893a25 CK	491	seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
	492	ring->last_semaphore_signal_addr);
	493	seq_printf(m, "last semaphore wait addr : 0x%016llx\n",
	494	ring->last_semaphore_wait_addr);
af9720f4 CK	495	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
af9720f4 CK	496	seq_printf(m, "%u dwords in ring\n", count);
df893a25	497
1b01fc34	498	if (!ring->ring)
df893a25 CK	499	return 0;
df893a25 CK	500
4d009190 JG	501	/* print 8 dw before current rptr as often it's the last executed
	502	* packet that is the root issue
	503	*/
df893a25 CK	504	i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
	505	for (j = 0; j <= (count + 32); j++) {
	506	seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
	507	if (rptr == i)
	508	seq_puts(m, " *");
	509	if (rptr_next == i)
	510	seq_puts(m, " #");
	511	seq_puts(m, "\n");
	512	i = (i + 1) & ring->ptr_mask;
af9720f4 CK	513	}
	514	return 0;
	515	}
	516
f2ba57b5 CK	517	static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
	518	static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
	519	static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
	520	static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
	521	static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
	522	static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
d93f7937 CK	523	static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX;
d93f7937 CK	524	static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX;
af9720f4 CK	525
af9720f4 CK	526	static struct drm_info_list radeon_debugfs_ring_info_list[] = {
f2ba57b5 CK	527	{"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
	528	{"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index},
	529	{"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index},
	530	{"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
	531	{"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
	532	{"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
d93f7937 CK	533	{"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index},
d93f7937 CK	534	{"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index},
af9720f4 CK	535	};
af9720f4 CK	536
771fe6b9 JG	537	#endif
771fe6b9 JG	538
1109ca09	539	static int radeon_debugfs_ring_init(struct radeon_device rdev, struct radeon_ring ring)
af9720f4 CK	540	{
af9720f4 CK	541	#if defined(CONFIG_DEBUG_FS)
ec1a6cce CK	542	unsigned i;
	543	for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
	544	struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
	545	int ridx = (int)radeon_debugfs_ring_info_list[i].data;
	546	unsigned r;
	547
	548	if (&rdev->ring[ridx] != ring)
	549	continue;
	550
	551	r = radeon_debugfs_add_files(rdev, info, 1);
	552	if (r)
	553	return r;
	554	}
af9720f4	555	#endif
ec1a6cce	556	return 0;
af9720f4	557	}