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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
c507f7ef | 27 | * Christian König |
771fe6b9 JG |
28 | */ |
29 | #include <linux/seq_file.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
33 | #include "radeon_reg.h" |
34 | #include "radeon.h" | |
35 | #include "atom.h" | |
36 | ||
c507f7ef | 37 | /* |
75923280 AD |
38 | * IB |
39 | * IBs (Indirect Buffers) and areas of GPU accessible memory where | |
40 | * commands are stored. You can put a pointer to the IB in the | |
41 | * command ring and the hw will fetch the commands from the IB | |
42 | * and execute them. Generally userspace acceleration drivers | |
43 | * produce command buffers which are send to the kernel and | |
44 | * put in IBs for execution by the requested ring. | |
c507f7ef | 45 | */ |
1109ca09 | 46 | static int radeon_debugfs_sa_init(struct radeon_device *rdev); |
771fe6b9 | 47 | |
75923280 AD |
48 | /** |
49 | * radeon_ib_get - request an IB (Indirect Buffer) | |
50 | * | |
51 | * @rdev: radeon_device pointer | |
52 | * @ring: ring index the IB is associated with | |
53 | * @ib: IB object returned | |
54 | * @size: requested IB size | |
55 | * | |
56 | * Request an IB (all asics). IBs are allocated using the | |
57 | * suballocator. | |
58 | * Returns 0 on success, error on failure. | |
59 | */ | |
69e130a6 | 60 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
4bf3dd92 CK |
61 | struct radeon_ib *ib, struct radeon_vm *vm, |
62 | unsigned size) | |
771fe6b9 | 63 | { |
220907d9 | 64 | int i, r; |
b15ba512 | 65 | |
f2e39221 | 66 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true); |
c507f7ef JG |
67 | if (r) { |
68 | dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); | |
c507f7ef | 69 | return r; |
b15ba512 | 70 | } |
c507f7ef | 71 | |
220907d9 CK |
72 | r = radeon_semaphore_create(rdev, &ib->semaphore); |
73 | if (r) { | |
74 | return r; | |
75 | } | |
76 | ||
876dc9f3 CK |
77 | ib->ring = ring; |
78 | ib->fence = NULL; | |
f2e39221 | 79 | ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); |
4bf3dd92 CK |
80 | ib->vm = vm; |
81 | if (vm) { | |
ca19f21e CK |
82 | /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address |
83 | * space and soffset is the offset inside the pool bo | |
4bf3dd92 | 84 | */ |
ca19f21e | 85 | ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET; |
4bf3dd92 CK |
86 | } else { |
87 | ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); | |
88 | } | |
f2e39221 | 89 | ib->is_const_ib = false; |
220907d9 CK |
90 | for (i = 0; i < RADEON_NUM_RINGS; ++i) |
91 | ib->sync_to[i] = NULL; | |
c507f7ef JG |
92 | |
93 | return 0; | |
771fe6b9 JG |
94 | } |
95 | ||
75923280 AD |
96 | /** |
97 | * radeon_ib_free - free an IB (Indirect Buffer) | |
98 | * | |
99 | * @rdev: radeon_device pointer | |
100 | * @ib: IB object to free | |
101 | * | |
102 | * Free an IB (all asics). | |
103 | */ | |
f2e39221 | 104 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) |
771fe6b9 | 105 | { |
220907d9 | 106 | radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); |
f2e39221 JG |
107 | radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); |
108 | radeon_fence_unref(&ib->fence); | |
771fe6b9 JG |
109 | } |
110 | ||
43f1214a AD |
111 | /** |
112 | * radeon_ib_sync_to - sync to fence before executing the IB | |
113 | * | |
114 | * @ib: IB object to add fence to | |
115 | * @fence: fence to sync to | |
116 | * | |
117 | * Sync to the fence before executing the IB | |
118 | */ | |
119 | void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence) | |
120 | { | |
121 | struct radeon_fence *other; | |
122 | ||
123 | if (!fence) | |
124 | return; | |
125 | ||
126 | other = ib->sync_to[fence->ring]; | |
127 | ib->sync_to[fence->ring] = radeon_fence_later(fence, other); | |
128 | } | |
129 | ||
75923280 AD |
130 | /** |
131 | * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring | |
132 | * | |
133 | * @rdev: radeon_device pointer | |
134 | * @ib: IB object to schedule | |
135 | * @const_ib: Const IB to schedule (SI only) | |
136 | * | |
137 | * Schedule an IB on the associated ring (all asics). | |
138 | * Returns 0 on success, error on failure. | |
139 | * | |
140 | * On SI, there are two parallel engines fed from the primary ring, | |
141 | * the CE (Constant Engine) and the DE (Drawing Engine). Since | |
142 | * resource descriptors have moved to memory, the CE allows you to | |
143 | * prime the caches while the DE is updating register state so that | |
144 | * the resource descriptors will be already in cache when the draw is | |
145 | * processed. To accomplish this, the userspace driver submits two | |
146 | * IBs, one for the CE and one for the DE. If there is a CE IB (called | |
147 | * a CONST_IB), it will be put on the ring prior to the DE IB. Prior | |
148 | * to SI there was just a DE IB. | |
149 | */ | |
4ef72566 CK |
150 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
151 | struct radeon_ib *const_ib) | |
771fe6b9 | 152 | { |
876dc9f3 | 153 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
220907d9 CK |
154 | bool need_sync = false; |
155 | int i, r = 0; | |
771fe6b9 | 156 | |
e32eb50d | 157 | if (!ib->length_dw || !ring->ready) { |
771fe6b9 | 158 | /* TODO: Nothings in the ib we should report. */ |
c507f7ef | 159 | dev_err(rdev->dev, "couldn't schedule ib\n"); |
771fe6b9 JG |
160 | return -EINVAL; |
161 | } | |
ecb114a1 | 162 | |
6cdf6585 | 163 | /* 64 dwords should be enough for fence too */ |
220907d9 | 164 | r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); |
771fe6b9 | 165 | if (r) { |
c507f7ef | 166 | dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); |
771fe6b9 JG |
167 | return r; |
168 | } | |
220907d9 CK |
169 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
170 | struct radeon_fence *fence = ib->sync_to[i]; | |
171 | if (radeon_fence_need_sync(fence, ib->ring)) { | |
172 | need_sync = true; | |
173 | radeon_semaphore_sync_rings(rdev, ib->semaphore, | |
174 | fence->ring, ib->ring); | |
175 | radeon_fence_note_sync(fence, ib->ring); | |
176 | } | |
177 | } | |
178 | /* immediately free semaphore when we don't need to sync */ | |
179 | if (!need_sync) { | |
180 | radeon_semaphore_free(rdev, &ib->semaphore, NULL); | |
181 | } | |
9b40e5d8 | 182 | /* if we can't remember our last VM flush then flush now! */ |
466476df JG |
183 | /* XXX figure out why we have to flush for every IB */ |
184 | if (ib->vm /*&& !ib->vm->last_flush*/) { | |
498522b4 | 185 | radeon_ring_vm_flush(rdev, ib->ring, ib->vm); |
9b40e5d8 | 186 | } |
4ef72566 CK |
187 | if (const_ib) { |
188 | radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); | |
189 | radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); | |
190 | } | |
876dc9f3 CK |
191 | radeon_ring_ib_execute(rdev, ib->ring, ib); |
192 | r = radeon_fence_emit(rdev, &ib->fence, ib->ring); | |
193 | if (r) { | |
194 | dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); | |
195 | radeon_ring_unlock_undo(rdev, ring); | |
196 | return r; | |
197 | } | |
4ef72566 CK |
198 | if (const_ib) { |
199 | const_ib->fence = radeon_fence_ref(ib->fence); | |
200 | } | |
9b40e5d8 CK |
201 | /* we just flushed the VM, remember that */ |
202 | if (ib->vm && !ib->vm->last_flush) { | |
203 | ib->vm->last_flush = radeon_fence_ref(ib->fence); | |
204 | } | |
e32eb50d | 205 | radeon_ring_unlock_commit(rdev, ring); |
771fe6b9 JG |
206 | return 0; |
207 | } | |
208 | ||
75923280 AD |
209 | /** |
210 | * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool | |
211 | * | |
212 | * @rdev: radeon_device pointer | |
213 | * | |
214 | * Initialize the suballocator to manage a pool of memory | |
215 | * for use as IBs (all asics). | |
216 | * Returns 0 on success, error on failure. | |
217 | */ | |
771fe6b9 JG |
218 | int radeon_ib_pool_init(struct radeon_device *rdev) |
219 | { | |
c507f7ef | 220 | int r; |
771fe6b9 | 221 | |
c507f7ef | 222 | if (rdev->ib_pool_ready) { |
d54fbd49 JG |
223 | return 0; |
224 | } | |
c507f7ef | 225 | r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, |
c3b7fe8b | 226 | RADEON_IB_POOL_SIZE*64*1024, |
6c4f978b | 227 | RADEON_GPU_PAGE_SIZE, |
c3b7fe8b CK |
228 | RADEON_GEM_DOMAIN_GTT); |
229 | if (r) { | |
c3b7fe8b CK |
230 | return r; |
231 | } | |
2898c348 CK |
232 | |
233 | r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); | |
234 | if (r) { | |
235 | return r; | |
236 | } | |
237 | ||
c507f7ef JG |
238 | rdev->ib_pool_ready = true; |
239 | if (radeon_debugfs_sa_init(rdev)) { | |
240 | dev_err(rdev->dev, "failed to register debugfs file for SA\n"); | |
771fe6b9 | 241 | } |
b15ba512 | 242 | return 0; |
771fe6b9 JG |
243 | } |
244 | ||
75923280 AD |
245 | /** |
246 | * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool | |
247 | * | |
248 | * @rdev: radeon_device pointer | |
249 | * | |
250 | * Tear down the suballocator managing the pool of memory | |
251 | * for use as IBs (all asics). | |
252 | */ | |
771fe6b9 JG |
253 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
254 | { | |
c507f7ef | 255 | if (rdev->ib_pool_ready) { |
2898c348 | 256 | radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); |
c507f7ef JG |
257 | radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); |
258 | rdev->ib_pool_ready = false; | |
771fe6b9 | 259 | } |
771fe6b9 JG |
260 | } |
261 | ||
75923280 AD |
262 | /** |
263 | * radeon_ib_ring_tests - test IBs on the rings | |
264 | * | |
265 | * @rdev: radeon_device pointer | |
266 | * | |
267 | * Test an IB (Indirect Buffer) on each ring. | |
268 | * If the test fails, disable the ring. | |
269 | * Returns 0 on success, error if the primary GFX ring | |
270 | * IB test fails. | |
271 | */ | |
7bd560e8 CK |
272 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
273 | { | |
274 | unsigned i; | |
275 | int r; | |
276 | ||
277 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | |
278 | struct radeon_ring *ring = &rdev->ring[i]; | |
279 | ||
280 | if (!ring->ready) | |
281 | continue; | |
282 | ||
283 | r = radeon_ib_test(rdev, i, ring); | |
284 | if (r) { | |
285 | ring->ready = false; | |
286 | ||
287 | if (i == RADEON_RING_TYPE_GFX_INDEX) { | |
288 | /* oh, oh, that's really bad */ | |
289 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); | |
290 | rdev->accel_working = false; | |
291 | return r; | |
292 | ||
293 | } else { | |
294 | /* still not good, but we can live with it */ | |
295 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); | |
296 | } | |
297 | } | |
298 | } | |
299 | return 0; | |
300 | } | |
301 | ||
771fe6b9 | 302 | /* |
75923280 AD |
303 | * Rings |
304 | * Most engines on the GPU are fed via ring buffers. Ring | |
305 | * buffers are areas of GPU accessible memory that the host | |
306 | * writes commands into and the GPU reads commands out of. | |
307 | * There is a rptr (read pointer) that determines where the | |
308 | * GPU is currently reading, and a wptr (write pointer) | |
309 | * which determines where the host has written. When the | |
310 | * pointers are equal, the ring is idle. When the host | |
311 | * writes commands to the ring buffer, it increments the | |
312 | * wptr. The GPU then starts fetching commands and executes | |
313 | * them until the pointers are equal again. | |
771fe6b9 | 314 | */ |
1109ca09 | 315 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
c507f7ef | 316 | |
75923280 AD |
317 | /** |
318 | * radeon_ring_write - write a value to the ring | |
319 | * | |
320 | * @ring: radeon_ring structure holding ring information | |
321 | * @v: dword (dw) value to write | |
322 | * | |
323 | * Write a value to the requested ring buffer (all asics). | |
324 | */ | |
c507f7ef JG |
325 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
326 | { | |
327 | #if DRM_DEBUG_CODE | |
328 | if (ring->count_dw <= 0) { | |
8ad33cdf | 329 | DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); |
c507f7ef JG |
330 | } |
331 | #endif | |
332 | ring->ring[ring->wptr++] = v; | |
333 | ring->wptr &= ring->ptr_mask; | |
334 | ring->count_dw--; | |
335 | ring->ring_free_dw--; | |
336 | } | |
337 | ||
75923280 AD |
338 | /** |
339 | * radeon_ring_supports_scratch_reg - check if the ring supports | |
340 | * writing to scratch registers | |
341 | * | |
342 | * @rdev: radeon_device pointer | |
343 | * @ring: radeon_ring structure holding ring information | |
344 | * | |
345 | * Check if a specific ring supports writing to scratch registers (all asics). | |
346 | * Returns true if the ring supports writing to scratch regs, false if not. | |
347 | */ | |
89d35807 AD |
348 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
349 | struct radeon_ring *ring) | |
350 | { | |
351 | switch (ring->idx) { | |
352 | case RADEON_RING_TYPE_GFX_INDEX: | |
353 | case CAYMAN_RING_TYPE_CP1_INDEX: | |
354 | case CAYMAN_RING_TYPE_CP2_INDEX: | |
355 | return true; | |
356 | default: | |
357 | return false; | |
358 | } | |
359 | } | |
360 | ||
f93bdefe AD |
361 | u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev, |
362 | struct radeon_ring *ring) | |
363 | { | |
364 | u32 rptr; | |
365 | ||
02c9f7fa | 366 | if (rdev->wb.enabled) |
f93bdefe AD |
367 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); |
368 | else | |
369 | rptr = RREG32(ring->rptr_reg); | |
f93bdefe AD |
370 | |
371 | return rptr; | |
372 | } | |
373 | ||
374 | u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev, | |
375 | struct radeon_ring *ring) | |
376 | { | |
377 | u32 wptr; | |
378 | ||
379 | wptr = RREG32(ring->wptr_reg); | |
f93bdefe AD |
380 | |
381 | return wptr; | |
382 | } | |
383 | ||
384 | void radeon_ring_generic_set_wptr(struct radeon_device *rdev, | |
385 | struct radeon_ring *ring) | |
386 | { | |
2e1e6dad | 387 | WREG32(ring->wptr_reg, ring->wptr); |
f93bdefe AD |
388 | (void)RREG32(ring->wptr_reg); |
389 | } | |
390 | ||
75923280 AD |
391 | /** |
392 | * radeon_ring_free_size - update the free size | |
393 | * | |
394 | * @rdev: radeon_device pointer | |
395 | * @ring: radeon_ring structure holding ring information | |
396 | * | |
397 | * Update the free dw slots in the ring buffer (all asics). | |
398 | */ | |
e32eb50d | 399 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 400 | { |
f93bdefe | 401 | ring->rptr = radeon_ring_get_rptr(rdev, ring); |
771fe6b9 | 402 | /* This works because ring_size is a power of 2 */ |
e32eb50d CK |
403 | ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); |
404 | ring->ring_free_dw -= ring->wptr; | |
405 | ring->ring_free_dw &= ring->ptr_mask; | |
406 | if (!ring->ring_free_dw) { | |
407 | ring->ring_free_dw = ring->ring_size / 4; | |
771fe6b9 JG |
408 | } |
409 | } | |
410 | ||
75923280 AD |
411 | /** |
412 | * radeon_ring_alloc - allocate space on the ring buffer | |
413 | * | |
414 | * @rdev: radeon_device pointer | |
415 | * @ring: radeon_ring structure holding ring information | |
416 | * @ndw: number of dwords to allocate in the ring buffer | |
417 | * | |
418 | * Allocate @ndw dwords in the ring buffer (all asics). | |
419 | * Returns 0 on success, error on failure. | |
420 | */ | |
e32eb50d | 421 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
771fe6b9 JG |
422 | { |
423 | int r; | |
424 | ||
fd5d93a0 AD |
425 | /* make sure we aren't trying to allocate more space than there is on the ring */ |
426 | if (ndw > (ring->ring_size / 4)) | |
427 | return -ENOMEM; | |
771fe6b9 JG |
428 | /* Align requested size with padding so unlock_commit can |
429 | * pad safely */ | |
8444d5c6 JG |
430 | radeon_ring_free_size(rdev, ring); |
431 | if (ring->ring_free_dw == (ring->ring_size / 4)) { | |
432 | /* This is an empty ring update lockup info to avoid | |
433 | * false positive. | |
434 | */ | |
435 | radeon_ring_lockup_update(ring); | |
436 | } | |
e32eb50d CK |
437 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
438 | while (ndw > (ring->ring_free_dw - 1)) { | |
439 | radeon_ring_free_size(rdev, ring); | |
440 | if (ndw < ring->ring_free_dw) { | |
771fe6b9 JG |
441 | break; |
442 | } | |
8b25ed34 | 443 | r = radeon_fence_wait_next_locked(rdev, ring->idx); |
91700f3c | 444 | if (r) |
771fe6b9 | 445 | return r; |
771fe6b9 | 446 | } |
e32eb50d CK |
447 | ring->count_dw = ndw; |
448 | ring->wptr_old = ring->wptr; | |
771fe6b9 JG |
449 | return 0; |
450 | } | |
451 | ||
75923280 AD |
452 | /** |
453 | * radeon_ring_lock - lock the ring and allocate space on it | |
454 | * | |
455 | * @rdev: radeon_device pointer | |
456 | * @ring: radeon_ring structure holding ring information | |
457 | * @ndw: number of dwords to allocate in the ring buffer | |
458 | * | |
459 | * Lock the ring and allocate @ndw dwords in the ring buffer | |
460 | * (all asics). | |
461 | * Returns 0 on success, error on failure. | |
462 | */ | |
e32eb50d | 463 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
91700f3c MG |
464 | { |
465 | int r; | |
466 | ||
d6999bc7 | 467 | mutex_lock(&rdev->ring_lock); |
e32eb50d | 468 | r = radeon_ring_alloc(rdev, ring, ndw); |
91700f3c | 469 | if (r) { |
d6999bc7 | 470 | mutex_unlock(&rdev->ring_lock); |
91700f3c MG |
471 | return r; |
472 | } | |
473 | return 0; | |
474 | } | |
475 | ||
75923280 AD |
476 | /** |
477 | * radeon_ring_commit - tell the GPU to execute the new | |
478 | * commands on the ring buffer | |
479 | * | |
480 | * @rdev: radeon_device pointer | |
481 | * @ring: radeon_ring structure holding ring information | |
482 | * | |
483 | * Update the wptr (write pointer) to tell the GPU to | |
484 | * execute new commands on the ring buffer (all asics). | |
485 | */ | |
e32eb50d | 486 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 487 | { |
771fe6b9 | 488 | /* We pad to match fetch size */ |
07a71330 | 489 | while (ring->wptr & ring->align_mask) { |
78c5560a | 490 | radeon_ring_write(ring, ring->nop); |
771fe6b9 JG |
491 | } |
492 | DRM_MEMORYBARRIER(); | |
f93bdefe | 493 | radeon_ring_set_wptr(rdev, ring); |
91700f3c MG |
494 | } |
495 | ||
75923280 AD |
496 | /** |
497 | * radeon_ring_unlock_commit - tell the GPU to execute the new | |
498 | * commands on the ring buffer and unlock it | |
499 | * | |
500 | * @rdev: radeon_device pointer | |
501 | * @ring: radeon_ring structure holding ring information | |
502 | * | |
503 | * Call radeon_ring_commit() then unlock the ring (all asics). | |
504 | */ | |
e32eb50d | 505 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
91700f3c | 506 | { |
e32eb50d | 507 | radeon_ring_commit(rdev, ring); |
d6999bc7 | 508 | mutex_unlock(&rdev->ring_lock); |
771fe6b9 JG |
509 | } |
510 | ||
75923280 AD |
511 | /** |
512 | * radeon_ring_undo - reset the wptr | |
513 | * | |
514 | * @ring: radeon_ring structure holding ring information | |
515 | * | |
501f9d4c | 516 | * Reset the driver's copy of the wptr (all asics). |
75923280 | 517 | */ |
d6999bc7 | 518 | void radeon_ring_undo(struct radeon_ring *ring) |
771fe6b9 | 519 | { |
e32eb50d | 520 | ring->wptr = ring->wptr_old; |
d6999bc7 CK |
521 | } |
522 | ||
75923280 AD |
523 | /** |
524 | * radeon_ring_unlock_undo - reset the wptr and unlock the ring | |
525 | * | |
526 | * @ring: radeon_ring structure holding ring information | |
527 | * | |
528 | * Call radeon_ring_undo() then unlock the ring (all asics). | |
529 | */ | |
d6999bc7 CK |
530 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
531 | { | |
532 | radeon_ring_undo(ring); | |
533 | mutex_unlock(&rdev->ring_lock); | |
771fe6b9 JG |
534 | } |
535 | ||
75923280 AD |
536 | /** |
537 | * radeon_ring_force_activity - add some nop packets to the ring | |
538 | * | |
539 | * @rdev: radeon_device pointer | |
540 | * @ring: radeon_ring structure holding ring information | |
541 | * | |
542 | * Add some nop packets to the ring to force activity (all asics). | |
543 | * Used for lockup detection to see if the rptr is advancing. | |
544 | */ | |
7b9ef16b CK |
545 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring) |
546 | { | |
547 | int r; | |
548 | ||
7b9ef16b CK |
549 | radeon_ring_free_size(rdev, ring); |
550 | if (ring->rptr == ring->wptr) { | |
551 | r = radeon_ring_alloc(rdev, ring, 1); | |
552 | if (!r) { | |
553 | radeon_ring_write(ring, ring->nop); | |
554 | radeon_ring_commit(rdev, ring); | |
555 | } | |
556 | } | |
7b9ef16b CK |
557 | } |
558 | ||
75923280 | 559 | /** |
501f9d4c | 560 | * radeon_ring_lockup_update - update lockup variables |
75923280 AD |
561 | * |
562 | * @ring: radeon_ring structure holding ring information | |
563 | * | |
564 | * Update the last rptr value and timestamp (all asics). | |
565 | */ | |
069211e5 CK |
566 | void radeon_ring_lockup_update(struct radeon_ring *ring) |
567 | { | |
568 | ring->last_rptr = ring->rptr; | |
569 | ring->last_activity = jiffies; | |
570 | } | |
571 | ||
572 | /** | |
573 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information | |
574 | * @rdev: radeon device structure | |
575 | * @ring: radeon_ring structure holding ring information | |
576 | * | |
577 | * We don't need to initialize the lockup tracking information as we will either | |
578 | * have CP rptr to a different value of jiffies wrap around which will force | |
579 | * initialization of the lockup tracking informations. | |
580 | * | |
581 | * A possible false positivie is if we get call after while and last_cp_rptr == | |
582 | * the current CP rptr, even if it's unlikely it might happen. To avoid this | |
583 | * if the elapsed time since last call is bigger than 2 second than we return | |
584 | * false and update the tracking information. Due to this the caller must call | |
585 | * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported | |
586 | * the fencing code should be cautious about that. | |
587 | * | |
588 | * Caller should write to the ring to force CP to do something so we don't get | |
589 | * false positive when CP is just gived nothing to do. | |
590 | * | |
591 | **/ | |
592 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) | |
593 | { | |
594 | unsigned long cjiffies, elapsed; | |
069211e5 CK |
595 | |
596 | cjiffies = jiffies; | |
597 | if (!time_after(cjiffies, ring->last_activity)) { | |
598 | /* likely a wrap around */ | |
599 | radeon_ring_lockup_update(ring); | |
600 | return false; | |
601 | } | |
f93bdefe | 602 | ring->rptr = radeon_ring_get_rptr(rdev, ring); |
069211e5 CK |
603 | if (ring->rptr != ring->last_rptr) { |
604 | /* CP is still working no lockup */ | |
605 | radeon_ring_lockup_update(ring); | |
606 | return false; | |
607 | } | |
608 | elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); | |
3368ff0c | 609 | if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { |
069211e5 CK |
610 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
611 | return true; | |
612 | } | |
613 | /* give a chance to the GPU ... */ | |
614 | return false; | |
615 | } | |
616 | ||
55d7c221 CK |
617 | /** |
618 | * radeon_ring_backup - Back up the content of a ring | |
619 | * | |
620 | * @rdev: radeon_device pointer | |
621 | * @ring: the ring we want to back up | |
622 | * | |
623 | * Saves all unprocessed commits from a ring, returns the number of dwords saved. | |
624 | */ | |
625 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, | |
626 | uint32_t **data) | |
627 | { | |
628 | unsigned size, ptr, i; | |
55d7c221 CK |
629 | |
630 | /* just in case lock the ring */ | |
631 | mutex_lock(&rdev->ring_lock); | |
632 | *data = NULL; | |
633 | ||
89d35807 | 634 | if (ring->ring_obj == NULL) { |
55d7c221 CK |
635 | mutex_unlock(&rdev->ring_lock); |
636 | return 0; | |
637 | } | |
638 | ||
639 | /* it doesn't make sense to save anything if all fences are signaled */ | |
8b25ed34 | 640 | if (!radeon_fence_count_emitted(rdev, ring->idx)) { |
55d7c221 CK |
641 | mutex_unlock(&rdev->ring_lock); |
642 | return 0; | |
643 | } | |
644 | ||
645 | /* calculate the number of dw on the ring */ | |
89d35807 AD |
646 | if (ring->rptr_save_reg) |
647 | ptr = RREG32(ring->rptr_save_reg); | |
648 | else if (rdev->wb.enabled) | |
649 | ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); | |
650 | else { | |
651 | /* no way to read back the next rptr */ | |
652 | mutex_unlock(&rdev->ring_lock); | |
653 | return 0; | |
654 | } | |
655 | ||
55d7c221 CK |
656 | size = ring->wptr + (ring->ring_size / 4); |
657 | size -= ptr; | |
658 | size &= ring->ptr_mask; | |
659 | if (size == 0) { | |
660 | mutex_unlock(&rdev->ring_lock); | |
661 | return 0; | |
662 | } | |
663 | ||
664 | /* and then save the content of the ring */ | |
1e179d4e DC |
665 | *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); |
666 | if (!*data) { | |
667 | mutex_unlock(&rdev->ring_lock); | |
668 | return 0; | |
669 | } | |
55d7c221 CK |
670 | for (i = 0; i < size; ++i) { |
671 | (*data)[i] = ring->ring[ptr++]; | |
672 | ptr &= ring->ptr_mask; | |
673 | } | |
674 | ||
675 | mutex_unlock(&rdev->ring_lock); | |
676 | return size; | |
677 | } | |
678 | ||
679 | /** | |
680 | * radeon_ring_restore - append saved commands to the ring again | |
681 | * | |
682 | * @rdev: radeon_device pointer | |
683 | * @ring: ring to append commands to | |
684 | * @size: number of dwords we want to write | |
685 | * @data: saved commands | |
686 | * | |
687 | * Allocates space on the ring and restore the previously saved commands. | |
688 | */ | |
689 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |
690 | unsigned size, uint32_t *data) | |
691 | { | |
692 | int i, r; | |
693 | ||
694 | if (!size || !data) | |
695 | return 0; | |
696 | ||
697 | /* restore the saved ring content */ | |
698 | r = radeon_ring_lock(rdev, ring, size); | |
699 | if (r) | |
700 | return r; | |
701 | ||
702 | for (i = 0; i < size; ++i) { | |
703 | radeon_ring_write(ring, data[i]); | |
704 | } | |
705 | ||
706 | radeon_ring_unlock_commit(rdev, ring); | |
707 | kfree(data); | |
708 | return 0; | |
709 | } | |
710 | ||
75923280 AD |
711 | /** |
712 | * radeon_ring_init - init driver ring struct. | |
713 | * | |
714 | * @rdev: radeon_device pointer | |
715 | * @ring: radeon_ring structure holding ring information | |
716 | * @ring_size: size of the ring | |
717 | * @rptr_offs: offset of the rptr writeback location in the WB buffer | |
718 | * @rptr_reg: MMIO offset of the rptr register | |
719 | * @wptr_reg: MMIO offset of the wptr register | |
75923280 AD |
720 | * @nop: nop packet for this ring |
721 | * | |
722 | * Initialize the driver information for the selected ring (all asics). | |
723 | * Returns 0 on success, error on failure. | |
724 | */ | |
e32eb50d | 725 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
2e1e6dad | 726 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop) |
771fe6b9 JG |
727 | { |
728 | int r; | |
729 | ||
e32eb50d CK |
730 | ring->ring_size = ring_size; |
731 | ring->rptr_offs = rptr_offs; | |
732 | ring->rptr_reg = rptr_reg; | |
733 | ring->wptr_reg = wptr_reg; | |
78c5560a | 734 | ring->nop = nop; |
771fe6b9 | 735 | /* Allocate ring buffer */ |
e32eb50d CK |
736 | if (ring->ring_obj == NULL) { |
737 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, | |
40f5cf99 AD |
738 | RADEON_GEM_DOMAIN_GTT, |
739 | NULL, &ring->ring_obj); | |
771fe6b9 | 740 | if (r) { |
4c788679 | 741 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
771fe6b9 JG |
742 | return r; |
743 | } | |
e32eb50d | 744 | r = radeon_bo_reserve(ring->ring_obj, false); |
4c788679 JG |
745 | if (unlikely(r != 0)) |
746 | return r; | |
e32eb50d CK |
747 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
748 | &ring->gpu_addr); | |
771fe6b9 | 749 | if (r) { |
e32eb50d | 750 | radeon_bo_unreserve(ring->ring_obj); |
4c788679 | 751 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
771fe6b9 JG |
752 | return r; |
753 | } | |
e32eb50d CK |
754 | r = radeon_bo_kmap(ring->ring_obj, |
755 | (void **)&ring->ring); | |
756 | radeon_bo_unreserve(ring->ring_obj); | |
771fe6b9 | 757 | if (r) { |
4c788679 | 758 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
771fe6b9 JG |
759 | return r; |
760 | } | |
761 | } | |
e32eb50d CK |
762 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
763 | ring->ring_free_dw = ring->ring_size / 4; | |
89d35807 AD |
764 | if (rdev->wb.enabled) { |
765 | u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); | |
766 | ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; | |
767 | ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; | |
768 | } | |
ec1a6cce CK |
769 | if (radeon_debugfs_ring_init(rdev, ring)) { |
770 | DRM_ERROR("Failed to register debugfs file for rings !\n"); | |
771 | } | |
48c0ac99 | 772 | radeon_ring_lockup_update(ring); |
771fe6b9 JG |
773 | return 0; |
774 | } | |
775 | ||
75923280 AD |
776 | /** |
777 | * radeon_ring_fini - tear down the driver ring struct. | |
778 | * | |
779 | * @rdev: radeon_device pointer | |
780 | * @ring: radeon_ring structure holding ring information | |
781 | * | |
782 | * Tear down the driver information for the selected ring (all asics). | |
783 | */ | |
e32eb50d | 784 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 785 | { |
4c788679 | 786 | int r; |
ca2af923 | 787 | struct radeon_bo *ring_obj; |
4c788679 | 788 | |
d6999bc7 | 789 | mutex_lock(&rdev->ring_lock); |
e32eb50d | 790 | ring_obj = ring->ring_obj; |
d6999bc7 | 791 | ring->ready = false; |
e32eb50d CK |
792 | ring->ring = NULL; |
793 | ring->ring_obj = NULL; | |
d6999bc7 | 794 | mutex_unlock(&rdev->ring_lock); |
ca2af923 AD |
795 | |
796 | if (ring_obj) { | |
797 | r = radeon_bo_reserve(ring_obj, false); | |
4c788679 | 798 | if (likely(r == 0)) { |
ca2af923 AD |
799 | radeon_bo_kunmap(ring_obj); |
800 | radeon_bo_unpin(ring_obj); | |
801 | radeon_bo_unreserve(ring_obj); | |
4c788679 | 802 | } |
ca2af923 | 803 | radeon_bo_unref(&ring_obj); |
771fe6b9 | 804 | } |
771fe6b9 JG |
805 | } |
806 | ||
771fe6b9 JG |
807 | /* |
808 | * Debugfs info | |
809 | */ | |
810 | #if defined(CONFIG_DEBUG_FS) | |
af9720f4 CK |
811 | |
812 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) | |
813 | { | |
814 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
815 | struct drm_device *dev = node->minor->dev; | |
816 | struct radeon_device *rdev = dev->dev_private; | |
817 | int ridx = *(int*)node->info_ent->data; | |
818 | struct radeon_ring *ring = &rdev->ring[ridx]; | |
819 | unsigned count, i, j; | |
4d009190 | 820 | u32 tmp; |
af9720f4 CK |
821 | |
822 | radeon_ring_free_size(rdev, ring); | |
823 | count = (ring->ring_size / 4) - ring->ring_free_dw; | |
f93bdefe | 824 | tmp = radeon_ring_get_wptr(rdev, ring); |
4d009190 | 825 | seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp); |
f93bdefe | 826 | tmp = radeon_ring_get_rptr(rdev, ring); |
4d009190 | 827 | seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp); |
45df6803 CK |
828 | if (ring->rptr_save_reg) { |
829 | seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg, | |
830 | RREG32(ring->rptr_save_reg)); | |
831 | } | |
4d009190 JG |
832 | seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr); |
833 | seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr); | |
5f0839c1 JG |
834 | seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr); |
835 | seq_printf(m, "last semaphore wait addr : 0x%016llx\n", ring->last_semaphore_wait_addr); | |
af9720f4 CK |
836 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
837 | seq_printf(m, "%u dwords in ring\n", count); | |
4d009190 JG |
838 | /* print 8 dw before current rptr as often it's the last executed |
839 | * packet that is the root issue | |
840 | */ | |
841 | i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; | |
0eb3448a AI |
842 | if (ring->ready) { |
843 | for (j = 0; j <= (count + 32); j++) { | |
844 | seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]); | |
845 | i = (i + 1) & ring->ptr_mask; | |
846 | } | |
af9720f4 CK |
847 | } |
848 | return 0; | |
849 | } | |
850 | ||
f2ba57b5 CK |
851 | static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX; |
852 | static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; | |
853 | static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; | |
854 | static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX; | |
855 | static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; | |
856 | static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX; | |
af9720f4 CK |
857 | |
858 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { | |
f2ba57b5 CK |
859 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index}, |
860 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index}, | |
861 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index}, | |
862 | {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index}, | |
863 | {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index}, | |
864 | {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index}, | |
af9720f4 CK |
865 | }; |
866 | ||
711a9729 CK |
867 | static int radeon_debugfs_sa_info(struct seq_file *m, void *data) |
868 | { | |
869 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
870 | struct drm_device *dev = node->minor->dev; | |
871 | struct radeon_device *rdev = dev->dev_private; | |
872 | ||
c507f7ef | 873 | radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); |
711a9729 CK |
874 | |
875 | return 0; | |
876 | ||
877 | } | |
878 | ||
879 | static struct drm_info_list radeon_debugfs_sa_list[] = { | |
880 | {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, | |
881 | }; | |
882 | ||
771fe6b9 JG |
883 | #endif |
884 | ||
1109ca09 | 885 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
af9720f4 CK |
886 | { |
887 | #if defined(CONFIG_DEBUG_FS) | |
ec1a6cce CK |
888 | unsigned i; |
889 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { | |
890 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; | |
891 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; | |
892 | unsigned r; | |
893 | ||
894 | if (&rdev->ring[ridx] != ring) | |
895 | continue; | |
896 | ||
897 | r = radeon_debugfs_add_files(rdev, info, 1); | |
898 | if (r) | |
899 | return r; | |
900 | } | |
af9720f4 | 901 | #endif |
ec1a6cce | 902 | return 0; |
af9720f4 CK |
903 | } |
904 | ||
1109ca09 | 905 | static int radeon_debugfs_sa_init(struct radeon_device *rdev) |
771fe6b9 JG |
906 | { |
907 | #if defined(CONFIG_DEBUG_FS) | |
c507f7ef | 908 | return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); |
771fe6b9 JG |
909 | #else |
910 | return 0; | |
911 | #endif | |
912 | } |