Commit | Line | Data |
---|---|---|
7433874e RM |
1 | /* |
2 | * Permission is hereby granted, free of charge, to any person obtaining a | |
3 | * copy of this software and associated documentation files (the "Software"), | |
4 | * to deal in the Software without restriction, including without limitation | |
5 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
6 | * and/or sell copies of the Software, and to permit persons to whom the | |
7 | * Software is furnished to do so, subject to the following conditions: | |
8 | * | |
9 | * The above copyright notice and this permission notice shall be included in | |
10 | * all copies or substantial portions of the Software. | |
11 | * | |
12 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
13 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
14 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
15 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
16 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
17 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
18 | * OTHER DEALINGS IN THE SOFTWARE. | |
19 | * | |
20 | * Authors: Rafał Miłecki <zajec5@gmail.com> | |
56278a8e | 21 | * Alex Deucher <alexdeucher@gmail.com> |
7433874e | 22 | */ |
760285e7 | 23 | #include <drm/drmP.h> |
7433874e | 24 | #include "radeon.h" |
f735261b | 25 | #include "avivod.h" |
8a83ec5e | 26 | #include "atom.h" |
ce8f5370 | 27 | #include <linux/power_supply.h> |
21a8122a AD |
28 | #include <linux/hwmon.h> |
29 | #include <linux/hwmon-sysfs.h> | |
7433874e | 30 | |
c913e23a RM |
31 | #define RADEON_IDLE_LOOP_MS 100 |
32 | #define RADEON_RECLOCK_DELAY_MS 200 | |
73a6d3fc | 33 | #define RADEON_WAIT_VBLANK_TIMEOUT 200 |
c913e23a | 34 | |
f712d0c7 | 35 | static const char *radeon_pm_state_type_name[5] = { |
eb2c27a0 | 36 | "", |
f712d0c7 RM |
37 | "Powersave", |
38 | "Battery", | |
39 | "Balanced", | |
40 | "Performance", | |
41 | }; | |
42 | ||
ce8f5370 | 43 | static void radeon_dynpm_idle_work_handler(struct work_struct *work); |
c913e23a | 44 | static int radeon_debugfs_pm_init(struct radeon_device *rdev); |
ce8f5370 AD |
45 | static bool radeon_pm_in_vbl(struct radeon_device *rdev); |
46 | static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); | |
47 | static void radeon_pm_update_profile(struct radeon_device *rdev); | |
48 | static void radeon_pm_set_clocks(struct radeon_device *rdev); | |
49 | ||
a4c9e2ee AD |
50 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
51 | enum radeon_pm_state_type ps_type, | |
52 | int instance) | |
53 | { | |
54 | int i; | |
55 | int found_instance = -1; | |
56 | ||
57 | for (i = 0; i < rdev->pm.num_power_states; i++) { | |
58 | if (rdev->pm.power_state[i].type == ps_type) { | |
59 | found_instance++; | |
60 | if (found_instance == instance) | |
61 | return i; | |
62 | } | |
63 | } | |
64 | /* return default if no match */ | |
65 | return rdev->pm.default_power_state_index; | |
66 | } | |
67 | ||
c4917074 | 68 | void radeon_pm_acpi_event_handler(struct radeon_device *rdev) |
ce8f5370 | 69 | { |
1c71bda0 AD |
70 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { |
71 | mutex_lock(&rdev->pm.mutex); | |
72 | if (power_supply_is_system_supplied() > 0) | |
73 | rdev->pm.dpm.ac_power = true; | |
74 | else | |
75 | rdev->pm.dpm.ac_power = false; | |
76 | if (rdev->asic->dpm.enable_bapm) | |
77 | radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); | |
78 | mutex_unlock(&rdev->pm.mutex); | |
79 | } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { | |
c4917074 AD |
80 | if (rdev->pm.profile == PM_PROFILE_AUTO) { |
81 | mutex_lock(&rdev->pm.mutex); | |
82 | radeon_pm_update_profile(rdev); | |
83 | radeon_pm_set_clocks(rdev); | |
84 | mutex_unlock(&rdev->pm.mutex); | |
ce8f5370 AD |
85 | } |
86 | } | |
ce8f5370 | 87 | } |
ce8f5370 AD |
88 | |
89 | static void radeon_pm_update_profile(struct radeon_device *rdev) | |
90 | { | |
91 | switch (rdev->pm.profile) { | |
92 | case PM_PROFILE_DEFAULT: | |
93 | rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; | |
94 | break; | |
95 | case PM_PROFILE_AUTO: | |
96 | if (power_supply_is_system_supplied() > 0) { | |
97 | if (rdev->pm.active_crtc_count > 1) | |
98 | rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; | |
99 | else | |
100 | rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; | |
101 | } else { | |
102 | if (rdev->pm.active_crtc_count > 1) | |
c9e75b21 | 103 | rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; |
ce8f5370 | 104 | else |
c9e75b21 | 105 | rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; |
ce8f5370 AD |
106 | } |
107 | break; | |
108 | case PM_PROFILE_LOW: | |
109 | if (rdev->pm.active_crtc_count > 1) | |
110 | rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; | |
111 | else | |
112 | rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; | |
113 | break; | |
c9e75b21 AD |
114 | case PM_PROFILE_MID: |
115 | if (rdev->pm.active_crtc_count > 1) | |
116 | rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; | |
117 | else | |
118 | rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; | |
119 | break; | |
ce8f5370 AD |
120 | case PM_PROFILE_HIGH: |
121 | if (rdev->pm.active_crtc_count > 1) | |
122 | rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; | |
123 | else | |
124 | rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; | |
125 | break; | |
126 | } | |
127 | ||
128 | if (rdev->pm.active_crtc_count == 0) { | |
129 | rdev->pm.requested_power_state_index = | |
130 | rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; | |
131 | rdev->pm.requested_clock_mode_index = | |
132 | rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; | |
133 | } else { | |
134 | rdev->pm.requested_power_state_index = | |
135 | rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; | |
136 | rdev->pm.requested_clock_mode_index = | |
137 | rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; | |
138 | } | |
139 | } | |
c913e23a | 140 | |
5876dd24 MG |
141 | static void radeon_unmap_vram_bos(struct radeon_device *rdev) |
142 | { | |
143 | struct radeon_bo *bo, *n; | |
144 | ||
145 | if (list_empty(&rdev->gem.objects)) | |
146 | return; | |
147 | ||
148 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { | |
149 | if (bo->tbo.mem.mem_type == TTM_PL_VRAM) | |
150 | ttm_bo_unmap_virtual(&bo->tbo); | |
151 | } | |
5876dd24 MG |
152 | } |
153 | ||
ce8f5370 | 154 | static void radeon_sync_with_vblank(struct radeon_device *rdev) |
a424816f | 155 | { |
ce8f5370 AD |
156 | if (rdev->pm.active_crtcs) { |
157 | rdev->pm.vblank_sync = false; | |
158 | wait_event_timeout( | |
159 | rdev->irq.vblank_queue, rdev->pm.vblank_sync, | |
160 | msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); | |
161 | } | |
162 | } | |
163 | ||
164 | static void radeon_set_power_state(struct radeon_device *rdev) | |
165 | { | |
166 | u32 sclk, mclk; | |
92645879 | 167 | bool misc_after = false; |
ce8f5370 AD |
168 | |
169 | if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && | |
170 | (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) | |
171 | return; | |
172 | ||
173 | if (radeon_gui_idle(rdev)) { | |
174 | sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
175 | clock_info[rdev->pm.requested_clock_mode_index].sclk; | |
9ace9f7b AD |
176 | if (sclk > rdev->pm.default_sclk) |
177 | sclk = rdev->pm.default_sclk; | |
ce8f5370 | 178 | |
27810fb2 AD |
179 | /* starting with BTC, there is one state that is used for both |
180 | * MH and SH. Difference is that we always use the high clock index for | |
7ae764b1 | 181 | * mclk and vddci. |
27810fb2 AD |
182 | */ |
183 | if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && | |
184 | (rdev->family >= CHIP_BARTS) && | |
185 | rdev->pm.active_crtc_count && | |
186 | ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || | |
187 | (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) | |
188 | mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
189 | clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; | |
190 | else | |
191 | mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
192 | clock_info[rdev->pm.requested_clock_mode_index].mclk; | |
193 | ||
9ace9f7b AD |
194 | if (mclk > rdev->pm.default_mclk) |
195 | mclk = rdev->pm.default_mclk; | |
ce8f5370 | 196 | |
92645879 AD |
197 | /* upvolt before raising clocks, downvolt after lowering clocks */ |
198 | if (sclk < rdev->pm.current_sclk) | |
199 | misc_after = true; | |
ce8f5370 | 200 | |
92645879 | 201 | radeon_sync_with_vblank(rdev); |
ce8f5370 | 202 | |
92645879 | 203 | if (rdev->pm.pm_method == PM_METHOD_DYNPM) { |
ce8f5370 AD |
204 | if (!radeon_pm_in_vbl(rdev)) |
205 | return; | |
92645879 | 206 | } |
ce8f5370 | 207 | |
92645879 | 208 | radeon_pm_prepare(rdev); |
ce8f5370 | 209 | |
92645879 AD |
210 | if (!misc_after) |
211 | /* voltage, pcie lanes, etc.*/ | |
212 | radeon_pm_misc(rdev); | |
213 | ||
214 | /* set engine clock */ | |
215 | if (sclk != rdev->pm.current_sclk) { | |
216 | radeon_pm_debug_check_in_vbl(rdev, false); | |
217 | radeon_set_engine_clock(rdev, sclk); | |
218 | radeon_pm_debug_check_in_vbl(rdev, true); | |
219 | rdev->pm.current_sclk = sclk; | |
d9fdaafb | 220 | DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); |
92645879 AD |
221 | } |
222 | ||
223 | /* set memory clock */ | |
798bcf73 | 224 | if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { |
92645879 AD |
225 | radeon_pm_debug_check_in_vbl(rdev, false); |
226 | radeon_set_memory_clock(rdev, mclk); | |
227 | radeon_pm_debug_check_in_vbl(rdev, true); | |
228 | rdev->pm.current_mclk = mclk; | |
d9fdaafb | 229 | DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); |
ce8f5370 | 230 | } |
2aba631c | 231 | |
92645879 AD |
232 | if (misc_after) |
233 | /* voltage, pcie lanes, etc.*/ | |
234 | radeon_pm_misc(rdev); | |
235 | ||
236 | radeon_pm_finish(rdev); | |
237 | ||
ce8f5370 AD |
238 | rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; |
239 | rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; | |
240 | } else | |
d9fdaafb | 241 | DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); |
ce8f5370 AD |
242 | } |
243 | ||
244 | static void radeon_pm_set_clocks(struct radeon_device *rdev) | |
245 | { | |
5f8f635e | 246 | int i, r; |
c37d230a | 247 | |
4e186b2d AD |
248 | /* no need to take locks, etc. if nothing's going to change */ |
249 | if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && | |
250 | (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) | |
251 | return; | |
252 | ||
612e06ce | 253 | mutex_lock(&rdev->ddev->struct_mutex); |
db7fce39 | 254 | down_write(&rdev->pm.mclk_lock); |
d6999bc7 | 255 | mutex_lock(&rdev->ring_lock); |
4f3218cb | 256 | |
95f5a3ac AD |
257 | /* wait for the rings to drain */ |
258 | for (i = 0; i < RADEON_NUM_RINGS; i++) { | |
259 | struct radeon_ring *ring = &rdev->ring[i]; | |
5f8f635e JG |
260 | if (!ring->ready) { |
261 | continue; | |
262 | } | |
263 | r = radeon_fence_wait_empty_locked(rdev, i); | |
264 | if (r) { | |
265 | /* needs a GPU reset dont reset here */ | |
266 | mutex_unlock(&rdev->ring_lock); | |
267 | up_write(&rdev->pm.mclk_lock); | |
268 | mutex_unlock(&rdev->ddev->struct_mutex); | |
269 | return; | |
270 | } | |
4f3218cb | 271 | } |
95f5a3ac | 272 | |
5876dd24 MG |
273 | radeon_unmap_vram_bos(rdev); |
274 | ||
ce8f5370 | 275 | if (rdev->irq.installed) { |
2aba631c MG |
276 | for (i = 0; i < rdev->num_crtc; i++) { |
277 | if (rdev->pm.active_crtcs & (1 << i)) { | |
278 | rdev->pm.req_vblank |= (1 << i); | |
279 | drm_vblank_get(rdev->ddev, i); | |
280 | } | |
281 | } | |
282 | } | |
539d2418 | 283 | |
ce8f5370 | 284 | radeon_set_power_state(rdev); |
2aba631c | 285 | |
ce8f5370 | 286 | if (rdev->irq.installed) { |
2aba631c MG |
287 | for (i = 0; i < rdev->num_crtc; i++) { |
288 | if (rdev->pm.req_vblank & (1 << i)) { | |
289 | rdev->pm.req_vblank &= ~(1 << i); | |
290 | drm_vblank_put(rdev->ddev, i); | |
291 | } | |
292 | } | |
293 | } | |
5876dd24 | 294 | |
a424816f AD |
295 | /* update display watermarks based on new power state */ |
296 | radeon_update_bandwidth_info(rdev); | |
297 | if (rdev->pm.active_crtc_count) | |
298 | radeon_bandwidth_update(rdev); | |
299 | ||
ce8f5370 | 300 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; |
2aba631c | 301 | |
d6999bc7 | 302 | mutex_unlock(&rdev->ring_lock); |
db7fce39 | 303 | up_write(&rdev->pm.mclk_lock); |
612e06ce | 304 | mutex_unlock(&rdev->ddev->struct_mutex); |
a424816f AD |
305 | } |
306 | ||
f712d0c7 RM |
307 | static void radeon_pm_print_states(struct radeon_device *rdev) |
308 | { | |
309 | int i, j; | |
310 | struct radeon_power_state *power_state; | |
311 | struct radeon_pm_clock_info *clock_info; | |
312 | ||
d9fdaafb | 313 | DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); |
f712d0c7 RM |
314 | for (i = 0; i < rdev->pm.num_power_states; i++) { |
315 | power_state = &rdev->pm.power_state[i]; | |
d9fdaafb | 316 | DRM_DEBUG_DRIVER("State %d: %s\n", i, |
f712d0c7 RM |
317 | radeon_pm_state_type_name[power_state->type]); |
318 | if (i == rdev->pm.default_power_state_index) | |
d9fdaafb | 319 | DRM_DEBUG_DRIVER("\tDefault"); |
f712d0c7 | 320 | if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) |
d9fdaafb | 321 | DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); |
f712d0c7 | 322 | if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
d9fdaafb DA |
323 | DRM_DEBUG_DRIVER("\tSingle display only\n"); |
324 | DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); | |
f712d0c7 RM |
325 | for (j = 0; j < power_state->num_clock_modes; j++) { |
326 | clock_info = &(power_state->clock_info[j]); | |
327 | if (rdev->flags & RADEON_IS_IGP) | |
eb2c27a0 AD |
328 | DRM_DEBUG_DRIVER("\t\t%d e: %d\n", |
329 | j, | |
330 | clock_info->sclk * 10); | |
f712d0c7 | 331 | else |
eb2c27a0 AD |
332 | DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n", |
333 | j, | |
334 | clock_info->sclk * 10, | |
335 | clock_info->mclk * 10, | |
336 | clock_info->voltage.voltage); | |
f712d0c7 RM |
337 | } |
338 | } | |
339 | } | |
340 | ||
ce8f5370 AD |
341 | static ssize_t radeon_get_pm_profile(struct device *dev, |
342 | struct device_attribute *attr, | |
343 | char *buf) | |
a424816f | 344 | { |
3e4e2129 | 345 | struct drm_device *ddev = dev_get_drvdata(dev); |
a424816f | 346 | struct radeon_device *rdev = ddev->dev_private; |
ce8f5370 | 347 | int cp = rdev->pm.profile; |
a424816f | 348 | |
ce8f5370 AD |
349 | return snprintf(buf, PAGE_SIZE, "%s\n", |
350 | (cp == PM_PROFILE_AUTO) ? "auto" : | |
351 | (cp == PM_PROFILE_LOW) ? "low" : | |
12e27be8 | 352 | (cp == PM_PROFILE_MID) ? "mid" : |
ce8f5370 | 353 | (cp == PM_PROFILE_HIGH) ? "high" : "default"); |
a424816f AD |
354 | } |
355 | ||
ce8f5370 AD |
356 | static ssize_t radeon_set_pm_profile(struct device *dev, |
357 | struct device_attribute *attr, | |
358 | const char *buf, | |
359 | size_t count) | |
a424816f | 360 | { |
3e4e2129 | 361 | struct drm_device *ddev = dev_get_drvdata(dev); |
a424816f | 362 | struct radeon_device *rdev = ddev->dev_private; |
a424816f AD |
363 | |
364 | mutex_lock(&rdev->pm.mutex); | |
ce8f5370 AD |
365 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
366 | if (strncmp("default", buf, strlen("default")) == 0) | |
367 | rdev->pm.profile = PM_PROFILE_DEFAULT; | |
368 | else if (strncmp("auto", buf, strlen("auto")) == 0) | |
369 | rdev->pm.profile = PM_PROFILE_AUTO; | |
370 | else if (strncmp("low", buf, strlen("low")) == 0) | |
371 | rdev->pm.profile = PM_PROFILE_LOW; | |
c9e75b21 AD |
372 | else if (strncmp("mid", buf, strlen("mid")) == 0) |
373 | rdev->pm.profile = PM_PROFILE_MID; | |
ce8f5370 AD |
374 | else if (strncmp("high", buf, strlen("high")) == 0) |
375 | rdev->pm.profile = PM_PROFILE_HIGH; | |
376 | else { | |
1783e4bf | 377 | count = -EINVAL; |
ce8f5370 | 378 | goto fail; |
a424816f | 379 | } |
ce8f5370 AD |
380 | radeon_pm_update_profile(rdev); |
381 | radeon_pm_set_clocks(rdev); | |
1783e4bf TR |
382 | } else |
383 | count = -EINVAL; | |
384 | ||
ce8f5370 | 385 | fail: |
a424816f AD |
386 | mutex_unlock(&rdev->pm.mutex); |
387 | ||
388 | return count; | |
389 | } | |
390 | ||
ce8f5370 AD |
391 | static ssize_t radeon_get_pm_method(struct device *dev, |
392 | struct device_attribute *attr, | |
393 | char *buf) | |
a424816f | 394 | { |
3e4e2129 | 395 | struct drm_device *ddev = dev_get_drvdata(dev); |
a424816f | 396 | struct radeon_device *rdev = ddev->dev_private; |
ce8f5370 | 397 | int pm = rdev->pm.pm_method; |
a424816f AD |
398 | |
399 | return snprintf(buf, PAGE_SIZE, "%s\n", | |
da321c8a AD |
400 | (pm == PM_METHOD_DYNPM) ? "dynpm" : |
401 | (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); | |
a424816f AD |
402 | } |
403 | ||
ce8f5370 AD |
404 | static ssize_t radeon_set_pm_method(struct device *dev, |
405 | struct device_attribute *attr, | |
406 | const char *buf, | |
407 | size_t count) | |
a424816f | 408 | { |
3e4e2129 | 409 | struct drm_device *ddev = dev_get_drvdata(dev); |
a424816f | 410 | struct radeon_device *rdev = ddev->dev_private; |
a424816f | 411 | |
da321c8a AD |
412 | /* we don't support the legacy modes with dpm */ |
413 | if (rdev->pm.pm_method == PM_METHOD_DPM) { | |
414 | count = -EINVAL; | |
415 | goto fail; | |
416 | } | |
ce8f5370 AD |
417 | |
418 | if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { | |
a424816f | 419 | mutex_lock(&rdev->pm.mutex); |
ce8f5370 AD |
420 | rdev->pm.pm_method = PM_METHOD_DYNPM; |
421 | rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; | |
422 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; | |
a424816f | 423 | mutex_unlock(&rdev->pm.mutex); |
ce8f5370 AD |
424 | } else if (strncmp("profile", buf, strlen("profile")) == 0) { |
425 | mutex_lock(&rdev->pm.mutex); | |
ce8f5370 AD |
426 | /* disable dynpm */ |
427 | rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; | |
428 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; | |
3f53eb6f | 429 | rdev->pm.pm_method = PM_METHOD_PROFILE; |
ce8f5370 | 430 | mutex_unlock(&rdev->pm.mutex); |
32c87fca | 431 | cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); |
ce8f5370 | 432 | } else { |
1783e4bf | 433 | count = -EINVAL; |
ce8f5370 AD |
434 | goto fail; |
435 | } | |
436 | radeon_pm_compute_clocks(rdev); | |
437 | fail: | |
a424816f AD |
438 | return count; |
439 | } | |
440 | ||
da321c8a AD |
441 | static ssize_t radeon_get_dpm_state(struct device *dev, |
442 | struct device_attribute *attr, | |
443 | char *buf) | |
444 | { | |
3e4e2129 | 445 | struct drm_device *ddev = dev_get_drvdata(dev); |
da321c8a AD |
446 | struct radeon_device *rdev = ddev->dev_private; |
447 | enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; | |
448 | ||
449 | return snprintf(buf, PAGE_SIZE, "%s\n", | |
450 | (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : | |
451 | (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); | |
452 | } | |
453 | ||
454 | static ssize_t radeon_set_dpm_state(struct device *dev, | |
455 | struct device_attribute *attr, | |
456 | const char *buf, | |
457 | size_t count) | |
458 | { | |
3e4e2129 | 459 | struct drm_device *ddev = dev_get_drvdata(dev); |
da321c8a AD |
460 | struct radeon_device *rdev = ddev->dev_private; |
461 | ||
462 | mutex_lock(&rdev->pm.mutex); | |
463 | if (strncmp("battery", buf, strlen("battery")) == 0) | |
464 | rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; | |
465 | else if (strncmp("balanced", buf, strlen("balanced")) == 0) | |
466 | rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; | |
467 | else if (strncmp("performance", buf, strlen("performance")) == 0) | |
468 | rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; | |
469 | else { | |
470 | mutex_unlock(&rdev->pm.mutex); | |
471 | count = -EINVAL; | |
472 | goto fail; | |
473 | } | |
474 | mutex_unlock(&rdev->pm.mutex); | |
475 | radeon_pm_compute_clocks(rdev); | |
476 | fail: | |
477 | return count; | |
478 | } | |
479 | ||
70d01a5e AD |
480 | static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev, |
481 | struct device_attribute *attr, | |
482 | char *buf) | |
483 | { | |
3e4e2129 | 484 | struct drm_device *ddev = dev_get_drvdata(dev); |
70d01a5e AD |
485 | struct radeon_device *rdev = ddev->dev_private; |
486 | enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; | |
487 | ||
488 | return snprintf(buf, PAGE_SIZE, "%s\n", | |
489 | (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : | |
490 | (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); | |
491 | } | |
492 | ||
493 | static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev, | |
494 | struct device_attribute *attr, | |
495 | const char *buf, | |
496 | size_t count) | |
497 | { | |
3e4e2129 | 498 | struct drm_device *ddev = dev_get_drvdata(dev); |
70d01a5e AD |
499 | struct radeon_device *rdev = ddev->dev_private; |
500 | enum radeon_dpm_forced_level level; | |
501 | int ret = 0; | |
502 | ||
503 | mutex_lock(&rdev->pm.mutex); | |
504 | if (strncmp("low", buf, strlen("low")) == 0) { | |
505 | level = RADEON_DPM_FORCED_LEVEL_LOW; | |
506 | } else if (strncmp("high", buf, strlen("high")) == 0) { | |
507 | level = RADEON_DPM_FORCED_LEVEL_HIGH; | |
508 | } else if (strncmp("auto", buf, strlen("auto")) == 0) { | |
509 | level = RADEON_DPM_FORCED_LEVEL_AUTO; | |
510 | } else { | |
70d01a5e AD |
511 | count = -EINVAL; |
512 | goto fail; | |
513 | } | |
514 | if (rdev->asic->dpm.force_performance_level) { | |
0a17af37 AD |
515 | if (rdev->pm.dpm.thermal_active) { |
516 | count = -EINVAL; | |
517 | goto fail; | |
518 | } | |
70d01a5e AD |
519 | ret = radeon_dpm_force_performance_level(rdev, level); |
520 | if (ret) | |
521 | count = -EINVAL; | |
522 | } | |
70d01a5e | 523 | fail: |
0a17af37 AD |
524 | mutex_unlock(&rdev->pm.mutex); |
525 | ||
70d01a5e AD |
526 | return count; |
527 | } | |
528 | ||
ce8f5370 AD |
529 | static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); |
530 | static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); | |
da321c8a | 531 | static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state); |
70d01a5e AD |
532 | static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, |
533 | radeon_get_dpm_forced_performance_level, | |
534 | radeon_set_dpm_forced_performance_level); | |
a424816f | 535 | |
21a8122a AD |
536 | static ssize_t radeon_hwmon_show_temp(struct device *dev, |
537 | struct device_attribute *attr, | |
538 | char *buf) | |
539 | { | |
ec39f64b | 540 | struct radeon_device *rdev = dev_get_drvdata(dev); |
20d391d7 | 541 | int temp; |
21a8122a | 542 | |
6bd1c385 AD |
543 | if (rdev->asic->pm.get_temperature) |
544 | temp = radeon_get_temperature(rdev); | |
545 | else | |
21a8122a | 546 | temp = 0; |
21a8122a AD |
547 | |
548 | return snprintf(buf, PAGE_SIZE, "%d\n", temp); | |
549 | } | |
550 | ||
6ea4e84d JD |
551 | static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, |
552 | struct device_attribute *attr, | |
553 | char *buf) | |
554 | { | |
e4158f1b | 555 | struct radeon_device *rdev = dev_get_drvdata(dev); |
6ea4e84d JD |
556 | int hyst = to_sensor_dev_attr(attr)->index; |
557 | int temp; | |
558 | ||
559 | if (hyst) | |
560 | temp = rdev->pm.dpm.thermal.min_temp; | |
561 | else | |
562 | temp = rdev->pm.dpm.thermal.max_temp; | |
563 | ||
564 | return snprintf(buf, PAGE_SIZE, "%d\n", temp); | |
565 | } | |
566 | ||
21a8122a | 567 | static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); |
6ea4e84d JD |
568 | static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0); |
569 | static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1); | |
21a8122a AD |
570 | |
571 | static struct attribute *hwmon_attributes[] = { | |
572 | &sensor_dev_attr_temp1_input.dev_attr.attr, | |
6ea4e84d JD |
573 | &sensor_dev_attr_temp1_crit.dev_attr.attr, |
574 | &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, | |
21a8122a AD |
575 | NULL |
576 | }; | |
577 | ||
6ea4e84d JD |
578 | static umode_t hwmon_attributes_visible(struct kobject *kobj, |
579 | struct attribute *attr, int index) | |
580 | { | |
581 | struct device *dev = container_of(kobj, struct device, kobj); | |
e4158f1b | 582 | struct radeon_device *rdev = dev_get_drvdata(dev); |
6ea4e84d JD |
583 | |
584 | /* Skip limit attributes if DPM is not enabled */ | |
585 | if (rdev->pm.pm_method != PM_METHOD_DPM && | |
586 | (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || | |
587 | attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) | |
588 | return 0; | |
589 | ||
590 | return attr->mode; | |
591 | } | |
592 | ||
21a8122a AD |
593 | static const struct attribute_group hwmon_attrgroup = { |
594 | .attrs = hwmon_attributes, | |
6ea4e84d | 595 | .is_visible = hwmon_attributes_visible, |
21a8122a AD |
596 | }; |
597 | ||
ec39f64b GR |
598 | static const struct attribute_group *hwmon_groups[] = { |
599 | &hwmon_attrgroup, | |
600 | NULL | |
601 | }; | |
602 | ||
0d18abed | 603 | static int radeon_hwmon_init(struct radeon_device *rdev) |
21a8122a | 604 | { |
0d18abed | 605 | int err = 0; |
ec39f64b | 606 | struct device *hwmon_dev; |
21a8122a AD |
607 | |
608 | switch (rdev->pm.int_thermal_type) { | |
609 | case THERMAL_TYPE_RV6XX: | |
610 | case THERMAL_TYPE_RV770: | |
611 | case THERMAL_TYPE_EVERGREEN: | |
457558ed | 612 | case THERMAL_TYPE_NI: |
e33df25f | 613 | case THERMAL_TYPE_SUMO: |
1bd47d2e | 614 | case THERMAL_TYPE_SI: |
286d9cc6 AD |
615 | case THERMAL_TYPE_CI: |
616 | case THERMAL_TYPE_KV: | |
6bd1c385 | 617 | if (rdev->asic->pm.get_temperature == NULL) |
5d7486c7 | 618 | return err; |
ec39f64b GR |
619 | hwmon_dev = hwmon_device_register_with_groups(rdev->dev, |
620 | "radeon", rdev, | |
621 | hwmon_groups); | |
622 | if (IS_ERR(hwmon_dev)) { | |
623 | err = PTR_ERR(hwmon_dev); | |
0d18abed DC |
624 | dev_err(rdev->dev, |
625 | "Unable to register hwmon device: %d\n", err); | |
0d18abed | 626 | } |
21a8122a AD |
627 | break; |
628 | default: | |
629 | break; | |
630 | } | |
0d18abed DC |
631 | |
632 | return err; | |
21a8122a AD |
633 | } |
634 | ||
da321c8a AD |
635 | static void radeon_dpm_thermal_work_handler(struct work_struct *work) |
636 | { | |
637 | struct radeon_device *rdev = | |
638 | container_of(work, struct radeon_device, | |
639 | pm.dpm.thermal.work); | |
640 | /* switch to the thermal state */ | |
641 | enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; | |
642 | ||
643 | if (!rdev->pm.dpm_enabled) | |
644 | return; | |
645 | ||
646 | if (rdev->asic->pm.get_temperature) { | |
647 | int temp = radeon_get_temperature(rdev); | |
648 | ||
649 | if (temp < rdev->pm.dpm.thermal.min_temp) | |
650 | /* switch back the user state */ | |
651 | dpm_state = rdev->pm.dpm.user_state; | |
652 | } else { | |
653 | if (rdev->pm.dpm.thermal.high_to_low) | |
654 | /* switch back the user state */ | |
655 | dpm_state = rdev->pm.dpm.user_state; | |
656 | } | |
60320347 AD |
657 | mutex_lock(&rdev->pm.mutex); |
658 | if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) | |
659 | rdev->pm.dpm.thermal_active = true; | |
660 | else | |
661 | rdev->pm.dpm.thermal_active = false; | |
662 | rdev->pm.dpm.state = dpm_state; | |
663 | mutex_unlock(&rdev->pm.mutex); | |
664 | ||
665 | radeon_pm_compute_clocks(rdev); | |
da321c8a AD |
666 | } |
667 | ||
668 | static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, | |
669 | enum radeon_pm_state_type dpm_state) | |
670 | { | |
671 | int i; | |
672 | struct radeon_ps *ps; | |
673 | u32 ui_class; | |
48783069 AD |
674 | bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? |
675 | true : false; | |
676 | ||
677 | /* check if the vblank period is too short to adjust the mclk */ | |
678 | if (single_display && rdev->asic->dpm.vblank_too_short) { | |
679 | if (radeon_dpm_vblank_too_short(rdev)) | |
680 | single_display = false; | |
681 | } | |
da321c8a | 682 | |
edcaa5b1 AD |
683 | /* certain older asics have a separare 3D performance state, |
684 | * so try that first if the user selected performance | |
685 | */ | |
686 | if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) | |
687 | dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; | |
da321c8a AD |
688 | /* balanced states don't exist at the moment */ |
689 | if (dpm_state == POWER_STATE_TYPE_BALANCED) | |
690 | dpm_state = POWER_STATE_TYPE_PERFORMANCE; | |
691 | ||
edcaa5b1 | 692 | restart_search: |
da321c8a AD |
693 | /* Pick the best power state based on current conditions */ |
694 | for (i = 0; i < rdev->pm.dpm.num_ps; i++) { | |
695 | ps = &rdev->pm.dpm.ps[i]; | |
696 | ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; | |
697 | switch (dpm_state) { | |
698 | /* user states */ | |
699 | case POWER_STATE_TYPE_BATTERY: | |
700 | if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { | |
701 | if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { | |
48783069 | 702 | if (single_display) |
da321c8a AD |
703 | return ps; |
704 | } else | |
705 | return ps; | |
706 | } | |
707 | break; | |
708 | case POWER_STATE_TYPE_BALANCED: | |
709 | if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { | |
710 | if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { | |
48783069 | 711 | if (single_display) |
da321c8a AD |
712 | return ps; |
713 | } else | |
714 | return ps; | |
715 | } | |
716 | break; | |
717 | case POWER_STATE_TYPE_PERFORMANCE: | |
718 | if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { | |
719 | if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { | |
48783069 | 720 | if (single_display) |
da321c8a AD |
721 | return ps; |
722 | } else | |
723 | return ps; | |
724 | } | |
725 | break; | |
726 | /* internal states */ | |
727 | case POWER_STATE_TYPE_INTERNAL_UVD: | |
d4d3278c AD |
728 | if (rdev->pm.dpm.uvd_ps) |
729 | return rdev->pm.dpm.uvd_ps; | |
730 | else | |
731 | break; | |
da321c8a AD |
732 | case POWER_STATE_TYPE_INTERNAL_UVD_SD: |
733 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) | |
734 | return ps; | |
735 | break; | |
736 | case POWER_STATE_TYPE_INTERNAL_UVD_HD: | |
737 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) | |
738 | return ps; | |
739 | break; | |
740 | case POWER_STATE_TYPE_INTERNAL_UVD_HD2: | |
741 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) | |
742 | return ps; | |
743 | break; | |
744 | case POWER_STATE_TYPE_INTERNAL_UVD_MVC: | |
745 | if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) | |
746 | return ps; | |
747 | break; | |
748 | case POWER_STATE_TYPE_INTERNAL_BOOT: | |
749 | return rdev->pm.dpm.boot_ps; | |
750 | case POWER_STATE_TYPE_INTERNAL_THERMAL: | |
751 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) | |
752 | return ps; | |
753 | break; | |
754 | case POWER_STATE_TYPE_INTERNAL_ACPI: | |
755 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) | |
756 | return ps; | |
757 | break; | |
758 | case POWER_STATE_TYPE_INTERNAL_ULV: | |
759 | if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) | |
760 | return ps; | |
761 | break; | |
edcaa5b1 AD |
762 | case POWER_STATE_TYPE_INTERNAL_3DPERF: |
763 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) | |
764 | return ps; | |
765 | break; | |
da321c8a AD |
766 | default: |
767 | break; | |
768 | } | |
769 | } | |
770 | /* use a fallback state if we didn't match */ | |
771 | switch (dpm_state) { | |
772 | case POWER_STATE_TYPE_INTERNAL_UVD_SD: | |
ce3537d5 AD |
773 | dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; |
774 | goto restart_search; | |
da321c8a AD |
775 | case POWER_STATE_TYPE_INTERNAL_UVD_HD: |
776 | case POWER_STATE_TYPE_INTERNAL_UVD_HD2: | |
777 | case POWER_STATE_TYPE_INTERNAL_UVD_MVC: | |
d4d3278c AD |
778 | if (rdev->pm.dpm.uvd_ps) { |
779 | return rdev->pm.dpm.uvd_ps; | |
780 | } else { | |
781 | dpm_state = POWER_STATE_TYPE_PERFORMANCE; | |
782 | goto restart_search; | |
783 | } | |
da321c8a AD |
784 | case POWER_STATE_TYPE_INTERNAL_THERMAL: |
785 | dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; | |
786 | goto restart_search; | |
787 | case POWER_STATE_TYPE_INTERNAL_ACPI: | |
788 | dpm_state = POWER_STATE_TYPE_BATTERY; | |
789 | goto restart_search; | |
790 | case POWER_STATE_TYPE_BATTERY: | |
edcaa5b1 AD |
791 | case POWER_STATE_TYPE_BALANCED: |
792 | case POWER_STATE_TYPE_INTERNAL_3DPERF: | |
da321c8a AD |
793 | dpm_state = POWER_STATE_TYPE_PERFORMANCE; |
794 | goto restart_search; | |
795 | default: | |
796 | break; | |
797 | } | |
798 | ||
799 | return NULL; | |
800 | } | |
801 | ||
802 | static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) | |
803 | { | |
804 | int i; | |
805 | struct radeon_ps *ps; | |
806 | enum radeon_pm_state_type dpm_state; | |
84dd1928 | 807 | int ret; |
da321c8a AD |
808 | |
809 | /* if dpm init failed */ | |
810 | if (!rdev->pm.dpm_enabled) | |
811 | return; | |
812 | ||
813 | if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { | |
814 | /* add other state override checks here */ | |
8a227555 AD |
815 | if ((!rdev->pm.dpm.thermal_active) && |
816 | (!rdev->pm.dpm.uvd_active)) | |
da321c8a AD |
817 | rdev->pm.dpm.state = rdev->pm.dpm.user_state; |
818 | } | |
819 | dpm_state = rdev->pm.dpm.state; | |
820 | ||
821 | ps = radeon_dpm_pick_power_state(rdev, dpm_state); | |
822 | if (ps) | |
89c9bc56 | 823 | rdev->pm.dpm.requested_ps = ps; |
da321c8a AD |
824 | else |
825 | return; | |
826 | ||
d22b7e40 | 827 | /* no need to reprogram if nothing changed unless we are on BTC+ */ |
da321c8a | 828 | if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { |
b62d628b AD |
829 | /* vce just modifies an existing state so force a change */ |
830 | if (ps->vce_active != rdev->pm.dpm.vce_active) | |
831 | goto force; | |
d22b7e40 AD |
832 | if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { |
833 | /* for pre-BTC and APUs if the num crtcs changed but state is the same, | |
834 | * all we need to do is update the display configuration. | |
835 | */ | |
836 | if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { | |
837 | /* update display watermarks based on new power state */ | |
838 | radeon_bandwidth_update(rdev); | |
839 | /* update displays */ | |
840 | radeon_dpm_display_configuration_changed(rdev); | |
841 | rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; | |
842 | rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; | |
843 | } | |
844 | return; | |
845 | } else { | |
846 | /* for BTC+ if the num crtcs hasn't changed and state is the same, | |
847 | * nothing to do, if the num crtcs is > 1 and state is the same, | |
848 | * update display configuration. | |
849 | */ | |
850 | if (rdev->pm.dpm.new_active_crtcs == | |
851 | rdev->pm.dpm.current_active_crtcs) { | |
852 | return; | |
853 | } else { | |
854 | if ((rdev->pm.dpm.current_active_crtc_count > 1) && | |
855 | (rdev->pm.dpm.new_active_crtc_count > 1)) { | |
856 | /* update display watermarks based on new power state */ | |
857 | radeon_bandwidth_update(rdev); | |
858 | /* update displays */ | |
859 | radeon_dpm_display_configuration_changed(rdev); | |
860 | rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; | |
861 | rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; | |
862 | return; | |
863 | } | |
864 | } | |
da321c8a | 865 | } |
da321c8a AD |
866 | } |
867 | ||
b62d628b | 868 | force: |
033a37df AD |
869 | if (radeon_dpm == 1) { |
870 | printk("switching from power state:\n"); | |
871 | radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); | |
872 | printk("switching to power state:\n"); | |
873 | radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); | |
874 | } | |
b62d628b | 875 | |
da321c8a AD |
876 | mutex_lock(&rdev->ddev->struct_mutex); |
877 | down_write(&rdev->pm.mclk_lock); | |
878 | mutex_lock(&rdev->ring_lock); | |
879 | ||
b62d628b AD |
880 | /* update whether vce is active */ |
881 | ps->vce_active = rdev->pm.dpm.vce_active; | |
882 | ||
89c9bc56 AD |
883 | ret = radeon_dpm_pre_set_power_state(rdev); |
884 | if (ret) | |
885 | goto done; | |
84dd1928 | 886 | |
da321c8a AD |
887 | /* update display watermarks based on new power state */ |
888 | radeon_bandwidth_update(rdev); | |
889 | /* update displays */ | |
890 | radeon_dpm_display_configuration_changed(rdev); | |
891 | ||
892 | rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; | |
893 | rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; | |
894 | ||
895 | /* wait for the rings to drain */ | |
896 | for (i = 0; i < RADEON_NUM_RINGS; i++) { | |
897 | struct radeon_ring *ring = &rdev->ring[i]; | |
898 | if (ring->ready) | |
899 | radeon_fence_wait_empty_locked(rdev, i); | |
900 | } | |
901 | ||
902 | /* program the new power state */ | |
903 | radeon_dpm_set_power_state(rdev); | |
904 | ||
905 | /* update current power state */ | |
906 | rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; | |
907 | ||
89c9bc56 | 908 | radeon_dpm_post_set_power_state(rdev); |
84dd1928 | 909 | |
1cd8b21a | 910 | if (rdev->asic->dpm.force_performance_level) { |
14ac88af AD |
911 | if (rdev->pm.dpm.thermal_active) { |
912 | enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; | |
1cd8b21a AD |
913 | /* force low perf level for thermal */ |
914 | radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW); | |
14ac88af AD |
915 | /* save the user's level */ |
916 | rdev->pm.dpm.forced_level = level; | |
917 | } else { | |
918 | /* otherwise, user selected level */ | |
919 | radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); | |
920 | } | |
60320347 AD |
921 | } |
922 | ||
84dd1928 | 923 | done: |
da321c8a AD |
924 | mutex_unlock(&rdev->ring_lock); |
925 | up_write(&rdev->pm.mclk_lock); | |
926 | mutex_unlock(&rdev->ddev->struct_mutex); | |
927 | } | |
928 | ||
ce3537d5 AD |
929 | void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) |
930 | { | |
931 | enum radeon_pm_state_type dpm_state; | |
932 | ||
9e9d9762 | 933 | if (rdev->asic->dpm.powergate_uvd) { |
ce3537d5 | 934 | mutex_lock(&rdev->pm.mutex); |
8158eb9e CK |
935 | /* don't powergate anything if we |
936 | have active but pause streams */ | |
937 | enable |= rdev->pm.dpm.sd > 0; | |
938 | enable |= rdev->pm.dpm.hd > 0; | |
9e9d9762 AD |
939 | /* enable/disable UVD */ |
940 | radeon_dpm_powergate_uvd(rdev, !enable); | |
ce3537d5 AD |
941 | mutex_unlock(&rdev->pm.mutex); |
942 | } else { | |
9e9d9762 AD |
943 | if (enable) { |
944 | mutex_lock(&rdev->pm.mutex); | |
945 | rdev->pm.dpm.uvd_active = true; | |
dca5086a AD |
946 | /* disable this for now */ |
947 | #if 0 | |
9e9d9762 AD |
948 | if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) |
949 | dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; | |
950 | else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) | |
951 | dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; | |
952 | else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) | |
953 | dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; | |
954 | else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) | |
955 | dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; | |
956 | else | |
dca5086a | 957 | #endif |
9e9d9762 AD |
958 | dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; |
959 | rdev->pm.dpm.state = dpm_state; | |
960 | mutex_unlock(&rdev->pm.mutex); | |
961 | } else { | |
962 | mutex_lock(&rdev->pm.mutex); | |
963 | rdev->pm.dpm.uvd_active = false; | |
964 | mutex_unlock(&rdev->pm.mutex); | |
965 | } | |
ce3537d5 | 966 | |
9e9d9762 AD |
967 | radeon_pm_compute_clocks(rdev); |
968 | } | |
ce3537d5 AD |
969 | } |
970 | ||
da321c8a | 971 | static void radeon_pm_suspend_old(struct radeon_device *rdev) |
56278a8e | 972 | { |
ce8f5370 | 973 | mutex_lock(&rdev->pm.mutex); |
3f53eb6f | 974 | if (rdev->pm.pm_method == PM_METHOD_DYNPM) { |
3f53eb6f RW |
975 | if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) |
976 | rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; | |
3f53eb6f | 977 | } |
ce8f5370 | 978 | mutex_unlock(&rdev->pm.mutex); |
32c87fca TH |
979 | |
980 | cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); | |
56278a8e AD |
981 | } |
982 | ||
da321c8a AD |
983 | static void radeon_pm_suspend_dpm(struct radeon_device *rdev) |
984 | { | |
985 | mutex_lock(&rdev->pm.mutex); | |
986 | /* disable dpm */ | |
987 | radeon_dpm_disable(rdev); | |
988 | /* reset the power state */ | |
989 | rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; | |
990 | rdev->pm.dpm_enabled = false; | |
991 | mutex_unlock(&rdev->pm.mutex); | |
992 | } | |
993 | ||
994 | void radeon_pm_suspend(struct radeon_device *rdev) | |
995 | { | |
996 | if (rdev->pm.pm_method == PM_METHOD_DPM) | |
997 | radeon_pm_suspend_dpm(rdev); | |
998 | else | |
999 | radeon_pm_suspend_old(rdev); | |
1000 | } | |
1001 | ||
1002 | static void radeon_pm_resume_old(struct radeon_device *rdev) | |
d0d6cb81 | 1003 | { |
ed18a360 | 1004 | /* set up the default clocks if the MC ucode is loaded */ |
2e3b3b10 | 1005 | if ((rdev->family >= CHIP_BARTS) && |
36099186 | 1006 | (rdev->family <= CHIP_CAYMAN) && |
2e3b3b10 | 1007 | rdev->mc_fw) { |
ed18a360 | 1008 | if (rdev->pm.default_vddc) |
8a83ec5e AD |
1009 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, |
1010 | SET_VOLTAGE_TYPE_ASIC_VDDC); | |
2feea49a AD |
1011 | if (rdev->pm.default_vddci) |
1012 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, | |
1013 | SET_VOLTAGE_TYPE_ASIC_VDDCI); | |
ed18a360 AD |
1014 | if (rdev->pm.default_sclk) |
1015 | radeon_set_engine_clock(rdev, rdev->pm.default_sclk); | |
1016 | if (rdev->pm.default_mclk) | |
1017 | radeon_set_memory_clock(rdev, rdev->pm.default_mclk); | |
1018 | } | |
f8ed8b4c AD |
1019 | /* asic init will reset the default power state */ |
1020 | mutex_lock(&rdev->pm.mutex); | |
1021 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; | |
1022 | rdev->pm.current_clock_mode_index = 0; | |
9ace9f7b AD |
1023 | rdev->pm.current_sclk = rdev->pm.default_sclk; |
1024 | rdev->pm.current_mclk = rdev->pm.default_mclk; | |
37016951 MD |
1025 | if (rdev->pm.power_state) { |
1026 | rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; | |
1027 | rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; | |
1028 | } | |
3f53eb6f RW |
1029 | if (rdev->pm.pm_method == PM_METHOD_DYNPM |
1030 | && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { | |
1031 | rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; | |
32c87fca TH |
1032 | schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
1033 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); | |
3f53eb6f | 1034 | } |
f8ed8b4c | 1035 | mutex_unlock(&rdev->pm.mutex); |
ce8f5370 | 1036 | radeon_pm_compute_clocks(rdev); |
d0d6cb81 RM |
1037 | } |
1038 | ||
da321c8a AD |
1039 | static void radeon_pm_resume_dpm(struct radeon_device *rdev) |
1040 | { | |
1041 | int ret; | |
1042 | ||
1043 | /* asic init will reset to the boot state */ | |
1044 | mutex_lock(&rdev->pm.mutex); | |
1045 | rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; | |
1046 | radeon_dpm_setup_asic(rdev); | |
1047 | ret = radeon_dpm_enable(rdev); | |
1048 | mutex_unlock(&rdev->pm.mutex); | |
e14cd2bb AD |
1049 | if (ret) |
1050 | goto dpm_resume_fail; | |
e14cd2bb AD |
1051 | rdev->pm.dpm_enabled = true; |
1052 | radeon_pm_compute_clocks(rdev); | |
1053 | return; | |
1054 | ||
1055 | dpm_resume_fail: | |
1056 | DRM_ERROR("radeon: dpm resume failed\n"); | |
1057 | if ((rdev->family >= CHIP_BARTS) && | |
1058 | (rdev->family <= CHIP_CAYMAN) && | |
1059 | rdev->mc_fw) { | |
1060 | if (rdev->pm.default_vddc) | |
1061 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, | |
1062 | SET_VOLTAGE_TYPE_ASIC_VDDC); | |
1063 | if (rdev->pm.default_vddci) | |
1064 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, | |
1065 | SET_VOLTAGE_TYPE_ASIC_VDDCI); | |
1066 | if (rdev->pm.default_sclk) | |
1067 | radeon_set_engine_clock(rdev, rdev->pm.default_sclk); | |
1068 | if (rdev->pm.default_mclk) | |
1069 | radeon_set_memory_clock(rdev, rdev->pm.default_mclk); | |
da321c8a AD |
1070 | } |
1071 | } | |
1072 | ||
1073 | void radeon_pm_resume(struct radeon_device *rdev) | |
1074 | { | |
1075 | if (rdev->pm.pm_method == PM_METHOD_DPM) | |
1076 | radeon_pm_resume_dpm(rdev); | |
1077 | else | |
1078 | radeon_pm_resume_old(rdev); | |
1079 | } | |
1080 | ||
1081 | static int radeon_pm_init_old(struct radeon_device *rdev) | |
7433874e | 1082 | { |
26481fb1 | 1083 | int ret; |
0d18abed | 1084 | |
f8ed8b4c | 1085 | rdev->pm.profile = PM_PROFILE_DEFAULT; |
ce8f5370 AD |
1086 | rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; |
1087 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; | |
1088 | rdev->pm.dynpm_can_upclock = true; | |
1089 | rdev->pm.dynpm_can_downclock = true; | |
9ace9f7b AD |
1090 | rdev->pm.default_sclk = rdev->clock.default_sclk; |
1091 | rdev->pm.default_mclk = rdev->clock.default_mclk; | |
f8ed8b4c AD |
1092 | rdev->pm.current_sclk = rdev->clock.default_sclk; |
1093 | rdev->pm.current_mclk = rdev->clock.default_mclk; | |
21a8122a | 1094 | rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; |
c913e23a | 1095 | |
56278a8e AD |
1096 | if (rdev->bios) { |
1097 | if (rdev->is_atom_bios) | |
1098 | radeon_atombios_get_power_modes(rdev); | |
1099 | else | |
1100 | radeon_combios_get_power_modes(rdev); | |
f712d0c7 | 1101 | radeon_pm_print_states(rdev); |
ce8f5370 | 1102 | radeon_pm_init_profile(rdev); |
ed18a360 | 1103 | /* set up the default clocks if the MC ucode is loaded */ |
2e3b3b10 | 1104 | if ((rdev->family >= CHIP_BARTS) && |
36099186 | 1105 | (rdev->family <= CHIP_CAYMAN) && |
2e3b3b10 | 1106 | rdev->mc_fw) { |
ed18a360 | 1107 | if (rdev->pm.default_vddc) |
8a83ec5e AD |
1108 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, |
1109 | SET_VOLTAGE_TYPE_ASIC_VDDC); | |
4639dd21 AD |
1110 | if (rdev->pm.default_vddci) |
1111 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, | |
1112 | SET_VOLTAGE_TYPE_ASIC_VDDCI); | |
ed18a360 AD |
1113 | if (rdev->pm.default_sclk) |
1114 | radeon_set_engine_clock(rdev, rdev->pm.default_sclk); | |
1115 | if (rdev->pm.default_mclk) | |
1116 | radeon_set_memory_clock(rdev, rdev->pm.default_mclk); | |
1117 | } | |
56278a8e AD |
1118 | } |
1119 | ||
21a8122a | 1120 | /* set up the internal thermal sensor if applicable */ |
0d18abed DC |
1121 | ret = radeon_hwmon_init(rdev); |
1122 | if (ret) | |
1123 | return ret; | |
32c87fca TH |
1124 | |
1125 | INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); | |
1126 | ||
ce8f5370 | 1127 | if (rdev->pm.num_power_states > 1) { |
ce8f5370 | 1128 | /* where's the best place to put these? */ |
26481fb1 DA |
1129 | ret = device_create_file(rdev->dev, &dev_attr_power_profile); |
1130 | if (ret) | |
1131 | DRM_ERROR("failed to create device file for power profile\n"); | |
1132 | ret = device_create_file(rdev->dev, &dev_attr_power_method); | |
1133 | if (ret) | |
1134 | DRM_ERROR("failed to create device file for power method\n"); | |
a424816f | 1135 | |
ce8f5370 AD |
1136 | if (radeon_debugfs_pm_init(rdev)) { |
1137 | DRM_ERROR("Failed to register debugfs file for PM!\n"); | |
1138 | } | |
c913e23a | 1139 | |
ce8f5370 AD |
1140 | DRM_INFO("radeon: power management initialized\n"); |
1141 | } | |
c913e23a | 1142 | |
7433874e RM |
1143 | return 0; |
1144 | } | |
1145 | ||
da321c8a AD |
1146 | static void radeon_dpm_print_power_states(struct radeon_device *rdev) |
1147 | { | |
1148 | int i; | |
1149 | ||
1150 | for (i = 0; i < rdev->pm.dpm.num_ps; i++) { | |
1151 | printk("== power state %d ==\n", i); | |
1152 | radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); | |
1153 | } | |
1154 | } | |
1155 | ||
1156 | static int radeon_pm_init_dpm(struct radeon_device *rdev) | |
1157 | { | |
1158 | int ret; | |
1159 | ||
1cd8b21a | 1160 | /* default to balanced state */ |
edcaa5b1 AD |
1161 | rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; |
1162 | rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; | |
1cd8b21a | 1163 | rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; |
da321c8a AD |
1164 | rdev->pm.default_sclk = rdev->clock.default_sclk; |
1165 | rdev->pm.default_mclk = rdev->clock.default_mclk; | |
1166 | rdev->pm.current_sclk = rdev->clock.default_sclk; | |
1167 | rdev->pm.current_mclk = rdev->clock.default_mclk; | |
1168 | rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; | |
1169 | ||
1170 | if (rdev->bios && rdev->is_atom_bios) | |
1171 | radeon_atombios_get_power_modes(rdev); | |
1172 | else | |
1173 | return -EINVAL; | |
1174 | ||
1175 | /* set up the internal thermal sensor if applicable */ | |
1176 | ret = radeon_hwmon_init(rdev); | |
1177 | if (ret) | |
1178 | return ret; | |
1179 | ||
1180 | INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); | |
1181 | mutex_lock(&rdev->pm.mutex); | |
1182 | radeon_dpm_init(rdev); | |
1183 | rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; | |
033a37df AD |
1184 | if (radeon_dpm == 1) |
1185 | radeon_dpm_print_power_states(rdev); | |
da321c8a AD |
1186 | radeon_dpm_setup_asic(rdev); |
1187 | ret = radeon_dpm_enable(rdev); | |
1188 | mutex_unlock(&rdev->pm.mutex); | |
e14cd2bb AD |
1189 | if (ret) |
1190 | goto dpm_failed; | |
da321c8a | 1191 | rdev->pm.dpm_enabled = true; |
da321c8a | 1192 | |
bb5abf9f AD |
1193 | ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); |
1194 | if (ret) | |
1195 | DRM_ERROR("failed to create device file for dpm state\n"); | |
1196 | ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); | |
1197 | if (ret) | |
1198 | DRM_ERROR("failed to create device file for dpm state\n"); | |
1199 | /* XXX: these are noops for dpm but are here for backwards compat */ | |
1200 | ret = device_create_file(rdev->dev, &dev_attr_power_profile); | |
1201 | if (ret) | |
1202 | DRM_ERROR("failed to create device file for power profile\n"); | |
1203 | ret = device_create_file(rdev->dev, &dev_attr_power_method); | |
1204 | if (ret) | |
1205 | DRM_ERROR("failed to create device file for power method\n"); | |
1316b792 | 1206 | |
bb5abf9f AD |
1207 | if (radeon_debugfs_pm_init(rdev)) { |
1208 | DRM_ERROR("Failed to register debugfs file for dpm!\n"); | |
da321c8a AD |
1209 | } |
1210 | ||
bb5abf9f AD |
1211 | DRM_INFO("radeon: dpm initialized\n"); |
1212 | ||
da321c8a | 1213 | return 0; |
e14cd2bb AD |
1214 | |
1215 | dpm_failed: | |
1216 | rdev->pm.dpm_enabled = false; | |
1217 | if ((rdev->family >= CHIP_BARTS) && | |
1218 | (rdev->family <= CHIP_CAYMAN) && | |
1219 | rdev->mc_fw) { | |
1220 | if (rdev->pm.default_vddc) | |
1221 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, | |
1222 | SET_VOLTAGE_TYPE_ASIC_VDDC); | |
1223 | if (rdev->pm.default_vddci) | |
1224 | radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, | |
1225 | SET_VOLTAGE_TYPE_ASIC_VDDCI); | |
1226 | if (rdev->pm.default_sclk) | |
1227 | radeon_set_engine_clock(rdev, rdev->pm.default_sclk); | |
1228 | if (rdev->pm.default_mclk) | |
1229 | radeon_set_memory_clock(rdev, rdev->pm.default_mclk); | |
1230 | } | |
1231 | DRM_ERROR("radeon: dpm initialization failed\n"); | |
1232 | return ret; | |
da321c8a AD |
1233 | } |
1234 | ||
1235 | int radeon_pm_init(struct radeon_device *rdev) | |
1236 | { | |
1237 | /* enable dpm on rv6xx+ */ | |
1238 | switch (rdev->family) { | |
4a6369e9 AD |
1239 | case CHIP_RV610: |
1240 | case CHIP_RV630: | |
1241 | case CHIP_RV620: | |
1242 | case CHIP_RV635: | |
1243 | case CHIP_RV670: | |
9d67006e AD |
1244 | case CHIP_RS780: |
1245 | case CHIP_RS880: | |
919cf555 AD |
1246 | case CHIP_BARTS: |
1247 | case CHIP_TURKS: | |
1248 | case CHIP_CAICOS: | |
69e0b57a | 1249 | case CHIP_CAYMAN: |
8a53fa23 | 1250 | /* DPM requires the RLC, RV770+ dGPU requires SMC */ |
761bfb99 AD |
1251 | if (!rdev->rlc_fw) |
1252 | rdev->pm.pm_method = PM_METHOD_PROFILE; | |
8a53fa23 AD |
1253 | else if ((rdev->family >= CHIP_RV770) && |
1254 | (!(rdev->flags & RADEON_IS_IGP)) && | |
1255 | (!rdev->smc_fw)) | |
1256 | rdev->pm.pm_method = PM_METHOD_PROFILE; | |
761bfb99 | 1257 | else if (radeon_dpm == 1) |
9d67006e AD |
1258 | rdev->pm.pm_method = PM_METHOD_DPM; |
1259 | else | |
1260 | rdev->pm.pm_method = PM_METHOD_PROFILE; | |
1261 | break; | |
ab70b1dd AD |
1262 | case CHIP_RV770: |
1263 | case CHIP_RV730: | |
1264 | case CHIP_RV710: | |
1265 | case CHIP_RV740: | |
59f7a2f2 AD |
1266 | case CHIP_CEDAR: |
1267 | case CHIP_REDWOOD: | |
1268 | case CHIP_JUNIPER: | |
1269 | case CHIP_CYPRESS: | |
1270 | case CHIP_HEMLOCK: | |
5a16f761 AD |
1271 | case CHIP_PALM: |
1272 | case CHIP_SUMO: | |
1273 | case CHIP_SUMO2: | |
3a118989 | 1274 | case CHIP_ARUBA: |
68bc7785 AD |
1275 | case CHIP_TAHITI: |
1276 | case CHIP_PITCAIRN: | |
1277 | case CHIP_VERDE: | |
1278 | case CHIP_OLAND: | |
1279 | case CHIP_HAINAN: | |
4f22dde3 | 1280 | case CHIP_BONAIRE: |
e308b1d3 AD |
1281 | case CHIP_KABINI: |
1282 | case CHIP_KAVERI: | |
4f22dde3 | 1283 | case CHIP_HAWAII: |
5a16f761 AD |
1284 | /* DPM requires the RLC, RV770+ dGPU requires SMC */ |
1285 | if (!rdev->rlc_fw) | |
1286 | rdev->pm.pm_method = PM_METHOD_PROFILE; | |
1287 | else if ((rdev->family >= CHIP_RV770) && | |
1288 | (!(rdev->flags & RADEON_IS_IGP)) && | |
1289 | (!rdev->smc_fw)) | |
1290 | rdev->pm.pm_method = PM_METHOD_PROFILE; | |
1291 | else if (radeon_dpm == 0) | |
1292 | rdev->pm.pm_method = PM_METHOD_PROFILE; | |
1293 | else | |
1294 | rdev->pm.pm_method = PM_METHOD_DPM; | |
1295 | break; | |
da321c8a AD |
1296 | default: |
1297 | /* default to profile method */ | |
1298 | rdev->pm.pm_method = PM_METHOD_PROFILE; | |
1299 | break; | |
1300 | } | |
1301 | ||
1302 | if (rdev->pm.pm_method == PM_METHOD_DPM) | |
1303 | return radeon_pm_init_dpm(rdev); | |
1304 | else | |
1305 | return radeon_pm_init_old(rdev); | |
1306 | } | |
1307 | ||
914a8987 AD |
1308 | int radeon_pm_late_init(struct radeon_device *rdev) |
1309 | { | |
1310 | int ret = 0; | |
1311 | ||
1312 | if (rdev->pm.pm_method == PM_METHOD_DPM) { | |
1313 | mutex_lock(&rdev->pm.mutex); | |
1314 | ret = radeon_dpm_late_enable(rdev); | |
1315 | mutex_unlock(&rdev->pm.mutex); | |
1316 | } | |
1317 | return ret; | |
1318 | } | |
1319 | ||
da321c8a | 1320 | static void radeon_pm_fini_old(struct radeon_device *rdev) |
29fb52ca | 1321 | { |
ce8f5370 | 1322 | if (rdev->pm.num_power_states > 1) { |
a424816f | 1323 | mutex_lock(&rdev->pm.mutex); |
ce8f5370 AD |
1324 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
1325 | rdev->pm.profile = PM_PROFILE_DEFAULT; | |
1326 | radeon_pm_update_profile(rdev); | |
1327 | radeon_pm_set_clocks(rdev); | |
1328 | } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { | |
ce8f5370 AD |
1329 | /* reset default clocks */ |
1330 | rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; | |
1331 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; | |
1332 | radeon_pm_set_clocks(rdev); | |
1333 | } | |
a424816f | 1334 | mutex_unlock(&rdev->pm.mutex); |
32c87fca TH |
1335 | |
1336 | cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); | |
58e21dff | 1337 | |
ce8f5370 AD |
1338 | device_remove_file(rdev->dev, &dev_attr_power_profile); |
1339 | device_remove_file(rdev->dev, &dev_attr_power_method); | |
ce8f5370 | 1340 | } |
a424816f | 1341 | |
0975b162 AD |
1342 | if (rdev->pm.power_state) |
1343 | kfree(rdev->pm.power_state); | |
29fb52ca AD |
1344 | } |
1345 | ||
da321c8a AD |
1346 | static void radeon_pm_fini_dpm(struct radeon_device *rdev) |
1347 | { | |
1348 | if (rdev->pm.num_power_states > 1) { | |
1349 | mutex_lock(&rdev->pm.mutex); | |
1350 | radeon_dpm_disable(rdev); | |
1351 | mutex_unlock(&rdev->pm.mutex); | |
1352 | ||
1353 | device_remove_file(rdev->dev, &dev_attr_power_dpm_state); | |
70d01a5e | 1354 | device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); |
da321c8a AD |
1355 | /* XXX backwards compat */ |
1356 | device_remove_file(rdev->dev, &dev_attr_power_profile); | |
1357 | device_remove_file(rdev->dev, &dev_attr_power_method); | |
1358 | } | |
1359 | radeon_dpm_fini(rdev); | |
1360 | ||
1361 | if (rdev->pm.power_state) | |
1362 | kfree(rdev->pm.power_state); | |
da321c8a AD |
1363 | } |
1364 | ||
1365 | void radeon_pm_fini(struct radeon_device *rdev) | |
1366 | { | |
1367 | if (rdev->pm.pm_method == PM_METHOD_DPM) | |
1368 | radeon_pm_fini_dpm(rdev); | |
1369 | else | |
1370 | radeon_pm_fini_old(rdev); | |
1371 | } | |
1372 | ||
1373 | static void radeon_pm_compute_clocks_old(struct radeon_device *rdev) | |
c913e23a RM |
1374 | { |
1375 | struct drm_device *ddev = rdev->ddev; | |
a48b9b4e | 1376 | struct drm_crtc *crtc; |
c913e23a | 1377 | struct radeon_crtc *radeon_crtc; |
c913e23a | 1378 | |
ce8f5370 AD |
1379 | if (rdev->pm.num_power_states < 2) |
1380 | return; | |
1381 | ||
c913e23a RM |
1382 | mutex_lock(&rdev->pm.mutex); |
1383 | ||
1384 | rdev->pm.active_crtcs = 0; | |
a48b9b4e AD |
1385 | rdev->pm.active_crtc_count = 0; |
1386 | list_for_each_entry(crtc, | |
1387 | &ddev->mode_config.crtc_list, head) { | |
1388 | radeon_crtc = to_radeon_crtc(crtc); | |
1389 | if (radeon_crtc->enabled) { | |
c913e23a | 1390 | rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); |
a48b9b4e | 1391 | rdev->pm.active_crtc_count++; |
c913e23a RM |
1392 | } |
1393 | } | |
1394 | ||
ce8f5370 AD |
1395 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
1396 | radeon_pm_update_profile(rdev); | |
1397 | radeon_pm_set_clocks(rdev); | |
1398 | } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { | |
1399 | if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { | |
1400 | if (rdev->pm.active_crtc_count > 1) { | |
1401 | if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { | |
1402 | cancel_delayed_work(&rdev->pm.dynpm_idle_work); | |
1403 | ||
1404 | rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; | |
1405 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; | |
1406 | radeon_pm_get_dynpm_state(rdev); | |
1407 | radeon_pm_set_clocks(rdev); | |
1408 | ||
d9fdaafb | 1409 | DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); |
ce8f5370 AD |
1410 | } |
1411 | } else if (rdev->pm.active_crtc_count == 1) { | |
1412 | /* TODO: Increase clocks if needed for current mode */ | |
1413 | ||
1414 | if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { | |
1415 | rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; | |
1416 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; | |
1417 | radeon_pm_get_dynpm_state(rdev); | |
1418 | radeon_pm_set_clocks(rdev); | |
1419 | ||
32c87fca TH |
1420 | schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
1421 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); | |
ce8f5370 AD |
1422 | } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { |
1423 | rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; | |
32c87fca TH |
1424 | schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
1425 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); | |
d9fdaafb | 1426 | DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); |
ce8f5370 AD |
1427 | } |
1428 | } else { /* count == 0 */ | |
1429 | if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { | |
1430 | cancel_delayed_work(&rdev->pm.dynpm_idle_work); | |
1431 | ||
1432 | rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; | |
1433 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; | |
1434 | radeon_pm_get_dynpm_state(rdev); | |
1435 | radeon_pm_set_clocks(rdev); | |
1436 | } | |
1437 | } | |
c913e23a | 1438 | } |
c913e23a | 1439 | } |
73a6d3fc RM |
1440 | |
1441 | mutex_unlock(&rdev->pm.mutex); | |
c913e23a RM |
1442 | } |
1443 | ||
da321c8a AD |
1444 | static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) |
1445 | { | |
1446 | struct drm_device *ddev = rdev->ddev; | |
1447 | struct drm_crtc *crtc; | |
1448 | struct radeon_crtc *radeon_crtc; | |
1449 | ||
6c7bccea AD |
1450 | if (!rdev->pm.dpm_enabled) |
1451 | return; | |
1452 | ||
da321c8a AD |
1453 | mutex_lock(&rdev->pm.mutex); |
1454 | ||
5ca302f7 | 1455 | /* update active crtc counts */ |
da321c8a AD |
1456 | rdev->pm.dpm.new_active_crtcs = 0; |
1457 | rdev->pm.dpm.new_active_crtc_count = 0; | |
1458 | list_for_each_entry(crtc, | |
1459 | &ddev->mode_config.crtc_list, head) { | |
1460 | radeon_crtc = to_radeon_crtc(crtc); | |
1461 | if (crtc->enabled) { | |
1462 | rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); | |
1463 | rdev->pm.dpm.new_active_crtc_count++; | |
1464 | } | |
1465 | } | |
1466 | ||
5ca302f7 AD |
1467 | /* update battery/ac status */ |
1468 | if (power_supply_is_system_supplied() > 0) | |
1469 | rdev->pm.dpm.ac_power = true; | |
1470 | else | |
1471 | rdev->pm.dpm.ac_power = false; | |
1472 | ||
da321c8a AD |
1473 | radeon_dpm_change_power_state_locked(rdev); |
1474 | ||
1475 | mutex_unlock(&rdev->pm.mutex); | |
8a227555 | 1476 | |
da321c8a AD |
1477 | } |
1478 | ||
1479 | void radeon_pm_compute_clocks(struct radeon_device *rdev) | |
1480 | { | |
1481 | if (rdev->pm.pm_method == PM_METHOD_DPM) | |
1482 | radeon_pm_compute_clocks_dpm(rdev); | |
1483 | else | |
1484 | radeon_pm_compute_clocks_old(rdev); | |
1485 | } | |
1486 | ||
ce8f5370 | 1487 | static bool radeon_pm_in_vbl(struct radeon_device *rdev) |
f735261b | 1488 | { |
75fa0b08 | 1489 | int crtc, vpos, hpos, vbl_status; |
f735261b DA |
1490 | bool in_vbl = true; |
1491 | ||
75fa0b08 MK |
1492 | /* Iterate over all active crtc's. All crtc's must be in vblank, |
1493 | * otherwise return in_vbl == false. | |
1494 | */ | |
1495 | for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { | |
1496 | if (rdev->pm.active_crtcs & (1 << crtc)) { | |
abca9e45 | 1497 | vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL); |
f5a80209 MK |
1498 | if ((vbl_status & DRM_SCANOUTPOS_VALID) && |
1499 | !(vbl_status & DRM_SCANOUTPOS_INVBL)) | |
f735261b DA |
1500 | in_vbl = false; |
1501 | } | |
1502 | } | |
f81f2024 MG |
1503 | |
1504 | return in_vbl; | |
1505 | } | |
1506 | ||
ce8f5370 | 1507 | static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) |
f81f2024 MG |
1508 | { |
1509 | u32 stat_crtc = 0; | |
1510 | bool in_vbl = radeon_pm_in_vbl(rdev); | |
1511 | ||
f735261b | 1512 | if (in_vbl == false) |
d9fdaafb | 1513 | DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, |
bae6b562 | 1514 | finish ? "exit" : "entry"); |
f735261b DA |
1515 | return in_vbl; |
1516 | } | |
c913e23a | 1517 | |
ce8f5370 | 1518 | static void radeon_dynpm_idle_work_handler(struct work_struct *work) |
c913e23a RM |
1519 | { |
1520 | struct radeon_device *rdev; | |
d9932a32 | 1521 | int resched; |
c913e23a | 1522 | rdev = container_of(work, struct radeon_device, |
ce8f5370 | 1523 | pm.dynpm_idle_work.work); |
c913e23a | 1524 | |
d9932a32 | 1525 | resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); |
c913e23a | 1526 | mutex_lock(&rdev->pm.mutex); |
ce8f5370 | 1527 | if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { |
c913e23a | 1528 | int not_processed = 0; |
7465280c AD |
1529 | int i; |
1530 | ||
7465280c | 1531 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
0ec0612a AD |
1532 | struct radeon_ring *ring = &rdev->ring[i]; |
1533 | ||
1534 | if (ring->ready) { | |
1535 | not_processed += radeon_fence_count_emitted(rdev, i); | |
1536 | if (not_processed >= 3) | |
1537 | break; | |
1538 | } | |
c913e23a | 1539 | } |
c913e23a RM |
1540 | |
1541 | if (not_processed >= 3) { /* should upclock */ | |
ce8f5370 AD |
1542 | if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { |
1543 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; | |
1544 | } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && | |
1545 | rdev->pm.dynpm_can_upclock) { | |
1546 | rdev->pm.dynpm_planned_action = | |
1547 | DYNPM_ACTION_UPCLOCK; | |
1548 | rdev->pm.dynpm_action_timeout = jiffies + | |
c913e23a RM |
1549 | msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); |
1550 | } | |
1551 | } else if (not_processed == 0) { /* should downclock */ | |
ce8f5370 AD |
1552 | if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { |
1553 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; | |
1554 | } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && | |
1555 | rdev->pm.dynpm_can_downclock) { | |
1556 | rdev->pm.dynpm_planned_action = | |
1557 | DYNPM_ACTION_DOWNCLOCK; | |
1558 | rdev->pm.dynpm_action_timeout = jiffies + | |
c913e23a RM |
1559 | msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); |
1560 | } | |
1561 | } | |
1562 | ||
d7311171 AD |
1563 | /* Note, radeon_pm_set_clocks is called with static_switch set |
1564 | * to false since we want to wait for vbl to avoid flicker. | |
1565 | */ | |
ce8f5370 AD |
1566 | if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && |
1567 | jiffies > rdev->pm.dynpm_action_timeout) { | |
1568 | radeon_pm_get_dynpm_state(rdev); | |
1569 | radeon_pm_set_clocks(rdev); | |
c913e23a | 1570 | } |
3f53eb6f | 1571 | |
32c87fca TH |
1572 | schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
1573 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); | |
c913e23a RM |
1574 | } |
1575 | mutex_unlock(&rdev->pm.mutex); | |
d9932a32 | 1576 | ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
c913e23a RM |
1577 | } |
1578 | ||
7433874e RM |
1579 | /* |
1580 | * Debugfs info | |
1581 | */ | |
1582 | #if defined(CONFIG_DEBUG_FS) | |
1583 | ||
1584 | static int radeon_debugfs_pm_info(struct seq_file *m, void *data) | |
1585 | { | |
1586 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1587 | struct drm_device *dev = node->minor->dev; | |
1588 | struct radeon_device *rdev = dev->dev_private; | |
1589 | ||
1316b792 AD |
1590 | if (rdev->pm.dpm_enabled) { |
1591 | mutex_lock(&rdev->pm.mutex); | |
1592 | if (rdev->asic->dpm.debugfs_print_current_performance_level) | |
1593 | radeon_dpm_debugfs_print_current_performance_level(rdev, m); | |
1594 | else | |
71375929 | 1595 | seq_printf(m, "Debugfs support not implemented for this asic\n"); |
1316b792 AD |
1596 | mutex_unlock(&rdev->pm.mutex); |
1597 | } else { | |
1598 | seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); | |
1599 | /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ | |
1600 | if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) | |
1601 | seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); | |
1602 | else | |
1603 | seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); | |
1604 | seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); | |
1605 | if (rdev->asic->pm.get_memory_clock) | |
1606 | seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); | |
1607 | if (rdev->pm.current_vddc) | |
1608 | seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); | |
1609 | if (rdev->asic->pm.get_pcie_lanes) | |
1610 | seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); | |
1611 | } | |
7433874e RM |
1612 | |
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | static struct drm_info_list radeon_pm_info_list[] = { | |
1617 | {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, | |
1618 | }; | |
1619 | #endif | |
1620 | ||
c913e23a | 1621 | static int radeon_debugfs_pm_init(struct radeon_device *rdev) |
7433874e RM |
1622 | { |
1623 | #if defined(CONFIG_DEBUG_FS) | |
1624 | return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); | |
1625 | #else | |
1626 | return 0; | |
1627 | #endif | |
1628 | } |