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drm/radeon: don't leave fence blocked process on failed GPU reset
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e 22 */
760285e7 23#include <drm/drmP.h>
7433874e 24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
ce8f5370 27#include <linux/power_supply.h>
21a8122a
AD		 28#include <linux/hwmon.h>
29#include <linux/hwmon-sysfs.h>
7433874e 30
c913e23a
RM		 31#define RADEON_IDLE_LOOP_MS 100
32#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 33#define RADEON_WAIT_VBLANK_TIMEOUT 200
c913e23a 34
f712d0c7 35static const char *radeon_pm_state_type_name[5] = {
eb2c27a0 36 "",
f712d0c7
RM		 37 "Powersave",
38 "Battery",
39 "Balanced",
40 "Performance",
41};
42
ce8f5370 43static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 44static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 45static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47static void radeon_pm_update_profile(struct radeon_device *rdev);
48static void radeon_pm_set_clocks(struct radeon_device *rdev);
49
a4c9e2ee
AD		 50int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
52 int instance)
53{
54 int i;
55 int found_instance = -1;
56
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
59 found_instance++;
60 if (found_instance == instance)
61 return i;
62 }
63 }
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
66}
67
c4917074 68void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
ce8f5370 69{
c4917074
AD		 70 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
71 if (rdev->pm.profile == PM_PROFILE_AUTO) {
72 mutex_lock(&rdev->pm.mutex);
73 radeon_pm_update_profile(rdev);
74 radeon_pm_set_clocks(rdev);
75 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 76 }
77 }
ce8f5370 78}
ce8f5370
AD		 79
80static void radeon_pm_update_profile(struct radeon_device *rdev)
81{
82 switch (rdev->pm.profile) {
83 case PM_PROFILE_DEFAULT:
84 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
85 break;
86 case PM_PROFILE_AUTO:
87 if (power_supply_is_system_supplied() > 0) {
88 if (rdev->pm.active_crtc_count > 1)
89 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
90 else
91 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
92 } else {
93 if (rdev->pm.active_crtc_count > 1)
c9e75b21 94 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 95 else
c9e75b21 96 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 97 }
98 break;
99 case PM_PROFILE_LOW:
100 if (rdev->pm.active_crtc_count > 1)
101 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
102 else
103 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
104 break;
c9e75b21
AD		 105 case PM_PROFILE_MID:
106 if (rdev->pm.active_crtc_count > 1)
107 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
108 else
109 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
110 break;
ce8f5370
AD		 111 case PM_PROFILE_HIGH:
112 if (rdev->pm.active_crtc_count > 1)
113 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
114 else
115 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
116 break;
117 }
118
119 if (rdev->pm.active_crtc_count == 0) {
120 rdev->pm.requested_power_state_index =
121 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
122 rdev->pm.requested_clock_mode_index =
123 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
124 } else {
125 rdev->pm.requested_power_state_index =
126 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
127 rdev->pm.requested_clock_mode_index =
128 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
129 }
130}
c913e23a 131
5876dd24
MG		 132static void radeon_unmap_vram_bos(struct radeon_device *rdev)
133{
134 struct radeon_bo *bo, *n;
135
136 if (list_empty(&rdev->gem.objects))
137 return;
138
139 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
140 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
141 ttm_bo_unmap_virtual(&bo->tbo);
142 }
5876dd24
MG		 143}
144
ce8f5370 145static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 146{
ce8f5370
AD		 147 if (rdev->pm.active_crtcs) {
148 rdev->pm.vblank_sync = false;
149 wait_event_timeout(
150 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
151 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
152 }
153}
154
155static void radeon_set_power_state(struct radeon_device *rdev)
156{
157 u32 sclk, mclk;
92645879 158 bool misc_after = false;
ce8f5370
AD		 159
160 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
161 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
162 return;
163
164 if (radeon_gui_idle(rdev)) {
165 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
166 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 167 if (sclk > rdev->pm.default_sclk)
168 sclk = rdev->pm.default_sclk;
ce8f5370 169
27810fb2
AD		 170 /* starting with BTC, there is one state that is used for both
171 * MH and SH. Difference is that we always use the high clock index for
172 * mclk.
173 */
174 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
175 (rdev->family >= CHIP_BARTS) &&
176 rdev->pm.active_crtc_count &&
177 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
178 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
179 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
180 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
181 else
182 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 clock_info[rdev->pm.requested_clock_mode_index].mclk;
184
9ace9f7b
AD		 185 if (mclk > rdev->pm.default_mclk)
186 mclk = rdev->pm.default_mclk;
ce8f5370 187
92645879
AD		 188 /* upvolt before raising clocks, downvolt after lowering clocks */
189 if (sclk < rdev->pm.current_sclk)
190 misc_after = true;
ce8f5370 191
92645879 192 radeon_sync_with_vblank(rdev);
ce8f5370 193
92645879 194 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 195 if (!radeon_pm_in_vbl(rdev))
196 return;
92645879 197 }
ce8f5370 198
92645879 199 radeon_pm_prepare(rdev);
ce8f5370 200
92645879
AD		 201 if (!misc_after)
202 /* voltage, pcie lanes, etc.*/
203 radeon_pm_misc(rdev);
204
205 /* set engine clock */
206 if (sclk != rdev->pm.current_sclk) {
207 radeon_pm_debug_check_in_vbl(rdev, false);
208 radeon_set_engine_clock(rdev, sclk);
209 radeon_pm_debug_check_in_vbl(rdev, true);
210 rdev->pm.current_sclk = sclk;
d9fdaafb 211 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 212 }
213
214 /* set memory clock */
798bcf73 215 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_memory_clock(rdev, mclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_mclk = mclk;
d9fdaafb 220 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 221 }
2aba631c 222
92645879
AD		 223 if (misc_after)
224 /* voltage, pcie lanes, etc.*/
225 radeon_pm_misc(rdev);
226
227 radeon_pm_finish(rdev);
228
ce8f5370
AD		 229 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
230 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
231 } else
d9fdaafb 232 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 233}
234
235static void radeon_pm_set_clocks(struct radeon_device *rdev)
236{
237 int i;
c37d230a 238
4e186b2d
AD		 239 /* no need to take locks, etc. if nothing's going to change */
240 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
241 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
242 return;
243
612e06ce 244 mutex_lock(&rdev->ddev->struct_mutex);
db7fce39 245 down_write(&rdev->pm.mclk_lock);
d6999bc7 246 mutex_lock(&rdev->ring_lock);
4f3218cb 247
95f5a3ac
AD		 248 /* wait for the rings to drain */
249 for (i = 0; i < RADEON_NUM_RINGS; i++) {
250 struct radeon_ring *ring = &rdev->ring[i];
251 if (ring->ready)
252 radeon_fence_wait_empty_locked(rdev, i);
4f3218cb 253 }
95f5a3ac 254
5876dd24
MG		 255 radeon_unmap_vram_bos(rdev);
256
ce8f5370 257 if (rdev->irq.installed) {
2aba631c
MG		 258 for (i = 0; i < rdev->num_crtc; i++) {
259 if (rdev->pm.active_crtcs & (1 << i)) {
260 rdev->pm.req_vblank |= (1 << i);
261 drm_vblank_get(rdev->ddev, i);
262 }
263 }
264 }
539d2418 265
ce8f5370 266 radeon_set_power_state(rdev);
2aba631c 267
ce8f5370 268 if (rdev->irq.installed) {
2aba631c
MG		 269 for (i = 0; i < rdev->num_crtc; i++) {
270 if (rdev->pm.req_vblank & (1 << i)) {
271 rdev->pm.req_vblank &= ~(1 << i);
272 drm_vblank_put(rdev->ddev, i);
273 }
274 }
275 }
5876dd24 276
a424816f
AD		 277 /* update display watermarks based on new power state */
278 radeon_update_bandwidth_info(rdev);
279 if (rdev->pm.active_crtc_count)
280 radeon_bandwidth_update(rdev);
281
ce8f5370 282 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 283
d6999bc7 284 mutex_unlock(&rdev->ring_lock);
db7fce39 285 up_write(&rdev->pm.mclk_lock);
612e06ce 286 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 287}
288
f712d0c7
RM		 289static void radeon_pm_print_states(struct radeon_device *rdev)
290{
291 int i, j;
292 struct radeon_power_state *power_state;
293 struct radeon_pm_clock_info *clock_info;
294
d9fdaafb 295 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 296 for (i = 0; i < rdev->pm.num_power_states; i++) {
297 power_state = &rdev->pm.power_state[i];
d9fdaafb 298 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 299 radeon_pm_state_type_name[power_state->type]);
300 if (i == rdev->pm.default_power_state_index)
d9fdaafb 301 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 302 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 303 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 304 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 305 DRM_DEBUG_DRIVER("\tSingle display only\n");
306 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 307 for (j = 0; j < power_state->num_clock_modes; j++) {
308 clock_info = &(power_state->clock_info[j]);
309 if (rdev->flags & RADEON_IS_IGP)
eb2c27a0
AD		 310 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
311 j,
312 clock_info->sclk * 10);
f712d0c7 313 else
eb2c27a0
AD		 314 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
315 j,
316 clock_info->sclk * 10,
317 clock_info->mclk * 10,
318 clock_info->voltage.voltage);
f712d0c7
RM		 319 }
320 }
321}
322
ce8f5370
AD		 323static ssize_t radeon_get_pm_profile(struct device *dev,
324 struct device_attribute *attr,
325 char *buf)
a424816f
AD		 326{
327 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
328 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 329 int cp = rdev->pm.profile;
a424816f 330
ce8f5370
AD		 331 return snprintf(buf, PAGE_SIZE, "%s\n",
332 (cp == PM_PROFILE_AUTO) ? "auto" :
333 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 334 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 335 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 336}
337
ce8f5370
AD		 338static ssize_t radeon_set_pm_profile(struct device *dev,
339 struct device_attribute *attr,
340 const char *buf,
341 size_t count)
a424816f
AD		 342{
343 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
344 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 345
346 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 347 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
348 if (strncmp("default", buf, strlen("default")) == 0)
349 rdev->pm.profile = PM_PROFILE_DEFAULT;
350 else if (strncmp("auto", buf, strlen("auto")) == 0)
351 rdev->pm.profile = PM_PROFILE_AUTO;
352 else if (strncmp("low", buf, strlen("low")) == 0)
353 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 354 else if (strncmp("mid", buf, strlen("mid")) == 0)
355 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 356 else if (strncmp("high", buf, strlen("high")) == 0)
357 rdev->pm.profile = PM_PROFILE_HIGH;
358 else {
1783e4bf 359 count = -EINVAL;
ce8f5370 360 goto fail;
a424816f 361 }
ce8f5370
AD		 362 radeon_pm_update_profile(rdev);
363 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 364 } else
365 count = -EINVAL;
366
ce8f5370 367fail:
a424816f
AD		 368 mutex_unlock(&rdev->pm.mutex);
369
370 return count;
371}
372
ce8f5370
AD		 373static ssize_t radeon_get_pm_method(struct device *dev,
374 struct device_attribute *attr,
375 char *buf)
a424816f
AD		 376{
377 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
378 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 379 int pm = rdev->pm.pm_method;
a424816f
AD		 380
381 return snprintf(buf, PAGE_SIZE, "%s\n",
ce8f5370 382 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
a424816f
AD		 383}
384
ce8f5370
AD		 385static ssize_t radeon_set_pm_method(struct device *dev,
386 struct device_attribute *attr,
387 const char *buf,
388 size_t count)
a424816f
AD		 389{
390 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
391 struct radeon_device *rdev = ddev->dev_private;
a424816f 392
ce8f5370
AD		 393
394 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 395 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 396 rdev->pm.pm_method = PM_METHOD_DYNPM;
397 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
398 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 399 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 400 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
401 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 402 /* disable dynpm */
403 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
404 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 405 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 406 mutex_unlock(&rdev->pm.mutex);
32c87fca 407 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 408 } else {
1783e4bf 409 count = -EINVAL;
ce8f5370
AD		 410 goto fail;
411 }
412 radeon_pm_compute_clocks(rdev);
413fail:
a424816f
AD		 414 return count;
415}
416
ce8f5370
AD		 417static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
418static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
a424816f 419
21a8122a
AD		 420static ssize_t radeon_hwmon_show_temp(struct device *dev,
421 struct device_attribute *attr,
422 char *buf)
423{
424 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
425 struct radeon_device *rdev = ddev->dev_private;
20d391d7 426 int temp;
21a8122a
AD		 427
428 switch (rdev->pm.int_thermal_type) {
429 case THERMAL_TYPE_RV6XX:
430 temp = rv6xx_get_temp(rdev);
431 break;
432 case THERMAL_TYPE_RV770:
433 temp = rv770_get_temp(rdev);
434 break;
435 case THERMAL_TYPE_EVERGREEN:
4fddba1f 436 case THERMAL_TYPE_NI:
21a8122a
AD		 437 temp = evergreen_get_temp(rdev);
438 break;
e33df25f
AD		 439 case THERMAL_TYPE_SUMO:
440 temp = sumo_get_temp(rdev);
441 break;
1bd47d2e
AD		 442 case THERMAL_TYPE_SI:
443 temp = si_get_temp(rdev);
444 break;
21a8122a
AD		 445 default:
446 temp = 0;
447 break;
448 }
449
450 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
451}
452
453static ssize_t radeon_hwmon_show_name(struct device *dev,
454 struct device_attribute *attr,
455 char *buf)
456{
457 return sprintf(buf, "radeon\n");
458}
459
460static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
461static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
462
463static struct attribute *hwmon_attributes[] = {
464 &sensor_dev_attr_temp1_input.dev_attr.attr,
465 &sensor_dev_attr_name.dev_attr.attr,
466 NULL
467};
468
469static const struct attribute_group hwmon_attrgroup = {
470 .attrs = hwmon_attributes,
471};
472
0d18abed 473static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 474{
0d18abed 475 int err = 0;
21a8122a
AD		 476
477 rdev->pm.int_hwmon_dev = NULL;
478
479 switch (rdev->pm.int_thermal_type) {
480 case THERMAL_TYPE_RV6XX:
481 case THERMAL_TYPE_RV770:
482 case THERMAL_TYPE_EVERGREEN:
457558ed 483 case THERMAL_TYPE_NI:
e33df25f 484 case THERMAL_TYPE_SUMO:
1bd47d2e 485 case THERMAL_TYPE_SI:
5d7486c7
AD		 486 /* No support for TN yet */
487 if (rdev->family == CHIP_ARUBA)
488 return err;
21a8122a 489 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 490 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
491 err = PTR_ERR(rdev->pm.int_hwmon_dev);
492 dev_err(rdev->dev,
493 "Unable to register hwmon device: %d\n", err);
494 break;
495 }
21a8122a
AD		 496 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
497 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
498 &hwmon_attrgroup);
0d18abed
DC		 499 if (err) {
500 dev_err(rdev->dev,
501 "Unable to create hwmon sysfs file: %d\n", err);
502 hwmon_device_unregister(rdev->dev);
503 }
21a8122a
AD		 504 break;
505 default:
506 break;
507 }
0d18abed
DC		 508
509 return err;
21a8122a
AD		 510}
511
512static void radeon_hwmon_fini(struct radeon_device *rdev)
513{
514 if (rdev->pm.int_hwmon_dev) {
515 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
516 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
517 }
518}
519
ce8f5370 520void radeon_pm_suspend(struct radeon_device *rdev)
56278a8e 521{
ce8f5370 522 mutex_lock(&rdev->pm.mutex);
3f53eb6f 523 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 524 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
525 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 526 }
ce8f5370 527 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 528
529 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 530}
531
ce8f5370 532void radeon_pm_resume(struct radeon_device *rdev)
d0d6cb81 533{
ed18a360 534 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10
AD		 535 if ((rdev->family >= CHIP_BARTS) &&
536 (rdev->family <= CHIP_CAYMAN) &&
537 rdev->mc_fw) {
ed18a360 538 if (rdev->pm.default_vddc)
8a83ec5e
AD		 539 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
540 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 541 if (rdev->pm.default_vddci)
542 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
543 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 544 if (rdev->pm.default_sclk)
545 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
546 if (rdev->pm.default_mclk)
547 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
548 }
f8ed8b4c
AD		 549 /* asic init will reset the default power state */
550 mutex_lock(&rdev->pm.mutex);
551 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
552 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 553 rdev->pm.current_sclk = rdev->pm.default_sclk;
554 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 555 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2feea49a 556 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
3f53eb6f
RW		 557 if (rdev->pm.pm_method == PM_METHOD_DYNPM
558 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
559 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 560 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
561 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 562 }
f8ed8b4c 563 mutex_unlock(&rdev->pm.mutex);
ce8f5370 564 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 565}
566
7433874e
RM		 567int radeon_pm_init(struct radeon_device *rdev)
568{
26481fb1 569 int ret;
0d18abed 570
ce8f5370
AD		 571 /* default to profile method */
572 rdev->pm.pm_method = PM_METHOD_PROFILE;
f8ed8b4c 573 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 574 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
575 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
576 rdev->pm.dynpm_can_upclock = true;
577 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 578 rdev->pm.default_sclk = rdev->clock.default_sclk;
579 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 580 rdev->pm.current_sclk = rdev->clock.default_sclk;
581 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 582 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 583
56278a8e
AD		 584 if (rdev->bios) {
585 if (rdev->is_atom_bios)
586 radeon_atombios_get_power_modes(rdev);
587 else
588 radeon_combios_get_power_modes(rdev);
f712d0c7 589 radeon_pm_print_states(rdev);
ce8f5370 590 radeon_pm_init_profile(rdev);
ed18a360 591 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10
AD		 592 if ((rdev->family >= CHIP_BARTS) &&
593 (rdev->family <= CHIP_CAYMAN) &&
594 rdev->mc_fw) {
ed18a360 595 if (rdev->pm.default_vddc)
8a83ec5e
AD		 596 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
597 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 598 if (rdev->pm.default_vddci)
599 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
600 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 601 if (rdev->pm.default_sclk)
602 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
603 if (rdev->pm.default_mclk)
604 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
605 }
56278a8e
AD		 606 }
607
21a8122a 608 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 609 ret = radeon_hwmon_init(rdev);
610 if (ret)
611 return ret;
32c87fca
TH		 612
613 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
614
ce8f5370 615 if (rdev->pm.num_power_states > 1) {
ce8f5370 616 /* where's the best place to put these? */
26481fb1
DA		 617 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
618 if (ret)
619 DRM_ERROR("failed to create device file for power profile\n");
620 ret = device_create_file(rdev->dev, &dev_attr_power_method);
621 if (ret)
622 DRM_ERROR("failed to create device file for power method\n");
a424816f 623
ce8f5370
AD		 624 if (radeon_debugfs_pm_init(rdev)) {
625 DRM_ERROR("Failed to register debugfs file for PM!\n");
626 }
c913e23a 627
ce8f5370
AD		 628 DRM_INFO("radeon: power management initialized\n");
629 }
c913e23a 630
7433874e
RM		 631 return 0;
632}
633
29fb52ca
AD		 634void radeon_pm_fini(struct radeon_device *rdev)
635{
ce8f5370 636 if (rdev->pm.num_power_states > 1) {
a424816f 637 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 638 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
639 rdev->pm.profile = PM_PROFILE_DEFAULT;
640 radeon_pm_update_profile(rdev);
641 radeon_pm_set_clocks(rdev);
642 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 643 /* reset default clocks */
644 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
645 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
646 radeon_pm_set_clocks(rdev);
647 }
a424816f 648 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 649
650 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 651
ce8f5370
AD		 652 device_remove_file(rdev->dev, &dev_attr_power_profile);
653 device_remove_file(rdev->dev, &dev_attr_power_method);
ce8f5370 654 }
a424816f 655
0975b162
AD		 656 if (rdev->pm.power_state)
657 kfree(rdev->pm.power_state);
658
21a8122a 659 radeon_hwmon_fini(rdev);
29fb52ca
AD		 660}
661
c913e23a
RM		 662void radeon_pm_compute_clocks(struct radeon_device *rdev)
663{
664 struct drm_device *ddev = rdev->ddev;
a48b9b4e 665 struct drm_crtc *crtc;
c913e23a 666 struct radeon_crtc *radeon_crtc;
c913e23a 667
ce8f5370
AD		 668 if (rdev->pm.num_power_states < 2)
669 return;
670
c913e23a
RM		 671 mutex_lock(&rdev->pm.mutex);
672
673 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 674 rdev->pm.active_crtc_count = 0;
675 list_for_each_entry(crtc,
676 &ddev->mode_config.crtc_list, head) {
677 radeon_crtc = to_radeon_crtc(crtc);
678 if (radeon_crtc->enabled) {
c913e23a 679 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 680 rdev->pm.active_crtc_count++;
c913e23a
RM		 681 }
682 }
683
ce8f5370
AD		 684 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
685 radeon_pm_update_profile(rdev);
686 radeon_pm_set_clocks(rdev);
687 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
688 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
689 if (rdev->pm.active_crtc_count > 1) {
690 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
691 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
692
693 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
694 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
695 radeon_pm_get_dynpm_state(rdev);
696 radeon_pm_set_clocks(rdev);
697
d9fdaafb 698 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 699 }
700 } else if (rdev->pm.active_crtc_count == 1) {
701 /* TODO: Increase clocks if needed for current mode */
702
703 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
704 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
705 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
706 radeon_pm_get_dynpm_state(rdev);
707 radeon_pm_set_clocks(rdev);
708
32c87fca
TH		 709 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
710 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 711 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
712 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 713 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
714 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 715 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 716 }
717 } else { /* count == 0 */
718 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
719 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
720
721 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
722 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
723 radeon_pm_get_dynpm_state(rdev);
724 radeon_pm_set_clocks(rdev);
725 }
726 }
c913e23a 727 }
c913e23a 728 }
73a6d3fc
RM		 729
730 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 731}
732
ce8f5370 733static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 734{
75fa0b08 735 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 736 bool in_vbl = true;
737
75fa0b08
MK		 738 /* Iterate over all active crtc's. All crtc's must be in vblank,
739 * otherwise return in_vbl == false.
740 */
741 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
742 if (rdev->pm.active_crtcs & (1 << crtc)) {
f5a80209
MK		 743 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
744 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
745 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 746 in_vbl = false;
747 }
748 }
f81f2024
MG		 749
750 return in_vbl;
751}
752
ce8f5370 753static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 754{
755 u32 stat_crtc = 0;
756 bool in_vbl = radeon_pm_in_vbl(rdev);
757
f735261b 758 if (in_vbl == false)
d9fdaafb 759 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 760 finish ? "exit" : "entry");
f735261b
DA		 761 return in_vbl;
762}
c913e23a 763
ce8f5370 764static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 765{
766 struct radeon_device *rdev;
d9932a32 767 int resched;
c913e23a 768 rdev = container_of(work, struct radeon_device,
ce8f5370 769 pm.dynpm_idle_work.work);
c913e23a 770
d9932a32 771 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 772 mutex_lock(&rdev->pm.mutex);
ce8f5370 773 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 774 int not_processed = 0;
7465280c
AD		 775 int i;
776
7465280c 777 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0ec0612a
AD		 778 struct radeon_ring *ring = &rdev->ring[i];
779
780 if (ring->ready) {
781 not_processed += radeon_fence_count_emitted(rdev, i);
782 if (not_processed >= 3)
783 break;
784 }
c913e23a 785 }
c913e23a
RM		 786
787 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 788 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
789 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
790 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
791 rdev->pm.dynpm_can_upclock) {
792 rdev->pm.dynpm_planned_action =
793 DYNPM_ACTION_UPCLOCK;
794 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 795 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
796 }
797 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 798 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
799 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
800 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
801 rdev->pm.dynpm_can_downclock) {
802 rdev->pm.dynpm_planned_action =
803 DYNPM_ACTION_DOWNCLOCK;
804 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 805 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
806 }
807 }
808
d7311171
AD		 809 /* Note, radeon_pm_set_clocks is called with static_switch set
810 * to false since we want to wait for vbl to avoid flicker.
811 */
ce8f5370
AD		 812 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
813 jiffies > rdev->pm.dynpm_action_timeout) {
814 radeon_pm_get_dynpm_state(rdev);
815 radeon_pm_set_clocks(rdev);
c913e23a 816 }
3f53eb6f 817
32c87fca
TH		 818 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
819 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 820 }
821 mutex_unlock(&rdev->pm.mutex);
d9932a32 822 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 823}
824
7433874e
RM		 825/*
826 * Debugfs info
827 */
828#if defined(CONFIG_DEBUG_FS)
829
830static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
831{
832 struct drm_info_node *node = (struct drm_info_node *) m->private;
833 struct drm_device *dev = node->minor->dev;
834 struct radeon_device *rdev = dev->dev_private;
835
9ace9f7b 836 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
6234077d 837 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
9ace9f7b 838 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
798bcf73 839 if (rdev->asic->pm.get_memory_clock)
6234077d 840 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 841 if (rdev->pm.current_vddc)
842 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
798bcf73 843 if (rdev->asic->pm.get_pcie_lanes)
aa5120d2 844 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 845
846 return 0;
847}
848
849static struct drm_info_list radeon_pm_info_list[] = {
850 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
851};
852#endif
853
c913e23a 854static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 855{
856#if defined(CONFIG_DEBUG_FS)
857 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
858#else
859 return 0;
860#endif
861}
Linux 6.x block layer and io_uring tree(s)