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drm/radeon: add pm sysfs files late
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e 22 */
760285e7 23#include <drm/drmP.h>
7433874e 24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
99736703 27#include "r600_dpm.h"
ce8f5370 28#include <linux/power_supply.h>
21a8122a
AD		 29#include <linux/hwmon.h>
30#include <linux/hwmon-sysfs.h>
7433874e 31
c913e23a
RM		 32#define RADEON_IDLE_LOOP_MS 100
33#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 34#define RADEON_WAIT_VBLANK_TIMEOUT 200
c913e23a 35
f712d0c7 36static const char *radeon_pm_state_type_name[5] = {
eb2c27a0 37 "",
f712d0c7
RM		 38 "Powersave",
39 "Battery",
40 "Balanced",
41 "Performance",
42};
43
ce8f5370 44static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 45static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 46static bool radeon_pm_in_vbl(struct radeon_device *rdev);
47static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
48static void radeon_pm_update_profile(struct radeon_device *rdev);
49static void radeon_pm_set_clocks(struct radeon_device *rdev);
50
a4c9e2ee
AD		 51int radeon_pm_get_type_index(struct radeon_device *rdev,
52 enum radeon_pm_state_type ps_type,
53 int instance)
54{
55 int i;
56 int found_instance = -1;
57
58 for (i = 0; i < rdev->pm.num_power_states; i++) {
59 if (rdev->pm.power_state[i].type == ps_type) {
60 found_instance++;
61 if (found_instance == instance)
62 return i;
63 }
64 }
65 /* return default if no match */
66 return rdev->pm.default_power_state_index;
67}
68
c4917074 69void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
ce8f5370 70{
1c71bda0
AD		 71 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
72 mutex_lock(&rdev->pm.mutex);
73 if (power_supply_is_system_supplied() > 0)
74 rdev->pm.dpm.ac_power = true;
75 else
76 rdev->pm.dpm.ac_power = false;
96682956
AD		 77 if (rdev->family == CHIP_ARUBA) {
78 if (rdev->asic->dpm.enable_bapm)
79 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
80 }
1c71bda0
AD		 81 mutex_unlock(&rdev->pm.mutex);
82 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
c4917074
AD		 83 if (rdev->pm.profile == PM_PROFILE_AUTO) {
84 mutex_lock(&rdev->pm.mutex);
85 radeon_pm_update_profile(rdev);
86 radeon_pm_set_clocks(rdev);
87 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 88 }
89 }
ce8f5370 90}
ce8f5370
AD		 91
92static void radeon_pm_update_profile(struct radeon_device *rdev)
93{
94 switch (rdev->pm.profile) {
95 case PM_PROFILE_DEFAULT:
96 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
97 break;
98 case PM_PROFILE_AUTO:
99 if (power_supply_is_system_supplied() > 0) {
100 if (rdev->pm.active_crtc_count > 1)
101 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
102 else
103 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
104 } else {
105 if (rdev->pm.active_crtc_count > 1)
c9e75b21 106 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 107 else
c9e75b21 108 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 109 }
110 break;
111 case PM_PROFILE_LOW:
112 if (rdev->pm.active_crtc_count > 1)
113 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
114 else
115 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
116 break;
c9e75b21
AD		 117 case PM_PROFILE_MID:
118 if (rdev->pm.active_crtc_count > 1)
119 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
120 else
121 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
122 break;
ce8f5370
AD		 123 case PM_PROFILE_HIGH:
124 if (rdev->pm.active_crtc_count > 1)
125 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
126 else
127 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
128 break;
129 }
130
131 if (rdev->pm.active_crtc_count == 0) {
132 rdev->pm.requested_power_state_index =
133 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
134 rdev->pm.requested_clock_mode_index =
135 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
136 } else {
137 rdev->pm.requested_power_state_index =
138 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
139 rdev->pm.requested_clock_mode_index =
140 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
141 }
142}
c913e23a 143
5876dd24
MG		 144static void radeon_unmap_vram_bos(struct radeon_device *rdev)
145{
146 struct radeon_bo *bo, *n;
147
148 if (list_empty(&rdev->gem.objects))
149 return;
150
151 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
152 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
153 ttm_bo_unmap_virtual(&bo->tbo);
154 }
5876dd24
MG		 155}
156
ce8f5370 157static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 158{
ce8f5370
AD		 159 if (rdev->pm.active_crtcs) {
160 rdev->pm.vblank_sync = false;
161 wait_event_timeout(
162 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
163 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
164 }
165}
166
167static void radeon_set_power_state(struct radeon_device *rdev)
168{
169 u32 sclk, mclk;
92645879 170 bool misc_after = false;
ce8f5370
AD		 171
172 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
173 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
174 return;
175
176 if (radeon_gui_idle(rdev)) {
177 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
178 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 179 if (sclk > rdev->pm.default_sclk)
180 sclk = rdev->pm.default_sclk;
ce8f5370 181
27810fb2
AD		 182 /* starting with BTC, there is one state that is used for both
183 * MH and SH. Difference is that we always use the high clock index for
7ae764b1 184 * mclk and vddci.
27810fb2
AD		 185 */
186 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
187 (rdev->family >= CHIP_BARTS) &&
188 rdev->pm.active_crtc_count &&
189 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
190 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
192 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
193 else
194 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
195 clock_info[rdev->pm.requested_clock_mode_index].mclk;
196
9ace9f7b
AD		 197 if (mclk > rdev->pm.default_mclk)
198 mclk = rdev->pm.default_mclk;
ce8f5370 199
92645879
AD		 200 /* upvolt before raising clocks, downvolt after lowering clocks */
201 if (sclk < rdev->pm.current_sclk)
202 misc_after = true;
ce8f5370 203
92645879 204 radeon_sync_with_vblank(rdev);
ce8f5370 205
92645879 206 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 207 if (!radeon_pm_in_vbl(rdev))
208 return;
92645879 209 }
ce8f5370 210
92645879 211 radeon_pm_prepare(rdev);
ce8f5370 212
92645879
AD		 213 if (!misc_after)
214 /* voltage, pcie lanes, etc.*/
215 radeon_pm_misc(rdev);
216
217 /* set engine clock */
218 if (sclk != rdev->pm.current_sclk) {
219 radeon_pm_debug_check_in_vbl(rdev, false);
220 radeon_set_engine_clock(rdev, sclk);
221 radeon_pm_debug_check_in_vbl(rdev, true);
222 rdev->pm.current_sclk = sclk;
d9fdaafb 223 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 224 }
225
226 /* set memory clock */
798bcf73 227 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 228 radeon_pm_debug_check_in_vbl(rdev, false);
229 radeon_set_memory_clock(rdev, mclk);
230 radeon_pm_debug_check_in_vbl(rdev, true);
231 rdev->pm.current_mclk = mclk;
d9fdaafb 232 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 233 }
2aba631c 234
92645879
AD		 235 if (misc_after)
236 /* voltage, pcie lanes, etc.*/
237 radeon_pm_misc(rdev);
238
239 radeon_pm_finish(rdev);
240
ce8f5370
AD		 241 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
242 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
243 } else
d9fdaafb 244 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 245}
246
247static void radeon_pm_set_clocks(struct radeon_device *rdev)
248{
5f8f635e 249 int i, r;
c37d230a 250
4e186b2d
AD		 251 /* no need to take locks, etc. if nothing's going to change */
252 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
253 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
254 return;
255
db7fce39 256 down_write(&rdev->pm.mclk_lock);
d6999bc7 257 mutex_lock(&rdev->ring_lock);
4f3218cb 258
95f5a3ac
AD		 259 /* wait for the rings to drain */
260 for (i = 0; i < RADEON_NUM_RINGS; i++) {
261 struct radeon_ring *ring = &rdev->ring[i];
5f8f635e
JG		 262 if (!ring->ready) {
263 continue;
264 }
37615527 265 r = radeon_fence_wait_empty(rdev, i);
5f8f635e
JG		 266 if (r) {
267 /* needs a GPU reset dont reset here */
268 mutex_unlock(&rdev->ring_lock);
269 up_write(&rdev->pm.mclk_lock);
5f8f635e
JG		 270 return;
271 }
4f3218cb 272 }
95f5a3ac 273
5876dd24
MG		 274 radeon_unmap_vram_bos(rdev);
275
ce8f5370 276 if (rdev->irq.installed) {
2aba631c
MG		 277 for (i = 0; i < rdev->num_crtc; i++) {
278 if (rdev->pm.active_crtcs & (1 << i)) {
279 rdev->pm.req_vblank |= (1 << i);
280 drm_vblank_get(rdev->ddev, i);
281 }
282 }
283 }
539d2418 284
ce8f5370 285 radeon_set_power_state(rdev);
2aba631c 286
ce8f5370 287 if (rdev->irq.installed) {
2aba631c
MG		 288 for (i = 0; i < rdev->num_crtc; i++) {
289 if (rdev->pm.req_vblank & (1 << i)) {
290 rdev->pm.req_vblank &= ~(1 << i);
291 drm_vblank_put(rdev->ddev, i);
292 }
293 }
294 }
5876dd24 295
a424816f
AD		 296 /* update display watermarks based on new power state */
297 radeon_update_bandwidth_info(rdev);
298 if (rdev->pm.active_crtc_count)
299 radeon_bandwidth_update(rdev);
300
ce8f5370 301 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 302
d6999bc7 303 mutex_unlock(&rdev->ring_lock);
db7fce39 304 up_write(&rdev->pm.mclk_lock);
a424816f
AD		 305}
306
f712d0c7
RM		 307static void radeon_pm_print_states(struct radeon_device *rdev)
308{
309 int i, j;
310 struct radeon_power_state *power_state;
311 struct radeon_pm_clock_info *clock_info;
312
d9fdaafb 313 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 314 for (i = 0; i < rdev->pm.num_power_states; i++) {
315 power_state = &rdev->pm.power_state[i];
d9fdaafb 316 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 317 radeon_pm_state_type_name[power_state->type]);
318 if (i == rdev->pm.default_power_state_index)
d9fdaafb 319 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 320 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 321 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 322 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 323 DRM_DEBUG_DRIVER("\tSingle display only\n");
324 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 325 for (j = 0; j < power_state->num_clock_modes; j++) {
326 clock_info = &(power_state->clock_info[j]);
327 if (rdev->flags & RADEON_IS_IGP)
eb2c27a0
AD		 328 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
329 j,
330 clock_info->sclk * 10);
f712d0c7 331 else
eb2c27a0
AD		 332 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
333 j,
334 clock_info->sclk * 10,
335 clock_info->mclk * 10,
336 clock_info->voltage.voltage);
f712d0c7
RM		 337 }
338 }
339}
340
ce8f5370
AD		 341static ssize_t radeon_get_pm_profile(struct device *dev,
342 struct device_attribute *attr,
343 char *buf)
a424816f 344{
3e4e2129 345 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 346 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 347 int cp = rdev->pm.profile;
a424816f 348
ce8f5370
AD		 349 return snprintf(buf, PAGE_SIZE, "%s\n",
350 (cp == PM_PROFILE_AUTO) ? "auto" :
351 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 352 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 353 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 354}
355
ce8f5370
AD		 356static ssize_t radeon_set_pm_profile(struct device *dev,
357 struct device_attribute *attr,
358 const char *buf,
359 size_t count)
a424816f 360{
3e4e2129 361 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 362 struct radeon_device *rdev = ddev->dev_private;
a424816f 363
4f2f2039
AD		 364 /* Can't set profile when the card is off */
365 if ((rdev->flags & RADEON_IS_PX) &&
366 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
367 return -EINVAL;
368
a424816f 369 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 370 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
371 if (strncmp("default", buf, strlen("default")) == 0)
372 rdev->pm.profile = PM_PROFILE_DEFAULT;
373 else if (strncmp("auto", buf, strlen("auto")) == 0)
374 rdev->pm.profile = PM_PROFILE_AUTO;
375 else if (strncmp("low", buf, strlen("low")) == 0)
376 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 377 else if (strncmp("mid", buf, strlen("mid")) == 0)
378 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 379 else if (strncmp("high", buf, strlen("high")) == 0)
380 rdev->pm.profile = PM_PROFILE_HIGH;
381 else {
1783e4bf 382 count = -EINVAL;
ce8f5370 383 goto fail;
a424816f 384 }
ce8f5370
AD		 385 radeon_pm_update_profile(rdev);
386 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 387 } else
388 count = -EINVAL;
389
ce8f5370 390fail:
a424816f
AD		 391 mutex_unlock(&rdev->pm.mutex);
392
393 return count;
394}
395
ce8f5370
AD		 396static ssize_t radeon_get_pm_method(struct device *dev,
397 struct device_attribute *attr,
398 char *buf)
a424816f 399{
3e4e2129 400 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 401 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 402 int pm = rdev->pm.pm_method;
a424816f
AD		 403
404 return snprintf(buf, PAGE_SIZE, "%s\n",
da321c8a
AD		 405 (pm == PM_METHOD_DYNPM) ? "dynpm" :
406 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
a424816f
AD		 407}
408
ce8f5370
AD		 409static ssize_t radeon_set_pm_method(struct device *dev,
410 struct device_attribute *attr,
411 const char *buf,
412 size_t count)
a424816f 413{
3e4e2129 414 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 415 struct radeon_device *rdev = ddev->dev_private;
a424816f 416
4f2f2039
AD		 417 /* Can't set method when the card is off */
418 if ((rdev->flags & RADEON_IS_PX) &&
419 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
420 count = -EINVAL;
421 goto fail;
422 }
423
da321c8a
AD		 424 /* we don't support the legacy modes with dpm */
425 if (rdev->pm.pm_method == PM_METHOD_DPM) {
426 count = -EINVAL;
427 goto fail;
428 }
ce8f5370
AD		 429
430 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 431 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 432 rdev->pm.pm_method = PM_METHOD_DYNPM;
433 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
434 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 435 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 436 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
437 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 438 /* disable dynpm */
439 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
440 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 441 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 442 mutex_unlock(&rdev->pm.mutex);
32c87fca 443 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 444 } else {
1783e4bf 445 count = -EINVAL;
ce8f5370
AD		 446 goto fail;
447 }
448 radeon_pm_compute_clocks(rdev);
449fail:
a424816f
AD		 450 return count;
451}
452
da321c8a
AD		 453static ssize_t radeon_get_dpm_state(struct device *dev,
454 struct device_attribute *attr,
455 char *buf)
456{
3e4e2129 457 struct drm_device *ddev = dev_get_drvdata(dev);
da321c8a
AD		 458 struct radeon_device *rdev = ddev->dev_private;
459 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
460
461 return snprintf(buf, PAGE_SIZE, "%s\n",
462 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
463 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
464}
465
466static ssize_t radeon_set_dpm_state(struct device *dev,
467 struct device_attribute *attr,
468 const char *buf,
469 size_t count)
470{
3e4e2129 471 struct drm_device *ddev = dev_get_drvdata(dev);
da321c8a
AD		 472 struct radeon_device *rdev = ddev->dev_private;
473
474 mutex_lock(&rdev->pm.mutex);
475 if (strncmp("battery", buf, strlen("battery")) == 0)
476 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
477 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
478 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
479 else if (strncmp("performance", buf, strlen("performance")) == 0)
480 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
481 else {
482 mutex_unlock(&rdev->pm.mutex);
483 count = -EINVAL;
484 goto fail;
485 }
486 mutex_unlock(&rdev->pm.mutex);
b07a657e
PR		 487
488 /* Can't set dpm state when the card is off */
489 if (!(rdev->flags & RADEON_IS_PX) ||
490 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
491 radeon_pm_compute_clocks(rdev);
492
da321c8a
AD		 493fail:
494 return count;
495}
496
70d01a5e
AD		 497static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
498 struct device_attribute *attr,
499 char *buf)
500{
3e4e2129 501 struct drm_device *ddev = dev_get_drvdata(dev);
70d01a5e
AD		 502 struct radeon_device *rdev = ddev->dev_private;
503 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
504
4f2f2039
AD		 505 if ((rdev->flags & RADEON_IS_PX) &&
506 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
507 return snprintf(buf, PAGE_SIZE, "off\n");
508
70d01a5e
AD		 509 return snprintf(buf, PAGE_SIZE, "%s\n",
510 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
511 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
512}
513
514static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
515 struct device_attribute *attr,
516 const char *buf,
517 size_t count)
518{
3e4e2129 519 struct drm_device *ddev = dev_get_drvdata(dev);
70d01a5e
AD		 520 struct radeon_device *rdev = ddev->dev_private;
521 enum radeon_dpm_forced_level level;
522 int ret = 0;
523
4f2f2039
AD		 524 /* Can't force performance level when the card is off */
525 if ((rdev->flags & RADEON_IS_PX) &&
526 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
527 return -EINVAL;
528
70d01a5e
AD		 529 mutex_lock(&rdev->pm.mutex);
530 if (strncmp("low", buf, strlen("low")) == 0) {
531 level = RADEON_DPM_FORCED_LEVEL_LOW;
532 } else if (strncmp("high", buf, strlen("high")) == 0) {
533 level = RADEON_DPM_FORCED_LEVEL_HIGH;
534 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
535 level = RADEON_DPM_FORCED_LEVEL_AUTO;
536 } else {
70d01a5e
AD		 537 count = -EINVAL;
538 goto fail;
539 }
540 if (rdev->asic->dpm.force_performance_level) {
0a17af37
AD		 541 if (rdev->pm.dpm.thermal_active) {
542 count = -EINVAL;
543 goto fail;
544 }
70d01a5e
AD		 545 ret = radeon_dpm_force_performance_level(rdev, level);
546 if (ret)
547 count = -EINVAL;
548 }
70d01a5e 549fail:
0a17af37
AD		 550 mutex_unlock(&rdev->pm.mutex);
551
70d01a5e
AD		 552 return count;
553}
554
99736703
OC		 555static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev,
556 struct device_attribute *attr,
557 char *buf)
558{
559 struct radeon_device *rdev = dev_get_drvdata(dev);
560 u32 pwm_mode = 0;
561
562 if (rdev->asic->dpm.fan_ctrl_get_mode)
563 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev);
564
565 /* never 0 (full-speed), fuse or smc-controlled always */
566 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
567}
568
569static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev,
570 struct device_attribute *attr,
571 const char *buf,
572 size_t count)
573{
574 struct radeon_device *rdev = dev_get_drvdata(dev);
575 int err;
576 int value;
577
578 if(!rdev->asic->dpm.fan_ctrl_set_mode)
579 return -EINVAL;
580
581 err = kstrtoint(buf, 10, &value);
582 if (err)
583 return err;
584
082452e1 585 switch (value) {
99736703
OC		 586 case 1: /* manual, percent-based */
587 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC);
588 break;
589 default: /* disable */
590 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0);
591 break;
592 }
593
594 return count;
595}
596
597static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev,
598 struct device_attribute *attr,
599 char *buf)
600{
601 return sprintf(buf, "%i\n", 0);
602}
603
604static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev,
605 struct device_attribute *attr,
606 char *buf)
607{
082452e1 608 return sprintf(buf, "%i\n", 255);
99736703
OC		 609}
610
611static ssize_t radeon_hwmon_set_pwm1(struct device *dev,
612 struct device_attribute *attr,
613 const char *buf, size_t count)
614{
615 struct radeon_device *rdev = dev_get_drvdata(dev);
616 int err;
617 u32 value;
618
619 err = kstrtou32(buf, 10, &value);
620 if (err)
621 return err;
622
082452e1
AD		 623 value = (value * 100) / 255;
624
99736703
OC		 625 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value);
626 if (err)
627 return err;
628
629 return count;
630}
631
632static ssize_t radeon_hwmon_get_pwm1(struct device *dev,
633 struct device_attribute *attr,
634 char *buf)
635{
636 struct radeon_device *rdev = dev_get_drvdata(dev);
637 int err;
638 u32 speed;
639
640 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed);
641 if (err)
642 return err;
643
082452e1
AD		 644 speed = (speed * 255) / 100;
645
99736703
OC		 646 return sprintf(buf, "%i\n", speed);
647}
648
ce8f5370
AD		 649static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
650static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
da321c8a 651static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
70d01a5e
AD		 652static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
653 radeon_get_dpm_forced_performance_level,
654 radeon_set_dpm_forced_performance_level);
a424816f 655
21a8122a
AD		 656static ssize_t radeon_hwmon_show_temp(struct device *dev,
657 struct device_attribute *attr,
658 char *buf)
659{
ec39f64b 660 struct radeon_device *rdev = dev_get_drvdata(dev);
4f2f2039 661 struct drm_device *ddev = rdev->ddev;
20d391d7 662 int temp;
21a8122a 663
4f2f2039
AD		 664 /* Can't get temperature when the card is off */
665 if ((rdev->flags & RADEON_IS_PX) &&
666 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
667 return -EINVAL;
668
6bd1c385
AD		 669 if (rdev->asic->pm.get_temperature)
670 temp = radeon_get_temperature(rdev);
671 else
21a8122a 672 temp = 0;
21a8122a
AD		 673
674 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
675}
676
6ea4e84d
JD		 677static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
678 struct device_attribute *attr,
679 char *buf)
680{
e4158f1b 681 struct radeon_device *rdev = dev_get_drvdata(dev);
6ea4e84d
JD		 682 int hyst = to_sensor_dev_attr(attr)->index;
683 int temp;
684
685 if (hyst)
686 temp = rdev->pm.dpm.thermal.min_temp;
687 else
688 temp = rdev->pm.dpm.thermal.max_temp;
689
690 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
691}
692
21a8122a 693static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
6ea4e84d
JD		 694static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
695static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
99736703
OC		 696static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0);
697static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0);
698static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0);
699static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0);
700
21a8122a
AD		 701
702static struct attribute *hwmon_attributes[] = {
703 &sensor_dev_attr_temp1_input.dev_attr.attr,
6ea4e84d
JD		 704 &sensor_dev_attr_temp1_crit.dev_attr.attr,
705 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
99736703
OC		 706 &sensor_dev_attr_pwm1.dev_attr.attr,
707 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
708 &sensor_dev_attr_pwm1_min.dev_attr.attr,
709 &sensor_dev_attr_pwm1_max.dev_attr.attr,
21a8122a
AD		 710 NULL
711};
712
6ea4e84d
JD		 713static umode_t hwmon_attributes_visible(struct kobject *kobj,
714 struct attribute *attr, int index)
715{
716 struct device *dev = container_of(kobj, struct device, kobj);
e4158f1b 717 struct radeon_device *rdev = dev_get_drvdata(dev);
99736703 718 umode_t effective_mode = attr->mode;
6ea4e84d
JD		 719
720 /* Skip limit attributes if DPM is not enabled */
721 if (rdev->pm.pm_method != PM_METHOD_DPM &&
722 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
723 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
724 return 0;
725
99736703
OC		 726 /* Skip fan attributes if fan is not present */
727 if (rdev->pm.no_fan &&
728 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
729 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
730 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
731 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
732 return 0;
733
734 /* mask fan attributes if we have no bindings for this asic to expose */
735 if ((!rdev->asic->dpm.get_fan_speed_percent &&
736 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
737 (!rdev->asic->dpm.fan_ctrl_get_mode &&
738 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
739 effective_mode &= ~S_IRUGO;
740
741 if ((!rdev->asic->dpm.set_fan_speed_percent &&
742 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
743 (!rdev->asic->dpm.fan_ctrl_set_mode &&
744 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
745 effective_mode &= ~S_IWUSR;
746
747 /* hide max/min values if we can't both query and manage the fan */
748 if ((!rdev->asic->dpm.set_fan_speed_percent &&
749 !rdev->asic->dpm.get_fan_speed_percent) &&
750 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
751 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
752 return 0;
753
754 return effective_mode;
6ea4e84d
JD		 755}
756
21a8122a
AD		 757static const struct attribute_group hwmon_attrgroup = {
758 .attrs = hwmon_attributes,
6ea4e84d 759 .is_visible = hwmon_attributes_visible,
21a8122a
AD		 760};
761
ec39f64b
GR		 762static const struct attribute_group *hwmon_groups[] = {
763 &hwmon_attrgroup,
764 NULL
765};
766
0d18abed 767static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 768{
0d18abed 769 int err = 0;
21a8122a
AD		 770
771 switch (rdev->pm.int_thermal_type) {
772 case THERMAL_TYPE_RV6XX:
773 case THERMAL_TYPE_RV770:
774 case THERMAL_TYPE_EVERGREEN:
457558ed 775 case THERMAL_TYPE_NI:
e33df25f 776 case THERMAL_TYPE_SUMO:
1bd47d2e 777 case THERMAL_TYPE_SI:
286d9cc6
AD		 778 case THERMAL_TYPE_CI:
779 case THERMAL_TYPE_KV:
6bd1c385 780 if (rdev->asic->pm.get_temperature == NULL)
5d7486c7 781 return err;
cb3e4e7c
AD		 782 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
783 "radeon", rdev,
784 hwmon_groups);
785 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
786 err = PTR_ERR(rdev->pm.int_hwmon_dev);
0d18abed
DC		 787 dev_err(rdev->dev,
788 "Unable to register hwmon device: %d\n", err);
0d18abed 789 }
21a8122a
AD		 790 break;
791 default:
792 break;
793 }
0d18abed
DC		 794
795 return err;
21a8122a
AD		 796}
797
cb3e4e7c
AD		 798static void radeon_hwmon_fini(struct radeon_device *rdev)
799{
800 if (rdev->pm.int_hwmon_dev)
801 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
802}
803
da321c8a
AD		 804static void radeon_dpm_thermal_work_handler(struct work_struct *work)
805{
806 struct radeon_device *rdev =
807 container_of(work, struct radeon_device,
808 pm.dpm.thermal.work);
809 /* switch to the thermal state */
810 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
811
812 if (!rdev->pm.dpm_enabled)
813 return;
814
815 if (rdev->asic->pm.get_temperature) {
816 int temp = radeon_get_temperature(rdev);
817
818 if (temp < rdev->pm.dpm.thermal.min_temp)
819 /* switch back the user state */
820 dpm_state = rdev->pm.dpm.user_state;
821 } else {
822 if (rdev->pm.dpm.thermal.high_to_low)
823 /* switch back the user state */
824 dpm_state = rdev->pm.dpm.user_state;
825 }
60320347
AD		 826 mutex_lock(&rdev->pm.mutex);
827 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
828 rdev->pm.dpm.thermal_active = true;
829 else
830 rdev->pm.dpm.thermal_active = false;
831 rdev->pm.dpm.state = dpm_state;
832 mutex_unlock(&rdev->pm.mutex);
833
834 radeon_pm_compute_clocks(rdev);
da321c8a
AD		 835}
836
3899ca84 837static bool radeon_dpm_single_display(struct radeon_device *rdev)
da321c8a 838{
48783069
AD		 839 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
840 true : false;
841
842 /* check if the vblank period is too short to adjust the mclk */
843 if (single_display && rdev->asic->dpm.vblank_too_short) {
844 if (radeon_dpm_vblank_too_short(rdev))
845 single_display = false;
846 }
da321c8a 847
951caa6a
AD		 848 /* 120hz tends to be problematic even if they are under the
849 * vblank limit.
850 */
851 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
852 single_display = false;
853
3899ca84
AD		 854 return single_display;
855}
856
857static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
858 enum radeon_pm_state_type dpm_state)
859{
860 int i;
861 struct radeon_ps *ps;
862 u32 ui_class;
863 bool single_display = radeon_dpm_single_display(rdev);
864
edcaa5b1
AD		 865 /* certain older asics have a separare 3D performance state,
866 * so try that first if the user selected performance
867 */
868 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
869 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
da321c8a
AD		 870 /* balanced states don't exist at the moment */
871 if (dpm_state == POWER_STATE_TYPE_BALANCED)
872 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
873
edcaa5b1 874restart_search:
da321c8a
AD		 875 /* Pick the best power state based on current conditions */
876 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
877 ps = &rdev->pm.dpm.ps[i];
878 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
879 switch (dpm_state) {
880 /* user states */
881 case POWER_STATE_TYPE_BATTERY:
882 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
883 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 884 if (single_display)
da321c8a
AD		 885 return ps;
886 } else
887 return ps;
888 }
889 break;
890 case POWER_STATE_TYPE_BALANCED:
891 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
892 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 893 if (single_display)
da321c8a
AD		 894 return ps;
895 } else
896 return ps;
897 }
898 break;
899 case POWER_STATE_TYPE_PERFORMANCE:
900 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
901 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 902 if (single_display)
da321c8a
AD		 903 return ps;
904 } else
905 return ps;
906 }
907 break;
908 /* internal states */
909 case POWER_STATE_TYPE_INTERNAL_UVD:
d4d3278c
AD		 910 if (rdev->pm.dpm.uvd_ps)
911 return rdev->pm.dpm.uvd_ps;
912 else
913 break;
da321c8a
AD		 914 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
915 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
916 return ps;
917 break;
918 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
919 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
920 return ps;
921 break;
922 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
923 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
924 return ps;
925 break;
926 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
927 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
928 return ps;
929 break;
930 case POWER_STATE_TYPE_INTERNAL_BOOT:
931 return rdev->pm.dpm.boot_ps;
932 case POWER_STATE_TYPE_INTERNAL_THERMAL:
933 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
934 return ps;
935 break;
936 case POWER_STATE_TYPE_INTERNAL_ACPI:
937 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
938 return ps;
939 break;
940 case POWER_STATE_TYPE_INTERNAL_ULV:
941 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
942 return ps;
943 break;
edcaa5b1
AD		 944 case POWER_STATE_TYPE_INTERNAL_3DPERF:
945 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
946 return ps;
947 break;
da321c8a
AD		 948 default:
949 break;
950 }
951 }
952 /* use a fallback state if we didn't match */
953 switch (dpm_state) {
954 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
ce3537d5
AD		 955 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
956 goto restart_search;
da321c8a
AD		 957 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
958 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
959 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
d4d3278c
AD		 960 if (rdev->pm.dpm.uvd_ps) {
961 return rdev->pm.dpm.uvd_ps;
962 } else {
963 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
964 goto restart_search;
965 }
da321c8a
AD		 966 case POWER_STATE_TYPE_INTERNAL_THERMAL:
967 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
968 goto restart_search;
969 case POWER_STATE_TYPE_INTERNAL_ACPI:
970 dpm_state = POWER_STATE_TYPE_BATTERY;
971 goto restart_search;
972 case POWER_STATE_TYPE_BATTERY:
edcaa5b1
AD		 973 case POWER_STATE_TYPE_BALANCED:
974 case POWER_STATE_TYPE_INTERNAL_3DPERF:
da321c8a
AD		 975 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
976 goto restart_search;
977 default:
978 break;
979 }
980
981 return NULL;
982}
983
984static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
985{
986 int i;
987 struct radeon_ps *ps;
988 enum radeon_pm_state_type dpm_state;
84dd1928 989 int ret;
3899ca84 990 bool single_display = radeon_dpm_single_display(rdev);
da321c8a
AD		 991
992 /* if dpm init failed */
993 if (!rdev->pm.dpm_enabled)
994 return;
995
996 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
997 /* add other state override checks here */
8a227555
AD		 998 if ((!rdev->pm.dpm.thermal_active) &&
999 (!rdev->pm.dpm.uvd_active))
da321c8a
AD		 1000 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
1001 }
1002 dpm_state = rdev->pm.dpm.state;
1003
1004 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
1005 if (ps)
89c9bc56 1006 rdev->pm.dpm.requested_ps = ps;
da321c8a
AD		 1007 else
1008 return;
1009
d22b7e40 1010 /* no need to reprogram if nothing changed unless we are on BTC+ */
da321c8a 1011 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
b62d628b
AD		 1012 /* vce just modifies an existing state so force a change */
1013 if (ps->vce_active != rdev->pm.dpm.vce_active)
1014 goto force;
3899ca84
AD		 1015 /* user has made a display change (such as timing) */
1016 if (rdev->pm.dpm.single_display != single_display)
1017 goto force;
d22b7e40
AD		 1018 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
1019 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
1020 * all we need to do is update the display configuration.
1021 */
1022 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1023 /* update display watermarks based on new power state */
1024 radeon_bandwidth_update(rdev);
1025 /* update displays */
1026 radeon_dpm_display_configuration_changed(rdev);
1027 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1028 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1029 }
1030 return;
1031 } else {
1032 /* for BTC+ if the num crtcs hasn't changed and state is the same,
1033 * nothing to do, if the num crtcs is > 1 and state is the same,
1034 * update display configuration.
1035 */
1036 if (rdev->pm.dpm.new_active_crtcs ==
1037 rdev->pm.dpm.current_active_crtcs) {
1038 return;
1039 } else {
1040 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1041 (rdev->pm.dpm.new_active_crtc_count > 1)) {
1042 /* update display watermarks based on new power state */
1043 radeon_bandwidth_update(rdev);
1044 /* update displays */
1045 radeon_dpm_display_configuration_changed(rdev);
1046 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1047 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1048 return;
1049 }
1050 }
da321c8a 1051 }
da321c8a
AD		 1052 }
1053
b62d628b 1054force:
033a37df
AD		 1055 if (radeon_dpm == 1) {
1056 printk("switching from power state:\n");
1057 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1058 printk("switching to power state:\n");
1059 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1060 }
b62d628b 1061
da321c8a
AD		 1062 down_write(&rdev->pm.mclk_lock);
1063 mutex_lock(&rdev->ring_lock);
1064
b62d628b
AD		 1065 /* update whether vce is active */
1066 ps->vce_active = rdev->pm.dpm.vce_active;
1067
89c9bc56
AD		 1068 ret = radeon_dpm_pre_set_power_state(rdev);
1069 if (ret)
1070 goto done;
84dd1928 1071
da321c8a
AD		 1072 /* update display watermarks based on new power state */
1073 radeon_bandwidth_update(rdev);
1074 /* update displays */
1075 radeon_dpm_display_configuration_changed(rdev);
1076
1077 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1078 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
3899ca84 1079 rdev->pm.dpm.single_display = single_display;
da321c8a
AD		 1080
1081 /* wait for the rings to drain */
1082 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1083 struct radeon_ring *ring = &rdev->ring[i];
1084 if (ring->ready)
37615527 1085 radeon_fence_wait_empty(rdev, i);
da321c8a
AD		 1086 }
1087
1088 /* program the new power state */
1089 radeon_dpm_set_power_state(rdev);
1090
1091 /* update current power state */
1092 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1093
89c9bc56 1094 radeon_dpm_post_set_power_state(rdev);
84dd1928 1095
1cd8b21a 1096 if (rdev->asic->dpm.force_performance_level) {
14ac88af
AD		 1097 if (rdev->pm.dpm.thermal_active) {
1098 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1cd8b21a
AD		 1099 /* force low perf level for thermal */
1100 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
14ac88af
AD		 1101 /* save the user's level */
1102 rdev->pm.dpm.forced_level = level;
1103 } else {
1104 /* otherwise, user selected level */
1105 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1106 }
60320347
AD		 1107 }
1108
84dd1928 1109done:
da321c8a
AD		 1110 mutex_unlock(&rdev->ring_lock);
1111 up_write(&rdev->pm.mclk_lock);
da321c8a
AD		 1112}
1113
ce3537d5
AD		 1114void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
1115{
1116 enum radeon_pm_state_type dpm_state;
1117
9e9d9762 1118 if (rdev->asic->dpm.powergate_uvd) {
ce3537d5 1119 mutex_lock(&rdev->pm.mutex);
8158eb9e
CK		 1120 /* don't powergate anything if we
1121 have active but pause streams */
1122 enable |= rdev->pm.dpm.sd > 0;
1123 enable |= rdev->pm.dpm.hd > 0;
9e9d9762
AD		 1124 /* enable/disable UVD */
1125 radeon_dpm_powergate_uvd(rdev, !enable);
ce3537d5
AD		 1126 mutex_unlock(&rdev->pm.mutex);
1127 } else {
9e9d9762
AD		 1128 if (enable) {
1129 mutex_lock(&rdev->pm.mutex);
1130 rdev->pm.dpm.uvd_active = true;
0690a229
AD		 1131 /* disable this for now */
1132#if 0
9e9d9762
AD		 1133 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1134 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
1135 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1136 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1137 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1138 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1139 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1140 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
1141 else
0690a229 1142#endif
9e9d9762
AD		 1143 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
1144 rdev->pm.dpm.state = dpm_state;
1145 mutex_unlock(&rdev->pm.mutex);
1146 } else {
1147 mutex_lock(&rdev->pm.mutex);
1148 rdev->pm.dpm.uvd_active = false;
1149 mutex_unlock(&rdev->pm.mutex);
1150 }
ce3537d5 1151
9e9d9762
AD		 1152 radeon_pm_compute_clocks(rdev);
1153 }
ce3537d5
AD		 1154}
1155
03afe6f6
AD		 1156void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1157{
1158 if (enable) {
1159 mutex_lock(&rdev->pm.mutex);
1160 rdev->pm.dpm.vce_active = true;
1161 /* XXX select vce level based on ring/task */
1162 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1163 mutex_unlock(&rdev->pm.mutex);
1164 } else {
1165 mutex_lock(&rdev->pm.mutex);
1166 rdev->pm.dpm.vce_active = false;
1167 mutex_unlock(&rdev->pm.mutex);
1168 }
1169
1170 radeon_pm_compute_clocks(rdev);
1171}
1172
da321c8a 1173static void radeon_pm_suspend_old(struct radeon_device *rdev)
56278a8e 1174{
ce8f5370 1175 mutex_lock(&rdev->pm.mutex);
3f53eb6f 1176 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 1177 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1178 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 1179 }
ce8f5370 1180 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 1181
1182 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 1183}
1184
da321c8a
AD		 1185static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1186{
1187 mutex_lock(&rdev->pm.mutex);
1188 /* disable dpm */
1189 radeon_dpm_disable(rdev);
1190 /* reset the power state */
1191 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1192 rdev->pm.dpm_enabled = false;
1193 mutex_unlock(&rdev->pm.mutex);
1194}
1195
1196void radeon_pm_suspend(struct radeon_device *rdev)
1197{
1198 if (rdev->pm.pm_method == PM_METHOD_DPM)
1199 radeon_pm_suspend_dpm(rdev);
1200 else
1201 radeon_pm_suspend_old(rdev);
1202}
1203
1204static void radeon_pm_resume_old(struct radeon_device *rdev)
d0d6cb81 1205{
ed18a360 1206 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 1207 if ((rdev->family >= CHIP_BARTS) &&
36099186 1208 (rdev->family <= CHIP_CAYMAN) &&
2e3b3b10 1209 rdev->mc_fw) {
ed18a360 1210 if (rdev->pm.default_vddc)
8a83ec5e
AD		 1211 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1212 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 1213 if (rdev->pm.default_vddci)
1214 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1215 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 1216 if (rdev->pm.default_sclk)
1217 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1218 if (rdev->pm.default_mclk)
1219 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1220 }
f8ed8b4c
AD		 1221 /* asic init will reset the default power state */
1222 mutex_lock(&rdev->pm.mutex);
1223 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1224 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 1225 rdev->pm.current_sclk = rdev->pm.default_sclk;
1226 rdev->pm.current_mclk = rdev->pm.default_mclk;
37016951
MD		 1227 if (rdev->pm.power_state) {
1228 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1229 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1230 }
3f53eb6f
RW		 1231 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1232 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1233 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1234 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1235 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 1236 }
f8ed8b4c 1237 mutex_unlock(&rdev->pm.mutex);
ce8f5370 1238 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 1239}
1240
da321c8a
AD		 1241static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1242{
1243 int ret;
1244
1245 /* asic init will reset to the boot state */
1246 mutex_lock(&rdev->pm.mutex);
1247 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1248 radeon_dpm_setup_asic(rdev);
1249 ret = radeon_dpm_enable(rdev);
1250 mutex_unlock(&rdev->pm.mutex);
e14cd2bb
AD		 1251 if (ret)
1252 goto dpm_resume_fail;
e14cd2bb 1253 rdev->pm.dpm_enabled = true;
e14cd2bb
AD		 1254 return;
1255
1256dpm_resume_fail:
1257 DRM_ERROR("radeon: dpm resume failed\n");
1258 if ((rdev->family >= CHIP_BARTS) &&
1259 (rdev->family <= CHIP_CAYMAN) &&
1260 rdev->mc_fw) {
1261 if (rdev->pm.default_vddc)
1262 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1263 SET_VOLTAGE_TYPE_ASIC_VDDC);
1264 if (rdev->pm.default_vddci)
1265 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1266 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1267 if (rdev->pm.default_sclk)
1268 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1269 if (rdev->pm.default_mclk)
1270 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
da321c8a
AD		 1271 }
1272}
1273
1274void radeon_pm_resume(struct radeon_device *rdev)
1275{
1276 if (rdev->pm.pm_method == PM_METHOD_DPM)
1277 radeon_pm_resume_dpm(rdev);
1278 else
1279 radeon_pm_resume_old(rdev);
1280}
1281
1282static int radeon_pm_init_old(struct radeon_device *rdev)
7433874e 1283{
26481fb1 1284 int ret;
0d18abed 1285
f8ed8b4c 1286 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 1287 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1288 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1289 rdev->pm.dynpm_can_upclock = true;
1290 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 1291 rdev->pm.default_sclk = rdev->clock.default_sclk;
1292 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 1293 rdev->pm.current_sclk = rdev->clock.default_sclk;
1294 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 1295 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 1296
56278a8e
AD		 1297 if (rdev->bios) {
1298 if (rdev->is_atom_bios)
1299 radeon_atombios_get_power_modes(rdev);
1300 else
1301 radeon_combios_get_power_modes(rdev);
f712d0c7 1302 radeon_pm_print_states(rdev);
ce8f5370 1303 radeon_pm_init_profile(rdev);
ed18a360 1304 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 1305 if ((rdev->family >= CHIP_BARTS) &&
36099186 1306 (rdev->family <= CHIP_CAYMAN) &&
2e3b3b10 1307 rdev->mc_fw) {
ed18a360 1308 if (rdev->pm.default_vddc)
8a83ec5e
AD		 1309 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1310 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 1311 if (rdev->pm.default_vddci)
1312 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1313 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 1314 if (rdev->pm.default_sclk)
1315 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1316 if (rdev->pm.default_mclk)
1317 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1318 }
56278a8e
AD		 1319 }
1320
21a8122a 1321 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 1322 ret = radeon_hwmon_init(rdev);
1323 if (ret)
1324 return ret;
32c87fca
TH		 1325
1326 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1327
ce8f5370 1328 if (rdev->pm.num_power_states > 1) {
ce8f5370
AD		 1329 if (radeon_debugfs_pm_init(rdev)) {
1330 DRM_ERROR("Failed to register debugfs file for PM!\n");
1331 }
c913e23a 1332
ce8f5370
AD		 1333 DRM_INFO("radeon: power management initialized\n");
1334 }
c913e23a 1335
7433874e
RM		 1336 return 0;
1337}
1338
da321c8a
AD		 1339static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1340{
1341 int i;
1342
1343 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1344 printk("== power state %d ==\n", i);
1345 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1346 }
1347}
1348
1349static int radeon_pm_init_dpm(struct radeon_device *rdev)
1350{
1351 int ret;
1352
1cd8b21a 1353 /* default to balanced state */
edcaa5b1
AD		 1354 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1355 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1cd8b21a 1356 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
da321c8a
AD		 1357 rdev->pm.default_sclk = rdev->clock.default_sclk;
1358 rdev->pm.default_mclk = rdev->clock.default_mclk;
1359 rdev->pm.current_sclk = rdev->clock.default_sclk;
1360 rdev->pm.current_mclk = rdev->clock.default_mclk;
1361 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1362
1363 if (rdev->bios && rdev->is_atom_bios)
1364 radeon_atombios_get_power_modes(rdev);
1365 else
1366 return -EINVAL;
1367
1368 /* set up the internal thermal sensor if applicable */
1369 ret = radeon_hwmon_init(rdev);
1370 if (ret)
1371 return ret;
1372
1373 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1374 mutex_lock(&rdev->pm.mutex);
1375 radeon_dpm_init(rdev);
1376 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
033a37df
AD		 1377 if (radeon_dpm == 1)
1378 radeon_dpm_print_power_states(rdev);
da321c8a
AD		 1379 radeon_dpm_setup_asic(rdev);
1380 ret = radeon_dpm_enable(rdev);
1381 mutex_unlock(&rdev->pm.mutex);
e14cd2bb
AD		 1382 if (ret)
1383 goto dpm_failed;
da321c8a 1384 rdev->pm.dpm_enabled = true;
da321c8a 1385
bb5abf9f
AD		 1386 if (radeon_debugfs_pm_init(rdev)) {
1387 DRM_ERROR("Failed to register debugfs file for dpm!\n");
da321c8a
AD		 1388 }
1389
bb5abf9f
AD		 1390 DRM_INFO("radeon: dpm initialized\n");
1391
da321c8a 1392 return 0;
e14cd2bb
AD		 1393
1394dpm_failed:
1395 rdev->pm.dpm_enabled = false;
1396 if ((rdev->family >= CHIP_BARTS) &&
1397 (rdev->family <= CHIP_CAYMAN) &&
1398 rdev->mc_fw) {
1399 if (rdev->pm.default_vddc)
1400 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1401 SET_VOLTAGE_TYPE_ASIC_VDDC);
1402 if (rdev->pm.default_vddci)
1403 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1404 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1405 if (rdev->pm.default_sclk)
1406 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1407 if (rdev->pm.default_mclk)
1408 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1409 }
1410 DRM_ERROR("radeon: dpm initialization failed\n");
1411 return ret;
da321c8a
AD		 1412}
1413
4369a69e
AD		 1414struct radeon_dpm_quirk {
1415 u32 chip_vendor;
1416 u32 chip_device;
1417 u32 subsys_vendor;
1418 u32 subsys_device;
1419};
1420
1421/* cards with dpm stability problems */
1422static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = {
1423 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */
1424 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 },
1425 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */
1426 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 },
1427 { 0, 0, 0, 0 },
1428};
1429
da321c8a
AD		 1430int radeon_pm_init(struct radeon_device *rdev)
1431{
4369a69e
AD		 1432 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list;
1433 bool disable_dpm = false;
1434
1435 /* Apply dpm quirks */
1436 while (p && p->chip_device != 0) {
1437 if (rdev->pdev->vendor == p->chip_vendor &&
1438 rdev->pdev->device == p->chip_device &&
1439 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1440 rdev->pdev->subsystem_device == p->subsys_device) {
1441 disable_dpm = true;
1442 break;
1443 }
1444 ++p;
1445 }
1446
da321c8a
AD		 1447 /* enable dpm on rv6xx+ */
1448 switch (rdev->family) {
4a6369e9
AD		 1449 case CHIP_RV610:
1450 case CHIP_RV630:
1451 case CHIP_RV620:
1452 case CHIP_RV635:
1453 case CHIP_RV670:
9d67006e
AD		 1454 case CHIP_RS780:
1455 case CHIP_RS880:
76e6dcec 1456 case CHIP_RV770:
8a53fa23 1457 /* DPM requires the RLC, RV770+ dGPU requires SMC */
761bfb99
AD		 1458 if (!rdev->rlc_fw)
1459 rdev->pm.pm_method = PM_METHOD_PROFILE;
8a53fa23
AD		 1460 else if ((rdev->family >= CHIP_RV770) &&
1461 (!(rdev->flags & RADEON_IS_IGP)) &&
1462 (!rdev->smc_fw))
1463 rdev->pm.pm_method = PM_METHOD_PROFILE;
761bfb99 1464 else if (radeon_dpm == 1)
9d67006e
AD		 1465 rdev->pm.pm_method = PM_METHOD_DPM;
1466 else
1467 rdev->pm.pm_method = PM_METHOD_PROFILE;
1468 break;
ab70b1dd
AD		 1469 case CHIP_RV730:
1470 case CHIP_RV710:
1471 case CHIP_RV740:
59f7a2f2
AD		 1472 case CHIP_CEDAR:
1473 case CHIP_REDWOOD:
1474 case CHIP_JUNIPER:
1475 case CHIP_CYPRESS:
1476 case CHIP_HEMLOCK:
5a16f761
AD		 1477 case CHIP_PALM:
1478 case CHIP_SUMO:
1479 case CHIP_SUMO2:
c08abf11
AD		 1480 case CHIP_BARTS:
1481 case CHIP_TURKS:
1482 case CHIP_CAICOS:
8f500af4 1483 case CHIP_CAYMAN:
3a118989 1484 case CHIP_ARUBA:
68bc7785
AD		 1485 case CHIP_TAHITI:
1486 case CHIP_PITCAIRN:
1487 case CHIP_VERDE:
1488 case CHIP_OLAND:
1489 case CHIP_HAINAN:
4f22dde3 1490 case CHIP_BONAIRE:
e308b1d3
AD		 1491 case CHIP_KABINI:
1492 case CHIP_KAVERI:
4f22dde3 1493 case CHIP_HAWAII:
7d032a4b 1494 case CHIP_MULLINS:
5a16f761
AD		 1495 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1496 if (!rdev->rlc_fw)
1497 rdev->pm.pm_method = PM_METHOD_PROFILE;
1498 else if ((rdev->family >= CHIP_RV770) &&
1499 (!(rdev->flags & RADEON_IS_IGP)) &&
1500 (!rdev->smc_fw))
1501 rdev->pm.pm_method = PM_METHOD_PROFILE;
4369a69e
AD		 1502 else if (disable_dpm && (radeon_dpm == -1))
1503 rdev->pm.pm_method = PM_METHOD_PROFILE;
5a16f761
AD		 1504 else if (radeon_dpm == 0)
1505 rdev->pm.pm_method = PM_METHOD_PROFILE;
1506 else
1507 rdev->pm.pm_method = PM_METHOD_DPM;
1508 break;
da321c8a
AD		 1509 default:
1510 /* default to profile method */
1511 rdev->pm.pm_method = PM_METHOD_PROFILE;
1512 break;
1513 }
1514
1515 if (rdev->pm.pm_method == PM_METHOD_DPM)
1516 return radeon_pm_init_dpm(rdev);
1517 else
1518 return radeon_pm_init_old(rdev);
1519}
1520
914a8987
AD		 1521int radeon_pm_late_init(struct radeon_device *rdev)
1522{
1523 int ret = 0;
1524
1525 if (rdev->pm.pm_method == PM_METHOD_DPM) {
51a4726b
AD		 1526 if (rdev->pm.dpm_enabled) {
1527 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1528 if (ret)
1529 DRM_ERROR("failed to create device file for dpm state\n");
1530 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1531 if (ret)
1532 DRM_ERROR("failed to create device file for dpm state\n");
1533 /* XXX: these are noops for dpm but are here for backwards compat */
1534 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1535 if (ret)
1536 DRM_ERROR("failed to create device file for power profile\n");
1537 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1538 if (ret)
1539 DRM_ERROR("failed to create device file for power method\n");
1540
1541 mutex_lock(&rdev->pm.mutex);
1542 ret = radeon_dpm_late_enable(rdev);
1543 mutex_unlock(&rdev->pm.mutex);
1544 if (ret) {
1545 rdev->pm.dpm_enabled = false;
1546 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1547 } else {
1548 /* set the dpm state for PX since there won't be
1549 * a modeset to call this.
1550 */
1551 radeon_pm_compute_clocks(rdev);
1552 }
1553 }
1554 } else {
1555 if (rdev->pm.num_power_states > 1) {
1556 /* where's the best place to put these? */
1557 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1558 if (ret)
1559 DRM_ERROR("failed to create device file for power profile\n");
1560 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1561 if (ret)
1562 DRM_ERROR("failed to create device file for power method\n");
1563 }
914a8987
AD		 1564 }
1565 return ret;
1566}
1567
da321c8a 1568static void radeon_pm_fini_old(struct radeon_device *rdev)
29fb52ca 1569{
ce8f5370 1570 if (rdev->pm.num_power_states > 1) {
a424816f 1571 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 1572 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1573 rdev->pm.profile = PM_PROFILE_DEFAULT;
1574 radeon_pm_update_profile(rdev);
1575 radeon_pm_set_clocks(rdev);
1576 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 1577 /* reset default clocks */
1578 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1579 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1580 radeon_pm_set_clocks(rdev);
1581 }
a424816f 1582 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 1583
1584 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 1585
ce8f5370
AD		 1586 device_remove_file(rdev->dev, &dev_attr_power_profile);
1587 device_remove_file(rdev->dev, &dev_attr_power_method);
ce8f5370 1588 }
a424816f 1589
cb3e4e7c 1590 radeon_hwmon_fini(rdev);
9c244878 1591 kfree(rdev->pm.power_state);
29fb52ca
AD		 1592}
1593
da321c8a
AD		 1594static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1595{
1596 if (rdev->pm.num_power_states > 1) {
1597 mutex_lock(&rdev->pm.mutex);
1598 radeon_dpm_disable(rdev);
1599 mutex_unlock(&rdev->pm.mutex);
1600
1601 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
70d01a5e 1602 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
da321c8a
AD		 1603 /* XXX backwards compat */
1604 device_remove_file(rdev->dev, &dev_attr_power_profile);
1605 device_remove_file(rdev->dev, &dev_attr_power_method);
1606 }
1607 radeon_dpm_fini(rdev);
1608
cb3e4e7c 1609 radeon_hwmon_fini(rdev);
9c244878 1610 kfree(rdev->pm.power_state);
da321c8a
AD		 1611}
1612
1613void radeon_pm_fini(struct radeon_device *rdev)
1614{
1615 if (rdev->pm.pm_method == PM_METHOD_DPM)
1616 radeon_pm_fini_dpm(rdev);
1617 else
1618 radeon_pm_fini_old(rdev);
1619}
1620
1621static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
c913e23a
RM		 1622{
1623 struct drm_device *ddev = rdev->ddev;
a48b9b4e 1624 struct drm_crtc *crtc;
c913e23a 1625 struct radeon_crtc *radeon_crtc;
c913e23a 1626
ce8f5370
AD		 1627 if (rdev->pm.num_power_states < 2)
1628 return;
1629
c913e23a
RM		 1630 mutex_lock(&rdev->pm.mutex);
1631
1632 rdev->pm.active_crtcs = 0;
a48b9b4e 1633 rdev->pm.active_crtc_count = 0;
3ed9a335
AD		 1634 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1635 list_for_each_entry(crtc,
1636 &ddev->mode_config.crtc_list, head) {
1637 radeon_crtc = to_radeon_crtc(crtc);
1638 if (radeon_crtc->enabled) {
1639 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1640 rdev->pm.active_crtc_count++;
1641 }
c913e23a
RM		 1642 }
1643 }
1644
ce8f5370
AD		 1645 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1646 radeon_pm_update_profile(rdev);
1647 radeon_pm_set_clocks(rdev);
1648 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1649 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1650 if (rdev->pm.active_crtc_count > 1) {
1651 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1652 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1653
1654 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1655 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1656 radeon_pm_get_dynpm_state(rdev);
1657 radeon_pm_set_clocks(rdev);
1658
d9fdaafb 1659 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 1660 }
1661 } else if (rdev->pm.active_crtc_count == 1) {
1662 /* TODO: Increase clocks if needed for current mode */
1663
1664 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1665 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1666 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1667 radeon_pm_get_dynpm_state(rdev);
1668 radeon_pm_set_clocks(rdev);
1669
32c87fca
TH		 1670 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1671 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 1672 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1673 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1674 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1675 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 1676 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 1677 }
1678 } else { /* count == 0 */
1679 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1680 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1681
1682 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1683 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1684 radeon_pm_get_dynpm_state(rdev);
1685 radeon_pm_set_clocks(rdev);
1686 }
1687 }
c913e23a 1688 }
c913e23a 1689 }
73a6d3fc
RM		 1690
1691 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 1692}
1693
da321c8a
AD		 1694static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1695{
1696 struct drm_device *ddev = rdev->ddev;
1697 struct drm_crtc *crtc;
1698 struct radeon_crtc *radeon_crtc;
1699
6c7bccea
AD		 1700 if (!rdev->pm.dpm_enabled)
1701 return;
1702
da321c8a
AD		 1703 mutex_lock(&rdev->pm.mutex);
1704
5ca302f7 1705 /* update active crtc counts */
da321c8a
AD		 1706 rdev->pm.dpm.new_active_crtcs = 0;
1707 rdev->pm.dpm.new_active_crtc_count = 0;
3ed9a335
AD		 1708 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1709 list_for_each_entry(crtc,
1710 &ddev->mode_config.crtc_list, head) {
1711 radeon_crtc = to_radeon_crtc(crtc);
1712 if (crtc->enabled) {
1713 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1714 rdev->pm.dpm.new_active_crtc_count++;
1715 }
da321c8a
AD		 1716 }
1717 }
1718
5ca302f7
AD		 1719 /* update battery/ac status */
1720 if (power_supply_is_system_supplied() > 0)
1721 rdev->pm.dpm.ac_power = true;
1722 else
1723 rdev->pm.dpm.ac_power = false;
1724
da321c8a
AD		 1725 radeon_dpm_change_power_state_locked(rdev);
1726
1727 mutex_unlock(&rdev->pm.mutex);
8a227555 1728
da321c8a
AD		 1729}
1730
1731void radeon_pm_compute_clocks(struct radeon_device *rdev)
1732{
1733 if (rdev->pm.pm_method == PM_METHOD_DPM)
1734 radeon_pm_compute_clocks_dpm(rdev);
1735 else
1736 radeon_pm_compute_clocks_old(rdev);
1737}
1738
ce8f5370 1739static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 1740{
75fa0b08 1741 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 1742 bool in_vbl = true;
1743
75fa0b08
MK		 1744 /* Iterate over all active crtc's. All crtc's must be in vblank,
1745 * otherwise return in_vbl == false.
1746 */
1747 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1748 if (rdev->pm.active_crtcs & (1 << crtc)) {
abca9e45 1749 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
f5a80209 1750 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
3d3cbd84 1751 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK))
f735261b
DA		 1752 in_vbl = false;
1753 }
1754 }
f81f2024
MG		 1755
1756 return in_vbl;
1757}
1758
ce8f5370 1759static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 1760{
1761 u32 stat_crtc = 0;
1762 bool in_vbl = radeon_pm_in_vbl(rdev);
1763
f735261b 1764 if (in_vbl == false)
d9fdaafb 1765 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 1766 finish ? "exit" : "entry");
f735261b
DA		 1767 return in_vbl;
1768}
c913e23a 1769
ce8f5370 1770static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 1771{
1772 struct radeon_device *rdev;
d9932a32 1773 int resched;
c913e23a 1774 rdev = container_of(work, struct radeon_device,
ce8f5370 1775 pm.dynpm_idle_work.work);
c913e23a 1776
d9932a32 1777 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 1778 mutex_lock(&rdev->pm.mutex);
ce8f5370 1779 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 1780 int not_processed = 0;
7465280c
AD		 1781 int i;
1782
7465280c 1783 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0ec0612a
AD		 1784 struct radeon_ring *ring = &rdev->ring[i];
1785
1786 if (ring->ready) {
1787 not_processed += radeon_fence_count_emitted(rdev, i);
1788 if (not_processed >= 3)
1789 break;
1790 }
c913e23a 1791 }
c913e23a
RM		 1792
1793 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 1794 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1795 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1796 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1797 rdev->pm.dynpm_can_upclock) {
1798 rdev->pm.dynpm_planned_action =
1799 DYNPM_ACTION_UPCLOCK;
1800 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1801 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1802 }
1803 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 1804 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1805 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1806 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1807 rdev->pm.dynpm_can_downclock) {
1808 rdev->pm.dynpm_planned_action =
1809 DYNPM_ACTION_DOWNCLOCK;
1810 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1811 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1812 }
1813 }
1814
d7311171
AD		 1815 /* Note, radeon_pm_set_clocks is called with static_switch set
1816 * to false since we want to wait for vbl to avoid flicker.
1817 */
ce8f5370
AD		 1818 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1819 jiffies > rdev->pm.dynpm_action_timeout) {
1820 radeon_pm_get_dynpm_state(rdev);
1821 radeon_pm_set_clocks(rdev);
c913e23a 1822 }
3f53eb6f 1823
32c87fca
TH		 1824 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1825 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 1826 }
1827 mutex_unlock(&rdev->pm.mutex);
d9932a32 1828 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 1829}
1830
7433874e
RM		 1831/*
1832 * Debugfs info
1833 */
1834#if defined(CONFIG_DEBUG_FS)
1835
1836static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1837{
1838 struct drm_info_node *node = (struct drm_info_node *) m->private;
1839 struct drm_device *dev = node->minor->dev;
1840 struct radeon_device *rdev = dev->dev_private;
4f2f2039 1841 struct drm_device *ddev = rdev->ddev;
7433874e 1842
4f2f2039
AD		 1843 if ((rdev->flags & RADEON_IS_PX) &&
1844 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1845 seq_printf(m, "PX asic powered off\n");
1846 } else if (rdev->pm.dpm_enabled) {
1316b792
AD		 1847 mutex_lock(&rdev->pm.mutex);
1848 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1849 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1850 else
71375929 1851 seq_printf(m, "Debugfs support not implemented for this asic\n");
1316b792
AD		 1852 mutex_unlock(&rdev->pm.mutex);
1853 } else {
1854 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1855 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1856 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1857 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1858 else
1859 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1860 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1861 if (rdev->asic->pm.get_memory_clock)
1862 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1863 if (rdev->pm.current_vddc)
1864 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1865 if (rdev->asic->pm.get_pcie_lanes)
1866 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1867 }
7433874e
RM		 1868
1869 return 0;
1870}
1871
1872static struct drm_info_list radeon_pm_info_list[] = {
1873 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1874};
1875#endif
1876
c913e23a 1877static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 1878{
1879#if defined(CONFIG_DEBUG_FS)
1880 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1881#else
1882 return 0;
1883#endif
1884}
Linux 6.x block layer and io_uring tree(s)