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drm/radeon/kms: add support for router objects
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e
RM		 22 */
23#include "drmP.h"
24#include "radeon.h"
f735261b 25#include "avivod.h"
ce8f5370
AD		 26#ifdef CONFIG_ACPI
27#include <linux/acpi.h>
28#endif
29#include <linux/power_supply.h>
21a8122a
AD		 30#include <linux/hwmon.h>
31#include <linux/hwmon-sysfs.h>
7433874e 32
c913e23a
RM		 33#define RADEON_IDLE_LOOP_MS 100
34#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 35#define RADEON_WAIT_VBLANK_TIMEOUT 200
2031f77c 36#define RADEON_WAIT_IDLE_TIMEOUT 200
c913e23a 37
f712d0c7
RM		 38static const char *radeon_pm_state_type_name[5] = {
39 "Default",
40 "Powersave",
41 "Battery",
42 "Balanced",
43 "Performance",
44};
45
ce8f5370 46static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 47static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 48static bool radeon_pm_in_vbl(struct radeon_device *rdev);
49static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
50static void radeon_pm_update_profile(struct radeon_device *rdev);
51static void radeon_pm_set_clocks(struct radeon_device *rdev);
52
53#define ACPI_AC_CLASS "ac_adapter"
54
55#ifdef CONFIG_ACPI
56static int radeon_acpi_event(struct notifier_block *nb,
57 unsigned long val,
58 void *data)
59{
60 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
61 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
62
63 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
64 if (power_supply_is_system_supplied() > 0)
d9fdaafb 65 DRM_DEBUG_DRIVER("pm: AC\n");
ce8f5370 66 else
d9fdaafb 67 DRM_DEBUG_DRIVER("pm: DC\n");
ce8f5370
AD		 68
69 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
70 if (rdev->pm.profile == PM_PROFILE_AUTO) {
71 mutex_lock(&rdev->pm.mutex);
72 radeon_pm_update_profile(rdev);
73 radeon_pm_set_clocks(rdev);
74 mutex_unlock(&rdev->pm.mutex);
75 }
76 }
77 }
78
79 return NOTIFY_OK;
80}
81#endif
82
83static void radeon_pm_update_profile(struct radeon_device *rdev)
84{
85 switch (rdev->pm.profile) {
86 case PM_PROFILE_DEFAULT:
87 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
88 break;
89 case PM_PROFILE_AUTO:
90 if (power_supply_is_system_supplied() > 0) {
91 if (rdev->pm.active_crtc_count > 1)
92 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
93 else
94 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
95 } else {
96 if (rdev->pm.active_crtc_count > 1)
c9e75b21 97 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 98 else
c9e75b21 99 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 100 }
101 break;
102 case PM_PROFILE_LOW:
103 if (rdev->pm.active_crtc_count > 1)
104 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
105 else
106 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
107 break;
c9e75b21
AD		 108 case PM_PROFILE_MID:
109 if (rdev->pm.active_crtc_count > 1)
110 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
111 else
112 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
113 break;
ce8f5370
AD		 114 case PM_PROFILE_HIGH:
115 if (rdev->pm.active_crtc_count > 1)
116 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
117 else
118 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
119 break;
120 }
121
122 if (rdev->pm.active_crtc_count == 0) {
123 rdev->pm.requested_power_state_index =
124 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
125 rdev->pm.requested_clock_mode_index =
126 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
127 } else {
128 rdev->pm.requested_power_state_index =
129 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
130 rdev->pm.requested_clock_mode_index =
131 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
132 }
133}
c913e23a 134
5876dd24
MG		 135static void radeon_unmap_vram_bos(struct radeon_device *rdev)
136{
137 struct radeon_bo *bo, *n;
138
139 if (list_empty(&rdev->gem.objects))
140 return;
141
142 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
143 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
144 ttm_bo_unmap_virtual(&bo->tbo);
145 }
5876dd24
MG		 146}
147
ce8f5370 148static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 149{
ce8f5370
AD		 150 if (rdev->pm.active_crtcs) {
151 rdev->pm.vblank_sync = false;
152 wait_event_timeout(
153 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
154 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
155 }
156}
157
158static void radeon_set_power_state(struct radeon_device *rdev)
159{
160 u32 sclk, mclk;
92645879 161 bool misc_after = false;
ce8f5370
AD		 162
163 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
164 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
165 return;
166
167 if (radeon_gui_idle(rdev)) {
168 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
169 clock_info[rdev->pm.requested_clock_mode_index].sclk;
170 if (sclk > rdev->clock.default_sclk)
171 sclk = rdev->clock.default_sclk;
172
173 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
174 clock_info[rdev->pm.requested_clock_mode_index].mclk;
175 if (mclk > rdev->clock.default_mclk)
176 mclk = rdev->clock.default_mclk;
177
92645879
AD		 178 /* upvolt before raising clocks, downvolt after lowering clocks */
179 if (sclk < rdev->pm.current_sclk)
180 misc_after = true;
ce8f5370 181
92645879 182 radeon_sync_with_vblank(rdev);
ce8f5370 183
92645879 184 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 185 if (!radeon_pm_in_vbl(rdev))
186 return;
92645879 187 }
ce8f5370 188
92645879 189 radeon_pm_prepare(rdev);
ce8f5370 190
92645879
AD		 191 if (!misc_after)
192 /* voltage, pcie lanes, etc.*/
193 radeon_pm_misc(rdev);
194
195 /* set engine clock */
196 if (sclk != rdev->pm.current_sclk) {
197 radeon_pm_debug_check_in_vbl(rdev, false);
198 radeon_set_engine_clock(rdev, sclk);
199 radeon_pm_debug_check_in_vbl(rdev, true);
200 rdev->pm.current_sclk = sclk;
d9fdaafb 201 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 202 }
203
204 /* set memory clock */
205 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
206 radeon_pm_debug_check_in_vbl(rdev, false);
207 radeon_set_memory_clock(rdev, mclk);
208 radeon_pm_debug_check_in_vbl(rdev, true);
209 rdev->pm.current_mclk = mclk;
d9fdaafb 210 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 211 }
2aba631c 212
92645879
AD		 213 if (misc_after)
214 /* voltage, pcie lanes, etc.*/
215 radeon_pm_misc(rdev);
216
217 radeon_pm_finish(rdev);
218
ce8f5370
AD		 219 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
220 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
221 } else
d9fdaafb 222 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 223}
224
225static void radeon_pm_set_clocks(struct radeon_device *rdev)
226{
227 int i;
c37d230a 228
612e06ce
MG		 229 mutex_lock(&rdev->ddev->struct_mutex);
230 mutex_lock(&rdev->vram_mutex);
a424816f 231 mutex_lock(&rdev->cp.mutex);
4f3218cb
AD		 232
233 /* gui idle int has issues on older chips it seems */
234 if (rdev->family >= CHIP_R600) {
ce8f5370
AD		 235 if (rdev->irq.installed) {
236 /* wait for GPU idle */
237 rdev->pm.gui_idle = false;
238 rdev->irq.gui_idle = true;
239 radeon_irq_set(rdev);
240 wait_event_interruptible_timeout(
241 rdev->irq.idle_queue, rdev->pm.gui_idle,
242 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
243 rdev->irq.gui_idle = false;
244 radeon_irq_set(rdev);
245 }
01434b4b 246 } else {
ce8f5370
AD		 247 if (rdev->cp.ready) {
248 struct radeon_fence *fence;
249 radeon_ring_alloc(rdev, 64);
250 radeon_fence_create(rdev, &fence);
251 radeon_fence_emit(rdev, fence);
252 radeon_ring_commit(rdev);
253 radeon_fence_wait(fence, false);
254 radeon_fence_unref(&fence);
255 }
4f3218cb 256 }
5876dd24
MG		 257 radeon_unmap_vram_bos(rdev);
258
ce8f5370 259 if (rdev->irq.installed) {
2aba631c
MG		 260 for (i = 0; i < rdev->num_crtc; i++) {
261 if (rdev->pm.active_crtcs & (1 << i)) {
262 rdev->pm.req_vblank |= (1 << i);
263 drm_vblank_get(rdev->ddev, i);
264 }
265 }
266 }
539d2418 267
ce8f5370 268 radeon_set_power_state(rdev);
2aba631c 269
ce8f5370 270 if (rdev->irq.installed) {
2aba631c
MG		 271 for (i = 0; i < rdev->num_crtc; i++) {
272 if (rdev->pm.req_vblank & (1 << i)) {
273 rdev->pm.req_vblank &= ~(1 << i);
274 drm_vblank_put(rdev->ddev, i);
275 }
276 }
277 }
5876dd24 278
a424816f
AD		 279 /* update display watermarks based on new power state */
280 radeon_update_bandwidth_info(rdev);
281 if (rdev->pm.active_crtc_count)
282 radeon_bandwidth_update(rdev);
283
ce8f5370 284 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 285
a424816f 286 mutex_unlock(&rdev->cp.mutex);
612e06ce
MG		 287 mutex_unlock(&rdev->vram_mutex);
288 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 289}
290
f712d0c7
RM		 291static void radeon_pm_print_states(struct radeon_device *rdev)
292{
293 int i, j;
294 struct radeon_power_state *power_state;
295 struct radeon_pm_clock_info *clock_info;
296
d9fdaafb 297 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 298 for (i = 0; i < rdev->pm.num_power_states; i++) {
299 power_state = &rdev->pm.power_state[i];
d9fdaafb 300 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 301 radeon_pm_state_type_name[power_state->type]);
302 if (i == rdev->pm.default_power_state_index)
d9fdaafb 303 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 304 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 305 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 306 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 307 DRM_DEBUG_DRIVER("\tSingle display only\n");
308 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 309 for (j = 0; j < power_state->num_clock_modes; j++) {
310 clock_info = &(power_state->clock_info[j]);
311 if (rdev->flags & RADEON_IS_IGP)
d9fdaafb 312 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
f712d0c7
RM		 313 j,
314 clock_info->sclk * 10,
315 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
316 else
d9fdaafb 317 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
f712d0c7
RM		 318 j,
319 clock_info->sclk * 10,
320 clock_info->mclk * 10,
321 clock_info->voltage.voltage,
322 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
323 }
324 }
325}
326
ce8f5370
AD		 327static ssize_t radeon_get_pm_profile(struct device *dev,
328 struct device_attribute *attr,
329 char *buf)
a424816f
AD		 330{
331 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
332 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 333 int cp = rdev->pm.profile;
a424816f 334
ce8f5370
AD		 335 return snprintf(buf, PAGE_SIZE, "%s\n",
336 (cp == PM_PROFILE_AUTO) ? "auto" :
337 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 338 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 339 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 340}
341
ce8f5370
AD		 342static ssize_t radeon_set_pm_profile(struct device *dev,
343 struct device_attribute *attr,
344 const char *buf,
345 size_t count)
a424816f
AD		 346{
347 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
348 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 349
350 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 351 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
352 if (strncmp("default", buf, strlen("default")) == 0)
353 rdev->pm.profile = PM_PROFILE_DEFAULT;
354 else if (strncmp("auto", buf, strlen("auto")) == 0)
355 rdev->pm.profile = PM_PROFILE_AUTO;
356 else if (strncmp("low", buf, strlen("low")) == 0)
357 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 358 else if (strncmp("mid", buf, strlen("mid")) == 0)
359 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 360 else if (strncmp("high", buf, strlen("high")) == 0)
361 rdev->pm.profile = PM_PROFILE_HIGH;
362 else {
363 DRM_ERROR("invalid power profile!\n");
364 goto fail;
a424816f 365 }
ce8f5370
AD		 366 radeon_pm_update_profile(rdev);
367 radeon_pm_set_clocks(rdev);
368 }
369fail:
a424816f
AD		 370 mutex_unlock(&rdev->pm.mutex);
371
372 return count;
373}
374
ce8f5370
AD		 375static ssize_t radeon_get_pm_method(struct device *dev,
376 struct device_attribute *attr,
377 char *buf)
a424816f
AD		 378{
379 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
380 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 381 int pm = rdev->pm.pm_method;
a424816f
AD		 382
383 return snprintf(buf, PAGE_SIZE, "%s\n",
ce8f5370 384 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
a424816f
AD		 385}
386
ce8f5370
AD		 387static ssize_t radeon_set_pm_method(struct device *dev,
388 struct device_attribute *attr,
389 const char *buf,
390 size_t count)
a424816f
AD		 391{
392 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
393 struct radeon_device *rdev = ddev->dev_private;
a424816f 394
ce8f5370
AD		 395
396 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 397 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 398 rdev->pm.pm_method = PM_METHOD_DYNPM;
399 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
400 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 401 mutex_unlock(&rdev->pm.mutex);
ce8f5370 402 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
3f53eb6f
RW		 403 bool flush_wq = false;
404
ce8f5370 405 mutex_lock(&rdev->pm.mutex);
3f53eb6f
RW		 406 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
407 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
408 flush_wq = true;
409 }
ce8f5370
AD		 410 /* disable dynpm */
411 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
412 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 413 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 414 mutex_unlock(&rdev->pm.mutex);
3f53eb6f
RW		 415 if (flush_wq)
416 flush_workqueue(rdev->wq);
ce8f5370
AD		 417 } else {
418 DRM_ERROR("invalid power method!\n");
419 goto fail;
420 }
421 radeon_pm_compute_clocks(rdev);
422fail:
a424816f
AD		 423 return count;
424}
425
ce8f5370
AD		 426static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
427static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
a424816f 428
21a8122a
AD		 429static ssize_t radeon_hwmon_show_temp(struct device *dev,
430 struct device_attribute *attr,
431 char *buf)
432{
433 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
434 struct radeon_device *rdev = ddev->dev_private;
435 u32 temp;
436
437 switch (rdev->pm.int_thermal_type) {
438 case THERMAL_TYPE_RV6XX:
439 temp = rv6xx_get_temp(rdev);
440 break;
441 case THERMAL_TYPE_RV770:
442 temp = rv770_get_temp(rdev);
443 break;
444 case THERMAL_TYPE_EVERGREEN:
445 temp = evergreen_get_temp(rdev);
446 break;
447 default:
448 temp = 0;
449 break;
450 }
451
452 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
453}
454
455static ssize_t radeon_hwmon_show_name(struct device *dev,
456 struct device_attribute *attr,
457 char *buf)
458{
459 return sprintf(buf, "radeon\n");
460}
461
462static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
463static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
464
465static struct attribute *hwmon_attributes[] = {
466 &sensor_dev_attr_temp1_input.dev_attr.attr,
467 &sensor_dev_attr_name.dev_attr.attr,
468 NULL
469};
470
471static const struct attribute_group hwmon_attrgroup = {
472 .attrs = hwmon_attributes,
473};
474
475static void radeon_hwmon_init(struct radeon_device *rdev)
476{
477 int err;
478
479 rdev->pm.int_hwmon_dev = NULL;
480
481 switch (rdev->pm.int_thermal_type) {
482 case THERMAL_TYPE_RV6XX:
483 case THERMAL_TYPE_RV770:
484 case THERMAL_TYPE_EVERGREEN:
485 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
486 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
487 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
488 &hwmon_attrgroup);
489 if (err)
490 DRM_ERROR("Unable to create hwmon sysfs file: %d\n", err);
491 break;
492 default:
493 break;
494 }
495}
496
497static void radeon_hwmon_fini(struct radeon_device *rdev)
498{
499 if (rdev->pm.int_hwmon_dev) {
500 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
501 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
502 }
503}
504
ce8f5370 505void radeon_pm_suspend(struct radeon_device *rdev)
56278a8e 506{
3f53eb6f
RW		 507 bool flush_wq = false;
508
ce8f5370 509 mutex_lock(&rdev->pm.mutex);
3f53eb6f
RW		 510 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
511 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
512 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
513 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
514 flush_wq = true;
515 }
ce8f5370 516 mutex_unlock(&rdev->pm.mutex);
3f53eb6f
RW		 517 if (flush_wq)
518 flush_workqueue(rdev->wq);
56278a8e
AD		 519}
520
ce8f5370 521void radeon_pm_resume(struct radeon_device *rdev)
d0d6cb81 522{
f8ed8b4c
AD		 523 /* asic init will reset the default power state */
524 mutex_lock(&rdev->pm.mutex);
525 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
526 rdev->pm.current_clock_mode_index = 0;
527 rdev->pm.current_sclk = rdev->clock.default_sclk;
528 rdev->pm.current_mclk = rdev->clock.default_mclk;
4d60173f 529 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
3f53eb6f
RW		 530 if (rdev->pm.pm_method == PM_METHOD_DYNPM
531 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
532 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
533 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
534 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
535 }
f8ed8b4c 536 mutex_unlock(&rdev->pm.mutex);
ce8f5370 537 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 538}
539
7433874e
RM		 540int radeon_pm_init(struct radeon_device *rdev)
541{
26481fb1 542 int ret;
ce8f5370
AD		 543 /* default to profile method */
544 rdev->pm.pm_method = PM_METHOD_PROFILE;
f8ed8b4c 545 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 546 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
547 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
548 rdev->pm.dynpm_can_upclock = true;
549 rdev->pm.dynpm_can_downclock = true;
f8ed8b4c
AD		 550 rdev->pm.current_sclk = rdev->clock.default_sclk;
551 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 552 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 553
56278a8e
AD		 554 if (rdev->bios) {
555 if (rdev->is_atom_bios)
556 radeon_atombios_get_power_modes(rdev);
557 else
558 radeon_combios_get_power_modes(rdev);
f712d0c7 559 radeon_pm_print_states(rdev);
ce8f5370 560 radeon_pm_init_profile(rdev);
56278a8e
AD		 561 }
562
21a8122a
AD		 563 /* set up the internal thermal sensor if applicable */
564 radeon_hwmon_init(rdev);
ce8f5370 565 if (rdev->pm.num_power_states > 1) {
ce8f5370 566 /* where's the best place to put these? */
26481fb1
DA		 567 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
568 if (ret)
569 DRM_ERROR("failed to create device file for power profile\n");
570 ret = device_create_file(rdev->dev, &dev_attr_power_method);
571 if (ret)
572 DRM_ERROR("failed to create device file for power method\n");
a424816f 573
ce8f5370
AD		 574#ifdef CONFIG_ACPI
575 rdev->acpi_nb.notifier_call = radeon_acpi_event;
576 register_acpi_notifier(&rdev->acpi_nb);
577#endif
578 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
c913e23a 579
ce8f5370
AD		 580 if (radeon_debugfs_pm_init(rdev)) {
581 DRM_ERROR("Failed to register debugfs file for PM!\n");
582 }
c913e23a 583
ce8f5370
AD		 584 DRM_INFO("radeon: power management initialized\n");
585 }
c913e23a 586
7433874e
RM		 587 return 0;
588}
589
29fb52ca
AD		 590void radeon_pm_fini(struct radeon_device *rdev)
591{
ce8f5370 592 if (rdev->pm.num_power_states > 1) {
3f53eb6f
RW		 593 bool flush_wq = false;
594
a424816f 595 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 596 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
597 rdev->pm.profile = PM_PROFILE_DEFAULT;
598 radeon_pm_update_profile(rdev);
599 radeon_pm_set_clocks(rdev);
600 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
601 /* cancel work */
3f53eb6f
RW		 602 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
603 flush_wq = true;
ce8f5370
AD		 604 /* reset default clocks */
605 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
606 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
607 radeon_pm_set_clocks(rdev);
608 }
a424816f 609 mutex_unlock(&rdev->pm.mutex);
3f53eb6f
RW		 610 if (flush_wq)
611 flush_workqueue(rdev->wq);
58e21dff 612
ce8f5370
AD		 613 device_remove_file(rdev->dev, &dev_attr_power_profile);
614 device_remove_file(rdev->dev, &dev_attr_power_method);
615#ifdef CONFIG_ACPI
616 unregister_acpi_notifier(&rdev->acpi_nb);
617#endif
618 }
a424816f 619
21a8122a 620 radeon_hwmon_fini(rdev);
29fb52ca
AD		 621 if (rdev->pm.i2c_bus)
622 radeon_i2c_destroy(rdev->pm.i2c_bus);
623}
624
c913e23a
RM		 625void radeon_pm_compute_clocks(struct radeon_device *rdev)
626{
627 struct drm_device *ddev = rdev->ddev;
a48b9b4e 628 struct drm_crtc *crtc;
c913e23a 629 struct radeon_crtc *radeon_crtc;
c913e23a 630
ce8f5370
AD		 631 if (rdev->pm.num_power_states < 2)
632 return;
633
c913e23a
RM		 634 mutex_lock(&rdev->pm.mutex);
635
636 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 637 rdev->pm.active_crtc_count = 0;
638 list_for_each_entry(crtc,
639 &ddev->mode_config.crtc_list, head) {
640 radeon_crtc = to_radeon_crtc(crtc);
641 if (radeon_crtc->enabled) {
c913e23a 642 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 643 rdev->pm.active_crtc_count++;
c913e23a
RM		 644 }
645 }
646
ce8f5370
AD		 647 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
648 radeon_pm_update_profile(rdev);
649 radeon_pm_set_clocks(rdev);
650 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
651 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
652 if (rdev->pm.active_crtc_count > 1) {
653 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
654 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
655
656 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
657 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
658 radeon_pm_get_dynpm_state(rdev);
659 radeon_pm_set_clocks(rdev);
660
d9fdaafb 661 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 662 }
663 } else if (rdev->pm.active_crtc_count == 1) {
664 /* TODO: Increase clocks if needed for current mode */
665
666 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
667 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
668 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
669 radeon_pm_get_dynpm_state(rdev);
670 radeon_pm_set_clocks(rdev);
671
672 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
673 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
674 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
675 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
676 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
677 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 678 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 679 }
680 } else { /* count == 0 */
681 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
682 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
683
684 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
685 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
686 radeon_pm_get_dynpm_state(rdev);
687 radeon_pm_set_clocks(rdev);
688 }
689 }
c913e23a 690 }
c913e23a 691 }
73a6d3fc
RM		 692
693 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 694}
695
ce8f5370 696static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 697{
539d2418 698 u32 stat_crtc = 0, vbl = 0, position = 0;
f735261b
DA		 699 bool in_vbl = true;
700
bae6b562
AD		 701 if (ASIC_IS_DCE4(rdev)) {
702 if (rdev->pm.active_crtcs & (1 << 0)) {
539d2418
AD		 703 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
704 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
705 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
706 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 707 }
708 if (rdev->pm.active_crtcs & (1 << 1)) {
539d2418
AD		 709 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
710 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
711 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
712 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 713 }
714 if (rdev->pm.active_crtcs & (1 << 2)) {
539d2418
AD		 715 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
716 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
717 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
718 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 719 }
720 if (rdev->pm.active_crtcs & (1 << 3)) {
539d2418
AD		 721 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
722 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
723 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
724 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 725 }
726 if (rdev->pm.active_crtcs & (1 << 4)) {
539d2418
AD		 727 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
728 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
729 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
730 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 731 }
732 if (rdev->pm.active_crtcs & (1 << 5)) {
539d2418
AD		 733 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
734 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
735 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
736 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 737 }
738 } else if (ASIC_IS_AVIVO(rdev)) {
739 if (rdev->pm.active_crtcs & (1 << 0)) {
539d2418
AD		 740 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
741 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
bae6b562
AD		 742 }
743 if (rdev->pm.active_crtcs & (1 << 1)) {
539d2418
AD		 744 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
745 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
bae6b562 746 }
539d2418
AD		 747 if (position < vbl && position > 1)
748 in_vbl = false;
bae6b562 749 } else {
f735261b 750 if (rdev->pm.active_crtcs & (1 << 0)) {
bae6b562
AD		 751 stat_crtc = RREG32(RADEON_CRTC_STATUS);
752 if (!(stat_crtc & 1))
f735261b
DA		 753 in_vbl = false;
754 }
755 if (rdev->pm.active_crtcs & (1 << 1)) {
bae6b562
AD		 756 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
757 if (!(stat_crtc & 1))
f735261b
DA		 758 in_vbl = false;
759 }
760 }
f81f2024 761
539d2418
AD		 762 if (position < vbl && position > 1)
763 in_vbl = false;
764
f81f2024
MG		 765 return in_vbl;
766}
767
ce8f5370 768static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 769{
770 u32 stat_crtc = 0;
771 bool in_vbl = radeon_pm_in_vbl(rdev);
772
f735261b 773 if (in_vbl == false)
d9fdaafb 774 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 775 finish ? "exit" : "entry");
f735261b
DA		 776 return in_vbl;
777}
c913e23a 778
ce8f5370 779static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 780{
781 struct radeon_device *rdev;
d9932a32 782 int resched;
c913e23a 783 rdev = container_of(work, struct radeon_device,
ce8f5370 784 pm.dynpm_idle_work.work);
c913e23a 785
d9932a32 786 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 787 mutex_lock(&rdev->pm.mutex);
ce8f5370 788 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a
RM		 789 unsigned long irq_flags;
790 int not_processed = 0;
791
792 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
793 if (!list_empty(&rdev->fence_drv.emited)) {
794 struct list_head *ptr;
795 list_for_each(ptr, &rdev->fence_drv.emited) {
796 /* count up to 3, that's enought info */
797 if (++not_processed >= 3)
798 break;
799 }
800 }
801 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
802
803 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 804 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
805 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
806 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
807 rdev->pm.dynpm_can_upclock) {
808 rdev->pm.dynpm_planned_action =
809 DYNPM_ACTION_UPCLOCK;
810 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 811 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
812 }
813 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 814 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
815 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
816 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
817 rdev->pm.dynpm_can_downclock) {
818 rdev->pm.dynpm_planned_action =
819 DYNPM_ACTION_DOWNCLOCK;
820 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 821 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
822 }
823 }
824
d7311171
AD		 825 /* Note, radeon_pm_set_clocks is called with static_switch set
826 * to false since we want to wait for vbl to avoid flicker.
827 */
ce8f5370
AD		 828 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
829 jiffies > rdev->pm.dynpm_action_timeout) {
830 radeon_pm_get_dynpm_state(rdev);
831 radeon_pm_set_clocks(rdev);
c913e23a 832 }
3f53eb6f
RW		 833
834 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
835 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 836 }
837 mutex_unlock(&rdev->pm.mutex);
d9932a32 838 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 839}
840
7433874e
RM		 841/*
842 * Debugfs info
843 */
844#if defined(CONFIG_DEBUG_FS)
845
846static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
847{
848 struct drm_info_node *node = (struct drm_info_node *) m->private;
849 struct drm_device *dev = node->minor->dev;
850 struct radeon_device *rdev = dev->dev_private;
851
6234077d
RM		 852 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
853 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
854 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
855 if (rdev->asic->get_memory_clock)
856 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 857 if (rdev->pm.current_vddc)
858 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
aa5120d2
RM		 859 if (rdev->asic->get_pcie_lanes)
860 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 861
862 return 0;
863}
864
865static struct drm_info_list radeon_pm_info_list[] = {
866 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
867};
868#endif
869
c913e23a 870static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 871{
872#if defined(CONFIG_DEBUG_FS)
873 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
874#else
875 return 0;
876#endif
877}
Linux 6.x block layer and io_uring tree(s)