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drm/radeon/kms: add support for internal thermal sensor on SI
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e
RM		 22 */
23#include "drmP.h"
24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
ce8f5370
AD		 27#ifdef CONFIG_ACPI
28#include <linux/acpi.h>
29#endif
30#include <linux/power_supply.h>
21a8122a
AD		 31#include <linux/hwmon.h>
32#include <linux/hwmon-sysfs.h>
7433874e 33
c913e23a
RM		 34#define RADEON_IDLE_LOOP_MS 100
35#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 36#define RADEON_WAIT_VBLANK_TIMEOUT 200
2031f77c 37#define RADEON_WAIT_IDLE_TIMEOUT 200
c913e23a 38
f712d0c7
RM		 39static const char *radeon_pm_state_type_name[5] = {
40 "Default",
41 "Powersave",
42 "Battery",
43 "Balanced",
44 "Performance",
45};
46
ce8f5370 47static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 48static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 49static bool radeon_pm_in_vbl(struct radeon_device *rdev);
50static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
51static void radeon_pm_update_profile(struct radeon_device *rdev);
52static void radeon_pm_set_clocks(struct radeon_device *rdev);
53
54#define ACPI_AC_CLASS "ac_adapter"
55
a4c9e2ee
AD		 56int radeon_pm_get_type_index(struct radeon_device *rdev,
57 enum radeon_pm_state_type ps_type,
58 int instance)
59{
60 int i;
61 int found_instance = -1;
62
63 for (i = 0; i < rdev->pm.num_power_states; i++) {
64 if (rdev->pm.power_state[i].type == ps_type) {
65 found_instance++;
66 if (found_instance == instance)
67 return i;
68 }
69 }
70 /* return default if no match */
71 return rdev->pm.default_power_state_index;
72}
73
ce8f5370
AD		 74#ifdef CONFIG_ACPI
75static int radeon_acpi_event(struct notifier_block *nb,
76 unsigned long val,
77 void *data)
78{
79 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
80 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
81
82 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
83 if (power_supply_is_system_supplied() > 0)
d9fdaafb 84 DRM_DEBUG_DRIVER("pm: AC\n");
ce8f5370 85 else
d9fdaafb 86 DRM_DEBUG_DRIVER("pm: DC\n");
ce8f5370
AD		 87
88 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
89 if (rdev->pm.profile == PM_PROFILE_AUTO) {
90 mutex_lock(&rdev->pm.mutex);
91 radeon_pm_update_profile(rdev);
92 radeon_pm_set_clocks(rdev);
93 mutex_unlock(&rdev->pm.mutex);
94 }
95 }
96 }
97
98 return NOTIFY_OK;
99}
100#endif
101
102static void radeon_pm_update_profile(struct radeon_device *rdev)
103{
104 switch (rdev->pm.profile) {
105 case PM_PROFILE_DEFAULT:
106 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
107 break;
108 case PM_PROFILE_AUTO:
109 if (power_supply_is_system_supplied() > 0) {
110 if (rdev->pm.active_crtc_count > 1)
111 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
112 else
113 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
114 } else {
115 if (rdev->pm.active_crtc_count > 1)
c9e75b21 116 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 117 else
c9e75b21 118 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 119 }
120 break;
121 case PM_PROFILE_LOW:
122 if (rdev->pm.active_crtc_count > 1)
123 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
124 else
125 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
126 break;
c9e75b21
AD		 127 case PM_PROFILE_MID:
128 if (rdev->pm.active_crtc_count > 1)
129 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
130 else
131 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
132 break;
ce8f5370
AD		 133 case PM_PROFILE_HIGH:
134 if (rdev->pm.active_crtc_count > 1)
135 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
136 else
137 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
138 break;
139 }
140
141 if (rdev->pm.active_crtc_count == 0) {
142 rdev->pm.requested_power_state_index =
143 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
144 rdev->pm.requested_clock_mode_index =
145 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
146 } else {
147 rdev->pm.requested_power_state_index =
148 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
149 rdev->pm.requested_clock_mode_index =
150 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
151 }
152}
c913e23a 153
5876dd24
MG		 154static void radeon_unmap_vram_bos(struct radeon_device *rdev)
155{
156 struct radeon_bo *bo, *n;
157
158 if (list_empty(&rdev->gem.objects))
159 return;
160
161 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
162 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
163 ttm_bo_unmap_virtual(&bo->tbo);
164 }
5876dd24
MG		 165}
166
ce8f5370 167static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 168{
ce8f5370
AD		 169 if (rdev->pm.active_crtcs) {
170 rdev->pm.vblank_sync = false;
171 wait_event_timeout(
172 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
173 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
174 }
175}
176
177static void radeon_set_power_state(struct radeon_device *rdev)
178{
179 u32 sclk, mclk;
92645879 180 bool misc_after = false;
ce8f5370
AD		 181
182 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
183 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
184 return;
185
186 if (radeon_gui_idle(rdev)) {
187 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
188 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 189 if (sclk > rdev->pm.default_sclk)
190 sclk = rdev->pm.default_sclk;
ce8f5370
AD		 191
192 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
193 clock_info[rdev->pm.requested_clock_mode_index].mclk;
9ace9f7b
AD		 194 if (mclk > rdev->pm.default_mclk)
195 mclk = rdev->pm.default_mclk;
ce8f5370 196
92645879
AD		 197 /* upvolt before raising clocks, downvolt after lowering clocks */
198 if (sclk < rdev->pm.current_sclk)
199 misc_after = true;
ce8f5370 200
92645879 201 radeon_sync_with_vblank(rdev);
ce8f5370 202
92645879 203 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 204 if (!radeon_pm_in_vbl(rdev))
205 return;
92645879 206 }
ce8f5370 207
92645879 208 radeon_pm_prepare(rdev);
ce8f5370 209
92645879
AD		 210 if (!misc_after)
211 /* voltage, pcie lanes, etc.*/
212 radeon_pm_misc(rdev);
213
214 /* set engine clock */
215 if (sclk != rdev->pm.current_sclk) {
216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_engine_clock(rdev, sclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_sclk = sclk;
d9fdaafb 220 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 221 }
222
223 /* set memory clock */
798bcf73 224 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 225 radeon_pm_debug_check_in_vbl(rdev, false);
226 radeon_set_memory_clock(rdev, mclk);
227 radeon_pm_debug_check_in_vbl(rdev, true);
228 rdev->pm.current_mclk = mclk;
d9fdaafb 229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 230 }
2aba631c 231
92645879
AD		 232 if (misc_after)
233 /* voltage, pcie lanes, etc.*/
234 radeon_pm_misc(rdev);
235
236 radeon_pm_finish(rdev);
237
ce8f5370
AD		 238 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
239 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
240 } else
d9fdaafb 241 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 242}
243
244static void radeon_pm_set_clocks(struct radeon_device *rdev)
245{
246 int i;
c37d230a 247
4e186b2d
AD		 248 /* no need to take locks, etc. if nothing's going to change */
249 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
250 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
251 return;
252
612e06ce
MG		 253 mutex_lock(&rdev->ddev->struct_mutex);
254 mutex_lock(&rdev->vram_mutex);
bf852799 255 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
e32eb50d
CK		 256 if (rdev->ring[i].ring_obj)
257 mutex_lock(&rdev->ring[i].mutex);
bf852799 258 }
4f3218cb
AD		 259
260 /* gui idle int has issues on older chips it seems */
261 if (rdev->family >= CHIP_R600) {
ce8f5370
AD		 262 if (rdev->irq.installed) {
263 /* wait for GPU idle */
264 rdev->pm.gui_idle = false;
265 rdev->irq.gui_idle = true;
266 radeon_irq_set(rdev);
267 wait_event_interruptible_timeout(
268 rdev->irq.idle_queue, rdev->pm.gui_idle,
269 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
270 rdev->irq.gui_idle = false;
271 radeon_irq_set(rdev);
272 }
01434b4b 273 } else {
e32eb50d
CK		 274 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
275 if (ring->ready) {
ce8f5370 276 struct radeon_fence *fence;
e32eb50d
CK		 277 radeon_ring_alloc(rdev, ring, 64);
278 radeon_fence_create(rdev, &fence, radeon_ring_index(rdev, ring));
ce8f5370 279 radeon_fence_emit(rdev, fence);
e32eb50d 280 radeon_ring_commit(rdev, ring);
ce8f5370
AD		 281 radeon_fence_wait(fence, false);
282 radeon_fence_unref(&fence);
283 }
4f3218cb 284 }
5876dd24
MG		 285 radeon_unmap_vram_bos(rdev);
286
ce8f5370 287 if (rdev->irq.installed) {
2aba631c
MG		 288 for (i = 0; i < rdev->num_crtc; i++) {
289 if (rdev->pm.active_crtcs & (1 << i)) {
290 rdev->pm.req_vblank |= (1 << i);
291 drm_vblank_get(rdev->ddev, i);
292 }
293 }
294 }
539d2418 295
ce8f5370 296 radeon_set_power_state(rdev);
2aba631c 297
ce8f5370 298 if (rdev->irq.installed) {
2aba631c
MG		 299 for (i = 0; i < rdev->num_crtc; i++) {
300 if (rdev->pm.req_vblank & (1 << i)) {
301 rdev->pm.req_vblank &= ~(1 << i);
302 drm_vblank_put(rdev->ddev, i);
303 }
304 }
305 }
5876dd24 306
a424816f
AD		 307 /* update display watermarks based on new power state */
308 radeon_update_bandwidth_info(rdev);
309 if (rdev->pm.active_crtc_count)
310 radeon_bandwidth_update(rdev);
311
ce8f5370 312 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 313
bf852799 314 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
e32eb50d
CK		 315 if (rdev->ring[i].ring_obj)
316 mutex_unlock(&rdev->ring[i].mutex);
bf852799 317 }
612e06ce
MG		 318 mutex_unlock(&rdev->vram_mutex);
319 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 320}
321
f712d0c7
RM		 322static void radeon_pm_print_states(struct radeon_device *rdev)
323{
324 int i, j;
325 struct radeon_power_state *power_state;
326 struct radeon_pm_clock_info *clock_info;
327
d9fdaafb 328 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 329 for (i = 0; i < rdev->pm.num_power_states; i++) {
330 power_state = &rdev->pm.power_state[i];
d9fdaafb 331 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 332 radeon_pm_state_type_name[power_state->type]);
333 if (i == rdev->pm.default_power_state_index)
d9fdaafb 334 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 335 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 336 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 337 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 338 DRM_DEBUG_DRIVER("\tSingle display only\n");
339 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 340 for (j = 0; j < power_state->num_clock_modes; j++) {
341 clock_info = &(power_state->clock_info[j]);
342 if (rdev->flags & RADEON_IS_IGP)
d9fdaafb 343 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
f712d0c7
RM		 344 j,
345 clock_info->sclk * 10,
346 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
347 else
d9fdaafb 348 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
f712d0c7
RM		 349 j,
350 clock_info->sclk * 10,
351 clock_info->mclk * 10,
352 clock_info->voltage.voltage,
353 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
354 }
355 }
356}
357
ce8f5370
AD		 358static ssize_t radeon_get_pm_profile(struct device *dev,
359 struct device_attribute *attr,
360 char *buf)
a424816f
AD		 361{
362 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
363 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 364 int cp = rdev->pm.profile;
a424816f 365
ce8f5370
AD		 366 return snprintf(buf, PAGE_SIZE, "%s\n",
367 (cp == PM_PROFILE_AUTO) ? "auto" :
368 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 369 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 370 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 371}
372
ce8f5370
AD		 373static ssize_t radeon_set_pm_profile(struct device *dev,
374 struct device_attribute *attr,
375 const char *buf,
376 size_t count)
a424816f
AD		 377{
378 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
379 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 380
381 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 382 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
383 if (strncmp("default", buf, strlen("default")) == 0)
384 rdev->pm.profile = PM_PROFILE_DEFAULT;
385 else if (strncmp("auto", buf, strlen("auto")) == 0)
386 rdev->pm.profile = PM_PROFILE_AUTO;
387 else if (strncmp("low", buf, strlen("low")) == 0)
388 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 389 else if (strncmp("mid", buf, strlen("mid")) == 0)
390 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 391 else if (strncmp("high", buf, strlen("high")) == 0)
392 rdev->pm.profile = PM_PROFILE_HIGH;
393 else {
1783e4bf 394 count = -EINVAL;
ce8f5370 395 goto fail;
a424816f 396 }
ce8f5370
AD		 397 radeon_pm_update_profile(rdev);
398 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 399 } else
400 count = -EINVAL;
401
ce8f5370 402fail:
a424816f
AD		 403 mutex_unlock(&rdev->pm.mutex);
404
405 return count;
406}
407
ce8f5370
AD		 408static ssize_t radeon_get_pm_method(struct device *dev,
409 struct device_attribute *attr,
410 char *buf)
a424816f
AD		 411{
412 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
413 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 414 int pm = rdev->pm.pm_method;
a424816f
AD		 415
416 return snprintf(buf, PAGE_SIZE, "%s\n",
ce8f5370 417 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
a424816f
AD		 418}
419
ce8f5370
AD		 420static ssize_t radeon_set_pm_method(struct device *dev,
421 struct device_attribute *attr,
422 const char *buf,
423 size_t count)
a424816f
AD		 424{
425 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
426 struct radeon_device *rdev = ddev->dev_private;
a424816f 427
ce8f5370
AD		 428
429 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 430 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 431 rdev->pm.pm_method = PM_METHOD_DYNPM;
432 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
433 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 434 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 435 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
436 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 437 /* disable dynpm */
438 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
439 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 440 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 441 mutex_unlock(&rdev->pm.mutex);
32c87fca 442 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 443 } else {
1783e4bf 444 count = -EINVAL;
ce8f5370
AD		 445 goto fail;
446 }
447 radeon_pm_compute_clocks(rdev);
448fail:
a424816f
AD		 449 return count;
450}
451
ce8f5370
AD		 452static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
453static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
a424816f 454
21a8122a
AD		 455static ssize_t radeon_hwmon_show_temp(struct device *dev,
456 struct device_attribute *attr,
457 char *buf)
458{
459 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
460 struct radeon_device *rdev = ddev->dev_private;
20d391d7 461 int temp;
21a8122a
AD		 462
463 switch (rdev->pm.int_thermal_type) {
464 case THERMAL_TYPE_RV6XX:
465 temp = rv6xx_get_temp(rdev);
466 break;
467 case THERMAL_TYPE_RV770:
468 temp = rv770_get_temp(rdev);
469 break;
470 case THERMAL_TYPE_EVERGREEN:
4fddba1f 471 case THERMAL_TYPE_NI:
21a8122a
AD		 472 temp = evergreen_get_temp(rdev);
473 break;
e33df25f
AD		 474 case THERMAL_TYPE_SUMO:
475 temp = sumo_get_temp(rdev);
476 break;
1bd47d2e
AD		 477 case THERMAL_TYPE_SI:
478 temp = si_get_temp(rdev);
479 break;
21a8122a
AD		 480 default:
481 temp = 0;
482 break;
483 }
484
485 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
486}
487
488static ssize_t radeon_hwmon_show_name(struct device *dev,
489 struct device_attribute *attr,
490 char *buf)
491{
492 return sprintf(buf, "radeon\n");
493}
494
495static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
496static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
497
498static struct attribute *hwmon_attributes[] = {
499 &sensor_dev_attr_temp1_input.dev_attr.attr,
500 &sensor_dev_attr_name.dev_attr.attr,
501 NULL
502};
503
504static const struct attribute_group hwmon_attrgroup = {
505 .attrs = hwmon_attributes,
506};
507
0d18abed 508static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 509{
0d18abed 510 int err = 0;
21a8122a
AD		 511
512 rdev->pm.int_hwmon_dev = NULL;
513
514 switch (rdev->pm.int_thermal_type) {
515 case THERMAL_TYPE_RV6XX:
516 case THERMAL_TYPE_RV770:
517 case THERMAL_TYPE_EVERGREEN:
457558ed 518 case THERMAL_TYPE_NI:
e33df25f 519 case THERMAL_TYPE_SUMO:
1bd47d2e 520 case THERMAL_TYPE_SI:
21a8122a 521 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 522 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
523 err = PTR_ERR(rdev->pm.int_hwmon_dev);
524 dev_err(rdev->dev,
525 "Unable to register hwmon device: %d\n", err);
526 break;
527 }
21a8122a
AD		 528 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
529 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
530 &hwmon_attrgroup);
0d18abed
DC		 531 if (err) {
532 dev_err(rdev->dev,
533 "Unable to create hwmon sysfs file: %d\n", err);
534 hwmon_device_unregister(rdev->dev);
535 }
21a8122a
AD		 536 break;
537 default:
538 break;
539 }
0d18abed
DC		 540
541 return err;
21a8122a
AD		 542}
543
544static void radeon_hwmon_fini(struct radeon_device *rdev)
545{
546 if (rdev->pm.int_hwmon_dev) {
547 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
548 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
549 }
550}
551
ce8f5370 552void radeon_pm_suspend(struct radeon_device *rdev)
56278a8e 553{
ce8f5370 554 mutex_lock(&rdev->pm.mutex);
3f53eb6f 555 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 556 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
557 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 558 }
ce8f5370 559 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 560
561 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 562}
563
ce8f5370 564void radeon_pm_resume(struct radeon_device *rdev)
d0d6cb81 565{
ed18a360
AD		 566 /* set up the default clocks if the MC ucode is loaded */
567 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
568 if (rdev->pm.default_vddc)
8a83ec5e
AD		 569 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
570 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 571 if (rdev->pm.default_vddci)
572 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
573 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 574 if (rdev->pm.default_sclk)
575 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
576 if (rdev->pm.default_mclk)
577 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
578 }
f8ed8b4c
AD		 579 /* asic init will reset the default power state */
580 mutex_lock(&rdev->pm.mutex);
581 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
582 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 583 rdev->pm.current_sclk = rdev->pm.default_sclk;
584 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 585 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2feea49a 586 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
3f53eb6f
RW		 587 if (rdev->pm.pm_method == PM_METHOD_DYNPM
588 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
589 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 590 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
591 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 592 }
f8ed8b4c 593 mutex_unlock(&rdev->pm.mutex);
ce8f5370 594 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 595}
596
7433874e
RM		 597int radeon_pm_init(struct radeon_device *rdev)
598{
26481fb1 599 int ret;
0d18abed 600
ce8f5370
AD		 601 /* default to profile method */
602 rdev->pm.pm_method = PM_METHOD_PROFILE;
f8ed8b4c 603 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 604 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
605 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
606 rdev->pm.dynpm_can_upclock = true;
607 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 608 rdev->pm.default_sclk = rdev->clock.default_sclk;
609 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 610 rdev->pm.current_sclk = rdev->clock.default_sclk;
611 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 612 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 613
56278a8e
AD		 614 if (rdev->bios) {
615 if (rdev->is_atom_bios)
616 radeon_atombios_get_power_modes(rdev);
617 else
618 radeon_combios_get_power_modes(rdev);
f712d0c7 619 radeon_pm_print_states(rdev);
ce8f5370 620 radeon_pm_init_profile(rdev);
ed18a360
AD		 621 /* set up the default clocks if the MC ucode is loaded */
622 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
623 if (rdev->pm.default_vddc)
8a83ec5e
AD		 624 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
625 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 626 if (rdev->pm.default_vddci)
627 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
628 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 629 if (rdev->pm.default_sclk)
630 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
631 if (rdev->pm.default_mclk)
632 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
633 }
56278a8e
AD		 634 }
635
21a8122a 636 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 637 ret = radeon_hwmon_init(rdev);
638 if (ret)
639 return ret;
32c87fca
TH		 640
641 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
642
ce8f5370 643 if (rdev->pm.num_power_states > 1) {
ce8f5370 644 /* where's the best place to put these? */
26481fb1
DA		 645 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
646 if (ret)
647 DRM_ERROR("failed to create device file for power profile\n");
648 ret = device_create_file(rdev->dev, &dev_attr_power_method);
649 if (ret)
650 DRM_ERROR("failed to create device file for power method\n");
a424816f 651
ce8f5370
AD		 652#ifdef CONFIG_ACPI
653 rdev->acpi_nb.notifier_call = radeon_acpi_event;
654 register_acpi_notifier(&rdev->acpi_nb);
655#endif
ce8f5370
AD		 656 if (radeon_debugfs_pm_init(rdev)) {
657 DRM_ERROR("Failed to register debugfs file for PM!\n");
658 }
c913e23a 659
ce8f5370
AD		 660 DRM_INFO("radeon: power management initialized\n");
661 }
c913e23a 662
7433874e
RM		 663 return 0;
664}
665
29fb52ca
AD		 666void radeon_pm_fini(struct radeon_device *rdev)
667{
ce8f5370 668 if (rdev->pm.num_power_states > 1) {
a424816f 669 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 670 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
671 rdev->pm.profile = PM_PROFILE_DEFAULT;
672 radeon_pm_update_profile(rdev);
673 radeon_pm_set_clocks(rdev);
674 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 675 /* reset default clocks */
676 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
677 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
678 radeon_pm_set_clocks(rdev);
679 }
a424816f 680 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 681
682 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 683
ce8f5370
AD		 684 device_remove_file(rdev->dev, &dev_attr_power_profile);
685 device_remove_file(rdev->dev, &dev_attr_power_method);
686#ifdef CONFIG_ACPI
687 unregister_acpi_notifier(&rdev->acpi_nb);
688#endif
689 }
a424816f 690
0975b162
AD		 691 if (rdev->pm.power_state)
692 kfree(rdev->pm.power_state);
693
21a8122a 694 radeon_hwmon_fini(rdev);
29fb52ca
AD		 695}
696
c913e23a
RM		 697void radeon_pm_compute_clocks(struct radeon_device *rdev)
698{
699 struct drm_device *ddev = rdev->ddev;
a48b9b4e 700 struct drm_crtc *crtc;
c913e23a 701 struct radeon_crtc *radeon_crtc;
c913e23a 702
ce8f5370
AD		 703 if (rdev->pm.num_power_states < 2)
704 return;
705
c913e23a
RM		 706 mutex_lock(&rdev->pm.mutex);
707
708 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 709 rdev->pm.active_crtc_count = 0;
710 list_for_each_entry(crtc,
711 &ddev->mode_config.crtc_list, head) {
712 radeon_crtc = to_radeon_crtc(crtc);
713 if (radeon_crtc->enabled) {
c913e23a 714 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 715 rdev->pm.active_crtc_count++;
c913e23a
RM		 716 }
717 }
718
ce8f5370
AD		 719 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
720 radeon_pm_update_profile(rdev);
721 radeon_pm_set_clocks(rdev);
722 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
723 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
724 if (rdev->pm.active_crtc_count > 1) {
725 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
726 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
727
728 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
729 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
730 radeon_pm_get_dynpm_state(rdev);
731 radeon_pm_set_clocks(rdev);
732
d9fdaafb 733 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 734 }
735 } else if (rdev->pm.active_crtc_count == 1) {
736 /* TODO: Increase clocks if needed for current mode */
737
738 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
739 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
740 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
741 radeon_pm_get_dynpm_state(rdev);
742 radeon_pm_set_clocks(rdev);
743
32c87fca
TH		 744 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
745 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 746 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
747 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 748 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
749 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 750 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 751 }
752 } else { /* count == 0 */
753 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
754 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
755
756 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
757 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
758 radeon_pm_get_dynpm_state(rdev);
759 radeon_pm_set_clocks(rdev);
760 }
761 }
c913e23a 762 }
c913e23a 763 }
73a6d3fc
RM		 764
765 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 766}
767
ce8f5370 768static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 769{
75fa0b08 770 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 771 bool in_vbl = true;
772
75fa0b08
MK		 773 /* Iterate over all active crtc's. All crtc's must be in vblank,
774 * otherwise return in_vbl == false.
775 */
776 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
777 if (rdev->pm.active_crtcs & (1 << crtc)) {
f5a80209
MK		 778 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
779 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
780 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 781 in_vbl = false;
782 }
783 }
f81f2024
MG		 784
785 return in_vbl;
786}
787
ce8f5370 788static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 789{
790 u32 stat_crtc = 0;
791 bool in_vbl = radeon_pm_in_vbl(rdev);
792
f735261b 793 if (in_vbl == false)
d9fdaafb 794 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 795 finish ? "exit" : "entry");
f735261b
DA		 796 return in_vbl;
797}
c913e23a 798
ce8f5370 799static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 800{
801 struct radeon_device *rdev;
d9932a32 802 int resched;
c913e23a 803 rdev = container_of(work, struct radeon_device,
ce8f5370 804 pm.dynpm_idle_work.work);
c913e23a 805
d9932a32 806 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 807 mutex_lock(&rdev->pm.mutex);
ce8f5370 808 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 809 int not_processed = 0;
7465280c
AD		 810 int i;
811
7465280c 812 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
47492a23 813 not_processed += radeon_fence_count_emitted(rdev, i);
7465280c
AD		 814 if (not_processed >= 3)
815 break;
c913e23a 816 }
c913e23a
RM		 817
818 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 819 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
820 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
821 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
822 rdev->pm.dynpm_can_upclock) {
823 rdev->pm.dynpm_planned_action =
824 DYNPM_ACTION_UPCLOCK;
825 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 826 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
827 }
828 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 829 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
830 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
831 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
832 rdev->pm.dynpm_can_downclock) {
833 rdev->pm.dynpm_planned_action =
834 DYNPM_ACTION_DOWNCLOCK;
835 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 836 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
837 }
838 }
839
d7311171
AD		 840 /* Note, radeon_pm_set_clocks is called with static_switch set
841 * to false since we want to wait for vbl to avoid flicker.
842 */
ce8f5370
AD		 843 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
844 jiffies > rdev->pm.dynpm_action_timeout) {
845 radeon_pm_get_dynpm_state(rdev);
846 radeon_pm_set_clocks(rdev);
c913e23a 847 }
3f53eb6f 848
32c87fca
TH		 849 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
850 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 851 }
852 mutex_unlock(&rdev->pm.mutex);
d9932a32 853 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 854}
855
7433874e
RM		 856/*
857 * Debugfs info
858 */
859#if defined(CONFIG_DEBUG_FS)
860
861static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
862{
863 struct drm_info_node *node = (struct drm_info_node *) m->private;
864 struct drm_device *dev = node->minor->dev;
865 struct radeon_device *rdev = dev->dev_private;
866
9ace9f7b 867 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
6234077d 868 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
9ace9f7b 869 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
798bcf73 870 if (rdev->asic->pm.get_memory_clock)
6234077d 871 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 872 if (rdev->pm.current_vddc)
873 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
798bcf73 874 if (rdev->asic->pm.get_pcie_lanes)
aa5120d2 875 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 876
877 return 0;
878}
879
880static struct drm_info_list radeon_pm_info_list[] = {
881 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
882};
883#endif
884
c913e23a 885static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 886{
887#if defined(CONFIG_DEBUG_FS)
888 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
889#else
890 return 0;
891#endif
892}
Linux 6.x block layer and io_uring tree(s)