projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon: add KB/KV to r600_is_internal_thermal_sensor
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e 22 */
760285e7 23#include <drm/drmP.h>
7433874e 24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
ce8f5370 27#include <linux/power_supply.h>
21a8122a
AD		 28#include <linux/hwmon.h>
29#include <linux/hwmon-sysfs.h>
7433874e 30
c913e23a
RM		 31#define RADEON_IDLE_LOOP_MS 100
32#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 33#define RADEON_WAIT_VBLANK_TIMEOUT 200
c913e23a 34
f712d0c7 35static const char *radeon_pm_state_type_name[5] = {
eb2c27a0 36 "",
f712d0c7
RM		 37 "Powersave",
38 "Battery",
39 "Balanced",
40 "Performance",
41};
42
ce8f5370 43static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 44static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 45static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47static void radeon_pm_update_profile(struct radeon_device *rdev);
48static void radeon_pm_set_clocks(struct radeon_device *rdev);
49
a4c9e2ee
AD		 50int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
52 int instance)
53{
54 int i;
55 int found_instance = -1;
56
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
59 found_instance++;
60 if (found_instance == instance)
61 return i;
62 }
63 }
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
66}
67
c4917074 68void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
ce8f5370 69{
c4917074
AD		 70 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
71 if (rdev->pm.profile == PM_PROFILE_AUTO) {
72 mutex_lock(&rdev->pm.mutex);
73 radeon_pm_update_profile(rdev);
74 radeon_pm_set_clocks(rdev);
75 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 76 }
77 }
ce8f5370 78}
ce8f5370
AD		 79
80static void radeon_pm_update_profile(struct radeon_device *rdev)
81{
82 switch (rdev->pm.profile) {
83 case PM_PROFILE_DEFAULT:
84 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
85 break;
86 case PM_PROFILE_AUTO:
87 if (power_supply_is_system_supplied() > 0) {
88 if (rdev->pm.active_crtc_count > 1)
89 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
90 else
91 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
92 } else {
93 if (rdev->pm.active_crtc_count > 1)
c9e75b21 94 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 95 else
c9e75b21 96 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 97 }
98 break;
99 case PM_PROFILE_LOW:
100 if (rdev->pm.active_crtc_count > 1)
101 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
102 else
103 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
104 break;
c9e75b21
AD		 105 case PM_PROFILE_MID:
106 if (rdev->pm.active_crtc_count > 1)
107 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
108 else
109 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
110 break;
ce8f5370
AD		 111 case PM_PROFILE_HIGH:
112 if (rdev->pm.active_crtc_count > 1)
113 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
114 else
115 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
116 break;
117 }
118
119 if (rdev->pm.active_crtc_count == 0) {
120 rdev->pm.requested_power_state_index =
121 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
122 rdev->pm.requested_clock_mode_index =
123 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
124 } else {
125 rdev->pm.requested_power_state_index =
126 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
127 rdev->pm.requested_clock_mode_index =
128 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
129 }
130}
c913e23a 131
5876dd24
MG		 132static void radeon_unmap_vram_bos(struct radeon_device *rdev)
133{
134 struct radeon_bo *bo, *n;
135
136 if (list_empty(&rdev->gem.objects))
137 return;
138
139 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
140 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
141 ttm_bo_unmap_virtual(&bo->tbo);
142 }
5876dd24
MG		 143}
144
ce8f5370 145static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 146{
ce8f5370
AD		 147 if (rdev->pm.active_crtcs) {
148 rdev->pm.vblank_sync = false;
149 wait_event_timeout(
150 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
151 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
152 }
153}
154
155static void radeon_set_power_state(struct radeon_device *rdev)
156{
157 u32 sclk, mclk;
92645879 158 bool misc_after = false;
ce8f5370
AD		 159
160 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
161 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
162 return;
163
164 if (radeon_gui_idle(rdev)) {
165 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
166 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 167 if (sclk > rdev->pm.default_sclk)
168 sclk = rdev->pm.default_sclk;
ce8f5370 169
27810fb2
AD		 170 /* starting with BTC, there is one state that is used for both
171 * MH and SH. Difference is that we always use the high clock index for
7ae764b1 172 * mclk and vddci.
27810fb2
AD		 173 */
174 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
175 (rdev->family >= CHIP_BARTS) &&
176 rdev->pm.active_crtc_count &&
177 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
178 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
179 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
180 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
181 else
182 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 clock_info[rdev->pm.requested_clock_mode_index].mclk;
184
9ace9f7b
AD		 185 if (mclk > rdev->pm.default_mclk)
186 mclk = rdev->pm.default_mclk;
ce8f5370 187
92645879
AD		 188 /* upvolt before raising clocks, downvolt after lowering clocks */
189 if (sclk < rdev->pm.current_sclk)
190 misc_after = true;
ce8f5370 191
92645879 192 radeon_sync_with_vblank(rdev);
ce8f5370 193
92645879 194 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 195 if (!radeon_pm_in_vbl(rdev))
196 return;
92645879 197 }
ce8f5370 198
92645879 199 radeon_pm_prepare(rdev);
ce8f5370 200
92645879
AD		 201 if (!misc_after)
202 /* voltage, pcie lanes, etc.*/
203 radeon_pm_misc(rdev);
204
205 /* set engine clock */
206 if (sclk != rdev->pm.current_sclk) {
207 radeon_pm_debug_check_in_vbl(rdev, false);
208 radeon_set_engine_clock(rdev, sclk);
209 radeon_pm_debug_check_in_vbl(rdev, true);
210 rdev->pm.current_sclk = sclk;
d9fdaafb 211 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 212 }
213
214 /* set memory clock */
798bcf73 215 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_memory_clock(rdev, mclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_mclk = mclk;
d9fdaafb 220 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 221 }
2aba631c 222
92645879
AD		 223 if (misc_after)
224 /* voltage, pcie lanes, etc.*/
225 radeon_pm_misc(rdev);
226
227 radeon_pm_finish(rdev);
228
ce8f5370
AD		 229 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
230 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
231 } else
d9fdaafb 232 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 233}
234
235static void radeon_pm_set_clocks(struct radeon_device *rdev)
236{
5f8f635e 237 int i, r;
c37d230a 238
4e186b2d
AD		 239 /* no need to take locks, etc. if nothing's going to change */
240 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
241 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
242 return;
243
612e06ce 244 mutex_lock(&rdev->ddev->struct_mutex);
db7fce39 245 down_write(&rdev->pm.mclk_lock);
d6999bc7 246 mutex_lock(&rdev->ring_lock);
4f3218cb 247
95f5a3ac
AD		 248 /* wait for the rings to drain */
249 for (i = 0; i < RADEON_NUM_RINGS; i++) {
250 struct radeon_ring *ring = &rdev->ring[i];
5f8f635e
JG		 251 if (!ring->ready) {
252 continue;
253 }
254 r = radeon_fence_wait_empty_locked(rdev, i);
255 if (r) {
256 /* needs a GPU reset dont reset here */
257 mutex_unlock(&rdev->ring_lock);
258 up_write(&rdev->pm.mclk_lock);
259 mutex_unlock(&rdev->ddev->struct_mutex);
260 return;
261 }
4f3218cb 262 }
95f5a3ac 263
5876dd24
MG		 264 radeon_unmap_vram_bos(rdev);
265
ce8f5370 266 if (rdev->irq.installed) {
2aba631c
MG		 267 for (i = 0; i < rdev->num_crtc; i++) {
268 if (rdev->pm.active_crtcs & (1 << i)) {
269 rdev->pm.req_vblank |= (1 << i);
270 drm_vblank_get(rdev->ddev, i);
271 }
272 }
273 }
539d2418 274
ce8f5370 275 radeon_set_power_state(rdev);
2aba631c 276
ce8f5370 277 if (rdev->irq.installed) {
2aba631c
MG		 278 for (i = 0; i < rdev->num_crtc; i++) {
279 if (rdev->pm.req_vblank & (1 << i)) {
280 rdev->pm.req_vblank &= ~(1 << i);
281 drm_vblank_put(rdev->ddev, i);
282 }
283 }
284 }
5876dd24 285
a424816f
AD		 286 /* update display watermarks based on new power state */
287 radeon_update_bandwidth_info(rdev);
288 if (rdev->pm.active_crtc_count)
289 radeon_bandwidth_update(rdev);
290
ce8f5370 291 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 292
d6999bc7 293 mutex_unlock(&rdev->ring_lock);
db7fce39 294 up_write(&rdev->pm.mclk_lock);
612e06ce 295 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 296}
297
f712d0c7
RM		 298static void radeon_pm_print_states(struct radeon_device *rdev)
299{
300 int i, j;
301 struct radeon_power_state *power_state;
302 struct radeon_pm_clock_info *clock_info;
303
d9fdaafb 304 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 305 for (i = 0; i < rdev->pm.num_power_states; i++) {
306 power_state = &rdev->pm.power_state[i];
d9fdaafb 307 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 308 radeon_pm_state_type_name[power_state->type]);
309 if (i == rdev->pm.default_power_state_index)
d9fdaafb 310 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 311 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 312 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 313 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 314 DRM_DEBUG_DRIVER("\tSingle display only\n");
315 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 316 for (j = 0; j < power_state->num_clock_modes; j++) {
317 clock_info = &(power_state->clock_info[j]);
318 if (rdev->flags & RADEON_IS_IGP)
eb2c27a0
AD		 319 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
320 j,
321 clock_info->sclk * 10);
f712d0c7 322 else
eb2c27a0
AD		 323 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
324 j,
325 clock_info->sclk * 10,
326 clock_info->mclk * 10,
327 clock_info->voltage.voltage);
f712d0c7
RM		 328 }
329 }
330}
331
ce8f5370
AD		 332static ssize_t radeon_get_pm_profile(struct device *dev,
333 struct device_attribute *attr,
334 char *buf)
a424816f
AD		 335{
336 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
337 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 338 int cp = rdev->pm.profile;
a424816f 339
ce8f5370
AD		 340 return snprintf(buf, PAGE_SIZE, "%s\n",
341 (cp == PM_PROFILE_AUTO) ? "auto" :
342 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 343 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 344 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 345}
346
ce8f5370
AD		 347static ssize_t radeon_set_pm_profile(struct device *dev,
348 struct device_attribute *attr,
349 const char *buf,
350 size_t count)
a424816f
AD		 351{
352 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
353 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 354
355 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 356 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
357 if (strncmp("default", buf, strlen("default")) == 0)
358 rdev->pm.profile = PM_PROFILE_DEFAULT;
359 else if (strncmp("auto", buf, strlen("auto")) == 0)
360 rdev->pm.profile = PM_PROFILE_AUTO;
361 else if (strncmp("low", buf, strlen("low")) == 0)
362 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 363 else if (strncmp("mid", buf, strlen("mid")) == 0)
364 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 365 else if (strncmp("high", buf, strlen("high")) == 0)
366 rdev->pm.profile = PM_PROFILE_HIGH;
367 else {
1783e4bf 368 count = -EINVAL;
ce8f5370 369 goto fail;
a424816f 370 }
ce8f5370
AD		 371 radeon_pm_update_profile(rdev);
372 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 373 } else
374 count = -EINVAL;
375
ce8f5370 376fail:
a424816f
AD		 377 mutex_unlock(&rdev->pm.mutex);
378
379 return count;
380}
381
ce8f5370
AD		 382static ssize_t radeon_get_pm_method(struct device *dev,
383 struct device_attribute *attr,
384 char *buf)
a424816f
AD		 385{
386 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
387 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 388 int pm = rdev->pm.pm_method;
a424816f
AD		 389
390 return snprintf(buf, PAGE_SIZE, "%s\n",
da321c8a
AD		 391 (pm == PM_METHOD_DYNPM) ? "dynpm" :
392 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
a424816f
AD		 393}
394
ce8f5370
AD		 395static ssize_t radeon_set_pm_method(struct device *dev,
396 struct device_attribute *attr,
397 const char *buf,
398 size_t count)
a424816f
AD		 399{
400 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
401 struct radeon_device *rdev = ddev->dev_private;
a424816f 402
da321c8a
AD		 403 /* we don't support the legacy modes with dpm */
404 if (rdev->pm.pm_method == PM_METHOD_DPM) {
405 count = -EINVAL;
406 goto fail;
407 }
ce8f5370
AD		 408
409 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 410 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 411 rdev->pm.pm_method = PM_METHOD_DYNPM;
412 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
413 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 414 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 415 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
416 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 417 /* disable dynpm */
418 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
419 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 420 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 421 mutex_unlock(&rdev->pm.mutex);
32c87fca 422 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 423 } else {
1783e4bf 424 count = -EINVAL;
ce8f5370
AD		 425 goto fail;
426 }
427 radeon_pm_compute_clocks(rdev);
428fail:
a424816f
AD		 429 return count;
430}
431
da321c8a
AD		 432static ssize_t radeon_get_dpm_state(struct device *dev,
433 struct device_attribute *attr,
434 char *buf)
435{
436 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
437 struct radeon_device *rdev = ddev->dev_private;
438 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
439
440 return snprintf(buf, PAGE_SIZE, "%s\n",
441 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
442 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
443}
444
445static ssize_t radeon_set_dpm_state(struct device *dev,
446 struct device_attribute *attr,
447 const char *buf,
448 size_t count)
449{
450 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
451 struct radeon_device *rdev = ddev->dev_private;
452
453 mutex_lock(&rdev->pm.mutex);
454 if (strncmp("battery", buf, strlen("battery")) == 0)
455 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
456 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
457 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
458 else if (strncmp("performance", buf, strlen("performance")) == 0)
459 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
460 else {
461 mutex_unlock(&rdev->pm.mutex);
462 count = -EINVAL;
463 goto fail;
464 }
465 mutex_unlock(&rdev->pm.mutex);
466 radeon_pm_compute_clocks(rdev);
467fail:
468 return count;
469}
470
70d01a5e
AD		 471static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
472 struct device_attribute *attr,
473 char *buf)
474{
475 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
476 struct radeon_device *rdev = ddev->dev_private;
477 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
478
479 return snprintf(buf, PAGE_SIZE, "%s\n",
480 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
481 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
482}
483
484static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
485 struct device_attribute *attr,
486 const char *buf,
487 size_t count)
488{
489 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
490 struct radeon_device *rdev = ddev->dev_private;
491 enum radeon_dpm_forced_level level;
492 int ret = 0;
493
494 mutex_lock(&rdev->pm.mutex);
495 if (strncmp("low", buf, strlen("low")) == 0) {
496 level = RADEON_DPM_FORCED_LEVEL_LOW;
497 } else if (strncmp("high", buf, strlen("high")) == 0) {
498 level = RADEON_DPM_FORCED_LEVEL_HIGH;
499 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
500 level = RADEON_DPM_FORCED_LEVEL_AUTO;
501 } else {
502 mutex_unlock(&rdev->pm.mutex);
503 count = -EINVAL;
504 goto fail;
505 }
506 if (rdev->asic->dpm.force_performance_level) {
507 ret = radeon_dpm_force_performance_level(rdev, level);
508 if (ret)
509 count = -EINVAL;
510 }
511 mutex_unlock(&rdev->pm.mutex);
512fail:
513 return count;
514}
515
ce8f5370
AD		 516static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
517static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
da321c8a 518static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
70d01a5e
AD		 519static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
520 radeon_get_dpm_forced_performance_level,
521 radeon_set_dpm_forced_performance_level);
a424816f 522
21a8122a
AD		 523static ssize_t radeon_hwmon_show_temp(struct device *dev,
524 struct device_attribute *attr,
525 char *buf)
526{
527 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
528 struct radeon_device *rdev = ddev->dev_private;
20d391d7 529 int temp;
21a8122a 530
6bd1c385
AD		 531 if (rdev->asic->pm.get_temperature)
532 temp = radeon_get_temperature(rdev);
533 else
21a8122a 534 temp = 0;
21a8122a
AD		 535
536 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
537}
538
539static ssize_t radeon_hwmon_show_name(struct device *dev,
540 struct device_attribute *attr,
541 char *buf)
542{
543 return sprintf(buf, "radeon\n");
544}
545
546static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
547static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
548
549static struct attribute *hwmon_attributes[] = {
550 &sensor_dev_attr_temp1_input.dev_attr.attr,
551 &sensor_dev_attr_name.dev_attr.attr,
552 NULL
553};
554
555static const struct attribute_group hwmon_attrgroup = {
556 .attrs = hwmon_attributes,
557};
558
0d18abed 559static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 560{
0d18abed 561 int err = 0;
21a8122a
AD		 562
563 rdev->pm.int_hwmon_dev = NULL;
564
565 switch (rdev->pm.int_thermal_type) {
566 case THERMAL_TYPE_RV6XX:
567 case THERMAL_TYPE_RV770:
568 case THERMAL_TYPE_EVERGREEN:
457558ed 569 case THERMAL_TYPE_NI:
e33df25f 570 case THERMAL_TYPE_SUMO:
1bd47d2e 571 case THERMAL_TYPE_SI:
6bd1c385 572 if (rdev->asic->pm.get_temperature == NULL)
5d7486c7 573 return err;
21a8122a 574 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 575 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
576 err = PTR_ERR(rdev->pm.int_hwmon_dev);
577 dev_err(rdev->dev,
578 "Unable to register hwmon device: %d\n", err);
579 break;
580 }
21a8122a
AD		 581 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
582 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
583 &hwmon_attrgroup);
0d18abed
DC		 584 if (err) {
585 dev_err(rdev->dev,
586 "Unable to create hwmon sysfs file: %d\n", err);
587 hwmon_device_unregister(rdev->dev);
588 }
21a8122a
AD		 589 break;
590 default:
591 break;
592 }
0d18abed
DC		 593
594 return err;
21a8122a
AD		 595}
596
597static void radeon_hwmon_fini(struct radeon_device *rdev)
598{
599 if (rdev->pm.int_hwmon_dev) {
600 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
601 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
602 }
603}
604
da321c8a
AD		 605static void radeon_dpm_thermal_work_handler(struct work_struct *work)
606{
607 struct radeon_device *rdev =
608 container_of(work, struct radeon_device,
609 pm.dpm.thermal.work);
610 /* switch to the thermal state */
611 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
612
613 if (!rdev->pm.dpm_enabled)
614 return;
615
616 if (rdev->asic->pm.get_temperature) {
617 int temp = radeon_get_temperature(rdev);
618
619 if (temp < rdev->pm.dpm.thermal.min_temp)
620 /* switch back the user state */
621 dpm_state = rdev->pm.dpm.user_state;
622 } else {
623 if (rdev->pm.dpm.thermal.high_to_low)
624 /* switch back the user state */
625 dpm_state = rdev->pm.dpm.user_state;
626 }
60320347
AD		 627 mutex_lock(&rdev->pm.mutex);
628 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
629 rdev->pm.dpm.thermal_active = true;
630 else
631 rdev->pm.dpm.thermal_active = false;
632 rdev->pm.dpm.state = dpm_state;
633 mutex_unlock(&rdev->pm.mutex);
634
635 radeon_pm_compute_clocks(rdev);
da321c8a
AD		 636}
637
638static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
639 enum radeon_pm_state_type dpm_state)
640{
641 int i;
642 struct radeon_ps *ps;
643 u32 ui_class;
48783069
AD		 644 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
645 true : false;
646
647 /* check if the vblank period is too short to adjust the mclk */
648 if (single_display && rdev->asic->dpm.vblank_too_short) {
649 if (radeon_dpm_vblank_too_short(rdev))
650 single_display = false;
651 }
da321c8a 652
edcaa5b1
AD		 653 /* certain older asics have a separare 3D performance state,
654 * so try that first if the user selected performance
655 */
656 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
657 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
da321c8a
AD		 658 /* balanced states don't exist at the moment */
659 if (dpm_state == POWER_STATE_TYPE_BALANCED)
660 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
661
edcaa5b1 662restart_search:
da321c8a
AD		 663 /* Pick the best power state based on current conditions */
664 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
665 ps = &rdev->pm.dpm.ps[i];
666 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
667 switch (dpm_state) {
668 /* user states */
669 case POWER_STATE_TYPE_BATTERY:
670 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
671 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 672 if (single_display)
da321c8a
AD		 673 return ps;
674 } else
675 return ps;
676 }
677 break;
678 case POWER_STATE_TYPE_BALANCED:
679 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
680 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 681 if (single_display)
da321c8a
AD		 682 return ps;
683 } else
684 return ps;
685 }
686 break;
687 case POWER_STATE_TYPE_PERFORMANCE:
688 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
689 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 690 if (single_display)
da321c8a
AD		 691 return ps;
692 } else
693 return ps;
694 }
695 break;
696 /* internal states */
697 case POWER_STATE_TYPE_INTERNAL_UVD:
d4d3278c
AD		 698 if (rdev->pm.dpm.uvd_ps)
699 return rdev->pm.dpm.uvd_ps;
700 else
701 break;
da321c8a
AD		 702 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
703 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
704 return ps;
705 break;
706 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
707 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
708 return ps;
709 break;
710 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
711 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
712 return ps;
713 break;
714 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
715 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
716 return ps;
717 break;
718 case POWER_STATE_TYPE_INTERNAL_BOOT:
719 return rdev->pm.dpm.boot_ps;
720 case POWER_STATE_TYPE_INTERNAL_THERMAL:
721 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
722 return ps;
723 break;
724 case POWER_STATE_TYPE_INTERNAL_ACPI:
725 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
726 return ps;
727 break;
728 case POWER_STATE_TYPE_INTERNAL_ULV:
729 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
730 return ps;
731 break;
edcaa5b1
AD		 732 case POWER_STATE_TYPE_INTERNAL_3DPERF:
733 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
734 return ps;
735 break;
da321c8a
AD		 736 default:
737 break;
738 }
739 }
740 /* use a fallback state if we didn't match */
741 switch (dpm_state) {
742 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
ce3537d5
AD		 743 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
744 goto restart_search;
da321c8a
AD		 745 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
746 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
747 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
d4d3278c
AD		 748 if (rdev->pm.dpm.uvd_ps) {
749 return rdev->pm.dpm.uvd_ps;
750 } else {
751 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
752 goto restart_search;
753 }
da321c8a
AD		 754 case POWER_STATE_TYPE_INTERNAL_THERMAL:
755 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
756 goto restart_search;
757 case POWER_STATE_TYPE_INTERNAL_ACPI:
758 dpm_state = POWER_STATE_TYPE_BATTERY;
759 goto restart_search;
760 case POWER_STATE_TYPE_BATTERY:
edcaa5b1
AD		 761 case POWER_STATE_TYPE_BALANCED:
762 case POWER_STATE_TYPE_INTERNAL_3DPERF:
da321c8a
AD		 763 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
764 goto restart_search;
765 default:
766 break;
767 }
768
769 return NULL;
770}
771
772static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
773{
774 int i;
775 struct radeon_ps *ps;
776 enum radeon_pm_state_type dpm_state;
84dd1928 777 int ret;
da321c8a
AD		 778
779 /* if dpm init failed */
780 if (!rdev->pm.dpm_enabled)
781 return;
782
783 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
784 /* add other state override checks here */
8a227555
AD		 785 if ((!rdev->pm.dpm.thermal_active) &&
786 (!rdev->pm.dpm.uvd_active))
da321c8a
AD		 787 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
788 }
789 dpm_state = rdev->pm.dpm.state;
790
791 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
792 if (ps)
89c9bc56 793 rdev->pm.dpm.requested_ps = ps;
da321c8a
AD		 794 else
795 return;
796
d22b7e40 797 /* no need to reprogram if nothing changed unless we are on BTC+ */
da321c8a 798 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
d22b7e40
AD		 799 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
800 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
801 * all we need to do is update the display configuration.
802 */
803 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
804 /* update display watermarks based on new power state */
805 radeon_bandwidth_update(rdev);
806 /* update displays */
807 radeon_dpm_display_configuration_changed(rdev);
808 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
809 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
810 }
811 return;
812 } else {
813 /* for BTC+ if the num crtcs hasn't changed and state is the same,
814 * nothing to do, if the num crtcs is > 1 and state is the same,
815 * update display configuration.
816 */
817 if (rdev->pm.dpm.new_active_crtcs ==
818 rdev->pm.dpm.current_active_crtcs) {
819 return;
820 } else {
821 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
822 (rdev->pm.dpm.new_active_crtc_count > 1)) {
823 /* update display watermarks based on new power state */
824 radeon_bandwidth_update(rdev);
825 /* update displays */
826 radeon_dpm_display_configuration_changed(rdev);
827 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
828 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
829 return;
830 }
831 }
da321c8a 832 }
da321c8a
AD		 833 }
834
835 printk("switching from power state:\n");
836 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
837 printk("switching to power state:\n");
838 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
839
840 mutex_lock(&rdev->ddev->struct_mutex);
841 down_write(&rdev->pm.mclk_lock);
842 mutex_lock(&rdev->ring_lock);
843
89c9bc56
AD		 844 ret = radeon_dpm_pre_set_power_state(rdev);
845 if (ret)
846 goto done;
84dd1928 847
da321c8a
AD		 848 /* update display watermarks based on new power state */
849 radeon_bandwidth_update(rdev);
850 /* update displays */
851 radeon_dpm_display_configuration_changed(rdev);
852
853 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
854 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
855
856 /* wait for the rings to drain */
857 for (i = 0; i < RADEON_NUM_RINGS; i++) {
858 struct radeon_ring *ring = &rdev->ring[i];
859 if (ring->ready)
860 radeon_fence_wait_empty_locked(rdev, i);
861 }
862
863 /* program the new power state */
864 radeon_dpm_set_power_state(rdev);
865
866 /* update current power state */
867 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
868
89c9bc56 869 radeon_dpm_post_set_power_state(rdev);
84dd1928 870
60320347
AD		 871 /* force low perf level for thermal */
872 if (rdev->pm.dpm.thermal_active &&
873 rdev->asic->dpm.force_performance_level) {
874 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
875 }
876
84dd1928 877done:
da321c8a
AD		 878 mutex_unlock(&rdev->ring_lock);
879 up_write(&rdev->pm.mclk_lock);
880 mutex_unlock(&rdev->ddev->struct_mutex);
881}
882
ce3537d5
AD		 883void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
884{
885 enum radeon_pm_state_type dpm_state;
886
887 if (enable) {
888 mutex_lock(&rdev->pm.mutex);
889 rdev->pm.dpm.uvd_active = true;
890 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
891 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
892 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
893 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
894 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
895 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
896 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
897 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
898 else
899 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
900 rdev->pm.dpm.state = dpm_state;
901 mutex_unlock(&rdev->pm.mutex);
902 } else {
903 mutex_lock(&rdev->pm.mutex);
904 rdev->pm.dpm.uvd_active = false;
905 mutex_unlock(&rdev->pm.mutex);
906 }
907
908 radeon_pm_compute_clocks(rdev);
909}
910
da321c8a 911static void radeon_pm_suspend_old(struct radeon_device *rdev)
56278a8e 912{
ce8f5370 913 mutex_lock(&rdev->pm.mutex);
3f53eb6f 914 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 915 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
916 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 917 }
ce8f5370 918 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 919
920 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 921}
922
da321c8a
AD		 923static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
924{
925 mutex_lock(&rdev->pm.mutex);
926 /* disable dpm */
927 radeon_dpm_disable(rdev);
928 /* reset the power state */
929 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
930 rdev->pm.dpm_enabled = false;
931 mutex_unlock(&rdev->pm.mutex);
932}
933
934void radeon_pm_suspend(struct radeon_device *rdev)
935{
936 if (rdev->pm.pm_method == PM_METHOD_DPM)
937 radeon_pm_suspend_dpm(rdev);
938 else
939 radeon_pm_suspend_old(rdev);
940}
941
942static void radeon_pm_resume_old(struct radeon_device *rdev)
d0d6cb81 943{
ed18a360 944 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 945 if ((rdev->family >= CHIP_BARTS) &&
c6cf7777 946 (rdev->family <= CHIP_HAINAN) &&
2e3b3b10 947 rdev->mc_fw) {
ed18a360 948 if (rdev->pm.default_vddc)
8a83ec5e
AD		 949 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
950 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 951 if (rdev->pm.default_vddci)
952 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
953 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 954 if (rdev->pm.default_sclk)
955 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
956 if (rdev->pm.default_mclk)
957 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
958 }
f8ed8b4c
AD		 959 /* asic init will reset the default power state */
960 mutex_lock(&rdev->pm.mutex);
961 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
962 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 963 rdev->pm.current_sclk = rdev->pm.default_sclk;
964 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 965 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2feea49a 966 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
3f53eb6f
RW		 967 if (rdev->pm.pm_method == PM_METHOD_DYNPM
968 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
969 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 970 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
971 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 972 }
f8ed8b4c 973 mutex_unlock(&rdev->pm.mutex);
ce8f5370 974 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 975}
976
da321c8a
AD		 977static void radeon_pm_resume_dpm(struct radeon_device *rdev)
978{
979 int ret;
980
981 /* asic init will reset to the boot state */
982 mutex_lock(&rdev->pm.mutex);
983 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
984 radeon_dpm_setup_asic(rdev);
985 ret = radeon_dpm_enable(rdev);
986 mutex_unlock(&rdev->pm.mutex);
987 if (ret) {
988 DRM_ERROR("radeon: dpm resume failed\n");
989 if ((rdev->family >= CHIP_BARTS) &&
c6cf7777 990 (rdev->family <= CHIP_HAINAN) &&
da321c8a
AD		 991 rdev->mc_fw) {
992 if (rdev->pm.default_vddc)
993 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
994 SET_VOLTAGE_TYPE_ASIC_VDDC);
995 if (rdev->pm.default_vddci)
996 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
997 SET_VOLTAGE_TYPE_ASIC_VDDCI);
998 if (rdev->pm.default_sclk)
999 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1000 if (rdev->pm.default_mclk)
1001 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1002 }
1003 } else {
1004 rdev->pm.dpm_enabled = true;
1005 radeon_pm_compute_clocks(rdev);
1006 }
1007}
1008
1009void radeon_pm_resume(struct radeon_device *rdev)
1010{
1011 if (rdev->pm.pm_method == PM_METHOD_DPM)
1012 radeon_pm_resume_dpm(rdev);
1013 else
1014 radeon_pm_resume_old(rdev);
1015}
1016
1017static int radeon_pm_init_old(struct radeon_device *rdev)
7433874e 1018{
26481fb1 1019 int ret;
0d18abed 1020
f8ed8b4c 1021 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 1022 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1023 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1024 rdev->pm.dynpm_can_upclock = true;
1025 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 1026 rdev->pm.default_sclk = rdev->clock.default_sclk;
1027 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 1028 rdev->pm.current_sclk = rdev->clock.default_sclk;
1029 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 1030 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 1031
56278a8e
AD		 1032 if (rdev->bios) {
1033 if (rdev->is_atom_bios)
1034 radeon_atombios_get_power_modes(rdev);
1035 else
1036 radeon_combios_get_power_modes(rdev);
f712d0c7 1037 radeon_pm_print_states(rdev);
ce8f5370 1038 radeon_pm_init_profile(rdev);
ed18a360 1039 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 1040 if ((rdev->family >= CHIP_BARTS) &&
c6cf7777 1041 (rdev->family <= CHIP_HAINAN) &&
2e3b3b10 1042 rdev->mc_fw) {
ed18a360 1043 if (rdev->pm.default_vddc)
8a83ec5e
AD		 1044 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1045 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 1046 if (rdev->pm.default_vddci)
1047 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1048 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 1049 if (rdev->pm.default_sclk)
1050 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1051 if (rdev->pm.default_mclk)
1052 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1053 }
56278a8e
AD		 1054 }
1055
21a8122a 1056 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 1057 ret = radeon_hwmon_init(rdev);
1058 if (ret)
1059 return ret;
32c87fca
TH		 1060
1061 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1062
ce8f5370 1063 if (rdev->pm.num_power_states > 1) {
ce8f5370 1064 /* where's the best place to put these? */
26481fb1
DA		 1065 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1066 if (ret)
1067 DRM_ERROR("failed to create device file for power profile\n");
1068 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1069 if (ret)
1070 DRM_ERROR("failed to create device file for power method\n");
a424816f 1071
ce8f5370
AD		 1072 if (radeon_debugfs_pm_init(rdev)) {
1073 DRM_ERROR("Failed to register debugfs file for PM!\n");
1074 }
c913e23a 1075
ce8f5370
AD		 1076 DRM_INFO("radeon: power management initialized\n");
1077 }
c913e23a 1078
7433874e
RM		 1079 return 0;
1080}
1081
da321c8a
AD		 1082static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1083{
1084 int i;
1085
1086 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1087 printk("== power state %d ==\n", i);
1088 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1089 }
1090}
1091
1092static int radeon_pm_init_dpm(struct radeon_device *rdev)
1093{
1094 int ret;
1095
1096 /* default to performance state */
edcaa5b1
AD		 1097 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1098 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
da321c8a
AD		 1099 rdev->pm.default_sclk = rdev->clock.default_sclk;
1100 rdev->pm.default_mclk = rdev->clock.default_mclk;
1101 rdev->pm.current_sclk = rdev->clock.default_sclk;
1102 rdev->pm.current_mclk = rdev->clock.default_mclk;
1103 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1104
1105 if (rdev->bios && rdev->is_atom_bios)
1106 radeon_atombios_get_power_modes(rdev);
1107 else
1108 return -EINVAL;
1109
1110 /* set up the internal thermal sensor if applicable */
1111 ret = radeon_hwmon_init(rdev);
1112 if (ret)
1113 return ret;
1114
1115 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1116 mutex_lock(&rdev->pm.mutex);
1117 radeon_dpm_init(rdev);
1118 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1119 radeon_dpm_print_power_states(rdev);
1120 radeon_dpm_setup_asic(rdev);
1121 ret = radeon_dpm_enable(rdev);
1122 mutex_unlock(&rdev->pm.mutex);
1123 if (ret) {
1124 rdev->pm.dpm_enabled = false;
1125 if ((rdev->family >= CHIP_BARTS) &&
c6cf7777 1126 (rdev->family <= CHIP_HAINAN) &&
da321c8a
AD		 1127 rdev->mc_fw) {
1128 if (rdev->pm.default_vddc)
1129 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1130 SET_VOLTAGE_TYPE_ASIC_VDDC);
1131 if (rdev->pm.default_vddci)
1132 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1133 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1134 if (rdev->pm.default_sclk)
1135 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1136 if (rdev->pm.default_mclk)
1137 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1138 }
1139 DRM_ERROR("radeon: dpm initialization failed\n");
1140 return ret;
1141 }
1142 rdev->pm.dpm_enabled = true;
1143 radeon_pm_compute_clocks(rdev);
1144
1145 if (rdev->pm.num_power_states > 1) {
1146 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
70d01a5e
AD		 1147 if (ret)
1148 DRM_ERROR("failed to create device file for dpm state\n");
1149 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
da321c8a
AD		 1150 if (ret)
1151 DRM_ERROR("failed to create device file for dpm state\n");
1152 /* XXX: these are noops for dpm but are here for backwards compat */
1153 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1154 if (ret)
1155 DRM_ERROR("failed to create device file for power profile\n");
1156 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1157 if (ret)
1158 DRM_ERROR("failed to create device file for power method\n");
1316b792
AD		 1159
1160 if (radeon_debugfs_pm_init(rdev)) {
1161 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1162 }
1163
da321c8a
AD		 1164 DRM_INFO("radeon: dpm initialized\n");
1165 }
1166
1167 return 0;
1168}
1169
1170int radeon_pm_init(struct radeon_device *rdev)
1171{
1172 /* enable dpm on rv6xx+ */
1173 switch (rdev->family) {
4a6369e9
AD		 1174 case CHIP_RV610:
1175 case CHIP_RV630:
1176 case CHIP_RV620:
1177 case CHIP_RV635:
1178 case CHIP_RV670:
9d67006e
AD		 1179 case CHIP_RS780:
1180 case CHIP_RS880:
66229b20
AD		 1181 case CHIP_RV770:
1182 case CHIP_RV730:
1183 case CHIP_RV710:
1184 case CHIP_RV740:
dc50ba7f
AD		 1185 case CHIP_CEDAR:
1186 case CHIP_REDWOOD:
1187 case CHIP_JUNIPER:
1188 case CHIP_CYPRESS:
1189 case CHIP_HEMLOCK:
80ea2c12
AD		 1190 case CHIP_PALM:
1191 case CHIP_SUMO:
1192 case CHIP_SUMO2:
6596afd4
AD		 1193 case CHIP_BARTS:
1194 case CHIP_TURKS:
1195 case CHIP_CAICOS:
69e0b57a 1196 case CHIP_CAYMAN:
d70229f7 1197 case CHIP_ARUBA:
a9e61410
AD		 1198 case CHIP_TAHITI:
1199 case CHIP_PITCAIRN:
1200 case CHIP_VERDE:
1201 case CHIP_OLAND:
1202 case CHIP_HAINAN:
8a53fa23 1203 /* DPM requires the RLC, RV770+ dGPU requires SMC */
761bfb99
AD		 1204 if (!rdev->rlc_fw)
1205 rdev->pm.pm_method = PM_METHOD_PROFILE;
8a53fa23
AD		 1206 else if ((rdev->family >= CHIP_RV770) &&
1207 (!(rdev->flags & RADEON_IS_IGP)) &&
1208 (!rdev->smc_fw))
1209 rdev->pm.pm_method = PM_METHOD_PROFILE;
761bfb99 1210 else if (radeon_dpm == 1)
9d67006e
AD		 1211 rdev->pm.pm_method = PM_METHOD_DPM;
1212 else
1213 rdev->pm.pm_method = PM_METHOD_PROFILE;
1214 break;
da321c8a
AD		 1215 default:
1216 /* default to profile method */
1217 rdev->pm.pm_method = PM_METHOD_PROFILE;
1218 break;
1219 }
1220
1221 if (rdev->pm.pm_method == PM_METHOD_DPM)
1222 return radeon_pm_init_dpm(rdev);
1223 else
1224 return radeon_pm_init_old(rdev);
1225}
1226
1227static void radeon_pm_fini_old(struct radeon_device *rdev)
29fb52ca 1228{
ce8f5370 1229 if (rdev->pm.num_power_states > 1) {
a424816f 1230 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 1231 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1232 rdev->pm.profile = PM_PROFILE_DEFAULT;
1233 radeon_pm_update_profile(rdev);
1234 radeon_pm_set_clocks(rdev);
1235 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 1236 /* reset default clocks */
1237 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1238 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1239 radeon_pm_set_clocks(rdev);
1240 }
a424816f 1241 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 1242
1243 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 1244
ce8f5370
AD		 1245 device_remove_file(rdev->dev, &dev_attr_power_profile);
1246 device_remove_file(rdev->dev, &dev_attr_power_method);
ce8f5370 1247 }
a424816f 1248
0975b162
AD		 1249 if (rdev->pm.power_state)
1250 kfree(rdev->pm.power_state);
1251
21a8122a 1252 radeon_hwmon_fini(rdev);
29fb52ca
AD		 1253}
1254
da321c8a
AD		 1255static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1256{
1257 if (rdev->pm.num_power_states > 1) {
1258 mutex_lock(&rdev->pm.mutex);
1259 radeon_dpm_disable(rdev);
1260 mutex_unlock(&rdev->pm.mutex);
1261
1262 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
70d01a5e 1263 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
da321c8a
AD		 1264 /* XXX backwards compat */
1265 device_remove_file(rdev->dev, &dev_attr_power_profile);
1266 device_remove_file(rdev->dev, &dev_attr_power_method);
1267 }
1268 radeon_dpm_fini(rdev);
1269
1270 if (rdev->pm.power_state)
1271 kfree(rdev->pm.power_state);
1272
1273 radeon_hwmon_fini(rdev);
1274}
1275
1276void radeon_pm_fini(struct radeon_device *rdev)
1277{
1278 if (rdev->pm.pm_method == PM_METHOD_DPM)
1279 radeon_pm_fini_dpm(rdev);
1280 else
1281 radeon_pm_fini_old(rdev);
1282}
1283
1284static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
c913e23a
RM		 1285{
1286 struct drm_device *ddev = rdev->ddev;
a48b9b4e 1287 struct drm_crtc *crtc;
c913e23a 1288 struct radeon_crtc *radeon_crtc;
c913e23a 1289
ce8f5370
AD		 1290 if (rdev->pm.num_power_states < 2)
1291 return;
1292
c913e23a
RM		 1293 mutex_lock(&rdev->pm.mutex);
1294
1295 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 1296 rdev->pm.active_crtc_count = 0;
1297 list_for_each_entry(crtc,
1298 &ddev->mode_config.crtc_list, head) {
1299 radeon_crtc = to_radeon_crtc(crtc);
1300 if (radeon_crtc->enabled) {
c913e23a 1301 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 1302 rdev->pm.active_crtc_count++;
c913e23a
RM		 1303 }
1304 }
1305
ce8f5370
AD		 1306 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1307 radeon_pm_update_profile(rdev);
1308 radeon_pm_set_clocks(rdev);
1309 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1310 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1311 if (rdev->pm.active_crtc_count > 1) {
1312 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1313 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1314
1315 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1316 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1317 radeon_pm_get_dynpm_state(rdev);
1318 radeon_pm_set_clocks(rdev);
1319
d9fdaafb 1320 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 1321 }
1322 } else if (rdev->pm.active_crtc_count == 1) {
1323 /* TODO: Increase clocks if needed for current mode */
1324
1325 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1326 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1327 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1328 radeon_pm_get_dynpm_state(rdev);
1329 radeon_pm_set_clocks(rdev);
1330
32c87fca
TH		 1331 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1332 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 1333 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1334 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1335 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1336 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 1337 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 1338 }
1339 } else { /* count == 0 */
1340 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1341 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1342
1343 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1344 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1345 radeon_pm_get_dynpm_state(rdev);
1346 radeon_pm_set_clocks(rdev);
1347 }
1348 }
c913e23a 1349 }
c913e23a 1350 }
73a6d3fc
RM		 1351
1352 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 1353}
1354
da321c8a
AD		 1355static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1356{
1357 struct drm_device *ddev = rdev->ddev;
1358 struct drm_crtc *crtc;
1359 struct radeon_crtc *radeon_crtc;
1360
1361 mutex_lock(&rdev->pm.mutex);
1362
5ca302f7 1363 /* update active crtc counts */
da321c8a
AD		 1364 rdev->pm.dpm.new_active_crtcs = 0;
1365 rdev->pm.dpm.new_active_crtc_count = 0;
1366 list_for_each_entry(crtc,
1367 &ddev->mode_config.crtc_list, head) {
1368 radeon_crtc = to_radeon_crtc(crtc);
1369 if (crtc->enabled) {
1370 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1371 rdev->pm.dpm.new_active_crtc_count++;
1372 }
1373 }
1374
5ca302f7
AD		 1375 /* update battery/ac status */
1376 if (power_supply_is_system_supplied() > 0)
1377 rdev->pm.dpm.ac_power = true;
1378 else
1379 rdev->pm.dpm.ac_power = false;
1380
da321c8a
AD		 1381 radeon_dpm_change_power_state_locked(rdev);
1382
1383 mutex_unlock(&rdev->pm.mutex);
8a227555 1384
da321c8a
AD		 1385}
1386
1387void radeon_pm_compute_clocks(struct radeon_device *rdev)
1388{
1389 if (rdev->pm.pm_method == PM_METHOD_DPM)
1390 radeon_pm_compute_clocks_dpm(rdev);
1391 else
1392 radeon_pm_compute_clocks_old(rdev);
1393}
1394
ce8f5370 1395static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 1396{
75fa0b08 1397 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 1398 bool in_vbl = true;
1399
75fa0b08
MK		 1400 /* Iterate over all active crtc's. All crtc's must be in vblank,
1401 * otherwise return in_vbl == false.
1402 */
1403 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1404 if (rdev->pm.active_crtcs & (1 << crtc)) {
f5a80209
MK		 1405 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
1406 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1407 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 1408 in_vbl = false;
1409 }
1410 }
f81f2024
MG		 1411
1412 return in_vbl;
1413}
1414
ce8f5370 1415static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 1416{
1417 u32 stat_crtc = 0;
1418 bool in_vbl = radeon_pm_in_vbl(rdev);
1419
f735261b 1420 if (in_vbl == false)
d9fdaafb 1421 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 1422 finish ? "exit" : "entry");
f735261b
DA		 1423 return in_vbl;
1424}
c913e23a 1425
ce8f5370 1426static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 1427{
1428 struct radeon_device *rdev;
d9932a32 1429 int resched;
c913e23a 1430 rdev = container_of(work, struct radeon_device,
ce8f5370 1431 pm.dynpm_idle_work.work);
c913e23a 1432
d9932a32 1433 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 1434 mutex_lock(&rdev->pm.mutex);
ce8f5370 1435 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 1436 int not_processed = 0;
7465280c
AD		 1437 int i;
1438
7465280c 1439 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0ec0612a
AD		 1440 struct radeon_ring *ring = &rdev->ring[i];
1441
1442 if (ring->ready) {
1443 not_processed += radeon_fence_count_emitted(rdev, i);
1444 if (not_processed >= 3)
1445 break;
1446 }
c913e23a 1447 }
c913e23a
RM		 1448
1449 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 1450 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1451 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1452 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1453 rdev->pm.dynpm_can_upclock) {
1454 rdev->pm.dynpm_planned_action =
1455 DYNPM_ACTION_UPCLOCK;
1456 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1457 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1458 }
1459 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 1460 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1461 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1462 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1463 rdev->pm.dynpm_can_downclock) {
1464 rdev->pm.dynpm_planned_action =
1465 DYNPM_ACTION_DOWNCLOCK;
1466 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1467 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1468 }
1469 }
1470
d7311171
AD		 1471 /* Note, radeon_pm_set_clocks is called with static_switch set
1472 * to false since we want to wait for vbl to avoid flicker.
1473 */
ce8f5370
AD		 1474 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1475 jiffies > rdev->pm.dynpm_action_timeout) {
1476 radeon_pm_get_dynpm_state(rdev);
1477 radeon_pm_set_clocks(rdev);
c913e23a 1478 }
3f53eb6f 1479
32c87fca
TH		 1480 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1481 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 1482 }
1483 mutex_unlock(&rdev->pm.mutex);
d9932a32 1484 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 1485}
1486
7433874e
RM		 1487/*
1488 * Debugfs info
1489 */
1490#if defined(CONFIG_DEBUG_FS)
1491
1492static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1493{
1494 struct drm_info_node *node = (struct drm_info_node *) m->private;
1495 struct drm_device *dev = node->minor->dev;
1496 struct radeon_device *rdev = dev->dev_private;
1497
1316b792
AD		 1498 if (rdev->pm.dpm_enabled) {
1499 mutex_lock(&rdev->pm.mutex);
1500 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1501 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1502 else
71375929 1503 seq_printf(m, "Debugfs support not implemented for this asic\n");
1316b792
AD		 1504 mutex_unlock(&rdev->pm.mutex);
1505 } else {
1506 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1507 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1508 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1509 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1510 else
1511 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1512 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1513 if (rdev->asic->pm.get_memory_clock)
1514 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1515 if (rdev->pm.current_vddc)
1516 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1517 if (rdev->asic->pm.get_pcie_lanes)
1518 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1519 }
7433874e
RM		 1520
1521 return 0;
1522}
1523
1524static struct drm_info_list radeon_pm_info_list[] = {
1525 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1526};
1527#endif
1528
c913e23a 1529static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 1530{
1531#if defined(CONFIG_DEBUG_FS)
1532 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1533#else
1534 return 0;
1535#endif
1536}
Linux 6.x block layer and io_uring tree(s)