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Merge branch 'devicetree/next' into spi/next
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e
RM		 22 */
23#include "drmP.h"
24#include "radeon.h"
f735261b 25#include "avivod.h"
ce8f5370
AD		 26#ifdef CONFIG_ACPI
27#include <linux/acpi.h>
28#endif
29#include <linux/power_supply.h>
21a8122a
AD		 30#include <linux/hwmon.h>
31#include <linux/hwmon-sysfs.h>
7433874e 32
c913e23a
RM		 33#define RADEON_IDLE_LOOP_MS 100
34#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 35#define RADEON_WAIT_VBLANK_TIMEOUT 200
2031f77c 36#define RADEON_WAIT_IDLE_TIMEOUT 200
c913e23a 37
f712d0c7
RM		 38static const char *radeon_pm_state_type_name[5] = {
39 "Default",
40 "Powersave",
41 "Battery",
42 "Balanced",
43 "Performance",
44};
45
ce8f5370 46static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 47static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 48static bool radeon_pm_in_vbl(struct radeon_device *rdev);
49static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
50static void radeon_pm_update_profile(struct radeon_device *rdev);
51static void radeon_pm_set_clocks(struct radeon_device *rdev);
52
53#define ACPI_AC_CLASS "ac_adapter"
54
55#ifdef CONFIG_ACPI
56static int radeon_acpi_event(struct notifier_block *nb,
57 unsigned long val,
58 void *data)
59{
60 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
61 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
62
63 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
64 if (power_supply_is_system_supplied() > 0)
d9fdaafb 65 DRM_DEBUG_DRIVER("pm: AC\n");
ce8f5370 66 else
d9fdaafb 67 DRM_DEBUG_DRIVER("pm: DC\n");
ce8f5370
AD		 68
69 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
70 if (rdev->pm.profile == PM_PROFILE_AUTO) {
71 mutex_lock(&rdev->pm.mutex);
72 radeon_pm_update_profile(rdev);
73 radeon_pm_set_clocks(rdev);
74 mutex_unlock(&rdev->pm.mutex);
75 }
76 }
77 }
78
79 return NOTIFY_OK;
80}
81#endif
82
83static void radeon_pm_update_profile(struct radeon_device *rdev)
84{
85 switch (rdev->pm.profile) {
86 case PM_PROFILE_DEFAULT:
87 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
88 break;
89 case PM_PROFILE_AUTO:
90 if (power_supply_is_system_supplied() > 0) {
91 if (rdev->pm.active_crtc_count > 1)
92 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
93 else
94 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
95 } else {
96 if (rdev->pm.active_crtc_count > 1)
c9e75b21 97 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 98 else
c9e75b21 99 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 100 }
101 break;
102 case PM_PROFILE_LOW:
103 if (rdev->pm.active_crtc_count > 1)
104 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
105 else
106 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
107 break;
c9e75b21
AD		 108 case PM_PROFILE_MID:
109 if (rdev->pm.active_crtc_count > 1)
110 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
111 else
112 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
113 break;
ce8f5370
AD		 114 case PM_PROFILE_HIGH:
115 if (rdev->pm.active_crtc_count > 1)
116 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
117 else
118 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
119 break;
120 }
121
122 if (rdev->pm.active_crtc_count == 0) {
123 rdev->pm.requested_power_state_index =
124 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
125 rdev->pm.requested_clock_mode_index =
126 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
127 } else {
128 rdev->pm.requested_power_state_index =
129 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
130 rdev->pm.requested_clock_mode_index =
131 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
132 }
133}
c913e23a 134
5876dd24
MG		 135static void radeon_unmap_vram_bos(struct radeon_device *rdev)
136{
137 struct radeon_bo *bo, *n;
138
139 if (list_empty(&rdev->gem.objects))
140 return;
141
142 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
143 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
144 ttm_bo_unmap_virtual(&bo->tbo);
145 }
5876dd24
MG		 146}
147
ce8f5370 148static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 149{
ce8f5370
AD		 150 if (rdev->pm.active_crtcs) {
151 rdev->pm.vblank_sync = false;
152 wait_event_timeout(
153 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
154 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
155 }
156}
157
158static void radeon_set_power_state(struct radeon_device *rdev)
159{
160 u32 sclk, mclk;
92645879 161 bool misc_after = false;
ce8f5370
AD		 162
163 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
164 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
165 return;
166
167 if (radeon_gui_idle(rdev)) {
168 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
169 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 170 if (sclk > rdev->pm.default_sclk)
171 sclk = rdev->pm.default_sclk;
ce8f5370
AD		 172
173 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
174 clock_info[rdev->pm.requested_clock_mode_index].mclk;
9ace9f7b
AD		 175 if (mclk > rdev->pm.default_mclk)
176 mclk = rdev->pm.default_mclk;
ce8f5370 177
92645879
AD		 178 /* upvolt before raising clocks, downvolt after lowering clocks */
179 if (sclk < rdev->pm.current_sclk)
180 misc_after = true;
ce8f5370 181
92645879 182 radeon_sync_with_vblank(rdev);
ce8f5370 183
92645879 184 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 185 if (!radeon_pm_in_vbl(rdev))
186 return;
92645879 187 }
ce8f5370 188
92645879 189 radeon_pm_prepare(rdev);
ce8f5370 190
92645879
AD		 191 if (!misc_after)
192 /* voltage, pcie lanes, etc.*/
193 radeon_pm_misc(rdev);
194
195 /* set engine clock */
196 if (sclk != rdev->pm.current_sclk) {
197 radeon_pm_debug_check_in_vbl(rdev, false);
198 radeon_set_engine_clock(rdev, sclk);
199 radeon_pm_debug_check_in_vbl(rdev, true);
200 rdev->pm.current_sclk = sclk;
d9fdaafb 201 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 202 }
203
204 /* set memory clock */
205 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
206 radeon_pm_debug_check_in_vbl(rdev, false);
207 radeon_set_memory_clock(rdev, mclk);
208 radeon_pm_debug_check_in_vbl(rdev, true);
209 rdev->pm.current_mclk = mclk;
d9fdaafb 210 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 211 }
2aba631c 212
92645879
AD		 213 if (misc_after)
214 /* voltage, pcie lanes, etc.*/
215 radeon_pm_misc(rdev);
216
217 radeon_pm_finish(rdev);
218
ce8f5370
AD		 219 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
220 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
221 } else
d9fdaafb 222 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 223}
224
225static void radeon_pm_set_clocks(struct radeon_device *rdev)
226{
227 int i;
c37d230a 228
4e186b2d
AD		 229 /* no need to take locks, etc. if nothing's going to change */
230 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
231 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
232 return;
233
612e06ce
MG		 234 mutex_lock(&rdev->ddev->struct_mutex);
235 mutex_lock(&rdev->vram_mutex);
a424816f 236 mutex_lock(&rdev->cp.mutex);
4f3218cb
AD		 237
238 /* gui idle int has issues on older chips it seems */
239 if (rdev->family >= CHIP_R600) {
ce8f5370
AD		 240 if (rdev->irq.installed) {
241 /* wait for GPU idle */
242 rdev->pm.gui_idle = false;
243 rdev->irq.gui_idle = true;
244 radeon_irq_set(rdev);
245 wait_event_interruptible_timeout(
246 rdev->irq.idle_queue, rdev->pm.gui_idle,
247 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
248 rdev->irq.gui_idle = false;
249 radeon_irq_set(rdev);
250 }
01434b4b 251 } else {
ce8f5370
AD		 252 if (rdev->cp.ready) {
253 struct radeon_fence *fence;
254 radeon_ring_alloc(rdev, 64);
255 radeon_fence_create(rdev, &fence);
256 radeon_fence_emit(rdev, fence);
257 radeon_ring_commit(rdev);
258 radeon_fence_wait(fence, false);
259 radeon_fence_unref(&fence);
260 }
4f3218cb 261 }
5876dd24
MG		 262 radeon_unmap_vram_bos(rdev);
263
ce8f5370 264 if (rdev->irq.installed) {
2aba631c
MG		 265 for (i = 0; i < rdev->num_crtc; i++) {
266 if (rdev->pm.active_crtcs & (1 << i)) {
267 rdev->pm.req_vblank |= (1 << i);
268 drm_vblank_get(rdev->ddev, i);
269 }
270 }
271 }
539d2418 272
ce8f5370 273 radeon_set_power_state(rdev);
2aba631c 274
ce8f5370 275 if (rdev->irq.installed) {
2aba631c
MG		 276 for (i = 0; i < rdev->num_crtc; i++) {
277 if (rdev->pm.req_vblank & (1 << i)) {
278 rdev->pm.req_vblank &= ~(1 << i);
279 drm_vblank_put(rdev->ddev, i);
280 }
281 }
282 }
5876dd24 283
a424816f
AD		 284 /* update display watermarks based on new power state */
285 radeon_update_bandwidth_info(rdev);
286 if (rdev->pm.active_crtc_count)
287 radeon_bandwidth_update(rdev);
288
ce8f5370 289 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 290
a424816f 291 mutex_unlock(&rdev->cp.mutex);
612e06ce
MG		 292 mutex_unlock(&rdev->vram_mutex);
293 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 294}
295
f712d0c7
RM		 296static void radeon_pm_print_states(struct radeon_device *rdev)
297{
298 int i, j;
299 struct radeon_power_state *power_state;
300 struct radeon_pm_clock_info *clock_info;
301
d9fdaafb 302 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 303 for (i = 0; i < rdev->pm.num_power_states; i++) {
304 power_state = &rdev->pm.power_state[i];
d9fdaafb 305 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 306 radeon_pm_state_type_name[power_state->type]);
307 if (i == rdev->pm.default_power_state_index)
d9fdaafb 308 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 309 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 310 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 311 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 312 DRM_DEBUG_DRIVER("\tSingle display only\n");
313 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 314 for (j = 0; j < power_state->num_clock_modes; j++) {
315 clock_info = &(power_state->clock_info[j]);
316 if (rdev->flags & RADEON_IS_IGP)
d9fdaafb 317 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
f712d0c7
RM		 318 j,
319 clock_info->sclk * 10,
320 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
321 else
d9fdaafb 322 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
f712d0c7
RM		 323 j,
324 clock_info->sclk * 10,
325 clock_info->mclk * 10,
326 clock_info->voltage.voltage,
327 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
328 }
329 }
330}
331
ce8f5370
AD		 332static ssize_t radeon_get_pm_profile(struct device *dev,
333 struct device_attribute *attr,
334 char *buf)
a424816f
AD		 335{
336 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
337 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 338 int cp = rdev->pm.profile;
a424816f 339
ce8f5370
AD		 340 return snprintf(buf, PAGE_SIZE, "%s\n",
341 (cp == PM_PROFILE_AUTO) ? "auto" :
342 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 343 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 344 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 345}
346
ce8f5370
AD		 347static ssize_t radeon_set_pm_profile(struct device *dev,
348 struct device_attribute *attr,
349 const char *buf,
350 size_t count)
a424816f
AD		 351{
352 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
353 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 354
355 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 356 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
357 if (strncmp("default", buf, strlen("default")) == 0)
358 rdev->pm.profile = PM_PROFILE_DEFAULT;
359 else if (strncmp("auto", buf, strlen("auto")) == 0)
360 rdev->pm.profile = PM_PROFILE_AUTO;
361 else if (strncmp("low", buf, strlen("low")) == 0)
362 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 363 else if (strncmp("mid", buf, strlen("mid")) == 0)
364 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 365 else if (strncmp("high", buf, strlen("high")) == 0)
366 rdev->pm.profile = PM_PROFILE_HIGH;
367 else {
368 DRM_ERROR("invalid power profile!\n");
369 goto fail;
a424816f 370 }
ce8f5370
AD		 371 radeon_pm_update_profile(rdev);
372 radeon_pm_set_clocks(rdev);
373 }
374fail:
a424816f
AD		 375 mutex_unlock(&rdev->pm.mutex);
376
377 return count;
378}
379
ce8f5370
AD		 380static ssize_t radeon_get_pm_method(struct device *dev,
381 struct device_attribute *attr,
382 char *buf)
a424816f
AD		 383{
384 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
385 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 386 int pm = rdev->pm.pm_method;
a424816f
AD		 387
388 return snprintf(buf, PAGE_SIZE, "%s\n",
ce8f5370 389 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
a424816f
AD		 390}
391
ce8f5370
AD		 392static ssize_t radeon_set_pm_method(struct device *dev,
393 struct device_attribute *attr,
394 const char *buf,
395 size_t count)
a424816f
AD		 396{
397 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
398 struct radeon_device *rdev = ddev->dev_private;
a424816f 399
ce8f5370
AD		 400
401 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 402 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 403 rdev->pm.pm_method = PM_METHOD_DYNPM;
404 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
405 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 406 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 407 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
408 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 409 /* disable dynpm */
410 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
411 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 412 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 413 mutex_unlock(&rdev->pm.mutex);
32c87fca 414 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370
AD		 415 } else {
416 DRM_ERROR("invalid power method!\n");
417 goto fail;
418 }
419 radeon_pm_compute_clocks(rdev);
420fail:
a424816f
AD		 421 return count;
422}
423
ce8f5370
AD		 424static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
425static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
a424816f 426
21a8122a
AD		 427static ssize_t radeon_hwmon_show_temp(struct device *dev,
428 struct device_attribute *attr,
429 char *buf)
430{
431 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
432 struct radeon_device *rdev = ddev->dev_private;
433 u32 temp;
434
435 switch (rdev->pm.int_thermal_type) {
436 case THERMAL_TYPE_RV6XX:
437 temp = rv6xx_get_temp(rdev);
438 break;
439 case THERMAL_TYPE_RV770:
440 temp = rv770_get_temp(rdev);
441 break;
442 case THERMAL_TYPE_EVERGREEN:
4fddba1f 443 case THERMAL_TYPE_NI:
21a8122a
AD		 444 temp = evergreen_get_temp(rdev);
445 break;
e33df25f
AD		 446 case THERMAL_TYPE_SUMO:
447 temp = sumo_get_temp(rdev);
448 break;
21a8122a
AD		 449 default:
450 temp = 0;
451 break;
452 }
453
454 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
455}
456
457static ssize_t radeon_hwmon_show_name(struct device *dev,
458 struct device_attribute *attr,
459 char *buf)
460{
461 return sprintf(buf, "radeon\n");
462}
463
464static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
465static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
466
467static struct attribute *hwmon_attributes[] = {
468 &sensor_dev_attr_temp1_input.dev_attr.attr,
469 &sensor_dev_attr_name.dev_attr.attr,
470 NULL
471};
472
473static const struct attribute_group hwmon_attrgroup = {
474 .attrs = hwmon_attributes,
475};
476
0d18abed 477static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 478{
0d18abed 479 int err = 0;
21a8122a
AD		 480
481 rdev->pm.int_hwmon_dev = NULL;
482
483 switch (rdev->pm.int_thermal_type) {
484 case THERMAL_TYPE_RV6XX:
485 case THERMAL_TYPE_RV770:
486 case THERMAL_TYPE_EVERGREEN:
e33df25f 487 case THERMAL_TYPE_SUMO:
21a8122a 488 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 489 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
490 err = PTR_ERR(rdev->pm.int_hwmon_dev);
491 dev_err(rdev->dev,
492 "Unable to register hwmon device: %d\n", err);
493 break;
494 }
21a8122a
AD		 495 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
496 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
497 &hwmon_attrgroup);
0d18abed
DC		 498 if (err) {
499 dev_err(rdev->dev,
500 "Unable to create hwmon sysfs file: %d\n", err);
501 hwmon_device_unregister(rdev->dev);
502 }
21a8122a
AD		 503 break;
504 default:
505 break;
506 }
0d18abed
DC		 507
508 return err;
21a8122a
AD		 509}
510
511static void radeon_hwmon_fini(struct radeon_device *rdev)
512{
513 if (rdev->pm.int_hwmon_dev) {
514 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
515 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
516 }
517}
518
ce8f5370 519void radeon_pm_suspend(struct radeon_device *rdev)
56278a8e 520{
ce8f5370 521 mutex_lock(&rdev->pm.mutex);
3f53eb6f 522 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 523 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
524 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 525 }
ce8f5370 526 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 527
528 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 529}
530
ce8f5370 531void radeon_pm_resume(struct radeon_device *rdev)
d0d6cb81 532{
ed18a360
AD		 533 /* set up the default clocks if the MC ucode is loaded */
534 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
535 if (rdev->pm.default_vddc)
536 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc);
537 if (rdev->pm.default_sclk)
538 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
539 if (rdev->pm.default_mclk)
540 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
541 }
f8ed8b4c
AD		 542 /* asic init will reset the default power state */
543 mutex_lock(&rdev->pm.mutex);
544 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
545 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 546 rdev->pm.current_sclk = rdev->pm.default_sclk;
547 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 548 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
3f53eb6f
RW		 549 if (rdev->pm.pm_method == PM_METHOD_DYNPM
550 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
551 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 552 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
553 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 554 }
f8ed8b4c 555 mutex_unlock(&rdev->pm.mutex);
ce8f5370 556 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 557}
558
7433874e
RM		 559int radeon_pm_init(struct radeon_device *rdev)
560{
26481fb1 561 int ret;
0d18abed 562
ce8f5370
AD		 563 /* default to profile method */
564 rdev->pm.pm_method = PM_METHOD_PROFILE;
f8ed8b4c 565 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 566 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
567 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
568 rdev->pm.dynpm_can_upclock = true;
569 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 570 rdev->pm.default_sclk = rdev->clock.default_sclk;
571 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 572 rdev->pm.current_sclk = rdev->clock.default_sclk;
573 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 574 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 575
56278a8e
AD		 576 if (rdev->bios) {
577 if (rdev->is_atom_bios)
578 radeon_atombios_get_power_modes(rdev);
579 else
580 radeon_combios_get_power_modes(rdev);
f712d0c7 581 radeon_pm_print_states(rdev);
ce8f5370 582 radeon_pm_init_profile(rdev);
ed18a360
AD		 583 /* set up the default clocks if the MC ucode is loaded */
584 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
585 if (rdev->pm.default_vddc)
586 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc);
587 if (rdev->pm.default_sclk)
588 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
589 if (rdev->pm.default_mclk)
590 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
591 }
56278a8e
AD		 592 }
593
21a8122a 594 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 595 ret = radeon_hwmon_init(rdev);
596 if (ret)
597 return ret;
32c87fca
TH		 598
599 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
600
ce8f5370 601 if (rdev->pm.num_power_states > 1) {
ce8f5370 602 /* where's the best place to put these? */
26481fb1
DA		 603 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
604 if (ret)
605 DRM_ERROR("failed to create device file for power profile\n");
606 ret = device_create_file(rdev->dev, &dev_attr_power_method);
607 if (ret)
608 DRM_ERROR("failed to create device file for power method\n");
a424816f 609
ce8f5370
AD		 610#ifdef CONFIG_ACPI
611 rdev->acpi_nb.notifier_call = radeon_acpi_event;
612 register_acpi_notifier(&rdev->acpi_nb);
613#endif
ce8f5370
AD		 614 if (radeon_debugfs_pm_init(rdev)) {
615 DRM_ERROR("Failed to register debugfs file for PM!\n");
616 }
c913e23a 617
ce8f5370
AD		 618 DRM_INFO("radeon: power management initialized\n");
619 }
c913e23a 620
7433874e
RM		 621 return 0;
622}
623
29fb52ca
AD		 624void radeon_pm_fini(struct radeon_device *rdev)
625{
ce8f5370 626 if (rdev->pm.num_power_states > 1) {
a424816f 627 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 628 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
629 rdev->pm.profile = PM_PROFILE_DEFAULT;
630 radeon_pm_update_profile(rdev);
631 radeon_pm_set_clocks(rdev);
632 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 633 /* reset default clocks */
634 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
635 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
636 radeon_pm_set_clocks(rdev);
637 }
a424816f 638 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 639
640 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 641
ce8f5370
AD		 642 device_remove_file(rdev->dev, &dev_attr_power_profile);
643 device_remove_file(rdev->dev, &dev_attr_power_method);
644#ifdef CONFIG_ACPI
645 unregister_acpi_notifier(&rdev->acpi_nb);
646#endif
647 }
a424816f 648
21a8122a 649 radeon_hwmon_fini(rdev);
29fb52ca
AD		 650}
651
c913e23a
RM		 652void radeon_pm_compute_clocks(struct radeon_device *rdev)
653{
654 struct drm_device *ddev = rdev->ddev;
a48b9b4e 655 struct drm_crtc *crtc;
c913e23a 656 struct radeon_crtc *radeon_crtc;
c913e23a 657
ce8f5370
AD		 658 if (rdev->pm.num_power_states < 2)
659 return;
660
c913e23a
RM		 661 mutex_lock(&rdev->pm.mutex);
662
663 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 664 rdev->pm.active_crtc_count = 0;
665 list_for_each_entry(crtc,
666 &ddev->mode_config.crtc_list, head) {
667 radeon_crtc = to_radeon_crtc(crtc);
668 if (radeon_crtc->enabled) {
c913e23a 669 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 670 rdev->pm.active_crtc_count++;
c913e23a
RM		 671 }
672 }
673
ce8f5370
AD		 674 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
675 radeon_pm_update_profile(rdev);
676 radeon_pm_set_clocks(rdev);
677 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
678 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
679 if (rdev->pm.active_crtc_count > 1) {
680 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
681 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
682
683 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
684 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
685 radeon_pm_get_dynpm_state(rdev);
686 radeon_pm_set_clocks(rdev);
687
d9fdaafb 688 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 689 }
690 } else if (rdev->pm.active_crtc_count == 1) {
691 /* TODO: Increase clocks if needed for current mode */
692
693 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
694 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
695 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
696 radeon_pm_get_dynpm_state(rdev);
697 radeon_pm_set_clocks(rdev);
698
32c87fca
TH		 699 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
700 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 701 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
702 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 703 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
704 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 705 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 706 }
707 } else { /* count == 0 */
708 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
709 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
710
711 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
712 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
713 radeon_pm_get_dynpm_state(rdev);
714 radeon_pm_set_clocks(rdev);
715 }
716 }
c913e23a 717 }
c913e23a 718 }
73a6d3fc
RM		 719
720 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 721}
722
ce8f5370 723static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 724{
75fa0b08 725 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 726 bool in_vbl = true;
727
75fa0b08
MK		 728 /* Iterate over all active crtc's. All crtc's must be in vblank,
729 * otherwise return in_vbl == false.
730 */
731 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
732 if (rdev->pm.active_crtcs & (1 << crtc)) {
f5a80209
MK		 733 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
734 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
735 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 736 in_vbl = false;
737 }
738 }
f81f2024
MG		 739
740 return in_vbl;
741}
742
ce8f5370 743static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 744{
745 u32 stat_crtc = 0;
746 bool in_vbl = radeon_pm_in_vbl(rdev);
747
f735261b 748 if (in_vbl == false)
d9fdaafb 749 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 750 finish ? "exit" : "entry");
f735261b
DA		 751 return in_vbl;
752}
c913e23a 753
ce8f5370 754static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 755{
756 struct radeon_device *rdev;
d9932a32 757 int resched;
c913e23a 758 rdev = container_of(work, struct radeon_device,
ce8f5370 759 pm.dynpm_idle_work.work);
c913e23a 760
d9932a32 761 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 762 mutex_lock(&rdev->pm.mutex);
ce8f5370 763 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a
RM		 764 unsigned long irq_flags;
765 int not_processed = 0;
766
767 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
768 if (!list_empty(&rdev->fence_drv.emited)) {
769 struct list_head *ptr;
770 list_for_each(ptr, &rdev->fence_drv.emited) {
771 /* count up to 3, that's enought info */
772 if (++not_processed >= 3)
773 break;
774 }
775 }
776 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
777
778 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 779 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
780 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
781 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
782 rdev->pm.dynpm_can_upclock) {
783 rdev->pm.dynpm_planned_action =
784 DYNPM_ACTION_UPCLOCK;
785 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 786 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
787 }
788 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 789 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
790 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
791 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
792 rdev->pm.dynpm_can_downclock) {
793 rdev->pm.dynpm_planned_action =
794 DYNPM_ACTION_DOWNCLOCK;
795 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 796 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
797 }
798 }
799
d7311171
AD		 800 /* Note, radeon_pm_set_clocks is called with static_switch set
801 * to false since we want to wait for vbl to avoid flicker.
802 */
ce8f5370
AD		 803 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
804 jiffies > rdev->pm.dynpm_action_timeout) {
805 radeon_pm_get_dynpm_state(rdev);
806 radeon_pm_set_clocks(rdev);
c913e23a 807 }
3f53eb6f 808
32c87fca
TH		 809 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
810 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 811 }
812 mutex_unlock(&rdev->pm.mutex);
d9932a32 813 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 814}
815
7433874e
RM		 816/*
817 * Debugfs info
818 */
819#if defined(CONFIG_DEBUG_FS)
820
821static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
822{
823 struct drm_info_node *node = (struct drm_info_node *) m->private;
824 struct drm_device *dev = node->minor->dev;
825 struct radeon_device *rdev = dev->dev_private;
826
9ace9f7b 827 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
6234077d 828 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
9ace9f7b 829 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
6234077d
RM		 830 if (rdev->asic->get_memory_clock)
831 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 832 if (rdev->pm.current_vddc)
833 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
aa5120d2
RM		 834 if (rdev->asic->get_pcie_lanes)
835 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 836
837 return 0;
838}
839
840static struct drm_info_list radeon_pm_info_list[] = {
841 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
842};
843#endif
844
c913e23a 845static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 846{
847#if defined(CONFIG_DEBUG_FS)
848 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
849#else
850 return 0;
851#endif
852}
Linux 6.x block layer and io_uring tree(s)