[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_object.c

/*
 * Copyright 2009 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
 *    Dave Airlie
 */
#include <linux/list.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include "radeon_drm.h"
#include "radeon.h"
#include "radeon_trace.h"


int radeon_ttm_init(struct radeon_device *rdev);
void radeon_ttm_fini(struct radeon_device *rdev);
static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);

/*
 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
 * function are calling it.
 */

static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
{
	struct radeon_bo *bo;

	bo = container_of(tbo, struct radeon_bo, tbo);
	mutex_lock(&bo->rdev->gem.mutex);
	list_del_init(&bo->list);
	mutex_unlock(&bo->rdev->gem.mutex);
	radeon_bo_clear_surface_reg(bo);
	drm_gem_object_release(&bo->gem_base);
	kfree(bo);
}

bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
{
	if (bo->destroy == &radeon_ttm_bo_destroy)
		return true;
	return false;
}

void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
{
	u32 c = 0;

	rbo->placement.fpfn = 0;
	rbo->placement.lpfn = 0;
	rbo->placement.placement = rbo->placements;
	rbo->placement.busy_placement = rbo->placements;
	if (domain & RADEON_GEM_DOMAIN_VRAM)
		rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
					TTM_PL_FLAG_VRAM;
	if (domain & RADEON_GEM_DOMAIN_GTT)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
	if (domain & RADEON_GEM_DOMAIN_CPU)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
	if (!c)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
	rbo->placement.num_placement = c;
	rbo->placement.num_busy_placement = c;
}

int radeon_bo_create(struct radeon_device *rdev,
		     unsigned long size, int byte_align, bool kernel, u32 domain,
		     struct radeon_bo **bo_ptr)
{
	struct radeon_bo *bo;
	enum ttm_bo_type type;
	unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
	unsigned long max_size = 0;
	int r;

	size = ALIGN(size, PAGE_SIZE);

	if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
		rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
	}
	if (kernel) {
		type = ttm_bo_type_kernel;
	} else {
		type = ttm_bo_type_device;
	}
	*bo_ptr = NULL;

	/* maximun bo size is the minimun btw visible vram and gtt size */
	max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
	if ((page_align << PAGE_SHIFT) >= max_size) {
		printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
			__func__, __LINE__, page_align  >> (20 - PAGE_SHIFT), max_size >> 20);
		return -ENOMEM;
	}

retry:
	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
	if (bo == NULL)
		return -ENOMEM;
	r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
	if (unlikely(r)) {
		kfree(bo);
		return r;
	}
	bo->rdev = rdev;
	bo->gobj = &bo->gem_base;
	bo->gem_base.driver_private = bo;
	bo->surface_reg = -1;
	INIT_LIST_HEAD(&bo->list);
	radeon_ttm_placement_from_domain(bo, domain);
	/* Kernel allocation are uninterruptible */
	mutex_lock(&rdev->vram_mutex);
	r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
			&bo->placement, page_align, 0, !kernel, NULL, size,
			&radeon_ttm_bo_destroy);
	mutex_unlock(&rdev->vram_mutex);
	if (unlikely(r != 0)) {
		if (r != -ERESTARTSYS) {
			if (domain == RADEON_GEM_DOMAIN_VRAM) {
				domain |= RADEON_GEM_DOMAIN_GTT;
				goto retry;
			}
			dev_err(rdev->dev,
				"object_init failed for (%lu, 0x%08X)\n",
				size, domain);
		}
		return r;
	}
	*bo_ptr = bo;

	trace_radeon_bo_create(bo);

	return 0;
}

int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
{
	bool is_iomem;
	int r;

	if (bo->kptr) {
		if (ptr) {
			*ptr = bo->kptr;
		}
		return 0;
	}
	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
	if (r) {
		return r;
	}
	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
	if (ptr) {
		*ptr = bo->kptr;
	}
	radeon_bo_check_tiling(bo, 0, 0);
	return 0;
}

void radeon_bo_kunmap(struct radeon_bo *bo)
{
	if (bo->kptr == NULL)
		return;
	bo->kptr = NULL;
	radeon_bo_check_tiling(bo, 0, 0);
	ttm_bo_kunmap(&bo->kmap);
}

void radeon_bo_unref(struct radeon_bo **bo)
{
	struct ttm_buffer_object *tbo;
	struct radeon_device *rdev;

	if ((*bo) == NULL)
		return;
	rdev = (*bo)->rdev;
	tbo = &((*bo)->tbo);
	mutex_lock(&rdev->vram_mutex);
	ttm_bo_unref(&tbo);
	mutex_unlock(&rdev->vram_mutex);
	if (tbo == NULL)
		*bo = NULL;
}

int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
{
	int r, i;

	if (bo->pin_count) {
		bo->pin_count++;
		if (gpu_addr)
			*gpu_addr = radeon_bo_gpu_offset(bo);
		return 0;
	}
	radeon_ttm_placement_from_domain(bo, domain);
	if (domain == RADEON_GEM_DOMAIN_VRAM) {
		/* force to pin into visible video ram */
		bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
	}
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
	if (likely(r == 0)) {
		bo->pin_count = 1;
		if (gpu_addr != NULL)
			*gpu_addr = radeon_bo_gpu_offset(bo);
	}
	if (unlikely(r != 0))
		dev_err(bo->rdev->dev, "%p pin failed\n", bo);
	return r;
}

int radeon_bo_unpin(struct radeon_bo *bo)
{
	int r, i;

	if (!bo->pin_count) {
		dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
		return 0;
	}
	bo->pin_count--;
	if (bo->pin_count)
		return 0;
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
	if (unlikely(r != 0))
		dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
	return r;
}

int radeon_bo_evict_vram(struct radeon_device *rdev)
{
	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
	if (0 && (rdev->flags & RADEON_IS_IGP)) {
		if (rdev->mc.igp_sideport_enabled == false)
			/* Useless to evict on IGP chips */
			return 0;
	}
	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
}

void radeon_bo_force_delete(struct radeon_device *rdev)
{
	struct radeon_bo *bo, *n;
	struct drm_gem_object *gobj;

	if (list_empty(&rdev->gem.objects)) {
		return;
	}
	dev_err(rdev->dev, "Userspace still has active objects !\n");
	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
		mutex_lock(&rdev->ddev->struct_mutex);
		gobj = bo->gobj;
		dev_err(rdev->dev, "%p %p %lu %lu force free\n",
			gobj, bo, (unsigned long)gobj->size,
			*((unsigned long *)&gobj->refcount));
		mutex_lock(&bo->rdev->gem.mutex);
		list_del_init(&bo->list);
		mutex_unlock(&bo->rdev->gem.mutex);
		radeon_bo_unref(&bo);
		gobj->driver_private = NULL;
		drm_gem_object_unreference(gobj);
		mutex_unlock(&rdev->ddev->struct_mutex);
	}
}

int radeon_bo_init(struct radeon_device *rdev)
{
	/* Add an MTRR for the VRAM */
	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
			MTRR_TYPE_WRCOMB, 1);
	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
		rdev->mc.mc_vram_size >> 20,
		(unsigned long long)rdev->mc.aper_size >> 20);
	DRM_INFO("RAM width %dbits %cDR\n",
			rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
	return radeon_ttm_init(rdev);
}

void radeon_bo_fini(struct radeon_device *rdev)
{
	radeon_ttm_fini(rdev);
}

void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
				struct list_head *head)
{
	if (lobj->wdomain) {
		list_add(&lobj->tv.head, head);
	} else {
		list_add_tail(&lobj->tv.head, head);
	}
}

int radeon_bo_list_validate(struct list_head *head)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	u32 domain;
	int r;

	r = ttm_eu_reserve_buffers(head);
	if (unlikely(r != 0)) {
		return r;
	}
	list_for_each_entry(lobj, head, tv.head) {
		bo = lobj->bo;
		if (!bo->pin_count) {
			domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
			
		retry:
			radeon_ttm_placement_from_domain(bo, domain);
			r = ttm_bo_validate(&bo->tbo, &bo->placement,
						true, false, false);
			if (unlikely(r)) {
				if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
					domain |= RADEON_GEM_DOMAIN_GTT;
					goto retry;
				}
				return r;
			}
		}
		lobj->gpu_offset = radeon_bo_gpu_offset(bo);
		lobj->tiling_flags = bo->tiling_flags;
	}
	return 0;
}

int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
			     struct vm_area_struct *vma)
{
	return ttm_fbdev_mmap(vma, &bo->tbo);
}

int radeon_bo_get_surface_reg(struct radeon_bo *bo)
{
	struct radeon_device *rdev = bo->rdev;
	struct radeon_surface_reg *reg;
	struct radeon_bo *old_object;
	int steal;
	int i;

	BUG_ON(!atomic_read(&bo->tbo.reserved));

	if (!bo->tiling_flags)
		return 0;

	if (bo->surface_reg >= 0) {
		reg = &rdev->surface_regs[bo->surface_reg];
		i = bo->surface_reg;
		goto out;
	}

	steal = -1;
	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {

		reg = &rdev->surface_regs[i];
		if (!reg->bo)
			break;

		old_object = reg->bo;
		if (old_object->pin_count == 0)
			steal = i;
	}

	/* if we are all out */
	if (i == RADEON_GEM_MAX_SURFACES) {
		if (steal == -1)
			return -ENOMEM;
		/* find someone with a surface reg and nuke their BO */
		reg = &rdev->surface_regs[steal];
		old_object = reg->bo;
		/* blow away the mapping */
		DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
		ttm_bo_unmap_virtual(&old_object->tbo);
		old_object->surface_reg = -1;
		i = steal;
	}

	bo->surface_reg = i;
	reg->bo = bo;

out:
	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
			       bo->tbo.mem.start << PAGE_SHIFT,
			       bo->tbo.num_pages << PAGE_SHIFT);
	return 0;
}

static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
{
	struct radeon_device *rdev = bo->rdev;
	struct radeon_surface_reg *reg;

	if (bo->surface_reg == -1)
		return;

	reg = &rdev->surface_regs[bo->surface_reg];
	radeon_clear_surface_reg(rdev, bo->surface_reg);

	reg->bo = NULL;
	bo->surface_reg = -1;
}

int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
				uint32_t tiling_flags, uint32_t pitch)
{
	int r;

	r = radeon_bo_reserve(bo, false);
	if (unlikely(r != 0))
		return r;
	bo->tiling_flags = tiling_flags;
	bo->pitch = pitch;
	radeon_bo_unreserve(bo);
	return 0;
}

void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
				uint32_t *tiling_flags,
				uint32_t *pitch)
{
	BUG_ON(!atomic_read(&bo->tbo.reserved));
	if (tiling_flags)
		*tiling_flags = bo->tiling_flags;
	if (pitch)
		*pitch = bo->pitch;
}

int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
				bool force_drop)
{
	BUG_ON(!atomic_read(&bo->tbo.reserved));

	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
		return 0;

	if (force_drop) {
		radeon_bo_clear_surface_reg(bo);
		return 0;
	}

	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
		if (!has_moved)
			return 0;

		if (bo->surface_reg >= 0)
			radeon_bo_clear_surface_reg(bo);
		return 0;
	}

	if ((bo->surface_reg >= 0) && !has_moved)
		return 0;

	return radeon_bo_get_surface_reg(bo);
}

void radeon_bo_move_notify(struct ttm_buffer_object *bo,
			   struct ttm_mem_reg *mem)
{
	struct radeon_bo *rbo;
	if (!radeon_ttm_bo_is_radeon_bo(bo))
		return;
	rbo = container_of(bo, struct radeon_bo, tbo);
	radeon_bo_check_tiling(rbo, 0, 1);
}

int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
{
	struct radeon_device *rdev;
	struct radeon_bo *rbo;
	unsigned long offset, size;
	int r;

	if (!radeon_ttm_bo_is_radeon_bo(bo))
		return 0;
	rbo = container_of(bo, struct radeon_bo, tbo);
	radeon_bo_check_tiling(rbo, 0, 0);
	rdev = rbo->rdev;
	if (bo->mem.mem_type == TTM_PL_VRAM) {
		size = bo->mem.num_pages << PAGE_SHIFT;
		offset = bo->mem.start << PAGE_SHIFT;
		if ((offset + size) > rdev->mc.visible_vram_size) {
			/* hurrah the memory is not visible ! */
			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
			rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
			r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
			if (unlikely(r != 0))
				return r;
			offset = bo->mem.start << PAGE_SHIFT;
			/* this should not happen */
			if ((offset + size) > rdev->mc.visible_vram_size)
				return -EINVAL;
		}
	}
	return 0;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2009 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	*/
	26	/*
	27	* Authors:
	28	* Jerome Glisse <glisse@freedesktop.org>
	29	* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
	30	* Dave Airlie
	31	*/
	32	#include <linux/list.h>
5a0e3ad6	33	#include <linux/slab.h>
771fe6b9 JG	34	#include <drm/drmP.h>
	35	#include "radeon_drm.h"
	36	#include "radeon.h"
99ee7fac	37	#include "radeon_trace.h"
771fe6b9	38
771fe6b9 JG	39
	40	int radeon_ttm_init(struct radeon_device *rdev);
	41	void radeon_ttm_fini(struct radeon_device *rdev);
4c788679	42	static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
771fe6b9 JG	43
	44	/*
	45	* To exclude mutual BO access we rely on bo_reserve exclusion, as all
	46	* function are calling it.
	47	*/
	48
4c788679	49	static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
771fe6b9	50	{
4c788679	51	struct radeon_bo *bo;
771fe6b9	52
4c788679 JG	53	bo = container_of(tbo, struct radeon_bo, tbo);
	54	mutex_lock(&bo->rdev->gem.mutex);
	55	list_del_init(&bo->list);
	56	mutex_unlock(&bo->rdev->gem.mutex);
	57	radeon_bo_clear_surface_reg(bo);
441921d5	58	drm_gem_object_release(&bo->gem_base);
4c788679	59	kfree(bo);
771fe6b9 JG	60	}
771fe6b9 JG	61
d03d8589 JG	62	bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
	63	{
	64	if (bo->destroy == &radeon_ttm_bo_destroy)
	65	return true;
	66	return false;
	67	}
	68
312ea8da JG	69	void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
	70	{
	71	u32 c = 0;
	72
	73	rbo->placement.fpfn = 0;
93225b0d	74	rbo->placement.lpfn = 0;
312ea8da JG	75	rbo->placement.placement = rbo->placements;
	76	rbo->placement.busy_placement = rbo->placements;
	77	if (domain & RADEON_GEM_DOMAIN_VRAM)
	78	rbo->placements[c++] = TTM_PL_FLAG_WC \| TTM_PL_FLAG_UNCACHED \|
	79	TTM_PL_FLAG_VRAM;
	80	if (domain & RADEON_GEM_DOMAIN_GTT)
	81	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_TT;
	82	if (domain & RADEON_GEM_DOMAIN_CPU)
	83	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_SYSTEM;
9fb03e63 JG	84	if (!c)
9fb03e63 JG	85	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_SYSTEM;
312ea8da JG	86	rbo->placement.num_placement = c;
	87	rbo->placement.num_busy_placement = c;
	88	}
	89
441921d5	90	int radeon_bo_create(struct radeon_device *rdev,
268b2510 AD	91	unsigned long size, int byte_align, bool kernel, u32 domain,
268b2510 AD	92	struct radeon_bo **bo_ptr)
771fe6b9	93	{
4c788679	94	struct radeon_bo *bo;
771fe6b9	95	enum ttm_bo_type type;
93225b0d JG	96	unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
93225b0d JG	97	unsigned long max_size = 0;
771fe6b9 JG	98	int r;
771fe6b9 JG	99
441921d5 DV	100	size = ALIGN(size, PAGE_SIZE);
441921d5 DV	101
771fe6b9 JG	102	if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
	103	rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
	104	}
	105	if (kernel) {
	106	type = ttm_bo_type_kernel;
	107	} else {
	108	type = ttm_bo_type_device;
	109	}
4c788679	110	*bo_ptr = NULL;
2b66b50b	111
93225b0d JG	112	/* maximun bo size is the minimun btw visible vram and gtt size */
	113	max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
	114	if ((page_align << PAGE_SHIFT) >= max_size) {
	115	printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
	116	__func__, __LINE__, page_align >> (20 - PAGE_SHIFT), max_size >> 20);
	117	return -ENOMEM;
	118	}
	119
2b66b50b	120	retry:
4c788679 JG	121	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
4c788679 JG	122	if (bo == NULL)
771fe6b9	123	return -ENOMEM;
441921d5 DV	124	r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
	125	if (unlikely(r)) {
	126	kfree(bo);
	127	return r;
	128	}
4c788679	129	bo->rdev = rdev;
441921d5 DV	130	bo->gobj = &bo->gem_base;
441921d5 DV	131	bo->gem_base.driver_private = bo;
4c788679 JG	132	bo->surface_reg = -1;
4c788679 JG	133	INIT_LIST_HEAD(&bo->list);
1fb107fc	134	radeon_ttm_placement_from_domain(bo, domain);
5cc6fbab	135	/* Kernel allocation are uninterruptible */
5876dd24	136	mutex_lock(&rdev->vram_mutex);
1fb107fc	137	r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
268b2510	138	&bo->placement, page_align, 0, !kernel, NULL, size,
1fb107fc	139	&radeon_ttm_bo_destroy);
5876dd24	140	mutex_unlock(&rdev->vram_mutex);
771fe6b9	141	if (unlikely(r != 0)) {
e376573f MD	142	if (r != -ERESTARTSYS) {
	143	if (domain == RADEON_GEM_DOMAIN_VRAM) {
	144	domain \|= RADEON_GEM_DOMAIN_GTT;
	145	goto retry;
	146	}
5cc6fbab	147	dev_err(rdev->dev,
1fb107fc JG	148	"object_init failed for (%lu, 0x%08X)\n",
1fb107fc JG	149	size, domain);
e376573f	150	}
771fe6b9 JG	151	return r;
771fe6b9 JG	152	}
4c788679	153	*bo_ptr = bo;
441921d5	154
99ee7fac	155	trace_radeon_bo_create(bo);
441921d5	156
771fe6b9 JG	157	return 0;
	158	}
	159
4c788679	160	int radeon_bo_kmap(struct radeon_bo bo, void *ptr)
771fe6b9	161	{
4c788679	162	bool is_iomem;
771fe6b9 JG	163	int r;
771fe6b9 JG	164
4c788679	165	if (bo->kptr) {
771fe6b9	166	if (ptr) {
4c788679	167	*ptr = bo->kptr;
771fe6b9	168	}
771fe6b9 JG	169	return 0;
771fe6b9 JG	170	}
4c788679	171	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
771fe6b9 JG	172	if (r) {
	173	return r;
	174	}
4c788679	175	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
771fe6b9	176	if (ptr) {
4c788679	177	*ptr = bo->kptr;
771fe6b9	178	}
4c788679	179	radeon_bo_check_tiling(bo, 0, 0);
771fe6b9 JG	180	return 0;
	181	}
	182
4c788679	183	void radeon_bo_kunmap(struct radeon_bo *bo)
771fe6b9	184	{
4c788679	185	if (bo->kptr == NULL)
771fe6b9	186	return;
4c788679 JG	187	bo->kptr = NULL;
	188	radeon_bo_check_tiling(bo, 0, 0);
	189	ttm_bo_kunmap(&bo->kmap);
771fe6b9 JG	190	}
771fe6b9 JG	191
4c788679	192	void radeon_bo_unref(struct radeon_bo **bo)
771fe6b9	193	{
4c788679	194	struct ttm_buffer_object *tbo;
f4b7fb94	195	struct radeon_device *rdev;
771fe6b9	196
4c788679	197	if ((*bo) == NULL)
771fe6b9	198	return;
f4b7fb94	199	rdev = (*bo)->rdev;
4c788679	200	tbo = &((*bo)->tbo);
f4b7fb94	201	mutex_lock(&rdev->vram_mutex);
4c788679	202	ttm_bo_unref(&tbo);
f4b7fb94	203	mutex_unlock(&rdev->vram_mutex);
4c788679 JG	204	if (tbo == NULL)
4c788679 JG	205	*bo = NULL;
771fe6b9 JG	206	}
771fe6b9 JG	207
4c788679	208	int radeon_bo_pin(struct radeon_bo bo, u32 domain, u64 gpu_addr)
771fe6b9	209	{
312ea8da	210	int r, i;
771fe6b9	211
4c788679 JG	212	if (bo->pin_count) {
	213	bo->pin_count++;
	214	if (gpu_addr)
	215	*gpu_addr = radeon_bo_gpu_offset(bo);
771fe6b9 JG	216	return 0;
771fe6b9 JG	217	}
312ea8da	218	radeon_ttm_placement_from_domain(bo, domain);
3ca82da3 MD	219	if (domain == RADEON_GEM_DOMAIN_VRAM) {
	220	/* force to pin into visible video ram */
	221	bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
	222	}
312ea8da JG	223	for (i = 0; i < bo->placement.num_placement; i++)
312ea8da JG	224	bo->placements[i] \|= TTM_PL_FLAG_NO_EVICT;
9d87fa21	225	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
4c788679 JG	226	if (likely(r == 0)) {
	227	bo->pin_count = 1;
	228	if (gpu_addr != NULL)
	229	*gpu_addr = radeon_bo_gpu_offset(bo);
771fe6b9	230	}
5cc6fbab	231	if (unlikely(r != 0))
4c788679	232	dev_err(bo->rdev->dev, "%p pin failed\n", bo);
771fe6b9 JG	233	return r;
	234	}
	235
4c788679	236	int radeon_bo_unpin(struct radeon_bo *bo)
771fe6b9	237	{
312ea8da	238	int r, i;
771fe6b9	239
4c788679 JG	240	if (!bo->pin_count) {
	241	dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
	242	return 0;
771fe6b9	243	}
4c788679 JG	244	bo->pin_count--;
	245	if (bo->pin_count)
	246	return 0;
312ea8da JG	247	for (i = 0; i < bo->placement.num_placement; i++)
312ea8da JG	248	bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
9d87fa21	249	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
5cc6fbab	250	if (unlikely(r != 0))
4c788679	251	dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
5cc6fbab	252	return r;
cefb87ef DA	253	}
cefb87ef DA	254
4c788679	255	int radeon_bo_evict_vram(struct radeon_device *rdev)
771fe6b9	256	{
d796d844 DA	257	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
d796d844 DA	258	if (0 && (rdev->flags & RADEON_IS_IGP)) {
06b6476d AD	259	if (rdev->mc.igp_sideport_enabled == false)
	260	/* Useless to evict on IGP chips */
	261	return 0;
771fe6b9 JG	262	}
	263	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
	264	}
	265
4c788679	266	void radeon_bo_force_delete(struct radeon_device *rdev)
771fe6b9	267	{
4c788679	268	struct radeon_bo bo, n;
771fe6b9 JG	269	struct drm_gem_object *gobj;
	270
	271	if (list_empty(&rdev->gem.objects)) {
	272	return;
	273	}
4c788679 JG	274	dev_err(rdev->dev, "Userspace still has active objects !\n");
4c788679 JG	275	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
771fe6b9	276	mutex_lock(&rdev->ddev->struct_mutex);
4c788679 JG	277	gobj = bo->gobj;
	278	dev_err(rdev->dev, "%p %p %lu %lu force free\n",
	279	gobj, bo, (unsigned long)gobj->size,
	280	((unsigned long )&gobj->refcount));
	281	mutex_lock(&bo->rdev->gem.mutex);
	282	list_del_init(&bo->list);
	283	mutex_unlock(&bo->rdev->gem.mutex);
	284	radeon_bo_unref(&bo);
771fe6b9 JG	285	gobj->driver_private = NULL;
	286	drm_gem_object_unreference(gobj);
	287	mutex_unlock(&rdev->ddev->struct_mutex);
	288	}
	289	}
	290
4c788679	291	int radeon_bo_init(struct radeon_device *rdev)
771fe6b9	292	{
a4d68279 JG	293	/* Add an MTRR for the VRAM */
	294	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
	295	MTRR_TYPE_WRCOMB, 1);
	296	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
	297	rdev->mc.mc_vram_size >> 20,
	298	(unsigned long long)rdev->mc.aper_size >> 20);
	299	DRM_INFO("RAM width %dbits %cDR\n",
	300	rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
771fe6b9 JG	301	return radeon_ttm_init(rdev);
	302	}
	303
4c788679	304	void radeon_bo_fini(struct radeon_device *rdev)
771fe6b9 JG	305	{
	306	radeon_ttm_fini(rdev);
	307	}
	308
4c788679 JG	309	void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
4c788679 JG	310	struct list_head *head)
771fe6b9 JG	311	{
771fe6b9 JG	312	if (lobj->wdomain) {
147666fb	313	list_add(&lobj->tv.head, head);
771fe6b9	314	} else {
147666fb	315	list_add_tail(&lobj->tv.head, head);
771fe6b9 JG	316	}
	317	}
	318
6cb8e1f7	319	int radeon_bo_list_validate(struct list_head *head)
771fe6b9	320	{
4c788679 JG	321	struct radeon_bo_list *lobj;
4c788679 JG	322	struct radeon_bo *bo;
e376573f	323	u32 domain;
771fe6b9 JG	324	int r;
771fe6b9 JG	325
147666fb	326	r = ttm_eu_reserve_buffers(head);
771fe6b9	327	if (unlikely(r != 0)) {
771fe6b9 JG	328	return r;
771fe6b9 JG	329	}
147666fb	330	list_for_each_entry(lobj, head, tv.head) {
4c788679 JG	331	bo = lobj->bo;
4c788679 JG	332	if (!bo->pin_count) {
e376573f MD	333	domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
	334
	335	retry:
	336	radeon_ttm_placement_from_domain(bo, domain);
1fb107fc	337	r = ttm_bo_validate(&bo->tbo, &bo->placement,
9d87fa21	338	true, false, false);
e376573f MD	339	if (unlikely(r)) {
	340	if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
	341	domain \|= RADEON_GEM_DOMAIN_GTT;
	342	goto retry;
	343	}
771fe6b9	344	return r;
e376573f	345	}
771fe6b9	346	}
4c788679 JG	347	lobj->gpu_offset = radeon_bo_gpu_offset(bo);
4c788679 JG	348	lobj->tiling_flags = bo->tiling_flags;
771fe6b9 JG	349	}
	350	return 0;
	351	}
	352
4c788679	353	int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
771fe6b9 JG	354	struct vm_area_struct *vma)
771fe6b9 JG	355	{
4c788679	356	return ttm_fbdev_mmap(vma, &bo->tbo);
771fe6b9 JG	357	}
771fe6b9 JG	358
550e2d92	359	int radeon_bo_get_surface_reg(struct radeon_bo *bo)
771fe6b9	360	{
4c788679	361	struct radeon_device *rdev = bo->rdev;
e024e110	362	struct radeon_surface_reg *reg;
4c788679	363	struct radeon_bo *old_object;
e024e110 DA	364	int steal;
	365	int i;
	366
4c788679 JG	367	BUG_ON(!atomic_read(&bo->tbo.reserved));
	368
	369	if (!bo->tiling_flags)
e024e110 DA	370	return 0;
e024e110 DA	371
4c788679 JG	372	if (bo->surface_reg >= 0) {
	373	reg = &rdev->surface_regs[bo->surface_reg];
	374	i = bo->surface_reg;
e024e110 DA	375	goto out;
	376	}
	377
	378	steal = -1;
	379	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
	380
	381	reg = &rdev->surface_regs[i];
4c788679	382	if (!reg->bo)
e024e110 DA	383	break;
e024e110 DA	384
4c788679	385	old_object = reg->bo;
e024e110 DA	386	if (old_object->pin_count == 0)
	387	steal = i;
	388	}
	389
	390	/* if we are all out */
	391	if (i == RADEON_GEM_MAX_SURFACES) {
	392	if (steal == -1)
	393	return -ENOMEM;
	394	/* find someone with a surface reg and nuke their BO */
	395	reg = &rdev->surface_regs[steal];
4c788679	396	old_object = reg->bo;
e024e110 DA	397	/* blow away the mapping */
e024e110 DA	398	DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
4c788679	399	ttm_bo_unmap_virtual(&old_object->tbo);
e024e110 DA	400	old_object->surface_reg = -1;
	401	i = steal;
	402	}
	403
4c788679 JG	404	bo->surface_reg = i;
4c788679 JG	405	reg->bo = bo;
e024e110 DA	406
e024e110 DA	407	out:
4c788679	408	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
d961db75	409	bo->tbo.mem.start << PAGE_SHIFT,
4c788679	410	bo->tbo.num_pages << PAGE_SHIFT);
e024e110 DA	411	return 0;
	412	}
	413
4c788679	414	static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
e024e110	415	{
4c788679	416	struct radeon_device *rdev = bo->rdev;
e024e110 DA	417	struct radeon_surface_reg *reg;
e024e110 DA	418
4c788679	419	if (bo->surface_reg == -1)
e024e110 DA	420	return;
e024e110 DA	421
4c788679 JG	422	reg = &rdev->surface_regs[bo->surface_reg];
4c788679 JG	423	radeon_clear_surface_reg(rdev, bo->surface_reg);
e024e110	424
4c788679 JG	425	reg->bo = NULL;
4c788679 JG	426	bo->surface_reg = -1;
e024e110 DA	427	}
e024e110 DA	428
4c788679 JG	429	int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
4c788679 JG	430	uint32_t tiling_flags, uint32_t pitch)
e024e110	431	{
4c788679 JG	432	int r;
	433
	434	r = radeon_bo_reserve(bo, false);
	435	if (unlikely(r != 0))
	436	return r;
	437	bo->tiling_flags = tiling_flags;
	438	bo->pitch = pitch;
	439	radeon_bo_unreserve(bo);
	440	return 0;
e024e110 DA	441	}
e024e110 DA	442
4c788679 JG	443	void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
	444	uint32_t *tiling_flags,
	445	uint32_t *pitch)
e024e110	446	{
4c788679	447	BUG_ON(!atomic_read(&bo->tbo.reserved));
e024e110	448	if (tiling_flags)
4c788679	449	*tiling_flags = bo->tiling_flags;
e024e110	450	if (pitch)
4c788679	451	*pitch = bo->pitch;
e024e110 DA	452	}
e024e110 DA	453
4c788679 JG	454	int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
4c788679 JG	455	bool force_drop)
e024e110	456	{
4c788679 JG	457	BUG_ON(!atomic_read(&bo->tbo.reserved));
	458
	459	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
e024e110 DA	460	return 0;
	461
	462	if (force_drop) {
4c788679	463	radeon_bo_clear_surface_reg(bo);
e024e110 DA	464	return 0;
	465	}
	466
4c788679	467	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
e024e110 DA	468	if (!has_moved)
	469	return 0;
	470
4c788679 JG	471	if (bo->surface_reg >= 0)
4c788679 JG	472	radeon_bo_clear_surface_reg(bo);
e024e110 DA	473	return 0;
	474	}
	475
4c788679	476	if ((bo->surface_reg >= 0) && !has_moved)
e024e110 DA	477	return 0;
e024e110 DA	478
4c788679	479	return radeon_bo_get_surface_reg(bo);
e024e110 DA	480	}
	481
	482	void radeon_bo_move_notify(struct ttm_buffer_object *bo,
d03d8589	483	struct ttm_mem_reg *mem)
e024e110	484	{
d03d8589 JG	485	struct radeon_bo *rbo;
	486	if (!radeon_ttm_bo_is_radeon_bo(bo))
	487	return;
	488	rbo = container_of(bo, struct radeon_bo, tbo);
4c788679	489	radeon_bo_check_tiling(rbo, 0, 1);
e024e110 DA	490	}
e024e110 DA	491
0a2d50e3	492	int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
e024e110	493	{
0a2d50e3	494	struct radeon_device *rdev;
d03d8589	495	struct radeon_bo *rbo;
0a2d50e3 JG	496	unsigned long offset, size;
	497	int r;
	498
d03d8589	499	if (!radeon_ttm_bo_is_radeon_bo(bo))
0a2d50e3	500	return 0;
d03d8589	501	rbo = container_of(bo, struct radeon_bo, tbo);
4c788679	502	radeon_bo_check_tiling(rbo, 0, 0);
0a2d50e3 JG	503	rdev = rbo->rdev;
	504	if (bo->mem.mem_type == TTM_PL_VRAM) {
	505	size = bo->mem.num_pages << PAGE_SHIFT;
d961db75	506	offset = bo->mem.start << PAGE_SHIFT;
0a2d50e3 JG	507	if ((offset + size) > rdev->mc.visible_vram_size) {
	508	/* hurrah the memory is not visible ! */
	509	radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
	510	rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
	511	r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
	512	if (unlikely(r != 0))
	513	return r;
d961db75	514	offset = bo->mem.start << PAGE_SHIFT;
0a2d50e3 JG	515	/* this should not happen */
	516	if ((offset + size) > rdev->mc.visible_vram_size)
	517	return -EINVAL;
	518	}
	519	}
	520	return 0;
e024e110	521	}