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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <linux/list.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
771fe6b9 | 34 | #include <drm/drmP.h> |
760285e7 | 35 | #include <drm/radeon_drm.h> |
771fe6b9 | 36 | #include "radeon.h" |
99ee7fac | 37 | #include "radeon_trace.h" |
771fe6b9 | 38 | |
771fe6b9 JG |
39 | |
40 | int radeon_ttm_init(struct radeon_device *rdev); | |
41 | void radeon_ttm_fini(struct radeon_device *rdev); | |
4c788679 | 42 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
771fe6b9 JG |
43 | |
44 | /* | |
45 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all | |
46 | * function are calling it. | |
47 | */ | |
48 | ||
67e8e3f9 MO |
49 | static void radeon_update_memory_usage(struct radeon_bo *bo, |
50 | unsigned mem_type, int sign) | |
51 | { | |
52 | struct radeon_device *rdev = bo->rdev; | |
53 | u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT; | |
54 | ||
55 | switch (mem_type) { | |
56 | case TTM_PL_TT: | |
57 | if (sign > 0) | |
58 | atomic64_add(size, &rdev->gtt_usage); | |
59 | else | |
60 | atomic64_sub(size, &rdev->gtt_usage); | |
61 | break; | |
62 | case TTM_PL_VRAM: | |
63 | if (sign > 0) | |
64 | atomic64_add(size, &rdev->vram_usage); | |
65 | else | |
66 | atomic64_sub(size, &rdev->vram_usage); | |
67 | break; | |
68 | } | |
69 | } | |
70 | ||
4c788679 | 71 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
771fe6b9 | 72 | { |
4c788679 | 73 | struct radeon_bo *bo; |
771fe6b9 | 74 | |
4c788679 | 75 | bo = container_of(tbo, struct radeon_bo, tbo); |
67e8e3f9 MO |
76 | |
77 | radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1); | |
78 | ||
4c788679 JG |
79 | mutex_lock(&bo->rdev->gem.mutex); |
80 | list_del_init(&bo->list); | |
81 | mutex_unlock(&bo->rdev->gem.mutex); | |
82 | radeon_bo_clear_surface_reg(bo); | |
c265f24d | 83 | WARN_ON(!list_empty(&bo->va)); |
441921d5 | 84 | drm_gem_object_release(&bo->gem_base); |
4c788679 | 85 | kfree(bo); |
771fe6b9 JG |
86 | } |
87 | ||
d03d8589 JG |
88 | bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) |
89 | { | |
90 | if (bo->destroy == &radeon_ttm_bo_destroy) | |
91 | return true; | |
92 | return false; | |
93 | } | |
94 | ||
312ea8da JG |
95 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
96 | { | |
deadcb36 | 97 | u32 c = 0, i; |
312ea8da | 98 | |
312ea8da | 99 | rbo->placement.placement = rbo->placements; |
20707874 | 100 | rbo->placement.busy_placement = rbo->placements; |
c9da4a4b MD |
101 | if (domain & RADEON_GEM_DOMAIN_VRAM) { |
102 | /* Try placing BOs which don't need CPU access outside of the | |
103 | * CPU accessible part of VRAM | |
104 | */ | |
105 | if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) && | |
106 | rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { | |
107 | rbo->placements[c].fpfn = | |
108 | rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
109 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | | |
110 | TTM_PL_FLAG_UNCACHED | | |
111 | TTM_PL_FLAG_VRAM; | |
112 | } | |
113 | ||
114 | rbo->placements[c].fpfn = 0; | |
f1217ed0 CK |
115 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
116 | TTM_PL_FLAG_UNCACHED | | |
117 | TTM_PL_FLAG_VRAM; | |
c9da4a4b | 118 | } |
f1217ed0 | 119 | |
0d0b3e74 | 120 | if (domain & RADEON_GEM_DOMAIN_GTT) { |
02376d82 | 121 | if (rbo->flags & RADEON_GEM_GTT_UC) { |
c9da4a4b | 122 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
123 | rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | |
124 | TTM_PL_FLAG_TT; | |
125 | ||
02376d82 MD |
126 | } else if ((rbo->flags & RADEON_GEM_GTT_WC) || |
127 | (rbo->rdev->flags & RADEON_IS_AGP)) { | |
c9da4a4b | 128 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
129 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
130 | TTM_PL_FLAG_UNCACHED | | |
02376d82 | 131 | TTM_PL_FLAG_TT; |
0d0b3e74 | 132 | } else { |
c9da4a4b | 133 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
134 | rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | |
135 | TTM_PL_FLAG_TT; | |
0d0b3e74 JG |
136 | } |
137 | } | |
f1217ed0 | 138 | |
0d0b3e74 | 139 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
02376d82 | 140 | if (rbo->flags & RADEON_GEM_GTT_UC) { |
c9da4a4b | 141 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
142 | rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | |
143 | TTM_PL_FLAG_SYSTEM; | |
144 | ||
02376d82 MD |
145 | } else if ((rbo->flags & RADEON_GEM_GTT_WC) || |
146 | rbo->rdev->flags & RADEON_IS_AGP) { | |
c9da4a4b | 147 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
148 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
149 | TTM_PL_FLAG_UNCACHED | | |
02376d82 | 150 | TTM_PL_FLAG_SYSTEM; |
0d0b3e74 | 151 | } else { |
c9da4a4b | 152 | rbo->placements[c].fpfn = 0; |
f1217ed0 CK |
153 | rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | |
154 | TTM_PL_FLAG_SYSTEM; | |
0d0b3e74 JG |
155 | } |
156 | } | |
c9da4a4b MD |
157 | if (!c) { |
158 | rbo->placements[c].fpfn = 0; | |
f1217ed0 CK |
159 | rbo->placements[c++].flags = TTM_PL_MASK_CACHING | |
160 | TTM_PL_FLAG_SYSTEM; | |
c9da4a4b | 161 | } |
f1217ed0 | 162 | |
312ea8da JG |
163 | rbo->placement.num_placement = c; |
164 | rbo->placement.num_busy_placement = c; | |
deadcb36 | 165 | |
f1217ed0 | 166 | for (i = 0; i < c; ++i) { |
c8584039 | 167 | if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && |
c9da4a4b MD |
168 | (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && |
169 | !rbo->placements[i].fpfn) | |
c8584039 MD |
170 | rbo->placements[i].lpfn = |
171 | rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
172 | else | |
173 | rbo->placements[i].lpfn = 0; | |
f1217ed0 | 174 | } |
312ea8da JG |
175 | } |
176 | ||
441921d5 | 177 | int radeon_bo_create(struct radeon_device *rdev, |
831b6966 ML |
178 | unsigned long size, int byte_align, bool kernel, |
179 | u32 domain, u32 flags, struct sg_table *sg, | |
180 | struct reservation_object *resv, | |
181 | struct radeon_bo **bo_ptr) | |
771fe6b9 | 182 | { |
4c788679 | 183 | struct radeon_bo *bo; |
771fe6b9 | 184 | enum ttm_bo_type type; |
93225b0d | 185 | unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; |
57de4ba9 | 186 | size_t acc_size; |
771fe6b9 JG |
187 | int r; |
188 | ||
441921d5 DV |
189 | size = ALIGN(size, PAGE_SIZE); |
190 | ||
771fe6b9 JG |
191 | if (kernel) { |
192 | type = ttm_bo_type_kernel; | |
40f5cf99 AD |
193 | } else if (sg) { |
194 | type = ttm_bo_type_sg; | |
771fe6b9 JG |
195 | } else { |
196 | type = ttm_bo_type_device; | |
197 | } | |
4c788679 | 198 | *bo_ptr = NULL; |
2b66b50b | 199 | |
57de4ba9 JG |
200 | acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, |
201 | sizeof(struct radeon_bo)); | |
202 | ||
4c788679 JG |
203 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
204 | if (bo == NULL) | |
771fe6b9 | 205 | return -ENOMEM; |
441921d5 DV |
206 | r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); |
207 | if (unlikely(r)) { | |
208 | kfree(bo); | |
209 | return r; | |
210 | } | |
4c788679 | 211 | bo->rdev = rdev; |
4c788679 JG |
212 | bo->surface_reg = -1; |
213 | INIT_LIST_HEAD(&bo->list); | |
721604a1 | 214 | INIT_LIST_HEAD(&bo->va); |
bda72d58 MO |
215 | bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | |
216 | RADEON_GEM_DOMAIN_GTT | | |
217 | RADEON_GEM_DOMAIN_CPU); | |
02376d82 MD |
218 | |
219 | bo->flags = flags; | |
220 | /* PCI GART is always snooped */ | |
221 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
222 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); | |
223 | ||
a08b588e MD |
224 | #ifdef CONFIG_X86_32 |
225 | /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit | |
226 | * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 | |
227 | */ | |
228 | bo->flags &= ~RADEON_GEM_GTT_WC; | |
a53fa438 MD |
229 | #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) |
230 | /* Don't try to enable write-combining when it can't work, or things | |
231 | * may be slow | |
232 | * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 | |
233 | */ | |
234 | ||
235 | #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ | |
236 | thanks to write-combining | |
237 | ||
238 | DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " | |
239 | "better performance thanks to write-combining\n"); | |
240 | bo->flags &= ~RADEON_GEM_GTT_WC; | |
a08b588e MD |
241 | #endif |
242 | ||
1fb107fc | 243 | radeon_ttm_placement_from_domain(bo, domain); |
5cc6fbab | 244 | /* Kernel allocation are uninterruptible */ |
db7fce39 | 245 | down_read(&rdev->pm.mclk_lock); |
1fb107fc | 246 | r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, |
0b91c4a1 | 247 | &bo->placement, page_align, !kernel, NULL, |
831b6966 | 248 | acc_size, sg, resv, &radeon_ttm_bo_destroy); |
db7fce39 | 249 | up_read(&rdev->pm.mclk_lock); |
771fe6b9 | 250 | if (unlikely(r != 0)) { |
771fe6b9 JG |
251 | return r; |
252 | } | |
4c788679 | 253 | *bo_ptr = bo; |
441921d5 | 254 | |
99ee7fac | 255 | trace_radeon_bo_create(bo); |
441921d5 | 256 | |
771fe6b9 JG |
257 | return 0; |
258 | } | |
259 | ||
4c788679 | 260 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
771fe6b9 | 261 | { |
4c788679 | 262 | bool is_iomem; |
771fe6b9 JG |
263 | int r; |
264 | ||
4c788679 | 265 | if (bo->kptr) { |
771fe6b9 | 266 | if (ptr) { |
4c788679 | 267 | *ptr = bo->kptr; |
771fe6b9 | 268 | } |
771fe6b9 JG |
269 | return 0; |
270 | } | |
4c788679 | 271 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
771fe6b9 JG |
272 | if (r) { |
273 | return r; | |
274 | } | |
4c788679 | 275 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
771fe6b9 | 276 | if (ptr) { |
4c788679 | 277 | *ptr = bo->kptr; |
771fe6b9 | 278 | } |
4c788679 | 279 | radeon_bo_check_tiling(bo, 0, 0); |
771fe6b9 JG |
280 | return 0; |
281 | } | |
282 | ||
4c788679 | 283 | void radeon_bo_kunmap(struct radeon_bo *bo) |
771fe6b9 | 284 | { |
4c788679 | 285 | if (bo->kptr == NULL) |
771fe6b9 | 286 | return; |
4c788679 JG |
287 | bo->kptr = NULL; |
288 | radeon_bo_check_tiling(bo, 0, 0); | |
289 | ttm_bo_kunmap(&bo->kmap); | |
771fe6b9 JG |
290 | } |
291 | ||
512d8afc CK |
292 | struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo) |
293 | { | |
294 | if (bo == NULL) | |
295 | return NULL; | |
296 | ||
297 | ttm_bo_reference(&bo->tbo); | |
298 | return bo; | |
299 | } | |
300 | ||
4c788679 | 301 | void radeon_bo_unref(struct radeon_bo **bo) |
771fe6b9 | 302 | { |
4c788679 | 303 | struct ttm_buffer_object *tbo; |
f4b7fb94 | 304 | struct radeon_device *rdev; |
771fe6b9 | 305 | |
4c788679 | 306 | if ((*bo) == NULL) |
771fe6b9 | 307 | return; |
f4b7fb94 | 308 | rdev = (*bo)->rdev; |
4c788679 JG |
309 | tbo = &((*bo)->tbo); |
310 | ttm_bo_unref(&tbo); | |
311 | if (tbo == NULL) | |
312 | *bo = NULL; | |
771fe6b9 JG |
313 | } |
314 | ||
c4353016 MD |
315 | int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, |
316 | u64 *gpu_addr) | |
771fe6b9 | 317 | { |
312ea8da | 318 | int r, i; |
771fe6b9 | 319 | |
f72a113a CK |
320 | if (radeon_ttm_tt_has_userptr(bo->tbo.ttm)) |
321 | return -EPERM; | |
322 | ||
4c788679 JG |
323 | if (bo->pin_count) { |
324 | bo->pin_count++; | |
325 | if (gpu_addr) | |
326 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
d936622c MD |
327 | |
328 | if (max_offset != 0) { | |
329 | u64 domain_start; | |
330 | ||
331 | if (domain == RADEON_GEM_DOMAIN_VRAM) | |
332 | domain_start = bo->rdev->mc.vram_start; | |
333 | else | |
334 | domain_start = bo->rdev->mc.gtt_start; | |
e199fd42 MD |
335 | WARN_ON_ONCE(max_offset < |
336 | (radeon_bo_gpu_offset(bo) - domain_start)); | |
d936622c MD |
337 | } |
338 | ||
771fe6b9 JG |
339 | return 0; |
340 | } | |
312ea8da | 341 | radeon_ttm_placement_from_domain(bo, domain); |
f1217ed0 | 342 | for (i = 0; i < bo->placement.num_placement; i++) { |
3ca82da3 | 343 | /* force to pin into visible video ram */ |
b76ee67a | 344 | if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && |
f266f04d | 345 | !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && |
b76ee67a MD |
346 | (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) |
347 | bo->placements[i].lpfn = | |
348 | bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
f1217ed0 | 349 | else |
b76ee67a | 350 | bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; |
c4353016 | 351 | |
f1217ed0 | 352 | bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; |
c4353016 | 353 | } |
f1217ed0 | 354 | |
97a875cb | 355 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
4c788679 JG |
356 | if (likely(r == 0)) { |
357 | bo->pin_count = 1; | |
358 | if (gpu_addr != NULL) | |
359 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
71ecc97e AD |
360 | if (domain == RADEON_GEM_DOMAIN_VRAM) |
361 | bo->rdev->vram_pin_size += radeon_bo_size(bo); | |
362 | else | |
363 | bo->rdev->gart_pin_size += radeon_bo_size(bo); | |
364 | } else { | |
4c788679 | 365 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
71ecc97e | 366 | } |
771fe6b9 JG |
367 | return r; |
368 | } | |
c4353016 MD |
369 | |
370 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) | |
371 | { | |
372 | return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); | |
373 | } | |
771fe6b9 | 374 | |
4c788679 | 375 | int radeon_bo_unpin(struct radeon_bo *bo) |
771fe6b9 | 376 | { |
312ea8da | 377 | int r, i; |
771fe6b9 | 378 | |
4c788679 JG |
379 | if (!bo->pin_count) { |
380 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); | |
381 | return 0; | |
771fe6b9 | 382 | } |
4c788679 JG |
383 | bo->pin_count--; |
384 | if (bo->pin_count) | |
385 | return 0; | |
f1217ed0 CK |
386 | for (i = 0; i < bo->placement.num_placement; i++) { |
387 | bo->placements[i].lpfn = 0; | |
388 | bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; | |
389 | } | |
97a875cb | 390 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
71ecc97e AD |
391 | if (likely(r == 0)) { |
392 | if (bo->tbo.mem.mem_type == TTM_PL_VRAM) | |
393 | bo->rdev->vram_pin_size -= radeon_bo_size(bo); | |
394 | else | |
395 | bo->rdev->gart_pin_size -= radeon_bo_size(bo); | |
396 | } else { | |
4c788679 | 397 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
71ecc97e | 398 | } |
5cc6fbab | 399 | return r; |
cefb87ef DA |
400 | } |
401 | ||
4c788679 | 402 | int radeon_bo_evict_vram(struct radeon_device *rdev) |
771fe6b9 | 403 | { |
d796d844 DA |
404 | /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ |
405 | if (0 && (rdev->flags & RADEON_IS_IGP)) { | |
06b6476d AD |
406 | if (rdev->mc.igp_sideport_enabled == false) |
407 | /* Useless to evict on IGP chips */ | |
408 | return 0; | |
771fe6b9 JG |
409 | } |
410 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
411 | } | |
412 | ||
4c788679 | 413 | void radeon_bo_force_delete(struct radeon_device *rdev) |
771fe6b9 | 414 | { |
4c788679 | 415 | struct radeon_bo *bo, *n; |
771fe6b9 JG |
416 | |
417 | if (list_empty(&rdev->gem.objects)) { | |
418 | return; | |
419 | } | |
4c788679 JG |
420 | dev_err(rdev->dev, "Userspace still has active objects !\n"); |
421 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { | |
771fe6b9 | 422 | mutex_lock(&rdev->ddev->struct_mutex); |
4c788679 | 423 | dev_err(rdev->dev, "%p %p %lu %lu force free\n", |
31c3603d DV |
424 | &bo->gem_base, bo, (unsigned long)bo->gem_base.size, |
425 | *((unsigned long *)&bo->gem_base.refcount)); | |
4c788679 JG |
426 | mutex_lock(&bo->rdev->gem.mutex); |
427 | list_del_init(&bo->list); | |
428 | mutex_unlock(&bo->rdev->gem.mutex); | |
91132d6b | 429 | /* this should unref the ttm bo */ |
31c3603d | 430 | drm_gem_object_unreference(&bo->gem_base); |
771fe6b9 JG |
431 | mutex_unlock(&rdev->ddev->struct_mutex); |
432 | } | |
433 | } | |
434 | ||
4c788679 | 435 | int radeon_bo_init(struct radeon_device *rdev) |
771fe6b9 | 436 | { |
a4d68279 | 437 | /* Add an MTRR for the VRAM */ |
a0a53aa8 | 438 | if (!rdev->fastfb_working) { |
07ebea25 AL |
439 | rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, |
440 | rdev->mc.aper_size); | |
a0a53aa8 | 441 | } |
a4d68279 JG |
442 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", |
443 | rdev->mc.mc_vram_size >> 20, | |
444 | (unsigned long long)rdev->mc.aper_size >> 20); | |
445 | DRM_INFO("RAM width %dbits %cDR\n", | |
446 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); | |
771fe6b9 JG |
447 | return radeon_ttm_init(rdev); |
448 | } | |
449 | ||
4c788679 | 450 | void radeon_bo_fini(struct radeon_device *rdev) |
771fe6b9 JG |
451 | { |
452 | radeon_ttm_fini(rdev); | |
07ebea25 | 453 | arch_phys_wc_del(rdev->mc.vram_mtrr); |
771fe6b9 JG |
454 | } |
455 | ||
19dff56a MO |
456 | /* Returns how many bytes TTM can move per IB. |
457 | */ | |
458 | static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) | |
459 | { | |
460 | u64 real_vram_size = rdev->mc.real_vram_size; | |
461 | u64 vram_usage = atomic64_read(&rdev->vram_usage); | |
462 | ||
463 | /* This function is based on the current VRAM usage. | |
464 | * | |
465 | * - If all of VRAM is free, allow relocating the number of bytes that | |
466 | * is equal to 1/4 of the size of VRAM for this IB. | |
467 | ||
468 | * - If more than one half of VRAM is occupied, only allow relocating | |
469 | * 1 MB of data for this IB. | |
470 | * | |
471 | * - From 0 to one half of used VRAM, the threshold decreases | |
472 | * linearly. | |
473 | * __________________ | |
474 | * 1/4 of -|\ | | |
475 | * VRAM | \ | | |
476 | * | \ | | |
477 | * | \ | | |
478 | * | \ | | |
479 | * | \ | | |
480 | * | \ | | |
481 | * | \________|1 MB | |
482 | * |----------------| | |
483 | * VRAM 0 % 100 % | |
484 | * used used | |
485 | * | |
486 | * Note: It's a threshold, not a limit. The threshold must be crossed | |
487 | * for buffer relocations to stop, so any buffer of an arbitrary size | |
488 | * can be moved as long as the threshold isn't crossed before | |
489 | * the relocation takes place. We don't want to disable buffer | |
490 | * relocations completely. | |
491 | * | |
492 | * The idea is that buffers should be placed in VRAM at creation time | |
493 | * and TTM should only do a minimum number of relocations during | |
494 | * command submission. In practice, you need to submit at least | |
495 | * a dozen IBs to move all buffers to VRAM if they are in GTT. | |
496 | * | |
497 | * Also, things can get pretty crazy under memory pressure and actual | |
498 | * VRAM usage can change a lot, so playing safe even at 50% does | |
499 | * consistently increase performance. | |
500 | */ | |
501 | ||
502 | u64 half_vram = real_vram_size >> 1; | |
503 | u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; | |
504 | u64 bytes_moved_threshold = half_free_vram >> 1; | |
505 | return max(bytes_moved_threshold, 1024*1024ull); | |
506 | } | |
507 | ||
508 | int radeon_bo_list_validate(struct radeon_device *rdev, | |
509 | struct ww_acquire_ctx *ticket, | |
ecff665f | 510 | struct list_head *head, int ring) |
771fe6b9 | 511 | { |
1d0c0942 | 512 | struct radeon_bo_list *lobj; |
466be338 | 513 | struct list_head duplicates; |
771fe6b9 | 514 | int r; |
19dff56a MO |
515 | u64 bytes_moved = 0, initial_bytes_moved; |
516 | u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev); | |
771fe6b9 | 517 | |
466be338 CK |
518 | INIT_LIST_HEAD(&duplicates); |
519 | r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates); | |
771fe6b9 | 520 | if (unlikely(r != 0)) { |
771fe6b9 JG |
521 | return r; |
522 | } | |
19dff56a | 523 | |
147666fb | 524 | list_for_each_entry(lobj, head, tv.head) { |
466be338 | 525 | struct radeon_bo *bo = lobj->robj; |
4c788679 | 526 | if (!bo->pin_count) { |
ce6758c8 | 527 | u32 domain = lobj->prefered_domains; |
3852752c | 528 | u32 allowed = lobj->allowed_domains; |
19dff56a MO |
529 | u32 current_domain = |
530 | radeon_mem_type_to_domain(bo->tbo.mem.mem_type); | |
531 | ||
532 | /* Check if this buffer will be moved and don't move it | |
533 | * if we have moved too many buffers for this IB already. | |
534 | * | |
535 | * Note that this allows moving at least one buffer of | |
536 | * any size, because it doesn't take the current "bo" | |
537 | * into account. We don't want to disallow buffer moves | |
538 | * completely. | |
539 | */ | |
3852752c | 540 | if ((allowed & current_domain) != 0 && |
19dff56a MO |
541 | (domain & current_domain) == 0 && /* will be moved */ |
542 | bytes_moved > bytes_moved_threshold) { | |
543 | /* don't move it */ | |
544 | domain = current_domain; | |
545 | } | |
546 | ||
20707874 AD |
547 | retry: |
548 | radeon_ttm_placement_from_domain(bo, domain); | |
f2ba57b5 | 549 | if (ring == R600_RING_TYPE_UVD_INDEX) |
3852752c | 550 | radeon_uvd_force_into_uvd_segment(bo, allowed); |
19dff56a MO |
551 | |
552 | initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); | |
553 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
554 | bytes_moved += atomic64_read(&rdev->num_bytes_moved) - | |
555 | initial_bytes_moved; | |
556 | ||
e376573f | 557 | if (unlikely(r)) { |
ce6758c8 CK |
558 | if (r != -ERESTARTSYS && |
559 | domain != lobj->allowed_domains) { | |
560 | domain = lobj->allowed_domains; | |
20707874 AD |
561 | goto retry; |
562 | } | |
1b6e5fd5 | 563 | ttm_eu_backoff_reservation(ticket, head); |
771fe6b9 | 564 | return r; |
e376573f | 565 | } |
771fe6b9 | 566 | } |
4c788679 JG |
567 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
568 | lobj->tiling_flags = bo->tiling_flags; | |
771fe6b9 | 569 | } |
466be338 CK |
570 | |
571 | list_for_each_entry(lobj, &duplicates, tv.head) { | |
572 | lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); | |
573 | lobj->tiling_flags = lobj->robj->tiling_flags; | |
574 | } | |
575 | ||
771fe6b9 JG |
576 | return 0; |
577 | } | |
578 | ||
550e2d92 | 579 | int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
771fe6b9 | 580 | { |
4c788679 | 581 | struct radeon_device *rdev = bo->rdev; |
e024e110 | 582 | struct radeon_surface_reg *reg; |
4c788679 | 583 | struct radeon_bo *old_object; |
e024e110 DA |
584 | int steal; |
585 | int i; | |
586 | ||
977c38d5 | 587 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
4c788679 JG |
588 | |
589 | if (!bo->tiling_flags) | |
e024e110 DA |
590 | return 0; |
591 | ||
4c788679 JG |
592 | if (bo->surface_reg >= 0) { |
593 | reg = &rdev->surface_regs[bo->surface_reg]; | |
594 | i = bo->surface_reg; | |
e024e110 DA |
595 | goto out; |
596 | } | |
597 | ||
598 | steal = -1; | |
599 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { | |
600 | ||
601 | reg = &rdev->surface_regs[i]; | |
4c788679 | 602 | if (!reg->bo) |
e024e110 DA |
603 | break; |
604 | ||
4c788679 | 605 | old_object = reg->bo; |
e024e110 DA |
606 | if (old_object->pin_count == 0) |
607 | steal = i; | |
608 | } | |
609 | ||
610 | /* if we are all out */ | |
611 | if (i == RADEON_GEM_MAX_SURFACES) { | |
612 | if (steal == -1) | |
613 | return -ENOMEM; | |
614 | /* find someone with a surface reg and nuke their BO */ | |
615 | reg = &rdev->surface_regs[steal]; | |
4c788679 | 616 | old_object = reg->bo; |
e024e110 DA |
617 | /* blow away the mapping */ |
618 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); | |
4c788679 | 619 | ttm_bo_unmap_virtual(&old_object->tbo); |
e024e110 DA |
620 | old_object->surface_reg = -1; |
621 | i = steal; | |
622 | } | |
623 | ||
4c788679 JG |
624 | bo->surface_reg = i; |
625 | reg->bo = bo; | |
e024e110 DA |
626 | |
627 | out: | |
4c788679 | 628 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
d961db75 | 629 | bo->tbo.mem.start << PAGE_SHIFT, |
4c788679 | 630 | bo->tbo.num_pages << PAGE_SHIFT); |
e024e110 DA |
631 | return 0; |
632 | } | |
633 | ||
4c788679 | 634 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
e024e110 | 635 | { |
4c788679 | 636 | struct radeon_device *rdev = bo->rdev; |
e024e110 DA |
637 | struct radeon_surface_reg *reg; |
638 | ||
4c788679 | 639 | if (bo->surface_reg == -1) |
e024e110 DA |
640 | return; |
641 | ||
4c788679 JG |
642 | reg = &rdev->surface_regs[bo->surface_reg]; |
643 | radeon_clear_surface_reg(rdev, bo->surface_reg); | |
e024e110 | 644 | |
4c788679 JG |
645 | reg->bo = NULL; |
646 | bo->surface_reg = -1; | |
e024e110 DA |
647 | } |
648 | ||
4c788679 JG |
649 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
650 | uint32_t tiling_flags, uint32_t pitch) | |
e024e110 | 651 | { |
285484e2 | 652 | struct radeon_device *rdev = bo->rdev; |
4c788679 JG |
653 | int r; |
654 | ||
285484e2 JG |
655 | if (rdev->family >= CHIP_CEDAR) { |
656 | unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; | |
657 | ||
658 | bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; | |
659 | bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; | |
660 | mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; | |
661 | tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; | |
662 | stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; | |
663 | switch (bankw) { | |
664 | case 0: | |
665 | case 1: | |
666 | case 2: | |
667 | case 4: | |
668 | case 8: | |
669 | break; | |
670 | default: | |
671 | return -EINVAL; | |
672 | } | |
673 | switch (bankh) { | |
674 | case 0: | |
675 | case 1: | |
676 | case 2: | |
677 | case 4: | |
678 | case 8: | |
679 | break; | |
680 | default: | |
681 | return -EINVAL; | |
682 | } | |
683 | switch (mtaspect) { | |
684 | case 0: | |
685 | case 1: | |
686 | case 2: | |
687 | case 4: | |
688 | case 8: | |
689 | break; | |
690 | default: | |
691 | return -EINVAL; | |
692 | } | |
693 | if (tilesplit > 6) { | |
694 | return -EINVAL; | |
695 | } | |
696 | if (stilesplit > 6) { | |
697 | return -EINVAL; | |
698 | } | |
699 | } | |
4c788679 JG |
700 | r = radeon_bo_reserve(bo, false); |
701 | if (unlikely(r != 0)) | |
702 | return r; | |
703 | bo->tiling_flags = tiling_flags; | |
704 | bo->pitch = pitch; | |
705 | radeon_bo_unreserve(bo); | |
706 | return 0; | |
e024e110 DA |
707 | } |
708 | ||
4c788679 JG |
709 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
710 | uint32_t *tiling_flags, | |
711 | uint32_t *pitch) | |
e024e110 | 712 | { |
977c38d5 ML |
713 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
714 | ||
e024e110 | 715 | if (tiling_flags) |
4c788679 | 716 | *tiling_flags = bo->tiling_flags; |
e024e110 | 717 | if (pitch) |
4c788679 | 718 | *pitch = bo->pitch; |
e024e110 DA |
719 | } |
720 | ||
4c788679 JG |
721 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
722 | bool force_drop) | |
e024e110 | 723 | { |
977c38d5 ML |
724 | if (!force_drop) |
725 | lockdep_assert_held(&bo->tbo.resv->lock.base); | |
4c788679 JG |
726 | |
727 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) | |
e024e110 DA |
728 | return 0; |
729 | ||
730 | if (force_drop) { | |
4c788679 | 731 | radeon_bo_clear_surface_reg(bo); |
e024e110 DA |
732 | return 0; |
733 | } | |
734 | ||
4c788679 | 735 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
e024e110 DA |
736 | if (!has_moved) |
737 | return 0; | |
738 | ||
4c788679 JG |
739 | if (bo->surface_reg >= 0) |
740 | radeon_bo_clear_surface_reg(bo); | |
e024e110 DA |
741 | return 0; |
742 | } | |
743 | ||
4c788679 | 744 | if ((bo->surface_reg >= 0) && !has_moved) |
e024e110 DA |
745 | return 0; |
746 | ||
4c788679 | 747 | return radeon_bo_get_surface_reg(bo); |
e024e110 DA |
748 | } |
749 | ||
750 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, | |
67e8e3f9 | 751 | struct ttm_mem_reg *new_mem) |
e024e110 | 752 | { |
d03d8589 | 753 | struct radeon_bo *rbo; |
67e8e3f9 | 754 | |
d03d8589 JG |
755 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
756 | return; | |
67e8e3f9 | 757 | |
d03d8589 | 758 | rbo = container_of(bo, struct radeon_bo, tbo); |
4c788679 | 759 | radeon_bo_check_tiling(rbo, 0, 1); |
721604a1 | 760 | radeon_vm_bo_invalidate(rbo->rdev, rbo); |
67e8e3f9 MO |
761 | |
762 | /* update statistics */ | |
763 | if (!new_mem) | |
764 | return; | |
765 | ||
766 | radeon_update_memory_usage(rbo, bo->mem.mem_type, -1); | |
767 | radeon_update_memory_usage(rbo, new_mem->mem_type, 1); | |
e024e110 DA |
768 | } |
769 | ||
0a2d50e3 | 770 | int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) |
e024e110 | 771 | { |
0a2d50e3 | 772 | struct radeon_device *rdev; |
d03d8589 | 773 | struct radeon_bo *rbo; |
c9da4a4b MD |
774 | unsigned long offset, size, lpfn; |
775 | int i, r; | |
0a2d50e3 | 776 | |
d03d8589 | 777 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
0a2d50e3 | 778 | return 0; |
d03d8589 | 779 | rbo = container_of(bo, struct radeon_bo, tbo); |
4c788679 | 780 | radeon_bo_check_tiling(rbo, 0, 0); |
0a2d50e3 | 781 | rdev = rbo->rdev; |
54409259 CK |
782 | if (bo->mem.mem_type != TTM_PL_VRAM) |
783 | return 0; | |
784 | ||
785 | size = bo->mem.num_pages << PAGE_SHIFT; | |
786 | offset = bo->mem.start << PAGE_SHIFT; | |
787 | if ((offset + size) <= rdev->mc.visible_vram_size) | |
788 | return 0; | |
789 | ||
790 | /* hurrah the memory is not visible ! */ | |
791 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); | |
c9da4a4b MD |
792 | lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; |
793 | for (i = 0; i < rbo->placement.num_placement; i++) { | |
794 | /* Force into visible VRAM */ | |
795 | if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && | |
796 | (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn)) | |
797 | rbo->placements[i].lpfn = lpfn; | |
798 | } | |
54409259 CK |
799 | r = ttm_bo_validate(bo, &rbo->placement, false, false); |
800 | if (unlikely(r == -ENOMEM)) { | |
801 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); | |
802 | return ttm_bo_validate(bo, &rbo->placement, false, false); | |
803 | } else if (unlikely(r != 0)) { | |
804 | return r; | |
0a2d50e3 | 805 | } |
54409259 CK |
806 | |
807 | offset = bo->mem.start << PAGE_SHIFT; | |
808 | /* this should never happen */ | |
809 | if ((offset + size) > rdev->mc.visible_vram_size) | |
810 | return -EINVAL; | |
811 | ||
0a2d50e3 | 812 | return 0; |
e024e110 | 813 | } |
ce580fab | 814 | |
83f30d0e | 815 | int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) |
ce580fab AK |
816 | { |
817 | int r; | |
818 | ||
12432354 | 819 | r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL); |
ce580fab AK |
820 | if (unlikely(r != 0)) |
821 | return r; | |
ce580fab AK |
822 | if (mem_type) |
823 | *mem_type = bo->tbo.mem.mem_type; | |
f2c24b83 ML |
824 | |
825 | r = ttm_bo_wait(&bo->tbo, true, true, no_wait); | |
ce580fab AK |
826 | ttm_bo_unreserve(&bo->tbo); |
827 | return r; | |
828 | } | |
587cdda8 CK |
829 | |
830 | /** | |
831 | * radeon_bo_fence - add fence to buffer object | |
832 | * | |
833 | * @bo: buffer object in question | |
834 | * @fence: fence to add | |
835 | * @shared: true if fence should be added shared | |
836 | * | |
837 | */ | |
838 | void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, | |
839 | bool shared) | |
840 | { | |
841 | struct reservation_object *resv = bo->tbo.resv; | |
842 | ||
843 | if (shared) | |
844 | reservation_object_add_shared_fence(resv, &fence->base); | |
845 | else | |
846 | reservation_object_add_excl_fence(resv, &fence->base); | |
847 | } |