Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <linux/list.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
771fe6b9 | 34 | #include <drm/drmP.h> |
760285e7 | 35 | #include <drm/radeon_drm.h> |
771fe6b9 | 36 | #include "radeon.h" |
99ee7fac | 37 | #include "radeon_trace.h" |
771fe6b9 | 38 | |
771fe6b9 JG |
39 | |
40 | int radeon_ttm_init(struct radeon_device *rdev); | |
41 | void radeon_ttm_fini(struct radeon_device *rdev); | |
4c788679 | 42 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
771fe6b9 JG |
43 | |
44 | /* | |
45 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all | |
46 | * function are calling it. | |
47 | */ | |
48 | ||
2f43651c | 49 | static void radeon_bo_clear_va(struct radeon_bo *bo) |
721604a1 JG |
50 | { |
51 | struct radeon_bo_va *bo_va, *tmp; | |
52 | ||
53 | list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) { | |
54 | /* remove from all vm address space */ | |
e971bd5e | 55 | radeon_vm_bo_rmv(bo->rdev, bo_va); |
721604a1 JG |
56 | } |
57 | } | |
58 | ||
4c788679 | 59 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
771fe6b9 | 60 | { |
4c788679 | 61 | struct radeon_bo *bo; |
771fe6b9 | 62 | |
4c788679 JG |
63 | bo = container_of(tbo, struct radeon_bo, tbo); |
64 | mutex_lock(&bo->rdev->gem.mutex); | |
65 | list_del_init(&bo->list); | |
66 | mutex_unlock(&bo->rdev->gem.mutex); | |
67 | radeon_bo_clear_surface_reg(bo); | |
721604a1 | 68 | radeon_bo_clear_va(bo); |
441921d5 | 69 | drm_gem_object_release(&bo->gem_base); |
4c788679 | 70 | kfree(bo); |
771fe6b9 JG |
71 | } |
72 | ||
d03d8589 JG |
73 | bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) |
74 | { | |
75 | if (bo->destroy == &radeon_ttm_bo_destroy) | |
76 | return true; | |
77 | return false; | |
78 | } | |
79 | ||
312ea8da JG |
80 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
81 | { | |
82 | u32 c = 0; | |
83 | ||
84 | rbo->placement.fpfn = 0; | |
93225b0d | 85 | rbo->placement.lpfn = 0; |
312ea8da | 86 | rbo->placement.placement = rbo->placements; |
20707874 | 87 | rbo->placement.busy_placement = rbo->placements; |
312ea8da JG |
88 | if (domain & RADEON_GEM_DOMAIN_VRAM) |
89 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | | |
90 | TTM_PL_FLAG_VRAM; | |
0d0b3e74 JG |
91 | if (domain & RADEON_GEM_DOMAIN_GTT) { |
92 | if (rbo->rdev->flags & RADEON_IS_AGP) { | |
93 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT; | |
94 | } else { | |
95 | rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; | |
96 | } | |
97 | } | |
98 | if (domain & RADEON_GEM_DOMAIN_CPU) { | |
99 | if (rbo->rdev->flags & RADEON_IS_AGP) { | |
dd54fee7 | 100 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM; |
0d0b3e74 | 101 | } else { |
dd54fee7 | 102 | rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM; |
0d0b3e74 JG |
103 | } |
104 | } | |
9fb03e63 JG |
105 | if (!c) |
106 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
312ea8da JG |
107 | rbo->placement.num_placement = c; |
108 | rbo->placement.num_busy_placement = c; | |
109 | } | |
110 | ||
441921d5 | 111 | int radeon_bo_create(struct radeon_device *rdev, |
268b2510 | 112 | unsigned long size, int byte_align, bool kernel, u32 domain, |
40f5cf99 | 113 | struct sg_table *sg, struct radeon_bo **bo_ptr) |
771fe6b9 | 114 | { |
4c788679 | 115 | struct radeon_bo *bo; |
771fe6b9 | 116 | enum ttm_bo_type type; |
93225b0d | 117 | unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; |
57de4ba9 | 118 | size_t acc_size; |
771fe6b9 JG |
119 | int r; |
120 | ||
441921d5 DV |
121 | size = ALIGN(size, PAGE_SIZE); |
122 | ||
949c4a34 | 123 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; |
771fe6b9 JG |
124 | if (kernel) { |
125 | type = ttm_bo_type_kernel; | |
40f5cf99 AD |
126 | } else if (sg) { |
127 | type = ttm_bo_type_sg; | |
771fe6b9 JG |
128 | } else { |
129 | type = ttm_bo_type_device; | |
130 | } | |
4c788679 | 131 | *bo_ptr = NULL; |
2b66b50b | 132 | |
57de4ba9 JG |
133 | acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, |
134 | sizeof(struct radeon_bo)); | |
135 | ||
4c788679 JG |
136 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
137 | if (bo == NULL) | |
771fe6b9 | 138 | return -ENOMEM; |
441921d5 DV |
139 | r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); |
140 | if (unlikely(r)) { | |
141 | kfree(bo); | |
142 | return r; | |
143 | } | |
4c788679 | 144 | bo->rdev = rdev; |
4c788679 JG |
145 | bo->surface_reg = -1; |
146 | INIT_LIST_HEAD(&bo->list); | |
721604a1 | 147 | INIT_LIST_HEAD(&bo->va); |
1fb107fc | 148 | radeon_ttm_placement_from_domain(bo, domain); |
5cc6fbab | 149 | /* Kernel allocation are uninterruptible */ |
db7fce39 | 150 | down_read(&rdev->pm.mclk_lock); |
1fb107fc | 151 | r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, |
0b91c4a1 | 152 | &bo->placement, page_align, !kernel, NULL, |
40f5cf99 | 153 | acc_size, sg, &radeon_ttm_bo_destroy); |
db7fce39 | 154 | up_read(&rdev->pm.mclk_lock); |
771fe6b9 | 155 | if (unlikely(r != 0)) { |
771fe6b9 JG |
156 | return r; |
157 | } | |
4c788679 | 158 | *bo_ptr = bo; |
441921d5 | 159 | |
99ee7fac | 160 | trace_radeon_bo_create(bo); |
441921d5 | 161 | |
771fe6b9 JG |
162 | return 0; |
163 | } | |
164 | ||
4c788679 | 165 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
771fe6b9 | 166 | { |
4c788679 | 167 | bool is_iomem; |
771fe6b9 JG |
168 | int r; |
169 | ||
4c788679 | 170 | if (bo->kptr) { |
771fe6b9 | 171 | if (ptr) { |
4c788679 | 172 | *ptr = bo->kptr; |
771fe6b9 | 173 | } |
771fe6b9 JG |
174 | return 0; |
175 | } | |
4c788679 | 176 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
771fe6b9 JG |
177 | if (r) { |
178 | return r; | |
179 | } | |
4c788679 | 180 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
771fe6b9 | 181 | if (ptr) { |
4c788679 | 182 | *ptr = bo->kptr; |
771fe6b9 | 183 | } |
4c788679 | 184 | radeon_bo_check_tiling(bo, 0, 0); |
771fe6b9 JG |
185 | return 0; |
186 | } | |
187 | ||
4c788679 | 188 | void radeon_bo_kunmap(struct radeon_bo *bo) |
771fe6b9 | 189 | { |
4c788679 | 190 | if (bo->kptr == NULL) |
771fe6b9 | 191 | return; |
4c788679 JG |
192 | bo->kptr = NULL; |
193 | radeon_bo_check_tiling(bo, 0, 0); | |
194 | ttm_bo_kunmap(&bo->kmap); | |
771fe6b9 JG |
195 | } |
196 | ||
4c788679 | 197 | void radeon_bo_unref(struct radeon_bo **bo) |
771fe6b9 | 198 | { |
4c788679 | 199 | struct ttm_buffer_object *tbo; |
f4b7fb94 | 200 | struct radeon_device *rdev; |
771fe6b9 | 201 | |
4c788679 | 202 | if ((*bo) == NULL) |
771fe6b9 | 203 | return; |
f4b7fb94 | 204 | rdev = (*bo)->rdev; |
4c788679 | 205 | tbo = &((*bo)->tbo); |
db7fce39 | 206 | down_read(&rdev->pm.mclk_lock); |
4c788679 | 207 | ttm_bo_unref(&tbo); |
db7fce39 | 208 | up_read(&rdev->pm.mclk_lock); |
4c788679 JG |
209 | if (tbo == NULL) |
210 | *bo = NULL; | |
771fe6b9 JG |
211 | } |
212 | ||
c4353016 MD |
213 | int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, |
214 | u64 *gpu_addr) | |
771fe6b9 | 215 | { |
312ea8da | 216 | int r, i; |
771fe6b9 | 217 | |
4c788679 JG |
218 | if (bo->pin_count) { |
219 | bo->pin_count++; | |
220 | if (gpu_addr) | |
221 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
d936622c MD |
222 | |
223 | if (max_offset != 0) { | |
224 | u64 domain_start; | |
225 | ||
226 | if (domain == RADEON_GEM_DOMAIN_VRAM) | |
227 | domain_start = bo->rdev->mc.vram_start; | |
228 | else | |
229 | domain_start = bo->rdev->mc.gtt_start; | |
e199fd42 MD |
230 | WARN_ON_ONCE(max_offset < |
231 | (radeon_bo_gpu_offset(bo) - domain_start)); | |
d936622c MD |
232 | } |
233 | ||
771fe6b9 JG |
234 | return 0; |
235 | } | |
312ea8da | 236 | radeon_ttm_placement_from_domain(bo, domain); |
3ca82da3 MD |
237 | if (domain == RADEON_GEM_DOMAIN_VRAM) { |
238 | /* force to pin into visible video ram */ | |
239 | bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
240 | } | |
c4353016 MD |
241 | if (max_offset) { |
242 | u64 lpfn = max_offset >> PAGE_SHIFT; | |
243 | ||
244 | if (!bo->placement.lpfn) | |
245 | bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; | |
246 | ||
247 | if (lpfn < bo->placement.lpfn) | |
248 | bo->placement.lpfn = lpfn; | |
249 | } | |
312ea8da JG |
250 | for (i = 0; i < bo->placement.num_placement; i++) |
251 | bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; | |
97a875cb | 252 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
4c788679 JG |
253 | if (likely(r == 0)) { |
254 | bo->pin_count = 1; | |
255 | if (gpu_addr != NULL) | |
256 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
771fe6b9 | 257 | } |
5cc6fbab | 258 | if (unlikely(r != 0)) |
4c788679 | 259 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
771fe6b9 JG |
260 | return r; |
261 | } | |
c4353016 MD |
262 | |
263 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) | |
264 | { | |
265 | return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); | |
266 | } | |
771fe6b9 | 267 | |
4c788679 | 268 | int radeon_bo_unpin(struct radeon_bo *bo) |
771fe6b9 | 269 | { |
312ea8da | 270 | int r, i; |
771fe6b9 | 271 | |
4c788679 JG |
272 | if (!bo->pin_count) { |
273 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); | |
274 | return 0; | |
771fe6b9 | 275 | } |
4c788679 JG |
276 | bo->pin_count--; |
277 | if (bo->pin_count) | |
278 | return 0; | |
312ea8da JG |
279 | for (i = 0; i < bo->placement.num_placement; i++) |
280 | bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; | |
97a875cb | 281 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
5cc6fbab | 282 | if (unlikely(r != 0)) |
4c788679 | 283 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
5cc6fbab | 284 | return r; |
cefb87ef DA |
285 | } |
286 | ||
4c788679 | 287 | int radeon_bo_evict_vram(struct radeon_device *rdev) |
771fe6b9 | 288 | { |
d796d844 DA |
289 | /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ |
290 | if (0 && (rdev->flags & RADEON_IS_IGP)) { | |
06b6476d AD |
291 | if (rdev->mc.igp_sideport_enabled == false) |
292 | /* Useless to evict on IGP chips */ | |
293 | return 0; | |
771fe6b9 JG |
294 | } |
295 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
296 | } | |
297 | ||
4c788679 | 298 | void radeon_bo_force_delete(struct radeon_device *rdev) |
771fe6b9 | 299 | { |
4c788679 | 300 | struct radeon_bo *bo, *n; |
771fe6b9 JG |
301 | |
302 | if (list_empty(&rdev->gem.objects)) { | |
303 | return; | |
304 | } | |
4c788679 JG |
305 | dev_err(rdev->dev, "Userspace still has active objects !\n"); |
306 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { | |
771fe6b9 | 307 | mutex_lock(&rdev->ddev->struct_mutex); |
4c788679 | 308 | dev_err(rdev->dev, "%p %p %lu %lu force free\n", |
31c3603d DV |
309 | &bo->gem_base, bo, (unsigned long)bo->gem_base.size, |
310 | *((unsigned long *)&bo->gem_base.refcount)); | |
4c788679 JG |
311 | mutex_lock(&bo->rdev->gem.mutex); |
312 | list_del_init(&bo->list); | |
313 | mutex_unlock(&bo->rdev->gem.mutex); | |
91132d6b | 314 | /* this should unref the ttm bo */ |
31c3603d | 315 | drm_gem_object_unreference(&bo->gem_base); |
771fe6b9 JG |
316 | mutex_unlock(&rdev->ddev->struct_mutex); |
317 | } | |
318 | } | |
319 | ||
4c788679 | 320 | int radeon_bo_init(struct radeon_device *rdev) |
771fe6b9 | 321 | { |
a4d68279 | 322 | /* Add an MTRR for the VRAM */ |
a0a53aa8 | 323 | if (!rdev->fastfb_working) { |
07ebea25 AL |
324 | rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, |
325 | rdev->mc.aper_size); | |
a0a53aa8 | 326 | } |
a4d68279 JG |
327 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", |
328 | rdev->mc.mc_vram_size >> 20, | |
329 | (unsigned long long)rdev->mc.aper_size >> 20); | |
330 | DRM_INFO("RAM width %dbits %cDR\n", | |
331 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); | |
771fe6b9 JG |
332 | return radeon_ttm_init(rdev); |
333 | } | |
334 | ||
4c788679 | 335 | void radeon_bo_fini(struct radeon_device *rdev) |
771fe6b9 JG |
336 | { |
337 | radeon_ttm_fini(rdev); | |
07ebea25 | 338 | arch_phys_wc_del(rdev->mc.vram_mtrr); |
771fe6b9 JG |
339 | } |
340 | ||
4c788679 JG |
341 | void radeon_bo_list_add_object(struct radeon_bo_list *lobj, |
342 | struct list_head *head) | |
771fe6b9 | 343 | { |
4474f3a9 | 344 | if (lobj->written) { |
147666fb | 345 | list_add(&lobj->tv.head, head); |
771fe6b9 | 346 | } else { |
147666fb | 347 | list_add_tail(&lobj->tv.head, head); |
771fe6b9 JG |
348 | } |
349 | } | |
350 | ||
ecff665f ML |
351 | int radeon_bo_list_validate(struct ww_acquire_ctx *ticket, |
352 | struct list_head *head, int ring) | |
771fe6b9 | 353 | { |
4c788679 JG |
354 | struct radeon_bo_list *lobj; |
355 | struct radeon_bo *bo; | |
20707874 | 356 | u32 domain; |
771fe6b9 JG |
357 | int r; |
358 | ||
ecff665f | 359 | r = ttm_eu_reserve_buffers(ticket, head); |
771fe6b9 | 360 | if (unlikely(r != 0)) { |
771fe6b9 JG |
361 | return r; |
362 | } | |
147666fb | 363 | list_for_each_entry(lobj, head, tv.head) { |
4c788679 JG |
364 | bo = lobj->bo; |
365 | if (!bo->pin_count) { | |
4474f3a9 | 366 | domain = lobj->domain; |
20707874 AD |
367 | |
368 | retry: | |
369 | radeon_ttm_placement_from_domain(bo, domain); | |
f2ba57b5 CK |
370 | if (ring == R600_RING_TYPE_UVD_INDEX) |
371 | radeon_uvd_force_into_uvd_segment(bo); | |
1fb107fc | 372 | r = ttm_bo_validate(&bo->tbo, &bo->placement, |
97a875cb | 373 | true, false); |
e376573f | 374 | if (unlikely(r)) { |
4474f3a9 CK |
375 | if (r != -ERESTARTSYS && domain != lobj->alt_domain) { |
376 | domain = lobj->alt_domain; | |
20707874 AD |
377 | goto retry; |
378 | } | |
1b6e5fd5 | 379 | ttm_eu_backoff_reservation(ticket, head); |
771fe6b9 | 380 | return r; |
e376573f | 381 | } |
771fe6b9 | 382 | } |
4c788679 JG |
383 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
384 | lobj->tiling_flags = bo->tiling_flags; | |
771fe6b9 JG |
385 | } |
386 | return 0; | |
387 | } | |
388 | ||
4c788679 | 389 | int radeon_bo_fbdev_mmap(struct radeon_bo *bo, |
771fe6b9 JG |
390 | struct vm_area_struct *vma) |
391 | { | |
4c788679 | 392 | return ttm_fbdev_mmap(vma, &bo->tbo); |
771fe6b9 JG |
393 | } |
394 | ||
550e2d92 | 395 | int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
771fe6b9 | 396 | { |
4c788679 | 397 | struct radeon_device *rdev = bo->rdev; |
e024e110 | 398 | struct radeon_surface_reg *reg; |
4c788679 | 399 | struct radeon_bo *old_object; |
e024e110 DA |
400 | int steal; |
401 | int i; | |
402 | ||
977c38d5 | 403 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
4c788679 JG |
404 | |
405 | if (!bo->tiling_flags) | |
e024e110 DA |
406 | return 0; |
407 | ||
4c788679 JG |
408 | if (bo->surface_reg >= 0) { |
409 | reg = &rdev->surface_regs[bo->surface_reg]; | |
410 | i = bo->surface_reg; | |
e024e110 DA |
411 | goto out; |
412 | } | |
413 | ||
414 | steal = -1; | |
415 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { | |
416 | ||
417 | reg = &rdev->surface_regs[i]; | |
4c788679 | 418 | if (!reg->bo) |
e024e110 DA |
419 | break; |
420 | ||
4c788679 | 421 | old_object = reg->bo; |
e024e110 DA |
422 | if (old_object->pin_count == 0) |
423 | steal = i; | |
424 | } | |
425 | ||
426 | /* if we are all out */ | |
427 | if (i == RADEON_GEM_MAX_SURFACES) { | |
428 | if (steal == -1) | |
429 | return -ENOMEM; | |
430 | /* find someone with a surface reg and nuke their BO */ | |
431 | reg = &rdev->surface_regs[steal]; | |
4c788679 | 432 | old_object = reg->bo; |
e024e110 DA |
433 | /* blow away the mapping */ |
434 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); | |
4c788679 | 435 | ttm_bo_unmap_virtual(&old_object->tbo); |
e024e110 DA |
436 | old_object->surface_reg = -1; |
437 | i = steal; | |
438 | } | |
439 | ||
4c788679 JG |
440 | bo->surface_reg = i; |
441 | reg->bo = bo; | |
e024e110 DA |
442 | |
443 | out: | |
4c788679 | 444 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
d961db75 | 445 | bo->tbo.mem.start << PAGE_SHIFT, |
4c788679 | 446 | bo->tbo.num_pages << PAGE_SHIFT); |
e024e110 DA |
447 | return 0; |
448 | } | |
449 | ||
4c788679 | 450 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
e024e110 | 451 | { |
4c788679 | 452 | struct radeon_device *rdev = bo->rdev; |
e024e110 DA |
453 | struct radeon_surface_reg *reg; |
454 | ||
4c788679 | 455 | if (bo->surface_reg == -1) |
e024e110 DA |
456 | return; |
457 | ||
4c788679 JG |
458 | reg = &rdev->surface_regs[bo->surface_reg]; |
459 | radeon_clear_surface_reg(rdev, bo->surface_reg); | |
e024e110 | 460 | |
4c788679 JG |
461 | reg->bo = NULL; |
462 | bo->surface_reg = -1; | |
e024e110 DA |
463 | } |
464 | ||
4c788679 JG |
465 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
466 | uint32_t tiling_flags, uint32_t pitch) | |
e024e110 | 467 | { |
285484e2 | 468 | struct radeon_device *rdev = bo->rdev; |
4c788679 JG |
469 | int r; |
470 | ||
285484e2 JG |
471 | if (rdev->family >= CHIP_CEDAR) { |
472 | unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; | |
473 | ||
474 | bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; | |
475 | bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; | |
476 | mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; | |
477 | tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; | |
478 | stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; | |
479 | switch (bankw) { | |
480 | case 0: | |
481 | case 1: | |
482 | case 2: | |
483 | case 4: | |
484 | case 8: | |
485 | break; | |
486 | default: | |
487 | return -EINVAL; | |
488 | } | |
489 | switch (bankh) { | |
490 | case 0: | |
491 | case 1: | |
492 | case 2: | |
493 | case 4: | |
494 | case 8: | |
495 | break; | |
496 | default: | |
497 | return -EINVAL; | |
498 | } | |
499 | switch (mtaspect) { | |
500 | case 0: | |
501 | case 1: | |
502 | case 2: | |
503 | case 4: | |
504 | case 8: | |
505 | break; | |
506 | default: | |
507 | return -EINVAL; | |
508 | } | |
509 | if (tilesplit > 6) { | |
510 | return -EINVAL; | |
511 | } | |
512 | if (stilesplit > 6) { | |
513 | return -EINVAL; | |
514 | } | |
515 | } | |
4c788679 JG |
516 | r = radeon_bo_reserve(bo, false); |
517 | if (unlikely(r != 0)) | |
518 | return r; | |
519 | bo->tiling_flags = tiling_flags; | |
520 | bo->pitch = pitch; | |
521 | radeon_bo_unreserve(bo); | |
522 | return 0; | |
e024e110 DA |
523 | } |
524 | ||
4c788679 JG |
525 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
526 | uint32_t *tiling_flags, | |
527 | uint32_t *pitch) | |
e024e110 | 528 | { |
977c38d5 ML |
529 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
530 | ||
e024e110 | 531 | if (tiling_flags) |
4c788679 | 532 | *tiling_flags = bo->tiling_flags; |
e024e110 | 533 | if (pitch) |
4c788679 | 534 | *pitch = bo->pitch; |
e024e110 DA |
535 | } |
536 | ||
4c788679 JG |
537 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
538 | bool force_drop) | |
e024e110 | 539 | { |
977c38d5 ML |
540 | if (!force_drop) |
541 | lockdep_assert_held(&bo->tbo.resv->lock.base); | |
4c788679 JG |
542 | |
543 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) | |
e024e110 DA |
544 | return 0; |
545 | ||
546 | if (force_drop) { | |
4c788679 | 547 | radeon_bo_clear_surface_reg(bo); |
e024e110 DA |
548 | return 0; |
549 | } | |
550 | ||
4c788679 | 551 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
e024e110 DA |
552 | if (!has_moved) |
553 | return 0; | |
554 | ||
4c788679 JG |
555 | if (bo->surface_reg >= 0) |
556 | radeon_bo_clear_surface_reg(bo); | |
e024e110 DA |
557 | return 0; |
558 | } | |
559 | ||
4c788679 | 560 | if ((bo->surface_reg >= 0) && !has_moved) |
e024e110 DA |
561 | return 0; |
562 | ||
4c788679 | 563 | return radeon_bo_get_surface_reg(bo); |
e024e110 DA |
564 | } |
565 | ||
566 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, | |
d03d8589 | 567 | struct ttm_mem_reg *mem) |
e024e110 | 568 | { |
d03d8589 JG |
569 | struct radeon_bo *rbo; |
570 | if (!radeon_ttm_bo_is_radeon_bo(bo)) | |
571 | return; | |
572 | rbo = container_of(bo, struct radeon_bo, tbo); | |
4c788679 | 573 | radeon_bo_check_tiling(rbo, 0, 1); |
721604a1 | 574 | radeon_vm_bo_invalidate(rbo->rdev, rbo); |
e024e110 DA |
575 | } |
576 | ||
0a2d50e3 | 577 | int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) |
e024e110 | 578 | { |
0a2d50e3 | 579 | struct radeon_device *rdev; |
d03d8589 | 580 | struct radeon_bo *rbo; |
0a2d50e3 JG |
581 | unsigned long offset, size; |
582 | int r; | |
583 | ||
d03d8589 | 584 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
0a2d50e3 | 585 | return 0; |
d03d8589 | 586 | rbo = container_of(bo, struct radeon_bo, tbo); |
4c788679 | 587 | radeon_bo_check_tiling(rbo, 0, 0); |
0a2d50e3 JG |
588 | rdev = rbo->rdev; |
589 | if (bo->mem.mem_type == TTM_PL_VRAM) { | |
590 | size = bo->mem.num_pages << PAGE_SHIFT; | |
d961db75 | 591 | offset = bo->mem.start << PAGE_SHIFT; |
0a2d50e3 JG |
592 | if ((offset + size) > rdev->mc.visible_vram_size) { |
593 | /* hurrah the memory is not visible ! */ | |
594 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); | |
595 | rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
97a875cb | 596 | r = ttm_bo_validate(bo, &rbo->placement, false, false); |
0a2d50e3 JG |
597 | if (unlikely(r != 0)) |
598 | return r; | |
d961db75 | 599 | offset = bo->mem.start << PAGE_SHIFT; |
0a2d50e3 JG |
600 | /* this should not happen */ |
601 | if ((offset + size) > rdev->mc.visible_vram_size) | |
602 | return -EINVAL; | |
603 | } | |
604 | } | |
605 | return 0; | |
e024e110 | 606 | } |
ce580fab | 607 | |
83f30d0e | 608 | int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) |
ce580fab AK |
609 | { |
610 | int r; | |
611 | ||
612 | r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); | |
613 | if (unlikely(r != 0)) | |
614 | return r; | |
615 | spin_lock(&bo->tbo.bdev->fence_lock); | |
616 | if (mem_type) | |
617 | *mem_type = bo->tbo.mem.mem_type; | |
618 | if (bo->tbo.sync_obj) | |
1717c0e2 | 619 | r = ttm_bo_wait(&bo->tbo, true, true, no_wait); |
ce580fab AK |
620 | spin_unlock(&bo->tbo.bdev->fence_lock); |
621 | ttm_bo_unreserve(&bo->tbo); | |
622 | return r; | |
623 | } |