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drm/radeon/kms: fix oops when set_base is call with no FB
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_mode.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
36#include <linux/i2c.h>
37#include <linux/i2c-id.h>
38#include <linux/i2c-algo-bit.h>
c93bb85b
JG		 39#include "radeon_fixed.h"
40
41struct radeon_device;
771fe6b9
JG		 42
43#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
44#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
45#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
46#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
47
48enum radeon_connector_type {
49 CONNECTOR_NONE,
50 CONNECTOR_VGA,
51 CONNECTOR_DVI_I,
52 CONNECTOR_DVI_D,
53 CONNECTOR_DVI_A,
54 CONNECTOR_STV,
55 CONNECTOR_CTV,
56 CONNECTOR_LVDS,
57 CONNECTOR_DIGITAL,
58 CONNECTOR_SCART,
59 CONNECTOR_HDMI_TYPE_A,
60 CONNECTOR_HDMI_TYPE_B,
61 CONNECTOR_0XC,
62 CONNECTOR_0XD,
63 CONNECTOR_DIN,
64 CONNECTOR_DISPLAY_PORT,
65 CONNECTOR_UNSUPPORTED
66};
67
68enum radeon_dvi_type {
69 DVI_AUTO,
70 DVI_DIGITAL,
71 DVI_ANALOG
72};
73
74enum radeon_rmx_type {
75 RMX_OFF,
76 RMX_FULL,
77 RMX_CENTER,
78 RMX_ASPECT
79};
80
81enum radeon_tv_std {
82 TV_STD_NTSC,
83 TV_STD_PAL,
84 TV_STD_PAL_M,
85 TV_STD_PAL_60,
86 TV_STD_NTSC_J,
87 TV_STD_SCART_PAL,
88 TV_STD_SECAM,
89 TV_STD_PAL_CN,
90};
91
9b9fe724
AD		 92/* radeon gpio-based i2c
93 * 1. "mask" reg and bits
94 * grabs the gpio pins for software use
95 * 0=not held 1=held
96 * 2. "a" reg and bits
97 * output pin value
98 * 0=low 1=high
99 * 3. "en" reg and bits
100 * sets the pin direction
101 * 0=input 1=output
102 * 4. "y" reg and bits
103 * input pin value
104 * 0=low 1=high
105 */
771fe6b9
JG		 106struct radeon_i2c_bus_rec {
107 bool valid;
108 uint32_t mask_clk_reg;
109 uint32_t mask_data_reg;
110 uint32_t a_clk_reg;
111 uint32_t a_data_reg;
9b9fe724
AD		 112 uint32_t en_clk_reg;
113 uint32_t en_data_reg;
114 uint32_t y_clk_reg;
115 uint32_t y_data_reg;
771fe6b9
JG		 116 uint32_t mask_clk_mask;
117 uint32_t mask_data_mask;
771fe6b9
JG		 118 uint32_t a_clk_mask;
119 uint32_t a_data_mask;
9b9fe724
AD		 120 uint32_t en_clk_mask;
121 uint32_t en_data_mask;
122 uint32_t y_clk_mask;
123 uint32_t y_data_mask;
771fe6b9
JG		 124};
125
126struct radeon_tmds_pll {
127 uint32_t freq;
128 uint32_t value;
129};
130
131#define RADEON_MAX_BIOS_CONNECTOR 16
132
133#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
134#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
135#define RADEON_PLL_USE_REF_DIV (1 << 2)
136#define RADEON_PLL_LEGACY (1 << 3)
137#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
138#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
139#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
140#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
141#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
142#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
143#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9 144#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
771fe6b9
JG		 145
146struct radeon_pll {
147 uint16_t reference_freq;
148 uint16_t reference_div;
149 uint32_t pll_in_min;
150 uint32_t pll_in_max;
151 uint32_t pll_out_min;
152 uint32_t pll_out_max;
153 uint16_t xclk;
154
155 uint32_t min_ref_div;
156 uint32_t max_ref_div;
157 uint32_t min_post_div;
158 uint32_t max_post_div;
159 uint32_t min_feedback_div;
160 uint32_t max_feedback_div;
161 uint32_t min_frac_feedback_div;
162 uint32_t max_frac_feedback_div;
163 uint32_t best_vco;
164};
165
166struct radeon_i2c_chan {
167 struct drm_device *dev;
168 struct i2c_adapter adapter;
169 struct i2c_algo_bit_data algo;
170 struct radeon_i2c_bus_rec rec;
171};
172
173/* mostly for macs, but really any system without connector tables */
174enum radeon_connector_table {
175 CT_NONE,
176 CT_GENERIC,
177 CT_IBOOK,
178 CT_POWERBOOK_EXTERNAL,
179 CT_POWERBOOK_INTERNAL,
180 CT_POWERBOOK_VGA,
181 CT_MINI_EXTERNAL,
182 CT_MINI_INTERNAL,
183 CT_IMAC_G5_ISIGHT,
184 CT_EMAC,
185};
186
fcec570b
AD		 187enum radeon_dvo_chip {
188 DVO_SIL164,
189 DVO_SIL1178,
190};
191
771fe6b9
JG		 192struct radeon_mode_info {
193 struct atom_context *atom_context;
61c4b24b 194 struct card_info *atom_card_info;
771fe6b9
JG		 195 enum radeon_connector_table connector_table;
196 bool mode_config_initialized;
c93bb85b 197 struct radeon_crtc *crtcs[2];
445282db
DA		 198 /* DVI-I properties */
199 struct drm_property *coherent_mode_property;
200 /* DAC enable load detect */
201 struct drm_property *load_detect_property;
202 /* TV standard load detect */
203 struct drm_property *tv_std_property;
204 /* legacy TMDS PLL detect */
205 struct drm_property *tmds_pll_property;
206
c93bb85b
JG		 207};
208
4ce001ab
DA		 209#define MAX_H_CODE_TIMING_LEN 32
210#define MAX_V_CODE_TIMING_LEN 32
211
212/* need to store these as reading
213 back code tables is excessive */
214struct radeon_tv_regs {
215 uint32_t tv_uv_adr;
216 uint32_t timing_cntl;
217 uint32_t hrestart;
218 uint32_t vrestart;
219 uint32_t frestart;
220 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
221 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
222};
223
771fe6b9
JG		 224struct radeon_crtc {
225 struct drm_crtc base;
226 int crtc_id;
227 u16 lut_r[256], lut_g[256], lut_b[256];
228 bool enabled;
229 bool can_tile;
230 uint32_t crtc_offset;
771fe6b9
JG		 231 struct drm_gem_object *cursor_bo;
232 uint64_t cursor_addr;
233 int cursor_width;
234 int cursor_height;
4162338a 235 uint32_t legacy_display_base_addr;
c836e862 236 uint32_t legacy_cursor_offset;
c93bb85b 237 enum radeon_rmx_type rmx_type;
c93bb85b
JG		 238 fixed20_12 vsc;
239 fixed20_12 hsc;
de2103e4 240 struct drm_display_mode native_mode;
771fe6b9
JG		 241};
242
243struct radeon_encoder_primary_dac {
244 /* legacy primary dac */
245 uint32_t ps2_pdac_adj;
246};
247
248struct radeon_encoder_lvds {
249 /* legacy lvds */
250 uint16_t panel_vcc_delay;
251 uint8_t panel_pwr_delay;
252 uint8_t panel_digon_delay;
253 uint8_t panel_blon_delay;
254 uint16_t panel_ref_divider;
255 uint8_t panel_post_divider;
256 uint16_t panel_fb_divider;
257 bool use_bios_dividers;
258 uint32_t lvds_gen_cntl;
259 /* panel mode */
de2103e4 260 struct drm_display_mode native_mode;
771fe6b9
JG		 261};
262
263struct radeon_encoder_tv_dac {
264 /* legacy tv dac */
265 uint32_t ps2_tvdac_adj;
266 uint32_t ntsc_tvdac_adj;
267 uint32_t pal_tvdac_adj;
268
4ce001ab
DA		 269 int h_pos;
270 int v_pos;
271 int h_size;
272 int supported_tv_stds;
273 bool tv_on;
771fe6b9 274 enum radeon_tv_std tv_std;
4ce001ab 275 struct radeon_tv_regs tv;
771fe6b9
JG		 276};
277
278struct radeon_encoder_int_tmds {
279 /* legacy int tmds */
280 struct radeon_tmds_pll tmds_pll[4];
281};
282
fcec570b
AD		 283struct radeon_encoder_ext_tmds {
284 /* tmds over dvo */
285 struct radeon_i2c_chan *i2c_bus;
286 uint8_t slave_addr;
287 enum radeon_dvo_chip dvo_chip;
288};
289
ebbe1cb9
AD		 290/* spread spectrum */
291struct radeon_atom_ss {
292 uint16_t percentage;
293 uint8_t type;
294 uint8_t step;
295 uint8_t delay;
296 uint8_t range;
297 uint8_t refdiv;
298};
299
771fe6b9
JG		 300struct radeon_encoder_atom_dig {
301 /* atom dig */
302 bool coherent_mode;
303 int dig_block;
304 /* atom lvds */
305 uint32_t lvds_misc;
306 uint16_t panel_pwr_delay;
ebbe1cb9 307 struct radeon_atom_ss *ss;
771fe6b9 308 /* panel mode */
de2103e4 309 struct drm_display_mode native_mode;
771fe6b9
JG		 310};
311
4ce001ab
DA		 312struct radeon_encoder_atom_dac {
313 enum radeon_tv_std tv_std;
314};
315
771fe6b9
JG		 316struct radeon_encoder {
317 struct drm_encoder base;
318 uint32_t encoder_id;
319 uint32_t devices;
4ce001ab 320 uint32_t active_device;
771fe6b9
JG		 321 uint32_t flags;
322 uint32_t pixel_clock;
323 enum radeon_rmx_type rmx_type;
de2103e4 324 struct drm_display_mode native_mode;
771fe6b9
JG		 325 void *enc_priv;
326};
327
328struct radeon_connector_atom_dig {
329 uint32_t igp_lane_info;
330 bool linkb;
331};
332
333struct radeon_connector {
334 struct drm_connector base;
335 uint32_t connector_id;
336 uint32_t devices;
337 struct radeon_i2c_chan *ddc_bus;
0294cf4f
AD		 338 /* some systems have a an hdmi and vga port with a shared ddc line */
339 bool shared_ddc;
4ce001ab
DA		 340 bool use_digital;
341 /* we need to mind the EDID between detect
342 and get modes due to analog/digital/tvencoder */
343 struct edid *edid;
771fe6b9 344 void *con_priv;
445282db 345 bool dac_load_detect;
b75fad06 346 uint16_t connector_object_id;
771fe6b9
JG		 347};
348
349struct radeon_framebuffer {
350 struct drm_framebuffer base;
351 struct drm_gem_object *obj;
352};
353
354extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
355 struct radeon_i2c_bus_rec *rec,
356 const char *name);
357extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
fcec570b
AD		 358extern void radeon_i2c_sw_get_byte(struct radeon_i2c_chan *i2c_bus,
359 u8 slave_addr,
360 u8 addr,
361 u8 *val);
362extern void radeon_i2c_sw_put_byte(struct radeon_i2c_chan *i2c,
363 u8 slave_addr,
364 u8 addr,
365 u8 val);
771fe6b9
JG		 366extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
367extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
368
369extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
370
371extern void radeon_compute_pll(struct radeon_pll *pll,
372 uint64_t freq,
373 uint32_t *dot_clock_p,
374 uint32_t *fb_div_p,
375 uint32_t *frac_fb_div_p,
376 uint32_t *ref_div_p,
377 uint32_t *post_div_p,
378 int flags);
379
380struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
381struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
382struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
383struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
384struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
385extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
386extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
4ce001ab 387extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9
JG		 388
389extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
390extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
391 struct drm_framebuffer *old_fb);
392extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
393 struct drm_display_mode *mode,
394 struct drm_display_mode *adjusted_mode,
395 int x, int y,
396 struct drm_framebuffer *old_fb);
397extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
398
399extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
400 struct drm_framebuffer *old_fb);
401extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc);
402
403extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
404 struct drm_file *file_priv,
405 uint32_t handle,
406 uint32_t width,
407 uint32_t height);
408extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
409 int x, int y);
410
411extern bool radeon_atom_get_clock_info(struct drm_device *dev);
412extern bool radeon_combios_get_clock_info(struct drm_device *dev);
413extern struct radeon_encoder_atom_dig *
414radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b
AD		 415extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
416 struct radeon_encoder_int_tmds *tmds);
417extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
418 struct radeon_encoder_int_tmds *tmds);
419extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
420 struct radeon_encoder_int_tmds *tmds);
421extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
422 struct radeon_encoder_ext_tmds *tmds);
423extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
424 struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f
AD		 425extern struct radeon_encoder_primary_dac *
426radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
427extern struct radeon_encoder_tv_dac *
428radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9
JG		 429extern struct radeon_encoder_lvds *
430radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9
JG		 431extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
432extern struct radeon_encoder_tv_dac *
433radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
434extern struct radeon_encoder_primary_dac *
435radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b
AD		 436extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
437extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9
JG		 438extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
439extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
440extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
441extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7
YZ		 442extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
443extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9
JG		 444extern void
445radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
446extern void
447radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
448extern void
449radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
450extern void
451radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
452extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
453 u16 blue, int regno);
b8c00ac5
DA		 454extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
455 u16 *blue, int regno);
771fe6b9
JG		 456struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev,
457 struct drm_mode_fb_cmd *mode_cmd,
458 struct drm_gem_object *obj);
459
460int radeonfb_probe(struct drm_device *dev);
461
462int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
463bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
464bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
465void radeon_atombios_init_crtc(struct drm_device *dev,
466 struct radeon_crtc *radeon_crtc);
467void radeon_legacy_init_crtc(struct drm_device *dev,
468 struct radeon_crtc *radeon_crtc);
ab1e9ea0 469extern void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state);
771fe6b9
JG		 470
471void radeon_get_clock_info(struct drm_device *dev);
472
473extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
474extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
475
771fe6b9
JG		 476void radeon_enc_destroy(struct drm_encoder *encoder);
477void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
478void radeon_combios_asic_init(struct drm_device *dev);
479extern int radeon_static_clocks_init(struct drm_device *dev);
c93bb85b
JG		 480bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
481 struct drm_display_mode *mode,
482 struct drm_display_mode *adjusted_mode);
4ce001ab
DA		 483void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
484
485/* legacy tv */
486void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
487 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
488 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
489void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
490 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
491 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
492void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
493 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
494 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
495void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
496 struct drm_display_mode *mode,
497 struct drm_display_mode *adjusted_mode);
771fe6b9 498#endif
Linux 6.x block layer and io_uring tree(s)