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drm/radeon/kms: DP fixes and cleanup from the ddx
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_mode.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
746c1aa4 36#include <drm_dp_helper.h>
771fe6b9
JG		 37#include <linux/i2c.h>
38#include <linux/i2c-id.h>
39#include <linux/i2c-algo-bit.h>
c93bb85b
JG		 40#include "radeon_fixed.h"
41
42struct radeon_device;
771fe6b9
JG		 43
44#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
45#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
46#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
47#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
48
49enum radeon_connector_type {
50 CONNECTOR_NONE,
51 CONNECTOR_VGA,
52 CONNECTOR_DVI_I,
53 CONNECTOR_DVI_D,
54 CONNECTOR_DVI_A,
55 CONNECTOR_STV,
56 CONNECTOR_CTV,
57 CONNECTOR_LVDS,
58 CONNECTOR_DIGITAL,
59 CONNECTOR_SCART,
60 CONNECTOR_HDMI_TYPE_A,
61 CONNECTOR_HDMI_TYPE_B,
62 CONNECTOR_0XC,
63 CONNECTOR_0XD,
64 CONNECTOR_DIN,
65 CONNECTOR_DISPLAY_PORT,
66 CONNECTOR_UNSUPPORTED
67};
68
69enum radeon_dvi_type {
70 DVI_AUTO,
71 DVI_DIGITAL,
72 DVI_ANALOG
73};
74
75enum radeon_rmx_type {
76 RMX_OFF,
77 RMX_FULL,
78 RMX_CENTER,
79 RMX_ASPECT
80};
81
82enum radeon_tv_std {
83 TV_STD_NTSC,
84 TV_STD_PAL,
85 TV_STD_PAL_M,
86 TV_STD_PAL_60,
87 TV_STD_NTSC_J,
88 TV_STD_SCART_PAL,
89 TV_STD_SECAM,
90 TV_STD_PAL_CN,
91};
92
9b9fe724
AD		 93/* radeon gpio-based i2c
94 * 1. "mask" reg and bits
95 * grabs the gpio pins for software use
96 * 0=not held 1=held
97 * 2. "a" reg and bits
98 * output pin value
99 * 0=low 1=high
100 * 3. "en" reg and bits
101 * sets the pin direction
102 * 0=input 1=output
103 * 4. "y" reg and bits
104 * input pin value
105 * 0=low 1=high
106 */
771fe6b9
JG		 107struct radeon_i2c_bus_rec {
108 bool valid;
109 uint32_t mask_clk_reg;
110 uint32_t mask_data_reg;
111 uint32_t a_clk_reg;
112 uint32_t a_data_reg;
9b9fe724
AD		 113 uint32_t en_clk_reg;
114 uint32_t en_data_reg;
115 uint32_t y_clk_reg;
116 uint32_t y_data_reg;
771fe6b9
JG		 117 uint32_t mask_clk_mask;
118 uint32_t mask_data_mask;
771fe6b9
JG		 119 uint32_t a_clk_mask;
120 uint32_t a_data_mask;
9b9fe724
AD		 121 uint32_t en_clk_mask;
122 uint32_t en_data_mask;
123 uint32_t y_clk_mask;
124 uint32_t y_data_mask;
771fe6b9
JG		 125};
126
127struct radeon_tmds_pll {
128 uint32_t freq;
129 uint32_t value;
130};
131
132#define RADEON_MAX_BIOS_CONNECTOR 16
133
134#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
135#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
136#define RADEON_PLL_USE_REF_DIV (1 << 2)
137#define RADEON_PLL_LEGACY (1 << 3)
138#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
139#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
140#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
141#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
142#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
143#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
144#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9 145#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
771fe6b9
JG		 146
147struct radeon_pll {
148 uint16_t reference_freq;
149 uint16_t reference_div;
150 uint32_t pll_in_min;
151 uint32_t pll_in_max;
152 uint32_t pll_out_min;
153 uint32_t pll_out_max;
154 uint16_t xclk;
155
156 uint32_t min_ref_div;
157 uint32_t max_ref_div;
158 uint32_t min_post_div;
159 uint32_t max_post_div;
160 uint32_t min_feedback_div;
161 uint32_t max_feedback_div;
162 uint32_t min_frac_feedback_div;
163 uint32_t max_frac_feedback_div;
164 uint32_t best_vco;
165};
166
167struct radeon_i2c_chan {
771fe6b9 168 struct i2c_adapter adapter;
746c1aa4
DA		 169 struct drm_device *dev;
170 union {
171 struct i2c_algo_dp_aux_data dp;
172 struct i2c_algo_bit_data bit;
173 } algo;
771fe6b9 174 struct radeon_i2c_bus_rec rec;
746c1aa4 175 uint8_t i2c_id;
771fe6b9
JG		 176};
177
178/* mostly for macs, but really any system without connector tables */
179enum radeon_connector_table {
180 CT_NONE,
181 CT_GENERIC,
182 CT_IBOOK,
183 CT_POWERBOOK_EXTERNAL,
184 CT_POWERBOOK_INTERNAL,
185 CT_POWERBOOK_VGA,
186 CT_MINI_EXTERNAL,
187 CT_MINI_INTERNAL,
188 CT_IMAC_G5_ISIGHT,
189 CT_EMAC,
190};
191
fcec570b
AD		 192enum radeon_dvo_chip {
193 DVO_SIL164,
194 DVO_SIL1178,
195};
196
771fe6b9
JG		 197struct radeon_mode_info {
198 struct atom_context *atom_context;
61c4b24b 199 struct card_info *atom_card_info;
771fe6b9
JG		 200 enum radeon_connector_table connector_table;
201 bool mode_config_initialized;
c93bb85b 202 struct radeon_crtc *crtcs[2];
445282db
DA		 203 /* DVI-I properties */
204 struct drm_property *coherent_mode_property;
205 /* DAC enable load detect */
206 struct drm_property *load_detect_property;
207 /* TV standard load detect */
208 struct drm_property *tv_std_property;
209 /* legacy TMDS PLL detect */
210 struct drm_property *tmds_pll_property;
211
c93bb85b
JG		 212};
213
4ce001ab
DA		 214#define MAX_H_CODE_TIMING_LEN 32
215#define MAX_V_CODE_TIMING_LEN 32
216
217/* need to store these as reading
218 back code tables is excessive */
219struct radeon_tv_regs {
220 uint32_t tv_uv_adr;
221 uint32_t timing_cntl;
222 uint32_t hrestart;
223 uint32_t vrestart;
224 uint32_t frestart;
225 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
226 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
227};
228
771fe6b9
JG		 229struct radeon_crtc {
230 struct drm_crtc base;
231 int crtc_id;
232 u16 lut_r[256], lut_g[256], lut_b[256];
233 bool enabled;
234 bool can_tile;
235 uint32_t crtc_offset;
771fe6b9
JG		 236 struct drm_gem_object *cursor_bo;
237 uint64_t cursor_addr;
238 int cursor_width;
239 int cursor_height;
4162338a 240 uint32_t legacy_display_base_addr;
c836e862 241 uint32_t legacy_cursor_offset;
c93bb85b 242 enum radeon_rmx_type rmx_type;
c93bb85b
JG		 243 fixed20_12 vsc;
244 fixed20_12 hsc;
de2103e4 245 struct drm_display_mode native_mode;
771fe6b9
JG		 246};
247
248struct radeon_encoder_primary_dac {
249 /* legacy primary dac */
250 uint32_t ps2_pdac_adj;
251};
252
253struct radeon_encoder_lvds {
254 /* legacy lvds */
255 uint16_t panel_vcc_delay;
256 uint8_t panel_pwr_delay;
257 uint8_t panel_digon_delay;
258 uint8_t panel_blon_delay;
259 uint16_t panel_ref_divider;
260 uint8_t panel_post_divider;
261 uint16_t panel_fb_divider;
262 bool use_bios_dividers;
263 uint32_t lvds_gen_cntl;
264 /* panel mode */
de2103e4 265 struct drm_display_mode native_mode;
771fe6b9
JG		 266};
267
268struct radeon_encoder_tv_dac {
269 /* legacy tv dac */
270 uint32_t ps2_tvdac_adj;
271 uint32_t ntsc_tvdac_adj;
272 uint32_t pal_tvdac_adj;
273
4ce001ab
DA		 274 int h_pos;
275 int v_pos;
276 int h_size;
277 int supported_tv_stds;
278 bool tv_on;
771fe6b9 279 enum radeon_tv_std tv_std;
4ce001ab 280 struct radeon_tv_regs tv;
771fe6b9
JG		 281};
282
283struct radeon_encoder_int_tmds {
284 /* legacy int tmds */
285 struct radeon_tmds_pll tmds_pll[4];
286};
287
fcec570b
AD		 288struct radeon_encoder_ext_tmds {
289 /* tmds over dvo */
290 struct radeon_i2c_chan *i2c_bus;
291 uint8_t slave_addr;
292 enum radeon_dvo_chip dvo_chip;
293};
294
ebbe1cb9
AD		 295/* spread spectrum */
296struct radeon_atom_ss {
297 uint16_t percentage;
298 uint8_t type;
299 uint8_t step;
300 uint8_t delay;
301 uint8_t range;
302 uint8_t refdiv;
303};
304
771fe6b9
JG		 305struct radeon_encoder_atom_dig {
306 /* atom dig */
307 bool coherent_mode;
308 int dig_block;
309 /* atom lvds */
310 uint32_t lvds_misc;
311 uint16_t panel_pwr_delay;
ebbe1cb9 312 struct radeon_atom_ss *ss;
771fe6b9 313 /* panel mode */
de2103e4 314 struct drm_display_mode native_mode;
771fe6b9
JG		 315};
316
4ce001ab
DA		 317struct radeon_encoder_atom_dac {
318 enum radeon_tv_std tv_std;
319};
320
771fe6b9
JG		 321struct radeon_encoder {
322 struct drm_encoder base;
323 uint32_t encoder_id;
324 uint32_t devices;
4ce001ab 325 uint32_t active_device;
771fe6b9
JG		 326 uint32_t flags;
327 uint32_t pixel_clock;
328 enum radeon_rmx_type rmx_type;
de2103e4 329 struct drm_display_mode native_mode;
771fe6b9
JG		 330 void *enc_priv;
331};
332
333struct radeon_connector_atom_dig {
334 uint32_t igp_lane_info;
335 bool linkb;
746c1aa4
DA		 336 uint16_t uc_i2c_id;
337 struct radeon_i2c_chan *dp_i2c_bus;
1a66c95a 338 u8 dpcd[8];
771fe6b9
JG		 339};
340
341struct radeon_connector {
342 struct drm_connector base;
343 uint32_t connector_id;
344 uint32_t devices;
345 struct radeon_i2c_chan *ddc_bus;
0294cf4f
AD		 346 /* some systems have a an hdmi and vga port with a shared ddc line */
347 bool shared_ddc;
4ce001ab
DA		 348 bool use_digital;
349 /* we need to mind the EDID between detect
350 and get modes due to analog/digital/tvencoder */
351 struct edid *edid;
771fe6b9 352 void *con_priv;
445282db 353 bool dac_load_detect;
b75fad06 354 uint16_t connector_object_id;
746c1aa4
DA		 355 /* need to keep this for display port */
356//
771fe6b9
JG		 357};
358
359struct radeon_framebuffer {
360 struct drm_framebuffer base;
361 struct drm_gem_object *obj;
362};
363
746c1aa4 364extern int radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
1a66c95a 365extern void radeon_dp_getdpcd(struct radeon_connector *connector);
746c1aa4
DA		 366extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
367 uint8_t write_byte, uint8_t *read_byte);
368
369extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
370 const char *name, bool dp, u8 i2c_id);
771fe6b9
JG		 371extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
372 struct radeon_i2c_bus_rec *rec,
373 const char *name);
374extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
fcec570b
AD		 375extern void radeon_i2c_sw_get_byte(struct radeon_i2c_chan *i2c_bus,
376 u8 slave_addr,
377 u8 addr,
378 u8 *val);
379extern void radeon_i2c_sw_put_byte(struct radeon_i2c_chan *i2c,
380 u8 slave_addr,
381 u8 addr,
382 u8 val);
771fe6b9
JG		 383extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
384extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
385
386extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
387
388extern void radeon_compute_pll(struct radeon_pll *pll,
389 uint64_t freq,
390 uint32_t *dot_clock_p,
391 uint32_t *fb_div_p,
392 uint32_t *frac_fb_div_p,
393 uint32_t *ref_div_p,
394 uint32_t *post_div_p,
395 int flags);
396
1f3b6a45
DA		 397extern void radeon_setup_encoder_clones(struct drm_device *dev);
398
771fe6b9
JG		 399struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
400struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
401struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
402struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
403struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
404extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
32f48ffe 405extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9 406extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
4ce001ab 407extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9
JG		 408
409extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
410extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
411 struct drm_framebuffer *old_fb);
412extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
413 struct drm_display_mode *mode,
414 struct drm_display_mode *adjusted_mode,
415 int x, int y,
416 struct drm_framebuffer *old_fb);
417extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
418
419extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
420 struct drm_framebuffer *old_fb);
421extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc);
422
423extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
424 struct drm_file *file_priv,
425 uint32_t handle,
426 uint32_t width,
427 uint32_t height);
428extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
429 int x, int y);
430
431extern bool radeon_atom_get_clock_info(struct drm_device *dev);
432extern bool radeon_combios_get_clock_info(struct drm_device *dev);
433extern struct radeon_encoder_atom_dig *
434radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b
AD		 435extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
436 struct radeon_encoder_int_tmds *tmds);
437extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
438 struct radeon_encoder_int_tmds *tmds);
439extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
440 struct radeon_encoder_int_tmds *tmds);
441extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
442 struct radeon_encoder_ext_tmds *tmds);
443extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
444 struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f
AD		 445extern struct radeon_encoder_primary_dac *
446radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
447extern struct radeon_encoder_tv_dac *
448radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9
JG		 449extern struct radeon_encoder_lvds *
450radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9
JG		 451extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
452extern struct radeon_encoder_tv_dac *
453radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
454extern struct radeon_encoder_primary_dac *
455radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b
AD		 456extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
457extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9
JG		 458extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
459extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
460extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
461extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7
YZ		 462extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
463extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9
JG		 464extern void
465radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
466extern void
467radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
468extern void
469radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
470extern void
471radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
472extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
473 u16 blue, int regno);
b8c00ac5
DA		 474extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
475 u16 *blue, int regno);
771fe6b9
JG		 476struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev,
477 struct drm_mode_fb_cmd *mode_cmd,
478 struct drm_gem_object *obj);
479
480int radeonfb_probe(struct drm_device *dev);
481
482int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
483bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
484bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
485void radeon_atombios_init_crtc(struct drm_device *dev,
486 struct radeon_crtc *radeon_crtc);
487void radeon_legacy_init_crtc(struct drm_device *dev,
488 struct radeon_crtc *radeon_crtc);
ab1e9ea0 489extern void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state);
771fe6b9
JG		 490
491void radeon_get_clock_info(struct drm_device *dev);
492
493extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
494extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
495
771fe6b9
JG		 496void radeon_enc_destroy(struct drm_encoder *encoder);
497void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
498void radeon_combios_asic_init(struct drm_device *dev);
499extern int radeon_static_clocks_init(struct drm_device *dev);
c93bb85b
JG		 500bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
501 struct drm_display_mode *mode,
502 struct drm_display_mode *adjusted_mode);
4ce001ab
DA		 503void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
504
505/* legacy tv */
506void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
507 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
508 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
509void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
510 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
511 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
512void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
513 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
514 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
515void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
516 struct drm_display_mode *mode,
517 struct drm_display_mode *adjusted_mode);
771fe6b9 518#endif
Linux 6.x block layer and io_uring tree(s)