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drm/radeon: fix sparse warning
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_legacy_encoders.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
771fe6b9
JG		 29#include "radeon.h"
30#include "atom.h"
63ec0119
MD		 31#include <linux/backlight.h>
32#ifdef CONFIG_PMAC_BACKLIGHT
33#include <asm/backlight.h>
34#endif
771fe6b9 35
4ce001ab
DA		 36static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
37{
38 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
39 struct drm_encoder_helper_funcs *encoder_funcs;
40
41 encoder_funcs = encoder->helper_private;
42 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
43 radeon_encoder->active_device = 0;
44}
771fe6b9 45
63ec0119 46static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
771fe6b9
JG		 47{
48 struct drm_device *dev = encoder->dev;
49 struct radeon_device *rdev = dev->dev_private;
50 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
51 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
52 int panel_pwr_delay = 2000;
3890ddf5 53 bool is_mac = false;
63ec0119 54 uint8_t backlight_level;
d9fdaafb 55 DRM_DEBUG_KMS("\n");
771fe6b9 56
63ec0119
MD		 57 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
58 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
59
771fe6b9
JG		 60 if (radeon_encoder->enc_priv) {
61 if (rdev->is_atom_bios) {
62 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
63 panel_pwr_delay = lvds->panel_pwr_delay;
63ec0119
MD		 64 if (lvds->bl_dev)
65 backlight_level = lvds->backlight_level;
771fe6b9
JG		 66 } else {
67 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
68 panel_pwr_delay = lvds->panel_pwr_delay;
63ec0119
MD		 69 if (lvds->bl_dev)
70 backlight_level = lvds->backlight_level;
771fe6b9
JG		 71 }
72 }
73
3890ddf5
AD		 74 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
75 * Taken from radeonfb.
76 */
77 if ((rdev->mode_info.connector_table == CT_IBOOK) ||
78 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
79 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
80 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
81 is_mac = true;
82
771fe6b9
JG		 83 switch (mode) {
84 case DRM_MODE_DPMS_ON:
85 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
86 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
87 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
88 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
89 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
90 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
4de833c3 91 mdelay(1);
771fe6b9
JG		 92
93 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
94 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
95 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
96
63ec0119
MD		 97 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
98 RADEON_LVDS_BL_MOD_LEVEL_MASK);
99 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
100 RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
101 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
3890ddf5
AD		 102 if (is_mac)
103 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
4de833c3 104 mdelay(panel_pwr_delay);
771fe6b9
JG		 105 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
106 break;
107 case DRM_MODE_DPMS_STANDBY:
108 case DRM_MODE_DPMS_SUSPEND:
109 case DRM_MODE_DPMS_OFF:
110 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
111 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
771fe6b9 112 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
3890ddf5
AD		 113 if (is_mac) {
114 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
115 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
116 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
117 } else {
118 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
119 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
120 }
4de833c3 121 mdelay(panel_pwr_delay);
771fe6b9
JG		 122 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
123 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
4de833c3 124 mdelay(panel_pwr_delay);
771fe6b9
JG		 125 break;
126 }
127
128 if (rdev->is_atom_bios)
129 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
130 else
131 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
c913e23a 132
771fe6b9
JG		 133}
134
63ec0119
MD		 135static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
136{
137 struct radeon_device *rdev = encoder->dev->dev_private;
138 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
139 DRM_DEBUG("\n");
140
141 if (radeon_encoder->enc_priv) {
142 if (rdev->is_atom_bios) {
143 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
144 lvds->dpms_mode = mode;
145 } else {
146 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
147 lvds->dpms_mode = mode;
148 }
149 }
150
151 radeon_legacy_lvds_update(encoder, mode);
152}
153
771fe6b9
JG		 154static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
155{
156 struct radeon_device *rdev = encoder->dev->dev_private;
157
158 if (rdev->is_atom_bios)
159 radeon_atom_output_lock(encoder, true);
160 else
161 radeon_combios_output_lock(encoder, true);
162 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
163}
164
165static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
166{
167 struct radeon_device *rdev = encoder->dev->dev_private;
168
169 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
170 if (rdev->is_atom_bios)
171 radeon_atom_output_lock(encoder, false);
172 else
173 radeon_combios_output_lock(encoder, false);
174}
175
176static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
177 struct drm_display_mode *mode,
178 struct drm_display_mode *adjusted_mode)
179{
180 struct drm_device *dev = encoder->dev;
181 struct radeon_device *rdev = dev->dev_private;
182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
183 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
184 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
185
d9fdaafb 186 DRM_DEBUG_KMS("\n");
771fe6b9 187
771fe6b9
JG		 188 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
189 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
190
191 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
32f48ffe
AD		 192 if (rdev->is_atom_bios) {
193 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
194 * need to call that on resume to set up the reg properly.
195 */
196 radeon_encoder->pixel_clock = adjusted_mode->clock;
197 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
198 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
199 } else {
771fe6b9
JG		 200 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
201 if (lvds) {
d9fdaafb 202 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
771fe6b9
JG		 203 lvds_gen_cntl = lvds->lvds_gen_cntl;
204 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
205 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
206 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
207 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
208 } else
209 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
32f48ffe 210 }
771fe6b9
JG		 211 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
212 lvds_gen_cntl &= ~(RADEON_LVDS_ON |
213 RADEON_LVDS_BLON |
214 RADEON_LVDS_EN |
215 RADEON_LVDS_RST_FM);
216
217 if (ASIC_IS_R300(rdev))
218 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
219
220 if (radeon_crtc->crtc_id == 0) {
221 if (ASIC_IS_R300(rdev)) {
c93bb85b 222 if (radeon_encoder->rmx_type != RMX_OFF)
771fe6b9
JG		 223 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
224 } else
225 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
226 } else {
227 if (ASIC_IS_R300(rdev))
228 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
229 else
230 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
231 }
232
233 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
234 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
235 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
236
237 if (rdev->family == CHIP_RV410)
238 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
239
240 if (rdev->is_atom_bios)
241 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
242 else
243 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
244}
245
80297e87 246static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
e811f5ae 247 const struct drm_display_mode *mode,
80297e87 248 struct drm_display_mode *adjusted_mode)
771fe6b9
JG		 249{
250 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
251
8c2a6d73
AD		 252 /* set the active encoder to connector routing */
253 radeon_encoder_set_active_device(encoder);
771fe6b9
JG		 254 drm_mode_set_crtcinfo(adjusted_mode, 0);
255
80297e87 256 /* get the native mode for LVDS */
3515387b
AD		 257 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
258 radeon_panel_mode_fixup(encoder, adjusted_mode);
771fe6b9
JG		 259
260 return true;
261}
262
263static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
264 .dpms = radeon_legacy_lvds_dpms,
80297e87 265 .mode_fixup = radeon_legacy_mode_fixup,
771fe6b9
JG		 266 .prepare = radeon_legacy_lvds_prepare,
267 .mode_set = radeon_legacy_lvds_mode_set,
268 .commit = radeon_legacy_lvds_commit,
4ce001ab 269 .disable = radeon_legacy_encoder_disable,
771fe6b9
JG		 270};
271
6d92f81d
AD		 272u8
273radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder)
274{
275 struct drm_device *dev = radeon_encoder->base.dev;
276 struct radeon_device *rdev = dev->dev_private;
277 u8 backlight_level;
278
279 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
280 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
281
282 return backlight_level;
283}
284
37e9b6a6
AD		 285void
286radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
63ec0119 287{
63ec0119
MD		 288 struct drm_device *dev = radeon_encoder->base.dev;
289 struct radeon_device *rdev = dev->dev_private;
290 int dpms_mode = DRM_MODE_DPMS_ON;
291
292 if (radeon_encoder->enc_priv) {
293 if (rdev->is_atom_bios) {
294 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
37e9b6a6
AD		 295 if (lvds->backlight_level > 0)
296 dpms_mode = lvds->dpms_mode;
297 else
298 dpms_mode = DRM_MODE_DPMS_OFF;
299 lvds->backlight_level = level;
63ec0119
MD		 300 } else {
301 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
37e9b6a6
AD		 302 if (lvds->backlight_level > 0)
303 dpms_mode = lvds->dpms_mode;
304 else
305 dpms_mode = DRM_MODE_DPMS_OFF;
306 lvds->backlight_level = level;
63ec0119
MD		 307 }
308 }
309
37e9b6a6
AD		 310 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
311}
312
cd23492a
AD		 313#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
314
315static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
316{
317 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
318 uint8_t level;
319
320 /* Convert brightness to hardware level */
321 if (bd->props.brightness < 0)
322 level = 0;
323 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
324 level = RADEON_MAX_BL_LEVEL;
325 else
326 level = bd->props.brightness;
327
328 if (pdata->negative)
329 level = RADEON_MAX_BL_LEVEL - level;
330
331 return level;
332}
333
37e9b6a6
AD		 334static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
335{
336 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
337 struct radeon_encoder *radeon_encoder = pdata->encoder;
338
339 radeon_legacy_set_backlight_level(radeon_encoder,
340 radeon_legacy_lvds_level(bd));
63ec0119
MD		 341
342 return 0;
343}
344
345static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
346{
347 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
348 struct radeon_encoder *radeon_encoder = pdata->encoder;
349 struct drm_device *dev = radeon_encoder->base.dev;
350 struct radeon_device *rdev = dev->dev_private;
351 uint8_t backlight_level;
352
353 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
354 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
355
91030880 356 return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level;
63ec0119
MD		 357}
358
359static const struct backlight_ops radeon_backlight_ops = {
360 .get_brightness = radeon_legacy_backlight_get_brightness,
361 .update_status = radeon_legacy_backlight_update_status,
362};
363
364void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
365 struct drm_connector *drm_connector)
366{
367 struct drm_device *dev = radeon_encoder->base.dev;
368 struct radeon_device *rdev = dev->dev_private;
369 struct backlight_device *bd;
370 struct backlight_properties props;
371 struct radeon_backlight_privdata *pdata;
372 uint8_t backlight_level;
373
374 if (!radeon_encoder->enc_priv)
375 return;
376
377#ifdef CONFIG_PMAC_BACKLIGHT
378 if (!pmac_has_backlight_type("ati") &&
379 !pmac_has_backlight_type("mnca"))
380 return;
381#endif
382
383 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
384 if (!pdata) {
385 DRM_ERROR("Memory allocation failed\n");
386 goto error;
387 }
388
af437cfd 389 memset(&props, 0, sizeof(props));
91030880 390 props.max_brightness = RADEON_MAX_BL_LEVEL;
63ec0119
MD		 391 props.type = BACKLIGHT_RAW;
392 bd = backlight_device_register("radeon_bl", &drm_connector->kdev,
393 pdata, &radeon_backlight_ops, &props);
394 if (IS_ERR(bd)) {
395 DRM_ERROR("Backlight registration failed\n");
396 goto error;
397 }
398
399 pdata->encoder = radeon_encoder;
400
401 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
402 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
403
404 /* First, try to detect backlight level sense based on the assumption
405 * that firmware set it up at full brightness
406 */
407 if (backlight_level == 0)
408 pdata->negative = true;
409 else if (backlight_level == 0xff)
410 pdata->negative = false;
411 else {
412 /* XXX hack... maybe some day we can figure out in what direction
413 * backlight should work on a given panel?
414 */
415 pdata->negative = (rdev->family != CHIP_RV200 &&
416 rdev->family != CHIP_RV250 &&
417 rdev->family != CHIP_RV280 &&
418 rdev->family != CHIP_RV350);
419
420#ifdef CONFIG_PMAC_BACKLIGHT
421 pdata->negative = (pdata->negative ||
422 of_machine_is_compatible("PowerBook4,3") ||
423 of_machine_is_compatible("PowerBook6,3") ||
424 of_machine_is_compatible("PowerBook6,5"));
425#endif
426 }
427
428 if (rdev->is_atom_bios) {
429 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
430 lvds->bl_dev = bd;
431 } else {
432 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
433 lvds->bl_dev = bd;
434 }
435
436 bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
437 bd->props.power = FB_BLANK_UNBLANK;
438 backlight_update_status(bd);
439
440 DRM_INFO("radeon legacy LVDS backlight initialized\n");
441
442 return;
443
444error:
445 kfree(pdata);
446 return;
447}
448
449static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
450{
451 struct drm_device *dev = radeon_encoder->base.dev;
452 struct radeon_device *rdev = dev->dev_private;
453 struct backlight_device *bd = NULL;
454
455 if (!radeon_encoder->enc_priv)
456 return;
457
458 if (rdev->is_atom_bios) {
459 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
460 bd = lvds->bl_dev;
461 lvds->bl_dev = NULL;
462 } else {
463 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
464 bd = lvds->bl_dev;
465 lvds->bl_dev = NULL;
466 }
467
468 if (bd) {
91030880 469 struct radeon_backlight_privdata *pdata;
63ec0119
MD		 470
471 pdata = bl_get_data(bd);
472 backlight_device_unregister(bd);
473 kfree(pdata);
474
475 DRM_INFO("radeon legacy LVDS backlight unloaded\n");
476 }
477}
478
479#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
480
481void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
482{
483}
484
485static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
486{
487}
488
489#endif
490
491
492static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
493{
494 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
495
496 if (radeon_encoder->enc_priv) {
497 radeon_legacy_backlight_exit(radeon_encoder);
498 kfree(radeon_encoder->enc_priv);
499 }
500 drm_encoder_cleanup(encoder);
501 kfree(radeon_encoder);
502}
771fe6b9
JG		 503
504static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
63ec0119 505 .destroy = radeon_lvds_enc_destroy,
771fe6b9
JG		 506};
507
771fe6b9
JG		 508static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
509{
510 struct drm_device *dev = encoder->dev;
511 struct radeon_device *rdev = dev->dev_private;
512 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
513 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
514 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
515
d9fdaafb 516 DRM_DEBUG_KMS("\n");
771fe6b9
JG		 517
518 switch (mode) {
519 case DRM_MODE_DPMS_ON:
520 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
521 dac_cntl &= ~RADEON_DAC_PDWN;
522 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
523 RADEON_DAC_PDWN_G |
524 RADEON_DAC_PDWN_B);
525 break;
526 case DRM_MODE_DPMS_STANDBY:
527 case DRM_MODE_DPMS_SUSPEND:
528 case DRM_MODE_DPMS_OFF:
529 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
530 dac_cntl |= RADEON_DAC_PDWN;
531 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
532 RADEON_DAC_PDWN_G |
533 RADEON_DAC_PDWN_B);
534 break;
535 }
536
537 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
538 WREG32(RADEON_DAC_CNTL, dac_cntl);
539 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
540
541 if (rdev->is_atom_bios)
542 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
543 else
544 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
c913e23a 545
771fe6b9
JG		 546}
547
548static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
549{
550 struct radeon_device *rdev = encoder->dev->dev_private;
551
552 if (rdev->is_atom_bios)
553 radeon_atom_output_lock(encoder, true);
554 else
555 radeon_combios_output_lock(encoder, true);
556 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
557}
558
559static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
560{
561 struct radeon_device *rdev = encoder->dev->dev_private;
562
563 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
564
565 if (rdev->is_atom_bios)
566 radeon_atom_output_lock(encoder, false);
567 else
568 radeon_combios_output_lock(encoder, false);
569}
570
571static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
572 struct drm_display_mode *mode,
573 struct drm_display_mode *adjusted_mode)
574{
575 struct drm_device *dev = encoder->dev;
576 struct radeon_device *rdev = dev->dev_private;
577 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
578 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
579 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
580
d9fdaafb 581 DRM_DEBUG_KMS("\n");
771fe6b9 582
771fe6b9
JG		 583 if (radeon_crtc->crtc_id == 0) {
584 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
585 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
586 ~(RADEON_DISP_DAC_SOURCE_MASK);
587 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
588 } else {
589 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
590 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
591 }
592 } else {
593 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
594 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
595 ~(RADEON_DISP_DAC_SOURCE_MASK);
596 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
597 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
598 } else {
599 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
600 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
601 }
602 }
603
604 dac_cntl = (RADEON_DAC_MASK_ALL |
605 RADEON_DAC_VGA_ADR_EN |
606 /* TODO 6-bits */
607 RADEON_DAC_8BIT_EN);
608
609 WREG32_P(RADEON_DAC_CNTL,
610 dac_cntl,
611 RADEON_DAC_RANGE_CNTL |
612 RADEON_DAC_BLANKING);
613
614 if (radeon_encoder->enc_priv) {
615 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
616 dac_macro_cntl = p_dac->ps2_pdac_adj;
617 } else
618 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
619 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
620 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
621
622 if (rdev->is_atom_bios)
623 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
624 else
625 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
626}
627
628static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
629 struct drm_connector *connector)
630{
631 struct drm_device *dev = encoder->dev;
632 struct radeon_device *rdev = dev->dev_private;
633 uint32_t vclk_ecp_cntl, crtc_ext_cntl;
634 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
635 enum drm_connector_status found = connector_status_disconnected;
636 bool color = true;
637
638 /* save the regs we need */
639 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
640 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
641 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
642 dac_cntl = RREG32(RADEON_DAC_CNTL);
643 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
644
645 tmp = vclk_ecp_cntl &
646 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
647 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
648
649 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
650 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
651
652 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
653 RADEON_DAC_FORCE_DATA_EN;
654
655 if (color)
656 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
657 else
658 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
659
660 if (ASIC_IS_R300(rdev))
661 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
662 else
663 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
664
665 WREG32(RADEON_DAC_EXT_CNTL, tmp);
666
667 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
668 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
669 WREG32(RADEON_DAC_CNTL, tmp);
670
671 tmp &= ~(RADEON_DAC_PDWN_R |
672 RADEON_DAC_PDWN_G |
673 RADEON_DAC_PDWN_B);
674
675 WREG32(RADEON_DAC_MACRO_CNTL, tmp);
676
4de833c3 677 mdelay(2);
771fe6b9
JG		 678
679 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
680 found = connector_status_connected;
681
682 /* restore the regs we used */
683 WREG32(RADEON_DAC_CNTL, dac_cntl);
684 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
685 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
686 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
687 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
688
689 return found;
690}
691
692static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
693 .dpms = radeon_legacy_primary_dac_dpms,
80297e87 694 .mode_fixup = radeon_legacy_mode_fixup,
771fe6b9
JG		 695 .prepare = radeon_legacy_primary_dac_prepare,
696 .mode_set = radeon_legacy_primary_dac_mode_set,
697 .commit = radeon_legacy_primary_dac_commit,
698 .detect = radeon_legacy_primary_dac_detect,
4ce001ab 699 .disable = radeon_legacy_encoder_disable,
771fe6b9
JG		 700};
701
702
703static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
704 .destroy = radeon_enc_destroy,
705};
706
771fe6b9
JG		 707static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
708{
709 struct drm_device *dev = encoder->dev;
710 struct radeon_device *rdev = dev->dev_private;
711 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
d9fdaafb 712 DRM_DEBUG_KMS("\n");
771fe6b9
JG		 713
714 switch (mode) {
715 case DRM_MODE_DPMS_ON:
716 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
717 break;
718 case DRM_MODE_DPMS_STANDBY:
719 case DRM_MODE_DPMS_SUSPEND:
720 case DRM_MODE_DPMS_OFF:
721 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
722 break;
723 }
724
725 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
726
727 if (rdev->is_atom_bios)
728 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
729 else
730 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
c913e23a 731
771fe6b9
JG		 732}
733
734static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
735{
736 struct radeon_device *rdev = encoder->dev->dev_private;
737
738 if (rdev->is_atom_bios)
739 radeon_atom_output_lock(encoder, true);
740 else
741 radeon_combios_output_lock(encoder, true);
742 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
743}
744
745static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
746{
747 struct radeon_device *rdev = encoder->dev->dev_private;
748
749 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
750
751 if (rdev->is_atom_bios)
752 radeon_atom_output_lock(encoder, true);
753 else
754 radeon_combios_output_lock(encoder, true);
755}
756
757static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
758 struct drm_display_mode *mode,
759 struct drm_display_mode *adjusted_mode)
760{
761 struct drm_device *dev = encoder->dev;
762 struct radeon_device *rdev = dev->dev_private;
763 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
764 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
765 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
766 int i;
767
d9fdaafb 768 DRM_DEBUG_KMS("\n");
771fe6b9 769
771fe6b9
JG		 770 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
771 tmp &= 0xfffff;
772 if (rdev->family == CHIP_RV280) {
773 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
774 tmp ^= (1 << 22);
775 tmds_pll_cntl ^= (1 << 22);
776 }
777
778 if (radeon_encoder->enc_priv) {
779 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
780
781 for (i = 0; i < 4; i++) {
782 if (tmds->tmds_pll[i].freq == 0)
783 break;
784 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
785 tmp = tmds->tmds_pll[i].value ;
786 break;
787 }
788 }
789 }
790
791 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
792 if (tmp & 0xfff00000)
793 tmds_pll_cntl = tmp;
794 else {
795 tmds_pll_cntl &= 0xfff00000;
796 tmds_pll_cntl |= tmp;
797 }
798 } else
799 tmds_pll_cntl = tmp;
800
801 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
802 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
803
804 if (rdev->family == CHIP_R200 ||
805 rdev->family == CHIP_R100 ||
806 ASIC_IS_R300(rdev))
807 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
808 else /* RV chips got this bit reversed */
809 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
810
811 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
812 (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
813 RADEON_FP_CRTC_DONT_SHADOW_HEND));
814
815 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
816
1b4d7d75
AD		 817 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
818 RADEON_FP_DFP_SYNC_SEL |
819 RADEON_FP_CRT_SYNC_SEL |
820 RADEON_FP_CRTC_LOCK_8DOT |
821 RADEON_FP_USE_SHADOW_EN |
822 RADEON_FP_CRTC_USE_SHADOW_VEND |
823 RADEON_FP_CRT_SYNC_ALT);
824
771fe6b9
JG		 825 if (1) /* FIXME rgbBits == 8 */
826 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
827 else
828 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
829
830 if (radeon_crtc->crtc_id == 0) {
831 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
832 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
c93bb85b 833 if (radeon_encoder->rmx_type != RMX_OFF)
771fe6b9
JG		 834 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
835 else
836 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
837 } else
1b4d7d75 838 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
771fe6b9
JG		 839 } else {
840 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
841 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
842 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
843 } else
844 fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
845 }
846
847 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
848 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
849 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
850
851 if (rdev->is_atom_bios)
852 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
853 else
854 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
855}
856
857static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
858 .dpms = radeon_legacy_tmds_int_dpms,
80297e87 859 .mode_fixup = radeon_legacy_mode_fixup,
771fe6b9
JG		 860 .prepare = radeon_legacy_tmds_int_prepare,
861 .mode_set = radeon_legacy_tmds_int_mode_set,
862 .commit = radeon_legacy_tmds_int_commit,
4ce001ab 863 .disable = radeon_legacy_encoder_disable,
771fe6b9
JG		 864};
865
866
867static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
868 .destroy = radeon_enc_destroy,
869};
870
771fe6b9
JG		 871static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
872{
873 struct drm_device *dev = encoder->dev;
874 struct radeon_device *rdev = dev->dev_private;
875 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
d9fdaafb 876 DRM_DEBUG_KMS("\n");
771fe6b9
JG		 877
878 switch (mode) {
879 case DRM_MODE_DPMS_ON:
880 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
881 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
882 break;
883 case DRM_MODE_DPMS_STANDBY:
884 case DRM_MODE_DPMS_SUSPEND:
885 case DRM_MODE_DPMS_OFF:
886 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
887 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
888 break;
889 }
890
891 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
892
893 if (rdev->is_atom_bios)
894 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
895 else
896 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
c913e23a 897
771fe6b9
JG		 898}
899
900static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
901{
902 struct radeon_device *rdev = encoder->dev->dev_private;
903
904 if (rdev->is_atom_bios)
905 radeon_atom_output_lock(encoder, true);
906 else
907 radeon_combios_output_lock(encoder, true);
908 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
909}
910
911static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
912{
913 struct radeon_device *rdev = encoder->dev->dev_private;
914 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
915
916 if (rdev->is_atom_bios)
917 radeon_atom_output_lock(encoder, false);
918 else
919 radeon_combios_output_lock(encoder, false);
920}
921
922static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
923 struct drm_display_mode *mode,
924 struct drm_display_mode *adjusted_mode)
925{
926 struct drm_device *dev = encoder->dev;
927 struct radeon_device *rdev = dev->dev_private;
928 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
929 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
930 uint32_t fp2_gen_cntl;
931
d9fdaafb 932 DRM_DEBUG_KMS("\n");
771fe6b9 933
771fe6b9
JG		 934 if (rdev->is_atom_bios) {
935 radeon_encoder->pixel_clock = adjusted_mode->clock;
99999aaa 936 atombios_dvo_setup(encoder, ATOM_ENABLE);
771fe6b9
JG		 937 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
938 } else {
939 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
940
941 if (1) /* FIXME rgbBits == 8 */
942 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
943 else
944 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
945
946 fp2_gen_cntl &= ~(RADEON_FP2_ON |
947 RADEON_FP2_DVO_EN |
948 RADEON_FP2_DVO_RATE_SEL_SDR);
949
950 /* XXX: these are oem specific */
951 if (ASIC_IS_R300(rdev)) {
952 if ((dev->pdev->device == 0x4850) &&
953 (dev->pdev->subsystem_vendor == 0x1028) &&
954 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
955 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
956 else
957 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
958
959 /*if (mode->clock > 165000)
960 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
961 }
fcec570b
AD		 962 if (!radeon_combios_external_tmds_setup(encoder))
963 radeon_external_tmds_setup(encoder);
771fe6b9
JG		 964 }
965
966 if (radeon_crtc->crtc_id == 0) {
967 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
968 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
c93bb85b 969 if (radeon_encoder->rmx_type != RMX_OFF)
771fe6b9
JG		 970 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
971 else
972 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
973 } else
974 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
975 } else {
976 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
977 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
978 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
979 } else
980 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
981 }
982
983 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
984
985 if (rdev->is_atom_bios)
986 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
987 else
988 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
989}
990
fcec570b
AD		 991static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
992{
993 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
08291847 994 /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
fcec570b
AD		 995 kfree(radeon_encoder->enc_priv);
996 drm_encoder_cleanup(encoder);
997 kfree(radeon_encoder);
998}
999
771fe6b9
JG		 1000static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
1001 .dpms = radeon_legacy_tmds_ext_dpms,
80297e87 1002 .mode_fixup = radeon_legacy_mode_fixup,
771fe6b9
JG		 1003 .prepare = radeon_legacy_tmds_ext_prepare,
1004 .mode_set = radeon_legacy_tmds_ext_mode_set,
1005 .commit = radeon_legacy_tmds_ext_commit,
4ce001ab 1006 .disable = radeon_legacy_encoder_disable,
771fe6b9
JG		 1007};
1008
1009
1010static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
fcec570b 1011 .destroy = radeon_ext_tmds_enc_destroy,
771fe6b9
JG		 1012};
1013
771fe6b9
JG		 1014static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1015{
1016 struct drm_device *dev = encoder->dev;
1017 struct radeon_device *rdev = dev->dev_private;
4ce001ab 1018 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
771fe6b9 1019 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
4ce001ab
DA		 1020 uint32_t tv_master_cntl = 0;
1021 bool is_tv;
d9fdaafb 1022 DRM_DEBUG_KMS("\n");
771fe6b9 1023
4ce001ab
DA		 1024 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1025
771fe6b9
JG		 1026 if (rdev->family == CHIP_R200)
1027 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1028 else {
4ce001ab
DA		 1029 if (is_tv)
1030 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1031 else
1032 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
771fe6b9
JG		 1033 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1034 }
1035
1036 switch (mode) {
1037 case DRM_MODE_DPMS_ON:
1038 if (rdev->family == CHIP_R200) {
1039 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1040 } else {
4ce001ab
DA		 1041 if (is_tv)
1042 tv_master_cntl |= RADEON_TV_ON;
1043 else
1044 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1045
771fe6b9 1046 if (rdev->family == CHIP_R420 ||
4ce001ab
DA		 1047 rdev->family == CHIP_R423 ||
1048 rdev->family == CHIP_RV410)
771fe6b9 1049 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
4ce001ab
DA		 1050 R420_TV_DAC_GDACPD |
1051 R420_TV_DAC_BDACPD |
1052 RADEON_TV_DAC_BGSLEEP);
771fe6b9
JG		 1053 else
1054 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
4ce001ab
DA		 1055 RADEON_TV_DAC_GDACPD |
1056 RADEON_TV_DAC_BDACPD |
1057 RADEON_TV_DAC_BGSLEEP);
771fe6b9
JG		 1058 }
1059 break;
1060 case DRM_MODE_DPMS_STANDBY:
1061 case DRM_MODE_DPMS_SUSPEND:
1062 case DRM_MODE_DPMS_OFF:
1063 if (rdev->family == CHIP_R200)
1064 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1065 else {
4ce001ab
DA		 1066 if (is_tv)
1067 tv_master_cntl &= ~RADEON_TV_ON;
1068 else
1069 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1070
771fe6b9 1071 if (rdev->family == CHIP_R420 ||
77416187
AD		 1072 rdev->family == CHIP_R423 ||
1073 rdev->family == CHIP_RV410)
771fe6b9
JG		 1074 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1075 R420_TV_DAC_GDACPD |
1076 R420_TV_DAC_BDACPD |
1077 RADEON_TV_DAC_BGSLEEP);
1078 else
1079 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1080 RADEON_TV_DAC_GDACPD |
1081 RADEON_TV_DAC_BDACPD |
1082 RADEON_TV_DAC_BGSLEEP);
1083 }
1084 break;
1085 }
1086
1087 if (rdev->family == CHIP_R200) {
1088 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1089 } else {
4ce001ab
DA		 1090 if (is_tv)
1091 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1092 else
1093 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
771fe6b9
JG		 1094 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1095 }
1096
1097 if (rdev->is_atom_bios)
1098 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1099 else
1100 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
c913e23a 1101
771fe6b9
JG		 1102}
1103
1104static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1105{
1106 struct radeon_device *rdev = encoder->dev->dev_private;
1107
1108 if (rdev->is_atom_bios)
1109 radeon_atom_output_lock(encoder, true);
1110 else
1111 radeon_combios_output_lock(encoder, true);
1112 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1113}
1114
1115static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1116{
1117 struct radeon_device *rdev = encoder->dev->dev_private;
1118
1119 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1120
1121 if (rdev->is_atom_bios)
1122 radeon_atom_output_lock(encoder, true);
1123 else
1124 radeon_combios_output_lock(encoder, true);
1125}
1126
1127static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1128 struct drm_display_mode *mode,
1129 struct drm_display_mode *adjusted_mode)
1130{
1131 struct drm_device *dev = encoder->dev;
1132 struct radeon_device *rdev = dev->dev_private;
1133 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1134 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1135 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
771fe6b9 1136 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
4ce001ab
DA		 1137 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1138 bool is_tv = false;
771fe6b9 1139
d9fdaafb 1140 DRM_DEBUG_KMS("\n");
771fe6b9 1141
4ce001ab
DA		 1142 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1143
771fe6b9
JG		 1144 if (rdev->family != CHIP_R200) {
1145 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1146 if (rdev->family == CHIP_R420 ||
77416187
AD		 1147 rdev->family == CHIP_R423 ||
1148 rdev->family == CHIP_RV410) {
771fe6b9 1149 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
77416187
AD		 1150 RADEON_TV_DAC_BGADJ_MASK |
1151 R420_TV_DAC_DACADJ_MASK |
1152 R420_TV_DAC_RDACPD |
1153 R420_TV_DAC_GDACPD |
1154 R420_TV_DAC_BDACPD |
1155 R420_TV_DAC_TVENABLE);
771fe6b9
JG		 1156 } else {
1157 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
77416187
AD		 1158 RADEON_TV_DAC_BGADJ_MASK |
1159 RADEON_TV_DAC_DACADJ_MASK |
1160 RADEON_TV_DAC_RDACPD |
1161 RADEON_TV_DAC_GDACPD |
1162 RADEON_TV_DAC_BDACPD);
771fe6b9
JG		 1163 }
1164
77416187
AD		 1165 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1166
1167 if (is_tv) {
1168 if (tv_dac->tv_std == TV_STD_NTSC ||
1169 tv_dac->tv_std == TV_STD_NTSC_J ||
1170 tv_dac->tv_std == TV_STD_PAL_M ||
1171 tv_dac->tv_std == TV_STD_PAL_60)
1172 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1173 else
1174 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1175
1176 if (tv_dac->tv_std == TV_STD_NTSC ||
1177 tv_dac->tv_std == TV_STD_NTSC_J)
1178 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1179 else
1180 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
771fe6b9 1181 } else
77416187
AD		 1182 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1183 tv_dac->ps2_tvdac_adj);
771fe6b9
JG		 1184
1185 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1186 }
1187
1188 if (ASIC_IS_R300(rdev)) {
1189 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1190 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1ab064de 1191 } else if (rdev->family != CHIP_R200)
771fe6b9 1192 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1ab064de 1193 else if (rdev->family == CHIP_R200)
4ce001ab 1194 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
771fe6b9 1195
1ab064de
DA		 1196 if (rdev->family >= CHIP_R200)
1197 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1198
4ce001ab
DA		 1199 if (is_tv) {
1200 uint32_t dac_cntl;
1201
1202 dac_cntl = RREG32(RADEON_DAC_CNTL);
1203 dac_cntl &= ~RADEON_DAC_TVO_EN;
1204 WREG32(RADEON_DAC_CNTL, dac_cntl);
1205
1206 if (ASIC_IS_R300(rdev))
1207 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1208
1209 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1210 if (radeon_crtc->crtc_id == 0) {
1211 if (ASIC_IS_R300(rdev)) {
1212 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1213 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1214 RADEON_DISP_TV_SOURCE_CRTC);
1215 }
1216 if (rdev->family >= CHIP_R200) {
1217 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1218 } else {
1219 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1220 }
1221 } else {
1222 if (ASIC_IS_R300(rdev)) {
1223 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1224 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1225 }
1226 if (rdev->family >= CHIP_R200) {
1227 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1228 } else {
1229 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1230 }
1231 }
1232 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
771fe6b9 1233 } else {
771fe6b9 1234
4ce001ab
DA		 1235 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1236
1237 if (radeon_crtc->crtc_id == 0) {
1238 if (ASIC_IS_R300(rdev)) {
1239 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1240 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1241 } else if (rdev->family == CHIP_R200) {
1242 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1243 RADEON_FP2_DVO_RATE_SEL_SDR);
1244 } else
1245 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1246 } else {
1247 if (ASIC_IS_R300(rdev)) {
1248 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1249 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1250 } else if (rdev->family == CHIP_R200) {
1251 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1252 RADEON_FP2_DVO_RATE_SEL_SDR);
1253 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1254 } else
1255 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1256 }
1257 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1258 }
771fe6b9
JG		 1259
1260 if (ASIC_IS_R300(rdev)) {
1261 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
4ce001ab 1262 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1ab064de
DA		 1263 } else if (rdev->family != CHIP_R200)
1264 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1265 else if (rdev->family == CHIP_R200)
1266 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
4ce001ab
DA		 1267
1268 if (rdev->family >= CHIP_R200)
1269 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
4ce001ab
DA		 1270
1271 if (is_tv)
1272 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1273
771fe6b9
JG		 1274 if (rdev->is_atom_bios)
1275 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1276 else
1277 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1278
1279}
1280
4ce001ab
DA		 1281static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1282 struct drm_connector *connector)
1283{
1284 struct drm_device *dev = encoder->dev;
1285 struct radeon_device *rdev = dev->dev_private;
1286 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1287 uint32_t disp_output_cntl, gpiopad_a, tmp;
1288 bool found = false;
1289
1290 /* save regs needed */
1291 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1292 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1293 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1294 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1295 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1296 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1297
1298 WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1299
1300 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1301
1302 WREG32(RADEON_CRTC2_GEN_CNTL,
1303 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1304
1305 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1306 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1307 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1308
1309 WREG32(RADEON_DAC_EXT_CNTL,
1310 RADEON_DAC2_FORCE_BLANK_OFF_EN |
1311 RADEON_DAC2_FORCE_DATA_EN |
1312 RADEON_DAC_FORCE_DATA_SEL_RGB |
1313 (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1314
1315 WREG32(RADEON_TV_DAC_CNTL,
1316 RADEON_TV_DAC_STD_NTSC |
1317 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1318 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1319
1320 RREG32(RADEON_TV_DAC_CNTL);
1321 mdelay(4);
1322
1323 WREG32(RADEON_TV_DAC_CNTL,
1324 RADEON_TV_DAC_NBLANK |
1325 RADEON_TV_DAC_NHOLD |
1326 RADEON_TV_MONITOR_DETECT_EN |
1327 RADEON_TV_DAC_STD_NTSC |
1328 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1329 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1330
1331 RREG32(RADEON_TV_DAC_CNTL);
1332 mdelay(6);
1333
1334 tmp = RREG32(RADEON_TV_DAC_CNTL);
1335 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1336 found = true;
d9fdaafb 1337 DRM_DEBUG_KMS("S-video TV connection detected\n");
4ce001ab
DA		 1338 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1339 found = true;
d9fdaafb 1340 DRM_DEBUG_KMS("Composite TV connection detected\n");
4ce001ab
DA		 1341 }
1342
1343 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1344 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1345 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1346 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1347 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1348 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1349 return found;
1350}
1351
1352static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1353 struct drm_connector *connector)
1354{
1355 struct drm_device *dev = encoder->dev;
1356 struct radeon_device *rdev = dev->dev_private;
1357 uint32_t tv_dac_cntl, dac_cntl2;
1358 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1359 bool found = false;
1360
1361 if (ASIC_IS_R300(rdev))
1362 return r300_legacy_tv_detect(encoder, connector);
1363
1364 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1365 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1366 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1367 config_cntl = RREG32(RADEON_CONFIG_CNTL);
1368 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1369
1370 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1371 WREG32(RADEON_DAC_CNTL2, tmp);
1372
1373 tmp = tv_master_cntl | RADEON_TV_ON;
1374 tmp &= ~(RADEON_TV_ASYNC_RST |
1375 RADEON_RESTART_PHASE_FIX |
1376 RADEON_CRT_FIFO_CE_EN |
1377 RADEON_TV_FIFO_CE_EN |
1378 RADEON_RE_SYNC_NOW_SEL_MASK);
1379 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1380 WREG32(RADEON_TV_MASTER_CNTL, tmp);
1381
1382 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1383 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1384 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1385
1386 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1387 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1388 else
1389 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1390 WREG32(RADEON_TV_DAC_CNTL, tmp);
1391
1392 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1393 RADEON_RED_MX_FORCE_DAC_DATA |
1394 RADEON_GRN_MX_FORCE_DAC_DATA |
1395 RADEON_BLU_MX_FORCE_DAC_DATA |
1396 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1397 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1398
1399 mdelay(3);
1400 tmp = RREG32(RADEON_TV_DAC_CNTL);
1401 if (tmp & RADEON_TV_DAC_GDACDET) {
1402 found = true;
d9fdaafb 1403 DRM_DEBUG_KMS("S-video TV connection detected\n");
4ce001ab
DA		 1404 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1405 found = true;
d9fdaafb 1406 DRM_DEBUG_KMS("Composite TV connection detected\n");
4ce001ab
DA		 1407 }
1408
1409 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1410 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1411 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1412 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1413 return found;
1414}
1415
771fe6b9
JG		 1416static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1417 struct drm_connector *connector)
1418{
1419 struct drm_device *dev = encoder->dev;
1420 struct radeon_device *rdev = dev->dev_private;
1421 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1422 uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1423 enum drm_connector_status found = connector_status_disconnected;
4ce001ab
DA		 1424 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1425 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
771fe6b9 1426 bool color = true;
b62e948f
DA		 1427 struct drm_crtc *crtc;
1428
1429 /* find out if crtc2 is in use or if this encoder is using it */
1430 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1431 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1432 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1433 if (encoder->crtc != crtc) {
1434 return connector_status_disconnected;
1435 }
1436 }
1437 }
771fe6b9 1438
4ce001ab
DA		 1439 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1440 connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1441 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1442 bool tv_detect;
1443
1444 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1445 return connector_status_disconnected;
1446
1447 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1448 if (tv_detect && tv_dac)
1449 found = connector_status_connected;
1450 return found;
1451 }
1452
1453 /* don't probe if the encoder is being used for something else not CRT related */
1454 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1455 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1456 return connector_status_disconnected;
1457 }
771fe6b9
JG		 1458
1459 /* save the regs we need */
1460 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1461 gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1462 disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1463 disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1464 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1465 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1466 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1467 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1468
1469 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1470 | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1471 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1472
1473 if (ASIC_IS_R300(rdev))
1474 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1475
1476 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1477 tmp |= RADEON_CRTC2_CRT2_ON |
1478 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1479
1480 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1481
1482 if (ASIC_IS_R300(rdev)) {
1483 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1484 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1485 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1486 } else {
1487 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1488 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1489 }
1490
1491 tmp = RADEON_TV_DAC_NBLANK |
1492 RADEON_TV_DAC_NHOLD |
1493 RADEON_TV_MONITOR_DETECT_EN |
1494 RADEON_TV_DAC_STD_PS2;
1495
1496 WREG32(RADEON_TV_DAC_CNTL, tmp);
1497
1498 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1499 RADEON_DAC2_FORCE_DATA_EN;
1500
1501 if (color)
1502 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1503 else
1504 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1505
1506 if (ASIC_IS_R300(rdev))
1507 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1508 else
1509 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1510
1511 WREG32(RADEON_DAC_EXT_CNTL, tmp);
1512
1513 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1514 WREG32(RADEON_DAC_CNTL2, tmp);
1515
4de833c3 1516 mdelay(10);
771fe6b9
JG		 1517
1518 if (ASIC_IS_R300(rdev)) {
1519 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1520 found = connector_status_connected;
1521 } else {
1522 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1523 found = connector_status_connected;
1524 }
1525
1526 /* restore regs we used */
1527 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1528 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1529 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1530 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1531
1532 if (ASIC_IS_R300(rdev)) {
1533 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1534 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1535 } else {
1536 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1537 }
1538 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1539
4ce001ab 1540 return found;
771fe6b9
JG		 1541
1542}
1543
1544static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1545 .dpms = radeon_legacy_tv_dac_dpms,
80297e87 1546 .mode_fixup = radeon_legacy_mode_fixup,
771fe6b9
JG		 1547 .prepare = radeon_legacy_tv_dac_prepare,
1548 .mode_set = radeon_legacy_tv_dac_mode_set,
1549 .commit = radeon_legacy_tv_dac_commit,
1550 .detect = radeon_legacy_tv_dac_detect,
4ce001ab 1551 .disable = radeon_legacy_encoder_disable,
771fe6b9
JG		 1552};
1553
1554
1555static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1556 .destroy = radeon_enc_destroy,
1557};
1558
445282db
DA		 1559
1560static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1561{
1562 struct drm_device *dev = encoder->base.dev;
1563 struct radeon_device *rdev = dev->dev_private;
1564 struct radeon_encoder_int_tmds *tmds = NULL;
1565 bool ret;
1566
1567 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1568
1569 if (!tmds)
1570 return NULL;
1571
1572 if (rdev->is_atom_bios)
1573 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1574 else
1575 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1576
1577 if (ret == false)
1578 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1579
1580 return tmds;
1581}
1582
fcec570b
AD		 1583static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1584{
1585 struct drm_device *dev = encoder->base.dev;
1586 struct radeon_device *rdev = dev->dev_private;
1587 struct radeon_encoder_ext_tmds *tmds = NULL;
1588 bool ret;
1589
1590 if (rdev->is_atom_bios)
1591 return NULL;
1592
1593 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1594
1595 if (!tmds)
1596 return NULL;
1597
1598 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1599
1600 if (ret == false)
1601 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1602
1603 return tmds;
1604}
1605
771fe6b9 1606void
5137ee94 1607radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
771fe6b9
JG		 1608{
1609 struct radeon_device *rdev = dev->dev_private;
1610 struct drm_encoder *encoder;
1611 struct radeon_encoder *radeon_encoder;
1612
1613 /* see if we already added it */
1614 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1615 radeon_encoder = to_radeon_encoder(encoder);
5137ee94 1616 if (radeon_encoder->encoder_enum == encoder_enum) {
771fe6b9
JG		 1617 radeon_encoder->devices |= supported_device;
1618 return;
1619 }
1620
1621 }
1622
1623 /* add a new one */
1624 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1625 if (!radeon_encoder)
1626 return;
1627
1628 encoder = &radeon_encoder->base;
dfee5614
DA		 1629 if (rdev->flags & RADEON_SINGLE_CRTC)
1630 encoder->possible_crtcs = 0x1;
1631 else
1632 encoder->possible_crtcs = 0x3;
771fe6b9
JG		 1633
1634 radeon_encoder->enc_priv = NULL;
1635
5137ee94
AD		 1636 radeon_encoder->encoder_enum = encoder_enum;
1637 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
771fe6b9 1638 radeon_encoder->devices = supported_device;
c93bb85b 1639 radeon_encoder->rmx_type = RMX_OFF;
771fe6b9
JG		 1640
1641 switch (radeon_encoder->encoder_id) {
1642 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
80e6914d 1643 encoder->possible_crtcs = 0x1;
771fe6b9
JG		 1644 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1645 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1646 if (rdev->is_atom_bios)
1647 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1648 else
1649 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1650 radeon_encoder->rmx_type = RMX_FULL;
1651 break;
1652 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1653 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1654 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
445282db 1655 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
771fe6b9
JG		 1656 break;
1657 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1658 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1659 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
6fe7ac3f
AD		 1660 if (rdev->is_atom_bios)
1661 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1662 else
771fe6b9
JG		 1663 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1664 break;
1665 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1666 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1667 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
6fe7ac3f
AD		 1668 if (rdev->is_atom_bios)
1669 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1670 else
771fe6b9
JG		 1671 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1672 break;
1673 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1674 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1675 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1676 if (!rdev->is_atom_bios)
fcec570b 1677 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
771fe6b9
JG		 1678 break;
1679 }
1680}
Linux 6.x block layer and io_uring tree(s)