[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_kms.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include "drmP.h"
#include "drm_sarea.h"
#include "radeon.h"
#include "radeon_drm.h"

#include <linux/vga_switcheroo.h>
#include <linux/slab.h>

int radeon_driver_unload_kms(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;

	if (rdev == NULL)
		return 0;
	radeon_modeset_fini(rdev);
	radeon_device_fini(rdev);
	kfree(rdev);
	dev->dev_private = NULL;
	return 0;
}

int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
{
	struct radeon_device *rdev;
	int r, acpi_status;

	rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
	if (rdev == NULL) {
		return -ENOMEM;
	}
	dev->dev_private = (void *)rdev;

	/* update BUS flag */
	if (drm_pci_device_is_agp(dev)) {
		flags |= RADEON_IS_AGP;
	} else if (pci_is_pcie(dev->pdev)) {
		flags |= RADEON_IS_PCIE;
	} else {
		flags |= RADEON_IS_PCI;
	}

	/* radeon_device_init should report only fatal error
	 * like memory allocation failure or iomapping failure,
	 * or memory manager initialization failure, it must
	 * properly initialize the GPU MC controller and permit
	 * VRAM allocation
	 */
	r = radeon_device_init(rdev, dev, dev->pdev, flags);
	if (r) {
		dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
		goto out;
	}

	/* Call ACPI methods */
	acpi_status = radeon_acpi_init(rdev);
	if (acpi_status)
		dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");

	/* Again modeset_init should fail only on fatal error
	 * otherwise it should provide enough functionalities
	 * for shadowfb to run
	 */
	r = radeon_modeset_init(rdev);
	if (r)
		dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
out:
	if (r)
		radeon_driver_unload_kms(dev);
	return r;
}

static void radeon_set_filp_rights(struct drm_device *dev,
				   struct drm_file **owner,
				   struct drm_file *applier,
				   uint32_t *value)
{
	mutex_lock(&dev->struct_mutex);
	if (*value == 1) {
		/* wants rights */
		if (!*owner)
			*owner = applier;
	} else if (*value == 0) {
		/* revokes rights */
		if (*owner == applier)
			*owner = NULL;
	}
	*value = *owner == applier ? 1 : 0;
	mutex_unlock(&dev->struct_mutex);
}

/*
 * Userspace get information ioctl
 */
int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	struct radeon_device *rdev = dev->dev_private;
	struct drm_radeon_info *info;
	struct radeon_mode_info *minfo = &rdev->mode_info;
	uint32_t *value_ptr;
	uint32_t value;
	struct drm_crtc *crtc;
	int i, found;

	info = data;
	value_ptr = (uint32_t *)((unsigned long)info->value);
	if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
		return -EFAULT;

	switch (info->request) {
	case RADEON_INFO_DEVICE_ID:
		value = dev->pci_device;
		break;
	case RADEON_INFO_NUM_GB_PIPES:
		value = rdev->num_gb_pipes;
		break;
	case RADEON_INFO_NUM_Z_PIPES:
		value = rdev->num_z_pipes;
		break;
	case RADEON_INFO_ACCEL_WORKING:
		/* xf86-video-ati 6.13.0 relies on this being false for evergreen */
		if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
			value = false;
		else
			value = rdev->accel_working;
		break;
	case RADEON_INFO_CRTC_FROM_ID:
		for (i = 0, found = 0; i < rdev->num_crtc; i++) {
			crtc = (struct drm_crtc *)minfo->crtcs[i];
			if (crtc && crtc->base.id == value) {
				struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
				value = radeon_crtc->crtc_id;
				found = 1;
				break;
			}
		}
		if (!found) {
			DRM_DEBUG_KMS("unknown crtc id %d\n", value);
			return -EINVAL;
		}
		break;
	case RADEON_INFO_ACCEL_WORKING2:
		value = rdev->accel_working;
		break;
	case RADEON_INFO_TILING_CONFIG:
		if (rdev->family >= CHIP_TAHITI)
			value = rdev->config.si.tile_config;
		else if (rdev->family >= CHIP_CAYMAN)
			value = rdev->config.cayman.tile_config;
		else if (rdev->family >= CHIP_CEDAR)
			value = rdev->config.evergreen.tile_config;
		else if (rdev->family >= CHIP_RV770)
			value = rdev->config.rv770.tile_config;
		else if (rdev->family >= CHIP_R600)
			value = rdev->config.r600.tile_config;
		else {
			DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
			return -EINVAL;
		}
		break;
	case RADEON_INFO_WANT_HYPERZ:
		/* The "value" here is both an input and output parameter.
		 * If the input value is 1, filp requests hyper-z access.
		 * If the input value is 0, filp revokes its hyper-z access.
		 *
		 * When returning, the value is 1 if filp owns hyper-z access,
		 * 0 otherwise. */
		if (value >= 2) {
			DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
			return -EINVAL;
		}
		radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
		break;
	case RADEON_INFO_WANT_CMASK:
		/* The same logic as Hyper-Z. */
		if (value >= 2) {
			DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
			return -EINVAL;
		}
		radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
		break;
	case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
		/* return clock value in KHz */
		value = rdev->clock.spll.reference_freq * 10;
		break;
	case RADEON_INFO_NUM_BACKENDS:
		if (rdev->family >= CHIP_TAHITI)
			value = rdev->config.si.max_backends_per_se *
				rdev->config.si.max_shader_engines;
		else if (rdev->family >= CHIP_CAYMAN)
			value = rdev->config.cayman.max_backends_per_se *
				rdev->config.cayman.max_shader_engines;
		else if (rdev->family >= CHIP_CEDAR)
			value = rdev->config.evergreen.max_backends;
		else if (rdev->family >= CHIP_RV770)
			value = rdev->config.rv770.max_backends;
		else if (rdev->family >= CHIP_R600)
			value = rdev->config.r600.max_backends;
		else {
			return -EINVAL;
		}
		break;
	case RADEON_INFO_NUM_TILE_PIPES:
		if (rdev->family >= CHIP_TAHITI)
			value = rdev->config.si.max_tile_pipes;
		else if (rdev->family >= CHIP_CAYMAN)
			value = rdev->config.cayman.max_tile_pipes;
		else if (rdev->family >= CHIP_CEDAR)
			value = rdev->config.evergreen.max_tile_pipes;
		else if (rdev->family >= CHIP_RV770)
			value = rdev->config.rv770.max_tile_pipes;
		else if (rdev->family >= CHIP_R600)
			value = rdev->config.r600.max_tile_pipes;
		else {
			return -EINVAL;
		}
		break;
	case RADEON_INFO_FUSION_GART_WORKING:
		value = 1;
		break;
	case RADEON_INFO_BACKEND_MAP:
		if (rdev->family >= CHIP_TAHITI)
			value = rdev->config.si.backend_map;
		else if (rdev->family >= CHIP_CAYMAN)
			value = rdev->config.cayman.backend_map;
		else if (rdev->family >= CHIP_CEDAR)
			value = rdev->config.evergreen.backend_map;
		else if (rdev->family >= CHIP_RV770)
			value = rdev->config.rv770.backend_map;
		else if (rdev->family >= CHIP_R600)
			value = rdev->config.r600.backend_map;
		else {
			return -EINVAL;
		}
		break;
	case RADEON_INFO_VA_START:
		/* this is where we report if vm is supported or not */
		if (rdev->family < CHIP_CAYMAN)
			return -EINVAL;
		value = RADEON_VA_RESERVED_SIZE;
		break;
	case RADEON_INFO_IB_VM_MAX_SIZE:
		/* this is where we report if vm is supported or not */
		if (rdev->family < CHIP_CAYMAN)
			return -EINVAL;
		value = RADEON_IB_VM_MAX_SIZE;
		break;
	case RADEON_INFO_MAX_PIPES:
		if (rdev->family >= CHIP_TAHITI)
			value = rdev->config.si.max_pipes_per_simd;
		else if (rdev->family >= CHIP_CAYMAN)
			value = rdev->config.cayman.max_pipes_per_simd;
		else if (rdev->family >= CHIP_CEDAR)
			value = rdev->config.evergreen.max_pipes;
		else if (rdev->family >= CHIP_RV770)
			value = rdev->config.rv770.max_pipes;
		else if (rdev->family >= CHIP_R600)
			value = rdev->config.r600.max_pipes;
		else {
			return -EINVAL;
		}
		break;
	default:
		DRM_DEBUG_KMS("Invalid request %d\n", info->request);
		return -EINVAL;
	}
	if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
		DRM_ERROR("copy_to_user\n");
		return -EFAULT;
	}
	return 0;
}


/*
 * Outdated mess for old drm with Xorg being in charge (void function now).
 */
int radeon_driver_firstopen_kms(struct drm_device *dev)
{
	return 0;
}

void radeon_driver_lastclose_kms(struct drm_device *dev)
{
	vga_switcheroo_process_delayed_switch();
}

int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
{
	struct radeon_device *rdev = dev->dev_private;

	file_priv->driver_priv = NULL;

	/* new gpu have virtual address space support */
	if (rdev->family >= CHIP_CAYMAN) {
		struct radeon_fpriv *fpriv;
		int r;

		fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
		if (unlikely(!fpriv)) {
			return -ENOMEM;
		}

		r = radeon_vm_init(rdev, &fpriv->vm);
		if (r) {
			radeon_vm_fini(rdev, &fpriv->vm);
			kfree(fpriv);
			return r;
		}

		file_priv->driver_priv = fpriv;
	}
	return 0;
}

void radeon_driver_postclose_kms(struct drm_device *dev,
				 struct drm_file *file_priv)
{
	struct radeon_device *rdev = dev->dev_private;

	/* new gpu have virtual address space support */
	if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
		struct radeon_fpriv *fpriv = file_priv->driver_priv;

		radeon_vm_fini(rdev, &fpriv->vm);
		kfree(fpriv);
		file_priv->driver_priv = NULL;
	}
}

void radeon_driver_preclose_kms(struct drm_device *dev,
				struct drm_file *file_priv)
{
	struct radeon_device *rdev = dev->dev_private;
	if (rdev->hyperz_filp == file_priv)
		rdev->hyperz_filp = NULL;
	if (rdev->cmask_filp == file_priv)
		rdev->cmask_filp = NULL;
}

/*
 * VBlank related functions.
 */
u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
{
	struct radeon_device *rdev = dev->dev_private;

	if (crtc < 0 || crtc >= rdev->num_crtc) {
		DRM_ERROR("Invalid crtc %d\n", crtc);
		return -EINVAL;
	}

	return radeon_get_vblank_counter(rdev, crtc);
}

int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
{
	struct radeon_device *rdev = dev->dev_private;

	if (crtc < 0 || crtc >= rdev->num_crtc) {
		DRM_ERROR("Invalid crtc %d\n", crtc);
		return -EINVAL;
	}

	rdev->irq.crtc_vblank_int[crtc] = true;

	return radeon_irq_set(rdev);
}

void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
{
	struct radeon_device *rdev = dev->dev_private;

	if (crtc < 0 || crtc >= rdev->num_crtc) {
		DRM_ERROR("Invalid crtc %d\n", crtc);
		return;
	}

	rdev->irq.crtc_vblank_int[crtc] = false;

	radeon_irq_set(rdev);
}

int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
				    int *max_error,
				    struct timeval *vblank_time,
				    unsigned flags)
{
	struct drm_crtc *drmcrtc;
	struct radeon_device *rdev = dev->dev_private;

	if (crtc < 0 || crtc >= dev->num_crtcs) {
		DRM_ERROR("Invalid crtc %d\n", crtc);
		return -EINVAL;
	}

	/* Get associated drm_crtc: */
	drmcrtc = &rdev->mode_info.crtcs[crtc]->base;

	/* Helper routine in DRM core does all the work: */
	return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
						     vblank_time, flags,
						     drmcrtc);
}

/*
 * IOCTL.
 */
int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	/* Not valid in KMS. */
	return -EINVAL;
}

#define KMS_INVALID_IOCTL(name)						\
int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
{									\
	DRM_ERROR("invalid ioctl with kms %s\n", __func__);		\
	return -EINVAL;							\
}

/*
 * All these ioctls are invalid in kms world.
 */
KMS_INVALID_IOCTL(radeon_cp_init_kms)
KMS_INVALID_IOCTL(radeon_cp_start_kms)
KMS_INVALID_IOCTL(radeon_cp_stop_kms)
KMS_INVALID_IOCTL(radeon_cp_reset_kms)
KMS_INVALID_IOCTL(radeon_cp_idle_kms)
KMS_INVALID_IOCTL(radeon_cp_resume_kms)
KMS_INVALID_IOCTL(radeon_engine_reset_kms)
KMS_INVALID_IOCTL(radeon_fullscreen_kms)
KMS_INVALID_IOCTL(radeon_cp_swap_kms)
KMS_INVALID_IOCTL(radeon_cp_clear_kms)
KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
KMS_INVALID_IOCTL(radeon_cp_indices_kms)
KMS_INVALID_IOCTL(radeon_cp_texture_kms)
KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
KMS_INVALID_IOCTL(radeon_cp_flip_kms)
KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
KMS_INVALID_IOCTL(radeon_mem_free_kms)
KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
KMS_INVALID_IOCTL(radeon_irq_emit_kms)
KMS_INVALID_IOCTL(radeon_irq_wait_kms)
KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
KMS_INVALID_IOCTL(radeon_surface_free_kms)


struct drm_ioctl_desc radeon_ioctls_kms[] = {
	DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
	/* KMS */
	DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED),
};
int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include "drmP.h"
	29	#include "drm_sarea.h"
	30	#include "radeon.h"
	31	#include "radeon_drm.h"
	32
6a9ee8af	33	#include <linux/vga_switcheroo.h>
5a0e3ad6	34	#include <linux/slab.h>
6a9ee8af	35
cf0fe456 JG	36	int radeon_driver_unload_kms(struct drm_device *dev)
	37	{
	38	struct radeon_device *rdev = dev->dev_private;
	39
	40	if (rdev == NULL)
	41	return 0;
	42	radeon_modeset_fini(rdev);
	43	radeon_device_fini(rdev);
	44	kfree(rdev);
	45	dev->dev_private = NULL;
	46	return 0;
	47	}
771fe6b9	48
771fe6b9 JG	49	int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
	50	{
	51	struct radeon_device *rdev;
d7a2952f	52	int r, acpi_status;
771fe6b9 JG	53
	54	rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
	55	if (rdev == NULL) {
	56	return -ENOMEM;
	57	}
	58	dev->dev_private = (void *)rdev;
	59
	60	/* update BUS flag */
8410ea3b	61	if (drm_pci_device_is_agp(dev)) {
771fe6b9	62	flags \|= RADEON_IS_AGP;
58b6542b	63	} else if (pci_is_pcie(dev->pdev)) {
771fe6b9 JG	64	flags \|= RADEON_IS_PCIE;
	65	} else {
	66	flags \|= RADEON_IS_PCI;
	67	}
	68
6cf8a3f5 JG	69	/* radeon_device_init should report only fatal error
	70	* like memory allocation failure or iomapping failure,
	71	* or memory manager initialization failure, it must
	72	* properly initialize the GPU MC controller and permit
	73	* VRAM allocation
	74	*/
771fe6b9 JG	75	r = radeon_device_init(rdev, dev, dev->pdev, flags);
771fe6b9 JG	76	if (r) {
cf0fe456 JG	77	dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
cf0fe456 JG	78	goto out;
6cf8a3f5	79	}
d7a2952f AM	80
	81	/* Call ACPI methods */
	82	acpi_status = radeon_acpi_init(rdev);
	83	if (acpi_status)
dc77de12	84	dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
d7a2952f	85
6cf8a3f5 JG	86	/* Again modeset_init should fail only on fatal error
	87	* otherwise it should provide enough functionalities
	88	* for shadowfb to run
	89	*/
	90	r = radeon_modeset_init(rdev);
cf0fe456 JG	91	if (r)
	92	dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
	93	out:
	94	if (r)
	95	radeon_driver_unload_kms(dev);
	96	return r;
771fe6b9 JG	97	}
771fe6b9 JG	98
9eba4a93 MO	99	static void radeon_set_filp_rights(struct drm_device *dev,
	100	struct drm_file **owner,
	101	struct drm_file *applier,
	102	uint32_t *value)
	103	{
	104	mutex_lock(&dev->struct_mutex);
	105	if (*value == 1) {
	106	/* wants rights */
	107	if (!*owner)
	108	*owner = applier;
	109	} else if (*value == 0) {
	110	/* revokes rights */
	111	if (*owner == applier)
	112	*owner = NULL;
	113	}
	114	value = owner == applier ? 1 : 0;
	115	mutex_unlock(&dev->struct_mutex);
	116	}
771fe6b9 JG	117
771fe6b9 JG	118	/*
9eba4a93	119	* Userspace get information ioctl
771fe6b9 JG	120	*/
	121	int radeon_info_ioctl(struct drm_device dev, void data, struct drm_file *filp)
	122	{
	123	struct radeon_device *rdev = dev->dev_private;
	124	struct drm_radeon_info *info;
bc35afdb	125	struct radeon_mode_info *minfo = &rdev->mode_info;
771fe6b9 JG	126	uint32_t *value_ptr;
771fe6b9 JG	127	uint32_t value;
bc35afdb JG	128	struct drm_crtc *crtc;
bc35afdb JG	129	int i, found;
771fe6b9 JG	130
	131	info = data;
	132	value_ptr = (uint32_t *)((unsigned long)info->value);
d8ab3557 DDAG	133	if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
	134	return -EFAULT;
	135
771fe6b9 JG	136	switch (info->request) {
	137	case RADEON_INFO_DEVICE_ID:
	138	value = dev->pci_device;
	139	break;
	140	case RADEON_INFO_NUM_GB_PIPES:
	141	value = rdev->num_gb_pipes;
	142	break;
f779b3e5 AD	143	case RADEON_INFO_NUM_Z_PIPES:
	144	value = rdev->num_z_pipes;
	145	break;
733289c2	146	case RADEON_INFO_ACCEL_WORKING:
148a03bc AD	147	/* xf86-video-ati 6.13.0 relies on this being false for evergreen */
	148	if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
	149	value = false;
	150	else
	151	value = rdev->accel_working;
733289c2	152	break;
bc35afdb JG	153	case RADEON_INFO_CRTC_FROM_ID:
	154	for (i = 0, found = 0; i < rdev->num_crtc; i++) {
	155	crtc = (struct drm_crtc *)minfo->crtcs[i];
	156	if (crtc && crtc->base.id == value) {
0baf2d8f AD	157	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0baf2d8f AD	158	value = radeon_crtc->crtc_id;
bc35afdb JG	159	found = 1;
	160	break;
	161	}
	162	}
	163	if (!found) {
d9fdaafb	164	DRM_DEBUG_KMS("unknown crtc id %d\n", value);
bc35afdb JG	165	return -EINVAL;
	166	}
	167	break;
148a03bc AD	168	case RADEON_INFO_ACCEL_WORKING2:
	169	value = rdev->accel_working;
	170	break;
e7aeeba6	171	case RADEON_INFO_TILING_CONFIG:
c1b2f69f MD	172	if (rdev->family >= CHIP_TAHITI)
	173	value = rdev->config.si.tile_config;
	174	else if (rdev->family >= CHIP_CAYMAN)
fecf1d07 AD	175	value = rdev->config.cayman.tile_config;
fecf1d07 AD	176	else if (rdev->family >= CHIP_CEDAR)
e7aeeba6 AD	177	value = rdev->config.evergreen.tile_config;
	178	else if (rdev->family >= CHIP_RV770)
	179	value = rdev->config.rv770.tile_config;
	180	else if (rdev->family >= CHIP_R600)
	181	value = rdev->config.r600.tile_config;
	182	else {
d9fdaafb	183	DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
e7aeeba6 AD	184	return -EINVAL;
e7aeeba6 AD	185	}
b824b364	186	break;
ab9e1f59	187	case RADEON_INFO_WANT_HYPERZ:
43861f71 MO	188	/* The "value" here is both an input and output parameter.
	189	* If the input value is 1, filp requests hyper-z access.
	190	* If the input value is 0, filp revokes its hyper-z access.
	191	*
	192	* When returning, the value is 1 if filp owns hyper-z access,
	193	* 0 otherwise. */
	194	if (value >= 2) {
	195	DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
	196	return -EINVAL;
	197	}
9eba4a93 MO	198	radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
	199	break;
	200	case RADEON_INFO_WANT_CMASK:
	201	/* The same logic as Hyper-Z. */
	202	if (value >= 2) {
	203	DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
	204	return -EINVAL;
ab9e1f59	205	}
9eba4a93	206	radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
e7aeeba6	207	break;
58bbf018 AD	208	case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
	209	/* return clock value in KHz */
	210	value = rdev->clock.spll.reference_freq * 10;
	211	break;
486af189	212	case RADEON_INFO_NUM_BACKENDS:
c1b2f69f MD	213	if (rdev->family >= CHIP_TAHITI)
	214	value = rdev->config.si.max_backends_per_se *
	215	rdev->config.si.max_shader_engines;
	216	else if (rdev->family >= CHIP_CAYMAN)
fecf1d07 AD	217	value = rdev->config.cayman.max_backends_per_se *
	218	rdev->config.cayman.max_shader_engines;
	219	else if (rdev->family >= CHIP_CEDAR)
486af189 DA	220	value = rdev->config.evergreen.max_backends;
	221	else if (rdev->family >= CHIP_RV770)
	222	value = rdev->config.rv770.max_backends;
	223	else if (rdev->family >= CHIP_R600)
	224	value = rdev->config.r600.max_backends;
	225	else {
	226	return -EINVAL;
	227	}
	228	break;
6565945b	229	case RADEON_INFO_NUM_TILE_PIPES:
c1b2f69f MD	230	if (rdev->family >= CHIP_TAHITI)
	231	value = rdev->config.si.max_tile_pipes;
	232	else if (rdev->family >= CHIP_CAYMAN)
6565945b AD	233	value = rdev->config.cayman.max_tile_pipes;
	234	else if (rdev->family >= CHIP_CEDAR)
	235	value = rdev->config.evergreen.max_tile_pipes;
	236	else if (rdev->family >= CHIP_RV770)
	237	value = rdev->config.rv770.max_tile_pipes;
	238	else if (rdev->family >= CHIP_R600)
	239	value = rdev->config.r600.max_tile_pipes;
	240	else {
	241	return -EINVAL;
	242	}
	243	break;
8aeb96f8 AD	244	case RADEON_INFO_FUSION_GART_WORKING:
	245	value = 1;
	246	break;
e55b9422	247	case RADEON_INFO_BACKEND_MAP:
c1b2f69f MD	248	if (rdev->family >= CHIP_TAHITI)
	249	value = rdev->config.si.backend_map;
	250	else if (rdev->family >= CHIP_CAYMAN)
e55b9422 AD	251	value = rdev->config.cayman.backend_map;
	252	else if (rdev->family >= CHIP_CEDAR)
	253	value = rdev->config.evergreen.backend_map;
	254	else if (rdev->family >= CHIP_RV770)
	255	value = rdev->config.rv770.backend_map;
	256	else if (rdev->family >= CHIP_R600)
	257	value = rdev->config.r600.backend_map;
	258	else {
	259	return -EINVAL;
	260	}
	261	break;
721604a1 JG	262	case RADEON_INFO_VA_START:
	263	/* this is where we report if vm is supported or not */
	264	if (rdev->family < CHIP_CAYMAN)
	265	return -EINVAL;
	266	value = RADEON_VA_RESERVED_SIZE;
	267	break;
	268	case RADEON_INFO_IB_VM_MAX_SIZE:
	269	/* this is where we report if vm is supported or not */
	270	if (rdev->family < CHIP_CAYMAN)
	271	return -EINVAL;
	272	value = RADEON_IB_VM_MAX_SIZE;
	273	break;
609c1e15	274	case RADEON_INFO_MAX_PIPES:
c1b2f69f MD	275	if (rdev->family >= CHIP_TAHITI)
	276	value = rdev->config.si.max_pipes_per_simd;
	277	else if (rdev->family >= CHIP_CAYMAN)
609c1e15 TS	278	value = rdev->config.cayman.max_pipes_per_simd;
	279	else if (rdev->family >= CHIP_CEDAR)
	280	value = rdev->config.evergreen.max_pipes;
	281	else if (rdev->family >= CHIP_RV770)
	282	value = rdev->config.rv770.max_pipes;
	283	else if (rdev->family >= CHIP_R600)
	284	value = rdev->config.r600.max_pipes;
	285	else {
	286	return -EINVAL;
	287	}
	288	break;
771fe6b9	289	default:
d9fdaafb	290	DRM_DEBUG_KMS("Invalid request %d\n", info->request);
771fe6b9 JG	291	return -EINVAL;
	292	}
	293	if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
	294	DRM_ERROR("copy_to_user\n");
	295	return -EFAULT;
	296	}
	297	return 0;
	298	}
	299
	300
	301	/*
	302	* Outdated mess for old drm with Xorg being in charge (void function now).
	303	*/
	304	int radeon_driver_firstopen_kms(struct drm_device *dev)
	305	{
	306	return 0;
	307	}
	308
771fe6b9 JG	309	void radeon_driver_lastclose_kms(struct drm_device *dev)
771fe6b9 JG	310	{
6a9ee8af	311	vga_switcheroo_process_delayed_switch();
771fe6b9 JG	312	}
	313
	314	int radeon_driver_open_kms(struct drm_device dev, struct drm_file file_priv)
	315	{
721604a1 JG	316	struct radeon_device *rdev = dev->dev_private;
	317
	318	file_priv->driver_priv = NULL;
	319
	320	/* new gpu have virtual address space support */
	321	if (rdev->family >= CHIP_CAYMAN) {
	322	struct radeon_fpriv *fpriv;
	323	int r;
	324
	325	fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
	326	if (unlikely(!fpriv)) {
	327	return -ENOMEM;
	328	}
	329
	330	r = radeon_vm_init(rdev, &fpriv->vm);
	331	if (r) {
	332	radeon_vm_fini(rdev, &fpriv->vm);
	333	kfree(fpriv);
	334	return r;
	335	}
	336
	337	file_priv->driver_priv = fpriv;
	338	}
771fe6b9 JG	339	return 0;
	340	}
	341
	342	void radeon_driver_postclose_kms(struct drm_device *dev,
	343	struct drm_file *file_priv)
	344	{
721604a1 JG	345	struct radeon_device *rdev = dev->dev_private;
	346
	347	/* new gpu have virtual address space support */
	348	if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
	349	struct radeon_fpriv *fpriv = file_priv->driver_priv;
	350
	351	radeon_vm_fini(rdev, &fpriv->vm);
	352	kfree(fpriv);
	353	file_priv->driver_priv = NULL;
	354	}
771fe6b9 JG	355	}
	356
	357	void radeon_driver_preclose_kms(struct drm_device *dev,
	358	struct drm_file *file_priv)
	359	{
ab9e1f59 DA	360	struct radeon_device *rdev = dev->dev_private;
	361	if (rdev->hyperz_filp == file_priv)
	362	rdev->hyperz_filp = NULL;
dca0d612 MO	363	if (rdev->cmask_filp == file_priv)
dca0d612 MO	364	rdev->cmask_filp = NULL;
771fe6b9 JG	365	}
771fe6b9 JG	366
771fe6b9 JG	367	/*
	368	* VBlank related functions.
	369	*/
	370	u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
	371	{
7ed220d7 MD	372	struct radeon_device *rdev = dev->dev_private;
7ed220d7 MD	373
9c950a43	374	if (crtc < 0 \|\| crtc >= rdev->num_crtc) {
7ed220d7 MD	375	DRM_ERROR("Invalid crtc %d\n", crtc);
	376	return -EINVAL;
	377	}
	378
	379	return radeon_get_vblank_counter(rdev, crtc);
771fe6b9 JG	380	}
	381
	382	int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
	383	{
7ed220d7 MD	384	struct radeon_device *rdev = dev->dev_private;
7ed220d7 MD	385
9c950a43	386	if (crtc < 0 \|\| crtc >= rdev->num_crtc) {
7ed220d7 MD	387	DRM_ERROR("Invalid crtc %d\n", crtc);
	388	return -EINVAL;
	389	}
	390
	391	rdev->irq.crtc_vblank_int[crtc] = true;
	392
	393	return radeon_irq_set(rdev);
771fe6b9 JG	394	}
	395
	396	void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
	397	{
7ed220d7 MD	398	struct radeon_device *rdev = dev->dev_private;
7ed220d7 MD	399
9c950a43	400	if (crtc < 0 \|\| crtc >= rdev->num_crtc) {
7ed220d7 MD	401	DRM_ERROR("Invalid crtc %d\n", crtc);
	402	return;
	403	}
	404
	405	rdev->irq.crtc_vblank_int[crtc] = false;
	406
	407	radeon_irq_set(rdev);
771fe6b9 JG	408	}
771fe6b9 JG	409
f5a80209 MK	410	int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
	411	int *max_error,
	412	struct timeval *vblank_time,
	413	unsigned flags)
	414	{
	415	struct drm_crtc *drmcrtc;
	416	struct radeon_device *rdev = dev->dev_private;
	417
	418	if (crtc < 0 \|\| crtc >= dev->num_crtcs) {
	419	DRM_ERROR("Invalid crtc %d\n", crtc);
	420	return -EINVAL;
	421	}
	422
	423	/* Get associated drm_crtc: */
	424	drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
	425
	426	/* Helper routine in DRM core does all the work: */
	427	return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
	428	vblank_time, flags,
	429	drmcrtc);
	430	}
771fe6b9	431
771fe6b9 JG	432	/*
	433	* IOCTL.
	434	*/
	435	int radeon_dma_ioctl_kms(struct drm_device dev, void data,
	436	struct drm_file *file_priv)
	437	{
	438	/* Not valid in KMS. */
	439	return -EINVAL;
	440	}
	441
	442	#define KMS_INVALID_IOCTL(name) \
	443	int name(struct drm_device dev, void data, struct drm_file *file_priv)\
	444	{ \
	445	DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
	446	return -EINVAL; \
	447	}
	448
	449	/*
	450	* All these ioctls are invalid in kms world.
	451	*/
	452	KMS_INVALID_IOCTL(radeon_cp_init_kms)
	453	KMS_INVALID_IOCTL(radeon_cp_start_kms)
	454	KMS_INVALID_IOCTL(radeon_cp_stop_kms)
	455	KMS_INVALID_IOCTL(radeon_cp_reset_kms)
	456	KMS_INVALID_IOCTL(radeon_cp_idle_kms)
	457	KMS_INVALID_IOCTL(radeon_cp_resume_kms)
	458	KMS_INVALID_IOCTL(radeon_engine_reset_kms)
	459	KMS_INVALID_IOCTL(radeon_fullscreen_kms)
	460	KMS_INVALID_IOCTL(radeon_cp_swap_kms)
	461	KMS_INVALID_IOCTL(radeon_cp_clear_kms)
	462	KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
	463	KMS_INVALID_IOCTL(radeon_cp_indices_kms)
	464	KMS_INVALID_IOCTL(radeon_cp_texture_kms)
	465	KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
	466	KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
	467	KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
	468	KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
	469	KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
	470	KMS_INVALID_IOCTL(radeon_cp_flip_kms)
	471	KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
	472	KMS_INVALID_IOCTL(radeon_mem_free_kms)
	473	KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
	474	KMS_INVALID_IOCTL(radeon_irq_emit_kms)
	475	KMS_INVALID_IOCTL(radeon_irq_wait_kms)
	476	KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
	477	KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
	478	KMS_INVALID_IOCTL(radeon_surface_free_kms)
	479
	480
	481	struct drm_ioctl_desc radeon_ioctls_kms[] = {
1b2f1489 DA	482	DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	483	DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	484	DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	485	DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	486	DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
	487	DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
	488	DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
	489	DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
	490	DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
	491	DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
	492	DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
	493	DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
	494	DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
	495	DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
	496	DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	497	DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
	498	DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
	499	DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
	500	DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
	501	DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
	502	DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
	503	DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	504	DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
	505	DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
	506	DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
	507	DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
	508	DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
771fe6b9	509	/* KMS */
1b2f1489 DA	510	DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	511	DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	512	DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	513	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	514	DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	515	DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	516	DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	517	DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	518	DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	519	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	520	DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH\|DRM_UNLOCKED),
	521	DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH\|DRM_UNLOCKED),
721604a1	522	DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH\|DRM_UNLOCKED),
771fe6b9 JG	523	};
771fe6b9 JG	524	int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);