Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
760285e7 | 28 | #include <drm/drmP.h> |
771fe6b9 | 29 | #include "radeon.h" |
760285e7 | 30 | #include <drm/radeon_drm.h> |
6759a0a7 | 31 | #include "radeon_asic.h" |
771fe6b9 | 32 | |
6a9ee8af | 33 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
10ebc0bc | 35 | #include <linux/pm_runtime.h> |
f482a141 AD |
36 | /** |
37 | * radeon_driver_unload_kms - Main unload function for KMS. | |
38 | * | |
39 | * @dev: drm dev pointer | |
40 | * | |
41 | * This is the main unload function for KMS (all asics). | |
42 | * It calls radeon_modeset_fini() to tear down the | |
43 | * displays, and radeon_device_fini() to tear down | |
44 | * the rest of the device (CP, writeback, etc.). | |
45 | * Returns 0 on success. | |
46 | */ | |
cf0fe456 JG |
47 | int radeon_driver_unload_kms(struct drm_device *dev) |
48 | { | |
49 | struct radeon_device *rdev = dev->dev_private; | |
50 | ||
51 | if (rdev == NULL) | |
52 | return 0; | |
10ebc0bc | 53 | |
0cd9cb76 AD |
54 | if (rdev->rmmio == NULL) |
55 | goto done_free; | |
10ebc0bc DA |
56 | |
57 | pm_runtime_get_sync(dev->dev); | |
58 | ||
c4917074 | 59 | radeon_acpi_fini(rdev); |
10ebc0bc | 60 | |
cf0fe456 JG |
61 | radeon_modeset_fini(rdev); |
62 | radeon_device_fini(rdev); | |
0cd9cb76 AD |
63 | |
64 | done_free: | |
cf0fe456 JG |
65 | kfree(rdev); |
66 | dev->dev_private = NULL; | |
67 | return 0; | |
68 | } | |
771fe6b9 | 69 | |
f482a141 AD |
70 | /** |
71 | * radeon_driver_load_kms - Main load function for KMS. | |
72 | * | |
73 | * @dev: drm dev pointer | |
74 | * @flags: device flags | |
75 | * | |
76 | * This is the main load function for KMS (all asics). | |
77 | * It calls radeon_device_init() to set up the non-display | |
78 | * parts of the chip (asic init, CP, writeback, etc.), and | |
79 | * radeon_modeset_init() to set up the display parts | |
80 | * (crtcs, encoders, hotplug detect, etc.). | |
81 | * Returns 0 on success, error on failure. | |
82 | */ | |
771fe6b9 JG |
83 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
84 | { | |
85 | struct radeon_device *rdev; | |
d7a2952f | 86 | int r, acpi_status; |
771fe6b9 JG |
87 | |
88 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); | |
89 | if (rdev == NULL) { | |
90 | return -ENOMEM; | |
91 | } | |
92 | dev->dev_private = (void *)rdev; | |
93 | ||
94 | /* update BUS flag */ | |
8410ea3b | 95 | if (drm_pci_device_is_agp(dev)) { |
771fe6b9 | 96 | flags |= RADEON_IS_AGP; |
58b6542b | 97 | } else if (pci_is_pcie(dev->pdev)) { |
771fe6b9 JG |
98 | flags |= RADEON_IS_PCIE; |
99 | } else { | |
100 | flags |= RADEON_IS_PCI; | |
101 | } | |
102 | ||
6cf8a3f5 JG |
103 | /* radeon_device_init should report only fatal error |
104 | * like memory allocation failure or iomapping failure, | |
105 | * or memory manager initialization failure, it must | |
106 | * properly initialize the GPU MC controller and permit | |
107 | * VRAM allocation | |
108 | */ | |
771fe6b9 JG |
109 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
110 | if (r) { | |
cf0fe456 JG |
111 | dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); |
112 | goto out; | |
6cf8a3f5 | 113 | } |
d7a2952f | 114 | |
6cf8a3f5 JG |
115 | /* Again modeset_init should fail only on fatal error |
116 | * otherwise it should provide enough functionalities | |
117 | * for shadowfb to run | |
118 | */ | |
119 | r = radeon_modeset_init(rdev); | |
cf0fe456 JG |
120 | if (r) |
121 | dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); | |
fda4b25c LT |
122 | |
123 | /* Call ACPI methods: require modeset init | |
124 | * but failure is not fatal | |
125 | */ | |
126 | if (!r) { | |
127 | acpi_status = radeon_acpi_init(rdev); | |
128 | if (acpi_status) | |
129 | dev_dbg(&dev->pdev->dev, | |
130 | "Error during ACPI methods call\n"); | |
131 | } | |
132 | ||
10ebc0bc DA |
133 | if (radeon_runtime_pm != 0) { |
134 | pm_runtime_use_autosuspend(dev->dev); | |
135 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | |
136 | pm_runtime_set_active(dev->dev); | |
137 | pm_runtime_allow(dev->dev); | |
138 | pm_runtime_mark_last_busy(dev->dev); | |
139 | pm_runtime_put_autosuspend(dev->dev); | |
140 | } | |
141 | ||
cf0fe456 JG |
142 | out: |
143 | if (r) | |
144 | radeon_driver_unload_kms(dev); | |
10ebc0bc DA |
145 | |
146 | ||
cf0fe456 | 147 | return r; |
771fe6b9 JG |
148 | } |
149 | ||
f482a141 AD |
150 | /** |
151 | * radeon_set_filp_rights - Set filp right. | |
152 | * | |
153 | * @dev: drm dev pointer | |
154 | * @owner: drm file | |
155 | * @applier: drm file | |
156 | * @value: value | |
157 | * | |
158 | * Sets the filp rights for the device (all asics). | |
159 | */ | |
9eba4a93 MO |
160 | static void radeon_set_filp_rights(struct drm_device *dev, |
161 | struct drm_file **owner, | |
162 | struct drm_file *applier, | |
163 | uint32_t *value) | |
164 | { | |
165 | mutex_lock(&dev->struct_mutex); | |
166 | if (*value == 1) { | |
167 | /* wants rights */ | |
168 | if (!*owner) | |
169 | *owner = applier; | |
170 | } else if (*value == 0) { | |
171 | /* revokes rights */ | |
172 | if (*owner == applier) | |
173 | *owner = NULL; | |
174 | } | |
175 | *value = *owner == applier ? 1 : 0; | |
176 | mutex_unlock(&dev->struct_mutex); | |
177 | } | |
771fe6b9 JG |
178 | |
179 | /* | |
9eba4a93 | 180 | * Userspace get information ioctl |
771fe6b9 | 181 | */ |
f482a141 AD |
182 | /** |
183 | * radeon_info_ioctl - answer a device specific request. | |
184 | * | |
185 | * @rdev: radeon device pointer | |
186 | * @data: request object | |
187 | * @filp: drm filp | |
188 | * | |
189 | * This function is used to pass device specific parameters to the userspace | |
190 | * drivers. Examples include: pci device id, pipeline parms, tiling params, | |
191 | * etc. (all asics). | |
192 | * Returns 0 on success, -EINVAL on failure. | |
193 | */ | |
5520345f | 194 | static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
771fe6b9 JG |
195 | { |
196 | struct radeon_device *rdev = dev->dev_private; | |
6759a0a7 | 197 | struct drm_radeon_info *info = data; |
bc35afdb | 198 | struct radeon_mode_info *minfo = &rdev->mode_info; |
64d7b8be JG |
199 | uint32_t *value, value_tmp, *value_ptr, value_size; |
200 | uint64_t value64; | |
bc35afdb JG |
201 | struct drm_crtc *crtc; |
202 | int i, found; | |
771fe6b9 | 203 | |
771fe6b9 | 204 | value_ptr = (uint32_t *)((unsigned long)info->value); |
64d7b8be JG |
205 | value = &value_tmp; |
206 | value_size = sizeof(uint32_t); | |
d8ab3557 | 207 | |
771fe6b9 JG |
208 | switch (info->request) { |
209 | case RADEON_INFO_DEVICE_ID: | |
ffbab09b | 210 | *value = dev->pdev->device; |
771fe6b9 JG |
211 | break; |
212 | case RADEON_INFO_NUM_GB_PIPES: | |
64d7b8be | 213 | *value = rdev->num_gb_pipes; |
771fe6b9 | 214 | break; |
f779b3e5 | 215 | case RADEON_INFO_NUM_Z_PIPES: |
64d7b8be | 216 | *value = rdev->num_z_pipes; |
f779b3e5 | 217 | break; |
733289c2 | 218 | case RADEON_INFO_ACCEL_WORKING: |
148a03bc AD |
219 | /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ |
220 | if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) | |
64d7b8be | 221 | *value = false; |
148a03bc | 222 | else |
64d7b8be | 223 | *value = rdev->accel_working; |
733289c2 | 224 | break; |
bc35afdb | 225 | case RADEON_INFO_CRTC_FROM_ID: |
1d6ac185 | 226 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
227 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
228 | return -EFAULT; | |
229 | } | |
bc35afdb JG |
230 | for (i = 0, found = 0; i < rdev->num_crtc; i++) { |
231 | crtc = (struct drm_crtc *)minfo->crtcs[i]; | |
64d7b8be | 232 | if (crtc && crtc->base.id == *value) { |
0baf2d8f | 233 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
64d7b8be | 234 | *value = radeon_crtc->crtc_id; |
bc35afdb JG |
235 | found = 1; |
236 | break; | |
237 | } | |
238 | } | |
239 | if (!found) { | |
64d7b8be | 240 | DRM_DEBUG_KMS("unknown crtc id %d\n", *value); |
bc35afdb JG |
241 | return -EINVAL; |
242 | } | |
243 | break; | |
148a03bc | 244 | case RADEON_INFO_ACCEL_WORKING2: |
64d7b8be | 245 | *value = rdev->accel_working; |
148a03bc | 246 | break; |
e7aeeba6 | 247 | case RADEON_INFO_TILING_CONFIG: |
64f759cc AD |
248 | if (rdev->family >= CHIP_BONAIRE) |
249 | *value = rdev->config.cik.tile_config; | |
250 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 251 | *value = rdev->config.si.tile_config; |
c1b2f69f | 252 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 253 | *value = rdev->config.cayman.tile_config; |
fecf1d07 | 254 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 255 | *value = rdev->config.evergreen.tile_config; |
e7aeeba6 | 256 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 257 | *value = rdev->config.rv770.tile_config; |
e7aeeba6 | 258 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 259 | *value = rdev->config.r600.tile_config; |
e7aeeba6 | 260 | else { |
d9fdaafb | 261 | DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); |
e7aeeba6 AD |
262 | return -EINVAL; |
263 | } | |
b824b364 | 264 | break; |
ab9e1f59 | 265 | case RADEON_INFO_WANT_HYPERZ: |
43861f71 MO |
266 | /* The "value" here is both an input and output parameter. |
267 | * If the input value is 1, filp requests hyper-z access. | |
268 | * If the input value is 0, filp revokes its hyper-z access. | |
269 | * | |
270 | * When returning, the value is 1 if filp owns hyper-z access, | |
271 | * 0 otherwise. */ | |
1d6ac185 | 272 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
273 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
274 | return -EFAULT; | |
275 | } | |
276 | if (*value >= 2) { | |
277 | DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); | |
43861f71 MO |
278 | return -EINVAL; |
279 | } | |
64d7b8be | 280 | radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); |
9eba4a93 MO |
281 | break; |
282 | case RADEON_INFO_WANT_CMASK: | |
283 | /* The same logic as Hyper-Z. */ | |
1d6ac185 | 284 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
285 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
286 | return -EFAULT; | |
287 | } | |
288 | if (*value >= 2) { | |
289 | DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); | |
9eba4a93 | 290 | return -EINVAL; |
ab9e1f59 | 291 | } |
64d7b8be | 292 | radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); |
e7aeeba6 | 293 | break; |
58bbf018 AD |
294 | case RADEON_INFO_CLOCK_CRYSTAL_FREQ: |
295 | /* return clock value in KHz */ | |
454d2e2a | 296 | if (rdev->asic->get_xclk) |
64d7b8be | 297 | *value = radeon_get_xclk(rdev) * 10; |
454d2e2a | 298 | else |
64d7b8be | 299 | *value = rdev->clock.spll.reference_freq * 10; |
58bbf018 | 300 | break; |
486af189 | 301 | case RADEON_INFO_NUM_BACKENDS: |
64f759cc AD |
302 | if (rdev->family >= CHIP_BONAIRE) |
303 | *value = rdev->config.cik.max_backends_per_se * | |
304 | rdev->config.cik.max_shader_engines; | |
305 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 306 | *value = rdev->config.si.max_backends_per_se * |
c1b2f69f MD |
307 | rdev->config.si.max_shader_engines; |
308 | else if (rdev->family >= CHIP_CAYMAN) | |
64d7b8be | 309 | *value = rdev->config.cayman.max_backends_per_se * |
fecf1d07 AD |
310 | rdev->config.cayman.max_shader_engines; |
311 | else if (rdev->family >= CHIP_CEDAR) | |
64d7b8be | 312 | *value = rdev->config.evergreen.max_backends; |
486af189 | 313 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 314 | *value = rdev->config.rv770.max_backends; |
486af189 | 315 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 316 | *value = rdev->config.r600.max_backends; |
486af189 DA |
317 | else { |
318 | return -EINVAL; | |
319 | } | |
320 | break; | |
6565945b | 321 | case RADEON_INFO_NUM_TILE_PIPES: |
64f759cc AD |
322 | if (rdev->family >= CHIP_BONAIRE) |
323 | *value = rdev->config.cik.max_tile_pipes; | |
324 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 325 | *value = rdev->config.si.max_tile_pipes; |
c1b2f69f | 326 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 327 | *value = rdev->config.cayman.max_tile_pipes; |
6565945b | 328 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 329 | *value = rdev->config.evergreen.max_tile_pipes; |
6565945b | 330 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 331 | *value = rdev->config.rv770.max_tile_pipes; |
6565945b | 332 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 333 | *value = rdev->config.r600.max_tile_pipes; |
6565945b AD |
334 | else { |
335 | return -EINVAL; | |
336 | } | |
337 | break; | |
8aeb96f8 | 338 | case RADEON_INFO_FUSION_GART_WORKING: |
64d7b8be | 339 | *value = 1; |
8aeb96f8 | 340 | break; |
e55b9422 | 341 | case RADEON_INFO_BACKEND_MAP: |
64f759cc | 342 | if (rdev->family >= CHIP_BONAIRE) |
1ddce27d | 343 | *value = rdev->config.cik.backend_map; |
64f759cc | 344 | else if (rdev->family >= CHIP_TAHITI) |
64d7b8be | 345 | *value = rdev->config.si.backend_map; |
c1b2f69f | 346 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 347 | *value = rdev->config.cayman.backend_map; |
e55b9422 | 348 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 349 | *value = rdev->config.evergreen.backend_map; |
e55b9422 | 350 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 351 | *value = rdev->config.rv770.backend_map; |
e55b9422 | 352 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 353 | *value = rdev->config.r600.backend_map; |
e55b9422 AD |
354 | else { |
355 | return -EINVAL; | |
356 | } | |
357 | break; | |
721604a1 JG |
358 | case RADEON_INFO_VA_START: |
359 | /* this is where we report if vm is supported or not */ | |
360 | if (rdev->family < CHIP_CAYMAN) | |
361 | return -EINVAL; | |
64d7b8be | 362 | *value = RADEON_VA_RESERVED_SIZE; |
721604a1 JG |
363 | break; |
364 | case RADEON_INFO_IB_VM_MAX_SIZE: | |
365 | /* this is where we report if vm is supported or not */ | |
366 | if (rdev->family < CHIP_CAYMAN) | |
367 | return -EINVAL; | |
64d7b8be | 368 | *value = RADEON_IB_VM_MAX_SIZE; |
721604a1 | 369 | break; |
609c1e15 | 370 | case RADEON_INFO_MAX_PIPES: |
64f759cc AD |
371 | if (rdev->family >= CHIP_BONAIRE) |
372 | *value = rdev->config.cik.max_cu_per_sh; | |
373 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 374 | *value = rdev->config.si.max_cu_per_sh; |
c1b2f69f | 375 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 376 | *value = rdev->config.cayman.max_pipes_per_simd; |
609c1e15 | 377 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 378 | *value = rdev->config.evergreen.max_pipes; |
609c1e15 | 379 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 380 | *value = rdev->config.rv770.max_pipes; |
609c1e15 | 381 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 382 | *value = rdev->config.r600.max_pipes; |
609c1e15 TS |
383 | else { |
384 | return -EINVAL; | |
385 | } | |
386 | break; | |
64d7b8be JG |
387 | case RADEON_INFO_TIMESTAMP: |
388 | if (rdev->family < CHIP_R600) { | |
389 | DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); | |
390 | return -EINVAL; | |
391 | } | |
392 | value = (uint32_t*)&value64; | |
393 | value_size = sizeof(uint64_t); | |
394 | value64 = radeon_get_gpu_clock_counter(rdev); | |
395 | break; | |
2e1a7674 | 396 | case RADEON_INFO_MAX_SE: |
64f759cc AD |
397 | if (rdev->family >= CHIP_BONAIRE) |
398 | *value = rdev->config.cik.max_shader_engines; | |
399 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 400 | *value = rdev->config.si.max_shader_engines; |
2e1a7674 | 401 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 402 | *value = rdev->config.cayman.max_shader_engines; |
2e1a7674 | 403 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 404 | *value = rdev->config.evergreen.num_ses; |
2e1a7674 | 405 | else |
64d7b8be | 406 | *value = 1; |
2e1a7674 AD |
407 | break; |
408 | case RADEON_INFO_MAX_SH_PER_SE: | |
64f759cc AD |
409 | if (rdev->family >= CHIP_BONAIRE) |
410 | *value = rdev->config.cik.max_sh_per_se; | |
411 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 412 | *value = rdev->config.si.max_sh_per_se; |
2e1a7674 AD |
413 | else |
414 | return -EINVAL; | |
415 | break; | |
a0a53aa8 | 416 | case RADEON_INFO_FASTFB_WORKING: |
64d7b8be | 417 | *value = rdev->fastfb_working; |
a0a53aa8 | 418 | break; |
902aaef6 | 419 | case RADEON_INFO_RING_WORKING: |
1d6ac185 | 420 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
421 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
422 | return -EFAULT; | |
423 | } | |
424 | switch (*value) { | |
902aaef6 CK |
425 | case RADEON_CS_RING_GFX: |
426 | case RADEON_CS_RING_COMPUTE: | |
64d7b8be | 427 | *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; |
902aaef6 CK |
428 | break; |
429 | case RADEON_CS_RING_DMA: | |
64d7b8be JG |
430 | *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; |
431 | *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; | |
902aaef6 CK |
432 | break; |
433 | case RADEON_CS_RING_UVD: | |
64d7b8be | 434 | *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; |
902aaef6 | 435 | break; |
f7ba8b04 CK |
436 | case RADEON_CS_RING_VCE: |
437 | *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; | |
438 | break; | |
902aaef6 CK |
439 | default: |
440 | return -EINVAL; | |
441 | } | |
442 | break; | |
64d7b8be | 443 | case RADEON_INFO_SI_TILE_MODE_ARRAY: |
64f759cc | 444 | if (rdev->family >= CHIP_BONAIRE) { |
39aee490 AD |
445 | value = rdev->config.cik.tile_mode_array; |
446 | value_size = sizeof(uint32_t)*32; | |
447 | } else if (rdev->family >= CHIP_TAHITI) { | |
448 | value = rdev->config.si.tile_mode_array; | |
449 | value_size = sizeof(uint32_t)*32; | |
450 | } else { | |
451 | DRM_DEBUG_KMS("tile mode array is si+ only!\n"); | |
64f759cc AD |
452 | return -EINVAL; |
453 | } | |
64d7b8be | 454 | break; |
32f79a8a MD |
455 | case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: |
456 | if (rdev->family >= CHIP_BONAIRE) { | |
457 | value = rdev->config.cik.macrotile_mode_array; | |
458 | value_size = sizeof(uint32_t)*16; | |
459 | } else { | |
460 | DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); | |
461 | return -EINVAL; | |
462 | } | |
463 | break; | |
e5b9e750 TS |
464 | case RADEON_INFO_SI_CP_DMA_COMPUTE: |
465 | *value = 1; | |
466 | break; | |
439a1cff MO |
467 | case RADEON_INFO_SI_BACKEND_ENABLED_MASK: |
468 | if (rdev->family >= CHIP_BONAIRE) { | |
469 | *value = rdev->config.cik.backend_enable_mask; | |
470 | } else if (rdev->family >= CHIP_TAHITI) { | |
471 | *value = rdev->config.si.backend_enable_mask; | |
472 | } else { | |
473 | DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); | |
474 | } | |
475 | break; | |
f5f1f897 AD |
476 | case RADEON_INFO_MAX_SCLK: |
477 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && | |
478 | rdev->pm.dpm_enabled) | |
479 | *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; | |
480 | else | |
481 | *value = rdev->pm.default_sclk * 10; | |
482 | break; | |
98ccc291 CK |
483 | case RADEON_INFO_VCE_FW_VERSION: |
484 | *value = rdev->vce.fw_version; | |
485 | break; | |
486 | case RADEON_INFO_VCE_FB_VERSION: | |
487 | *value = rdev->vce.fb_version; | |
488 | break; | |
67e8e3f9 MO |
489 | case RADEON_INFO_NUM_BYTES_MOVED: |
490 | value = (uint32_t*)&value64; | |
491 | value_size = sizeof(uint64_t); | |
492 | value64 = atomic64_read(&rdev->num_bytes_moved); | |
493 | break; | |
494 | case RADEON_INFO_VRAM_USAGE: | |
495 | value = (uint32_t*)&value64; | |
496 | value_size = sizeof(uint64_t); | |
497 | value64 = atomic64_read(&rdev->vram_usage); | |
498 | break; | |
499 | case RADEON_INFO_GTT_USAGE: | |
500 | value = (uint32_t*)&value64; | |
501 | value_size = sizeof(uint64_t); | |
502 | value64 = atomic64_read(&rdev->gtt_usage); | |
503 | break; | |
771fe6b9 | 504 | default: |
d9fdaafb | 505 | DRM_DEBUG_KMS("Invalid request %d\n", info->request); |
771fe6b9 JG |
506 | return -EINVAL; |
507 | } | |
1d6ac185 | 508 | if (copy_to_user(value_ptr, (char*)value, value_size)) { |
6759a0a7 | 509 | DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); |
771fe6b9 JG |
510 | return -EFAULT; |
511 | } | |
512 | return 0; | |
513 | } | |
514 | ||
515 | ||
516 | /* | |
517 | * Outdated mess for old drm with Xorg being in charge (void function now). | |
518 | */ | |
f482a141 AD |
519 | /** |
520 | * radeon_driver_firstopen_kms - drm callback for last close | |
521 | * | |
522 | * @dev: drm dev pointer | |
523 | * | |
524 | * Switch vga switcheroo state after last close (all asics). | |
525 | */ | |
771fe6b9 JG |
526 | void radeon_driver_lastclose_kms(struct drm_device *dev) |
527 | { | |
6a9ee8af | 528 | vga_switcheroo_process_delayed_switch(); |
771fe6b9 JG |
529 | } |
530 | ||
f482a141 AD |
531 | /** |
532 | * radeon_driver_open_kms - drm callback for open | |
533 | * | |
534 | * @dev: drm dev pointer | |
535 | * @file_priv: drm file | |
536 | * | |
537 | * On device open, init vm on cayman+ (all asics). | |
538 | * Returns 0 on success, error on failure. | |
539 | */ | |
771fe6b9 JG |
540 | int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) |
541 | { | |
721604a1 | 542 | struct radeon_device *rdev = dev->dev_private; |
10ebc0bc | 543 | int r; |
721604a1 JG |
544 | |
545 | file_priv->driver_priv = NULL; | |
546 | ||
10ebc0bc DA |
547 | r = pm_runtime_get_sync(dev->dev); |
548 | if (r < 0) | |
549 | return r; | |
550 | ||
721604a1 JG |
551 | /* new gpu have virtual address space support */ |
552 | if (rdev->family >= CHIP_CAYMAN) { | |
553 | struct radeon_fpriv *fpriv; | |
d72d43cf | 554 | struct radeon_bo_va *bo_va; |
721604a1 JG |
555 | int r; |
556 | ||
557 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
558 | if (unlikely(!fpriv)) { | |
559 | return -ENOMEM; | |
560 | } | |
561 | ||
d72d43cf CK |
562 | radeon_vm_init(rdev, &fpriv->vm); |
563 | ||
564 | /* map the ib pool buffer read only into | |
565 | * virtual address space */ | |
566 | bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, | |
567 | rdev->ring_tmp_bo.bo); | |
568 | r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, | |
569 | RADEON_VM_PAGE_READABLE | | |
570 | RADEON_VM_PAGE_SNOOPED); | |
721604a1 JG |
571 | if (r) { |
572 | radeon_vm_fini(rdev, &fpriv->vm); | |
573 | kfree(fpriv); | |
574 | return r; | |
575 | } | |
576 | ||
577 | file_priv->driver_priv = fpriv; | |
578 | } | |
10ebc0bc DA |
579 | |
580 | pm_runtime_mark_last_busy(dev->dev); | |
581 | pm_runtime_put_autosuspend(dev->dev); | |
771fe6b9 JG |
582 | return 0; |
583 | } | |
584 | ||
f482a141 AD |
585 | /** |
586 | * radeon_driver_postclose_kms - drm callback for post close | |
587 | * | |
588 | * @dev: drm dev pointer | |
589 | * @file_priv: drm file | |
590 | * | |
591 | * On device post close, tear down vm on cayman+ (all asics). | |
592 | */ | |
771fe6b9 JG |
593 | void radeon_driver_postclose_kms(struct drm_device *dev, |
594 | struct drm_file *file_priv) | |
595 | { | |
721604a1 JG |
596 | struct radeon_device *rdev = dev->dev_private; |
597 | ||
598 | /* new gpu have virtual address space support */ | |
599 | if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { | |
600 | struct radeon_fpriv *fpriv = file_priv->driver_priv; | |
d72d43cf CK |
601 | struct radeon_bo_va *bo_va; |
602 | int r; | |
603 | ||
604 | r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); | |
605 | if (!r) { | |
606 | bo_va = radeon_vm_bo_find(&fpriv->vm, | |
607 | rdev->ring_tmp_bo.bo); | |
608 | if (bo_va) | |
609 | radeon_vm_bo_rmv(rdev, bo_va); | |
610 | radeon_bo_unreserve(rdev->ring_tmp_bo.bo); | |
611 | } | |
721604a1 JG |
612 | |
613 | radeon_vm_fini(rdev, &fpriv->vm); | |
614 | kfree(fpriv); | |
615 | file_priv->driver_priv = NULL; | |
616 | } | |
771fe6b9 JG |
617 | } |
618 | ||
f482a141 AD |
619 | /** |
620 | * radeon_driver_preclose_kms - drm callback for pre close | |
621 | * | |
622 | * @dev: drm dev pointer | |
623 | * @file_priv: drm file | |
624 | * | |
625 | * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx | |
626 | * (all asics). | |
627 | */ | |
771fe6b9 JG |
628 | void radeon_driver_preclose_kms(struct drm_device *dev, |
629 | struct drm_file *file_priv) | |
630 | { | |
ab9e1f59 DA |
631 | struct radeon_device *rdev = dev->dev_private; |
632 | if (rdev->hyperz_filp == file_priv) | |
633 | rdev->hyperz_filp = NULL; | |
dca0d612 MO |
634 | if (rdev->cmask_filp == file_priv) |
635 | rdev->cmask_filp = NULL; | |
f2ba57b5 | 636 | radeon_uvd_free_handles(rdev, file_priv); |
d93f7937 | 637 | radeon_vce_free_handles(rdev, file_priv); |
771fe6b9 JG |
638 | } |
639 | ||
771fe6b9 JG |
640 | /* |
641 | * VBlank related functions. | |
642 | */ | |
f482a141 AD |
643 | /** |
644 | * radeon_get_vblank_counter_kms - get frame count | |
645 | * | |
646 | * @dev: drm dev pointer | |
647 | * @crtc: crtc to get the frame count from | |
648 | * | |
649 | * Gets the frame count on the requested crtc (all asics). | |
650 | * Returns frame count on success, -EINVAL on failure. | |
651 | */ | |
771fe6b9 JG |
652 | u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) |
653 | { | |
7ed220d7 MD |
654 | struct radeon_device *rdev = dev->dev_private; |
655 | ||
9c950a43 | 656 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
657 | DRM_ERROR("Invalid crtc %d\n", crtc); |
658 | return -EINVAL; | |
659 | } | |
660 | ||
661 | return radeon_get_vblank_counter(rdev, crtc); | |
771fe6b9 JG |
662 | } |
663 | ||
f482a141 AD |
664 | /** |
665 | * radeon_enable_vblank_kms - enable vblank interrupt | |
666 | * | |
667 | * @dev: drm dev pointer | |
668 | * @crtc: crtc to enable vblank interrupt for | |
669 | * | |
670 | * Enable the interrupt on the requested crtc (all asics). | |
671 | * Returns 0 on success, -EINVAL on failure. | |
672 | */ | |
771fe6b9 JG |
673 | int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) |
674 | { | |
7ed220d7 | 675 | struct radeon_device *rdev = dev->dev_private; |
fb98257a CK |
676 | unsigned long irqflags; |
677 | int r; | |
7ed220d7 | 678 | |
9c950a43 | 679 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
680 | DRM_ERROR("Invalid crtc %d\n", crtc); |
681 | return -EINVAL; | |
682 | } | |
683 | ||
fb98257a | 684 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
7ed220d7 | 685 | rdev->irq.crtc_vblank_int[crtc] = true; |
fb98257a CK |
686 | r = radeon_irq_set(rdev); |
687 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); | |
688 | return r; | |
771fe6b9 JG |
689 | } |
690 | ||
f482a141 AD |
691 | /** |
692 | * radeon_disable_vblank_kms - disable vblank interrupt | |
693 | * | |
694 | * @dev: drm dev pointer | |
695 | * @crtc: crtc to disable vblank interrupt for | |
696 | * | |
697 | * Disable the interrupt on the requested crtc (all asics). | |
698 | */ | |
771fe6b9 JG |
699 | void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) |
700 | { | |
7ed220d7 | 701 | struct radeon_device *rdev = dev->dev_private; |
fb98257a | 702 | unsigned long irqflags; |
7ed220d7 | 703 | |
9c950a43 | 704 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
705 | DRM_ERROR("Invalid crtc %d\n", crtc); |
706 | return; | |
707 | } | |
708 | ||
fb98257a | 709 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
7ed220d7 | 710 | rdev->irq.crtc_vblank_int[crtc] = false; |
7ed220d7 | 711 | radeon_irq_set(rdev); |
fb98257a | 712 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
771fe6b9 JG |
713 | } |
714 | ||
f482a141 AD |
715 | /** |
716 | * radeon_get_vblank_timestamp_kms - get vblank timestamp | |
717 | * | |
718 | * @dev: drm dev pointer | |
719 | * @crtc: crtc to get the timestamp for | |
720 | * @max_error: max error | |
721 | * @vblank_time: time value | |
722 | * @flags: flags passed to the driver | |
723 | * | |
724 | * Gets the timestamp on the requested crtc based on the | |
725 | * scanout position. (all asics). | |
726 | * Returns postive status flags on success, negative error on failure. | |
727 | */ | |
f5a80209 MK |
728 | int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, |
729 | int *max_error, | |
730 | struct timeval *vblank_time, | |
731 | unsigned flags) | |
732 | { | |
733 | struct drm_crtc *drmcrtc; | |
734 | struct radeon_device *rdev = dev->dev_private; | |
735 | ||
736 | if (crtc < 0 || crtc >= dev->num_crtcs) { | |
737 | DRM_ERROR("Invalid crtc %d\n", crtc); | |
738 | return -EINVAL; | |
739 | } | |
740 | ||
741 | /* Get associated drm_crtc: */ | |
742 | drmcrtc = &rdev->mode_info.crtcs[crtc]->base; | |
743 | ||
744 | /* Helper routine in DRM core does all the work: */ | |
745 | return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, | |
746 | vblank_time, flags, | |
7da903ef | 747 | drmcrtc, &drmcrtc->hwmode); |
f5a80209 | 748 | } |
771fe6b9 | 749 | |
771fe6b9 | 750 | #define KMS_INVALID_IOCTL(name) \ |
f6e2e407 RK |
751 | static int name(struct drm_device *dev, void *data, struct drm_file \ |
752 | *file_priv) \ | |
771fe6b9 JG |
753 | { \ |
754 | DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ | |
755 | return -EINVAL; \ | |
756 | } | |
757 | ||
758 | /* | |
759 | * All these ioctls are invalid in kms world. | |
760 | */ | |
761 | KMS_INVALID_IOCTL(radeon_cp_init_kms) | |
762 | KMS_INVALID_IOCTL(radeon_cp_start_kms) | |
763 | KMS_INVALID_IOCTL(radeon_cp_stop_kms) | |
764 | KMS_INVALID_IOCTL(radeon_cp_reset_kms) | |
765 | KMS_INVALID_IOCTL(radeon_cp_idle_kms) | |
766 | KMS_INVALID_IOCTL(radeon_cp_resume_kms) | |
767 | KMS_INVALID_IOCTL(radeon_engine_reset_kms) | |
768 | KMS_INVALID_IOCTL(radeon_fullscreen_kms) | |
769 | KMS_INVALID_IOCTL(radeon_cp_swap_kms) | |
770 | KMS_INVALID_IOCTL(radeon_cp_clear_kms) | |
771 | KMS_INVALID_IOCTL(radeon_cp_vertex_kms) | |
772 | KMS_INVALID_IOCTL(radeon_cp_indices_kms) | |
773 | KMS_INVALID_IOCTL(radeon_cp_texture_kms) | |
774 | KMS_INVALID_IOCTL(radeon_cp_stipple_kms) | |
775 | KMS_INVALID_IOCTL(radeon_cp_indirect_kms) | |
776 | KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) | |
777 | KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) | |
778 | KMS_INVALID_IOCTL(radeon_cp_getparam_kms) | |
779 | KMS_INVALID_IOCTL(radeon_cp_flip_kms) | |
780 | KMS_INVALID_IOCTL(radeon_mem_alloc_kms) | |
781 | KMS_INVALID_IOCTL(radeon_mem_free_kms) | |
782 | KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) | |
783 | KMS_INVALID_IOCTL(radeon_irq_emit_kms) | |
784 | KMS_INVALID_IOCTL(radeon_irq_wait_kms) | |
785 | KMS_INVALID_IOCTL(radeon_cp_setparam_kms) | |
786 | KMS_INVALID_IOCTL(radeon_surface_alloc_kms) | |
787 | KMS_INVALID_IOCTL(radeon_surface_free_kms) | |
788 | ||
789 | ||
baa70943 | 790 | const struct drm_ioctl_desc radeon_ioctls_kms[] = { |
1b2f1489 DA |
791 | DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
792 | DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
793 | DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
794 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
795 | DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), | |
796 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), | |
797 | DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), | |
798 | DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), | |
799 | DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), | |
800 | DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), | |
801 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), | |
802 | DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), | |
803 | DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), | |
804 | DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), | |
805 | DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
806 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), | |
807 | DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), | |
808 | DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), | |
809 | DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), | |
810 | DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), | |
811 | DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), | |
812 | DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
813 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), | |
814 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), | |
815 | DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), | |
816 | DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), | |
817 | DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), | |
771fe6b9 | 818 | /* KMS */ |
f33bcab9 CK |
819 | DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
820 | DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
821 | DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
822 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1b2f1489 DA |
823 | DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), |
824 | DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
f33bcab9 CK |
825 | DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
826 | DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
827 | DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
828 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
829 | DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
830 | DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
831 | DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
bda72d58 | 832 | DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
771fe6b9 JG |
833 | }; |
834 | int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); |