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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include "drmP.h" | |
27 | #include "radeon_drm.h" | |
28 | #include "radeon.h" | |
40bacf16 | 29 | #include "atom.h" |
771fe6b9 JG |
30 | |
31 | /** | |
32 | * radeon_ddc_probe | |
33 | * | |
34 | */ | |
35 | bool radeon_ddc_probe(struct radeon_connector *radeon_connector) | |
36 | { | |
37 | u8 out_buf[] = { 0x0, 0x0}; | |
38 | u8 buf[2]; | |
39 | int ret; | |
40 | struct i2c_msg msgs[] = { | |
41 | { | |
42 | .addr = 0x50, | |
43 | .flags = 0, | |
44 | .len = 1, | |
45 | .buf = out_buf, | |
46 | }, | |
47 | { | |
48 | .addr = 0x50, | |
49 | .flags = I2C_M_RD, | |
50 | .len = 1, | |
51 | .buf = buf, | |
52 | } | |
53 | }; | |
54 | ||
26b5bc98 AD |
55 | /* on hw with routers, select right port */ |
56 | if (radeon_connector->router.valid) | |
57 | radeon_router_select_port(radeon_connector); | |
58 | ||
771fe6b9 JG |
59 | ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); |
60 | if (ret == 2) | |
61 | return true; | |
62 | ||
63 | return false; | |
64 | } | |
65 | ||
ac1aade6 | 66 | /* bit banging i2c */ |
771fe6b9 | 67 | |
5a6f98f5 | 68 | static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state) |
771fe6b9 | 69 | { |
ab1e9ea0 AD |
70 | struct radeon_device *rdev = i2c->dev->dev_private; |
71 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
771fe6b9 | 72 | uint32_t temp; |
771fe6b9 JG |
73 | |
74 | /* RV410 appears to have a bug where the hw i2c in reset | |
75 | * holds the i2c port in a bad state - switch hw i2c away before | |
76 | * doing DDC - do this for all r200s/r300s/r400s for safety sake | |
77 | */ | |
6a93cb25 AD |
78 | if (rec->hw_capable) { |
79 | if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { | |
40bacf16 AD |
80 | u32 reg; |
81 | ||
82 | if (rdev->family >= CHIP_RV350) | |
83 | reg = RADEON_GPIO_MONID; | |
84 | else if ((rdev->family == CHIP_R300) || | |
85 | (rdev->family == CHIP_R350)) | |
86 | reg = RADEON_GPIO_DVI_DDC; | |
87 | else | |
88 | reg = RADEON_GPIO_CRT2_DDC; | |
89 | ||
90 | mutex_lock(&rdev->dc_hw_i2c_mutex); | |
91 | if (rec->a_clk_reg == reg) { | |
6a93cb25 AD |
92 | WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | |
93 | R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); | |
94 | } else { | |
95 | WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | | |
96 | R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); | |
97 | } | |
40bacf16 | 98 | mutex_unlock(&rdev->dc_hw_i2c_mutex); |
771fe6b9 JG |
99 | } |
100 | } | |
771fe6b9 | 101 | |
9b9fe724 AD |
102 | /* clear the output pin values */ |
103 | temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; | |
104 | WREG32(rec->a_clk_reg, temp); | |
105 | ||
106 | temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; | |
107 | WREG32(rec->a_data_reg, temp); | |
108 | ||
6a93cb25 AD |
109 | /* set the pins to input */ |
110 | temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; | |
111 | WREG32(rec->en_clk_reg, temp); | |
112 | ||
113 | temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; | |
114 | WREG32(rec->en_data_reg, temp); | |
9b9fe724 AD |
115 | |
116 | /* mask the gpio pins for software use */ | |
771fe6b9 JG |
117 | temp = RREG32(rec->mask_clk_reg); |
118 | if (lock_state) | |
119 | temp |= rec->mask_clk_mask; | |
120 | else | |
121 | temp &= ~rec->mask_clk_mask; | |
122 | WREG32(rec->mask_clk_reg, temp); | |
123 | temp = RREG32(rec->mask_clk_reg); | |
124 | ||
125 | temp = RREG32(rec->mask_data_reg); | |
126 | if (lock_state) | |
127 | temp |= rec->mask_data_mask; | |
128 | else | |
129 | temp &= ~rec->mask_data_mask; | |
130 | WREG32(rec->mask_data_reg, temp); | |
131 | temp = RREG32(rec->mask_data_reg); | |
132 | } | |
133 | ||
134 | static int get_clock(void *i2c_priv) | |
135 | { | |
136 | struct radeon_i2c_chan *i2c = i2c_priv; | |
137 | struct radeon_device *rdev = i2c->dev->dev_private; | |
138 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
139 | uint32_t val; | |
140 | ||
9b9fe724 AD |
141 | /* read the value off the pin */ |
142 | val = RREG32(rec->y_clk_reg); | |
143 | val &= rec->y_clk_mask; | |
771fe6b9 JG |
144 | |
145 | return (val != 0); | |
146 | } | |
147 | ||
148 | ||
149 | static int get_data(void *i2c_priv) | |
150 | { | |
151 | struct radeon_i2c_chan *i2c = i2c_priv; | |
152 | struct radeon_device *rdev = i2c->dev->dev_private; | |
153 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
154 | uint32_t val; | |
155 | ||
9b9fe724 AD |
156 | /* read the value off the pin */ |
157 | val = RREG32(rec->y_data_reg); | |
158 | val &= rec->y_data_mask; | |
159 | ||
771fe6b9 JG |
160 | return (val != 0); |
161 | } | |
162 | ||
163 | static void set_clock(void *i2c_priv, int clock) | |
164 | { | |
165 | struct radeon_i2c_chan *i2c = i2c_priv; | |
166 | struct radeon_device *rdev = i2c->dev->dev_private; | |
167 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
168 | uint32_t val; | |
169 | ||
9b9fe724 AD |
170 | /* set pin direction */ |
171 | val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; | |
172 | val |= clock ? 0 : rec->en_clk_mask; | |
173 | WREG32(rec->en_clk_reg, val); | |
771fe6b9 JG |
174 | } |
175 | ||
176 | static void set_data(void *i2c_priv, int data) | |
177 | { | |
178 | struct radeon_i2c_chan *i2c = i2c_priv; | |
179 | struct radeon_device *rdev = i2c->dev->dev_private; | |
180 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
181 | uint32_t val; | |
182 | ||
9b9fe724 AD |
183 | /* set pin direction */ |
184 | val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; | |
185 | val |= data ? 0 : rec->en_data_mask; | |
186 | WREG32(rec->en_data_reg, val); | |
771fe6b9 JG |
187 | } |
188 | ||
ac1aade6 AD |
189 | static int pre_xfer(struct i2c_adapter *i2c_adap) |
190 | { | |
191 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |
192 | ||
193 | radeon_i2c_do_lock(i2c, 1); | |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
198 | static void post_xfer(struct i2c_adapter *i2c_adap) | |
199 | { | |
200 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |
201 | ||
202 | radeon_i2c_do_lock(i2c, 0); | |
203 | } | |
204 | ||
205 | /* hw i2c */ | |
206 | ||
9dad76e8 AD |
207 | static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) |
208 | { | |
9dad76e8 AD |
209 | u32 sclk = radeon_get_engine_clock(rdev); |
210 | u32 prescale = 0; | |
96a4c8d5 AD |
211 | u32 nm; |
212 | u8 n, m, loop; | |
9dad76e8 AD |
213 | int i2c_clock; |
214 | ||
215 | switch (rdev->family) { | |
216 | case CHIP_R100: | |
217 | case CHIP_RV100: | |
218 | case CHIP_RS100: | |
219 | case CHIP_RV200: | |
220 | case CHIP_RS200: | |
221 | case CHIP_R200: | |
222 | case CHIP_RV250: | |
223 | case CHIP_RS300: | |
224 | case CHIP_RV280: | |
225 | case CHIP_R300: | |
226 | case CHIP_R350: | |
227 | case CHIP_RV350: | |
96a4c8d5 AD |
228 | i2c_clock = 60; |
229 | nm = (sclk * 10) / (i2c_clock * 4); | |
9dad76e8 | 230 | for (loop = 1; loop < 255; loop++) { |
96a4c8d5 | 231 | if ((nm / loop) < loop) |
9dad76e8 AD |
232 | break; |
233 | } | |
96a4c8d5 AD |
234 | n = loop - 1; |
235 | m = loop - 2; | |
236 | prescale = m | (n << 8); | |
9dad76e8 AD |
237 | break; |
238 | case CHIP_RV380: | |
239 | case CHIP_RS400: | |
240 | case CHIP_RS480: | |
241 | case CHIP_R420: | |
242 | case CHIP_R423: | |
243 | case CHIP_RV410: | |
9dad76e8 AD |
244 | prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; |
245 | break; | |
246 | case CHIP_RS600: | |
247 | case CHIP_RS690: | |
248 | case CHIP_RS740: | |
249 | /* todo */ | |
250 | break; | |
251 | case CHIP_RV515: | |
252 | case CHIP_R520: | |
253 | case CHIP_RV530: | |
254 | case CHIP_RV560: | |
255 | case CHIP_RV570: | |
256 | case CHIP_R580: | |
257 | i2c_clock = 50; | |
9dad76e8 AD |
258 | if (rdev->family == CHIP_R520) |
259 | prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); | |
260 | else | |
261 | prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; | |
262 | break; | |
263 | case CHIP_R600: | |
264 | case CHIP_RV610: | |
265 | case CHIP_RV630: | |
266 | case CHIP_RV670: | |
267 | /* todo */ | |
268 | break; | |
269 | case CHIP_RV620: | |
270 | case CHIP_RV635: | |
271 | case CHIP_RS780: | |
272 | case CHIP_RS880: | |
273 | case CHIP_RV770: | |
274 | case CHIP_RV730: | |
275 | case CHIP_RV710: | |
276 | case CHIP_RV740: | |
277 | /* todo */ | |
278 | break; | |
4c36b678 AD |
279 | case CHIP_CEDAR: |
280 | case CHIP_REDWOOD: | |
281 | case CHIP_JUNIPER: | |
282 | case CHIP_CYPRESS: | |
283 | case CHIP_HEMLOCK: | |
284 | /* todo */ | |
285 | break; | |
9dad76e8 AD |
286 | default: |
287 | DRM_ERROR("i2c: unhandled radeon chip\n"); | |
288 | break; | |
289 | } | |
290 | return prescale; | |
291 | } | |
292 | ||
293 | ||
40bacf16 AD |
294 | /* hw i2c engine for r1xx-4xx hardware |
295 | * hw can buffer up to 15 bytes | |
296 | */ | |
297 | static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, | |
298 | struct i2c_msg *msgs, int num) | |
299 | { | |
300 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |
301 | struct radeon_device *rdev = i2c->dev->dev_private; | |
302 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
303 | struct i2c_msg *p; | |
304 | int i, j, k, ret = num; | |
9dad76e8 | 305 | u32 prescale; |
40bacf16 AD |
306 | u32 i2c_cntl_0, i2c_cntl_1, i2c_data; |
307 | u32 tmp, reg; | |
308 | ||
309 | mutex_lock(&rdev->dc_hw_i2c_mutex); | |
57fcab62 AD |
310 | /* take the pm lock since we need a constant sclk */ |
311 | mutex_lock(&rdev->pm.mutex); | |
312 | ||
9dad76e8 | 313 | prescale = radeon_get_i2c_prescale(rdev); |
40bacf16 AD |
314 | |
315 | reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | | |
ae08819c | 316 | RADEON_I2C_DRIVE_EN | |
40bacf16 AD |
317 | RADEON_I2C_START | |
318 | RADEON_I2C_STOP | | |
319 | RADEON_I2C_GO); | |
320 | ||
321 | if (rdev->is_atom_bios) { | |
322 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); | |
323 | WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); | |
324 | } | |
325 | ||
326 | if (rec->mm_i2c) { | |
327 | i2c_cntl_0 = RADEON_I2C_CNTL_0; | |
328 | i2c_cntl_1 = RADEON_I2C_CNTL_1; | |
329 | i2c_data = RADEON_I2C_DATA; | |
330 | } else { | |
331 | i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; | |
332 | i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; | |
333 | i2c_data = RADEON_DVI_I2C_DATA; | |
334 | ||
335 | switch (rdev->family) { | |
336 | case CHIP_R100: | |
337 | case CHIP_RV100: | |
338 | case CHIP_RS100: | |
339 | case CHIP_RV200: | |
340 | case CHIP_RS200: | |
341 | case CHIP_RS300: | |
342 | switch (rec->mask_clk_reg) { | |
343 | case RADEON_GPIO_DVI_DDC: | |
344 | /* no gpio select bit */ | |
345 | break; | |
346 | default: | |
347 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
348 | ret = -EINVAL; | |
349 | goto done; | |
350 | } | |
351 | break; | |
352 | case CHIP_R200: | |
353 | /* only bit 4 on r200 */ | |
354 | switch (rec->mask_clk_reg) { | |
355 | case RADEON_GPIO_DVI_DDC: | |
356 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); | |
357 | break; | |
358 | case RADEON_GPIO_MONID: | |
359 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); | |
360 | break; | |
361 | default: | |
362 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
363 | ret = -EINVAL; | |
364 | goto done; | |
365 | } | |
366 | break; | |
367 | case CHIP_RV250: | |
368 | case CHIP_RV280: | |
369 | /* bits 3 and 4 */ | |
370 | switch (rec->mask_clk_reg) { | |
371 | case RADEON_GPIO_DVI_DDC: | |
372 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); | |
373 | break; | |
374 | case RADEON_GPIO_VGA_DDC: | |
375 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); | |
376 | break; | |
377 | case RADEON_GPIO_CRT2_DDC: | |
378 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); | |
379 | break; | |
380 | default: | |
381 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
382 | ret = -EINVAL; | |
383 | goto done; | |
384 | } | |
385 | break; | |
386 | case CHIP_R300: | |
387 | case CHIP_R350: | |
388 | /* only bit 4 on r300/r350 */ | |
389 | switch (rec->mask_clk_reg) { | |
390 | case RADEON_GPIO_VGA_DDC: | |
391 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); | |
392 | break; | |
393 | case RADEON_GPIO_DVI_DDC: | |
394 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); | |
395 | break; | |
396 | default: | |
397 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
398 | ret = -EINVAL; | |
399 | goto done; | |
400 | } | |
401 | break; | |
402 | case CHIP_RV350: | |
403 | case CHIP_RV380: | |
404 | case CHIP_R420: | |
405 | case CHIP_R423: | |
406 | case CHIP_RV410: | |
407 | case CHIP_RS400: | |
408 | case CHIP_RS480: | |
409 | /* bits 3 and 4 */ | |
410 | switch (rec->mask_clk_reg) { | |
411 | case RADEON_GPIO_VGA_DDC: | |
412 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); | |
413 | break; | |
414 | case RADEON_GPIO_DVI_DDC: | |
415 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); | |
416 | break; | |
417 | case RADEON_GPIO_MONID: | |
418 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); | |
419 | break; | |
420 | default: | |
421 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
422 | ret = -EINVAL; | |
423 | goto done; | |
424 | } | |
425 | break; | |
426 | default: | |
427 | DRM_ERROR("unsupported asic\n"); | |
428 | ret = -EINVAL; | |
429 | goto done; | |
430 | break; | |
431 | } | |
432 | } | |
433 | ||
434 | /* check for bus probe */ | |
435 | p = &msgs[0]; | |
436 | if ((num == 1) && (p->len == 0)) { | |
437 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | | |
438 | RADEON_I2C_NACK | | |
439 | RADEON_I2C_HALT | | |
440 | RADEON_I2C_SOFT_RST)); | |
441 | WREG32(i2c_data, (p->addr << 1) & 0xff); | |
442 | WREG32(i2c_data, 0); | |
443 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | | |
444 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | | |
445 | RADEON_I2C_EN | | |
446 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); | |
447 | WREG32(i2c_cntl_0, reg); | |
448 | for (k = 0; k < 32; k++) { | |
449 | udelay(10); | |
450 | tmp = RREG32(i2c_cntl_0); | |
451 | if (tmp & RADEON_I2C_GO) | |
452 | continue; | |
453 | tmp = RREG32(i2c_cntl_0); | |
454 | if (tmp & RADEON_I2C_DONE) | |
455 | break; | |
456 | else { | |
457 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); | |
458 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); | |
459 | ret = -EIO; | |
460 | goto done; | |
461 | } | |
462 | } | |
463 | goto done; | |
464 | } | |
465 | ||
466 | for (i = 0; i < num; i++) { | |
467 | p = &msgs[i]; | |
468 | for (j = 0; j < p->len; j++) { | |
469 | if (p->flags & I2C_M_RD) { | |
470 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | | |
471 | RADEON_I2C_NACK | | |
472 | RADEON_I2C_HALT | | |
473 | RADEON_I2C_SOFT_RST)); | |
474 | WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); | |
475 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | | |
476 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | | |
477 | RADEON_I2C_EN | | |
478 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); | |
479 | WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); | |
480 | for (k = 0; k < 32; k++) { | |
481 | udelay(10); | |
482 | tmp = RREG32(i2c_cntl_0); | |
483 | if (tmp & RADEON_I2C_GO) | |
484 | continue; | |
485 | tmp = RREG32(i2c_cntl_0); | |
486 | if (tmp & RADEON_I2C_DONE) | |
487 | break; | |
488 | else { | |
489 | DRM_DEBUG("i2c read error 0x%08x\n", tmp); | |
490 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); | |
491 | ret = -EIO; | |
492 | goto done; | |
493 | } | |
494 | } | |
495 | p->buf[j] = RREG32(i2c_data) & 0xff; | |
496 | } else { | |
497 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | | |
498 | RADEON_I2C_NACK | | |
499 | RADEON_I2C_HALT | | |
500 | RADEON_I2C_SOFT_RST)); | |
501 | WREG32(i2c_data, (p->addr << 1) & 0xff); | |
502 | WREG32(i2c_data, p->buf[j]); | |
503 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | | |
504 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | | |
505 | RADEON_I2C_EN | | |
506 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); | |
507 | WREG32(i2c_cntl_0, reg); | |
508 | for (k = 0; k < 32; k++) { | |
509 | udelay(10); | |
510 | tmp = RREG32(i2c_cntl_0); | |
511 | if (tmp & RADEON_I2C_GO) | |
512 | continue; | |
513 | tmp = RREG32(i2c_cntl_0); | |
514 | if (tmp & RADEON_I2C_DONE) | |
515 | break; | |
516 | else { | |
517 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); | |
518 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); | |
519 | ret = -EIO; | |
520 | goto done; | |
521 | } | |
522 | } | |
523 | } | |
524 | } | |
525 | } | |
526 | ||
527 | done: | |
528 | WREG32(i2c_cntl_0, 0); | |
529 | WREG32(i2c_cntl_1, 0); | |
530 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | | |
531 | RADEON_I2C_NACK | | |
532 | RADEON_I2C_HALT | | |
533 | RADEON_I2C_SOFT_RST)); | |
534 | ||
535 | if (rdev->is_atom_bios) { | |
536 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); | |
537 | tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; | |
538 | WREG32(RADEON_BIOS_6_SCRATCH, tmp); | |
539 | } | |
540 | ||
57fcab62 | 541 | mutex_unlock(&rdev->pm.mutex); |
40bacf16 AD |
542 | mutex_unlock(&rdev->dc_hw_i2c_mutex); |
543 | ||
544 | return ret; | |
545 | } | |
546 | ||
547 | /* hw i2c engine for r5xx hardware | |
548 | * hw can buffer up to 15 bytes | |
549 | */ | |
550 | static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, | |
551 | struct i2c_msg *msgs, int num) | |
552 | { | |
553 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |
554 | struct radeon_device *rdev = i2c->dev->dev_private; | |
555 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
556 | struct i2c_msg *p; | |
40bacf16 | 557 | int i, j, remaining, current_count, buffer_offset, ret = num; |
9dad76e8 | 558 | u32 prescale; |
40bacf16 AD |
559 | u32 tmp, reg; |
560 | u32 saved1, saved2; | |
561 | ||
562 | mutex_lock(&rdev->dc_hw_i2c_mutex); | |
57fcab62 AD |
563 | /* take the pm lock since we need a constant sclk */ |
564 | mutex_lock(&rdev->pm.mutex); | |
565 | ||
9dad76e8 | 566 | prescale = radeon_get_i2c_prescale(rdev); |
40bacf16 AD |
567 | |
568 | /* clear gpio mask bits */ | |
569 | tmp = RREG32(rec->mask_clk_reg); | |
570 | tmp &= ~rec->mask_clk_mask; | |
571 | WREG32(rec->mask_clk_reg, tmp); | |
572 | tmp = RREG32(rec->mask_clk_reg); | |
573 | ||
574 | tmp = RREG32(rec->mask_data_reg); | |
575 | tmp &= ~rec->mask_data_mask; | |
576 | WREG32(rec->mask_data_reg, tmp); | |
577 | tmp = RREG32(rec->mask_data_reg); | |
578 | ||
579 | /* clear pin values */ | |
580 | tmp = RREG32(rec->a_clk_reg); | |
581 | tmp &= ~rec->a_clk_mask; | |
582 | WREG32(rec->a_clk_reg, tmp); | |
583 | tmp = RREG32(rec->a_clk_reg); | |
584 | ||
585 | tmp = RREG32(rec->a_data_reg); | |
586 | tmp &= ~rec->a_data_mask; | |
587 | WREG32(rec->a_data_reg, tmp); | |
588 | tmp = RREG32(rec->a_data_reg); | |
589 | ||
590 | /* set the pins to input */ | |
591 | tmp = RREG32(rec->en_clk_reg); | |
592 | tmp &= ~rec->en_clk_mask; | |
593 | WREG32(rec->en_clk_reg, tmp); | |
594 | tmp = RREG32(rec->en_clk_reg); | |
595 | ||
596 | tmp = RREG32(rec->en_data_reg); | |
597 | tmp &= ~rec->en_data_mask; | |
598 | WREG32(rec->en_data_reg, tmp); | |
599 | tmp = RREG32(rec->en_data_reg); | |
600 | ||
601 | /* */ | |
602 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); | |
603 | WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); | |
604 | saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); | |
605 | saved2 = RREG32(0x494); | |
606 | WREG32(0x494, saved2 | 0x1); | |
607 | ||
608 | WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); | |
609 | for (i = 0; i < 50; i++) { | |
610 | udelay(1); | |
611 | if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) | |
612 | break; | |
613 | } | |
614 | if (i == 50) { | |
615 | DRM_ERROR("failed to get i2c bus\n"); | |
616 | ret = -EBUSY; | |
617 | goto done; | |
618 | } | |
619 | ||
40bacf16 AD |
620 | reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; |
621 | switch (rec->mask_clk_reg) { | |
622 | case AVIVO_DC_GPIO_DDC1_MASK: | |
623 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); | |
624 | break; | |
625 | case AVIVO_DC_GPIO_DDC2_MASK: | |
626 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); | |
627 | break; | |
628 | case AVIVO_DC_GPIO_DDC3_MASK: | |
629 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); | |
630 | break; | |
631 | default: | |
632 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
633 | ret = -EINVAL; | |
634 | goto done; | |
635 | } | |
636 | ||
637 | /* check for bus probe */ | |
638 | p = &msgs[0]; | |
639 | if ((num == 1) && (p->len == 0)) { | |
640 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | | |
641 | AVIVO_DC_I2C_NACK | | |
642 | AVIVO_DC_I2C_HALT)); | |
643 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); | |
644 | udelay(1); | |
645 | WREG32(AVIVO_DC_I2C_RESET, 0); | |
646 | ||
647 | WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); | |
648 | WREG32(AVIVO_DC_I2C_DATA, 0); | |
649 | ||
650 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); | |
651 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | | |
652 | AVIVO_DC_I2C_DATA_COUNT(1) | | |
653 | (prescale << 16))); | |
654 | WREG32(AVIVO_DC_I2C_CONTROL1, reg); | |
655 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); | |
656 | for (j = 0; j < 200; j++) { | |
657 | udelay(50); | |
658 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
659 | if (tmp & AVIVO_DC_I2C_GO) | |
660 | continue; | |
661 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
662 | if (tmp & AVIVO_DC_I2C_DONE) | |
663 | break; | |
664 | else { | |
665 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); | |
666 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); | |
667 | ret = -EIO; | |
668 | goto done; | |
669 | } | |
670 | } | |
671 | goto done; | |
672 | } | |
673 | ||
674 | for (i = 0; i < num; i++) { | |
675 | p = &msgs[i]; | |
676 | remaining = p->len; | |
677 | buffer_offset = 0; | |
678 | if (p->flags & I2C_M_RD) { | |
679 | while (remaining) { | |
680 | if (remaining > 15) | |
681 | current_count = 15; | |
682 | else | |
683 | current_count = remaining; | |
684 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | | |
685 | AVIVO_DC_I2C_NACK | | |
686 | AVIVO_DC_I2C_HALT)); | |
687 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); | |
688 | udelay(1); | |
689 | WREG32(AVIVO_DC_I2C_RESET, 0); | |
690 | ||
691 | WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); | |
692 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); | |
693 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | | |
694 | AVIVO_DC_I2C_DATA_COUNT(current_count) | | |
695 | (prescale << 16))); | |
696 | WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); | |
697 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); | |
698 | for (j = 0; j < 200; j++) { | |
699 | udelay(50); | |
700 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
701 | if (tmp & AVIVO_DC_I2C_GO) | |
702 | continue; | |
703 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
704 | if (tmp & AVIVO_DC_I2C_DONE) | |
705 | break; | |
706 | else { | |
707 | DRM_DEBUG("i2c read error 0x%08x\n", tmp); | |
708 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); | |
709 | ret = -EIO; | |
710 | goto done; | |
711 | } | |
712 | } | |
713 | for (j = 0; j < current_count; j++) | |
714 | p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; | |
715 | remaining -= current_count; | |
716 | buffer_offset += current_count; | |
717 | } | |
718 | } else { | |
719 | while (remaining) { | |
720 | if (remaining > 15) | |
721 | current_count = 15; | |
722 | else | |
723 | current_count = remaining; | |
724 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | | |
725 | AVIVO_DC_I2C_NACK | | |
726 | AVIVO_DC_I2C_HALT)); | |
727 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); | |
728 | udelay(1); | |
729 | WREG32(AVIVO_DC_I2C_RESET, 0); | |
730 | ||
731 | WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); | |
732 | for (j = 0; j < current_count; j++) | |
733 | WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); | |
734 | ||
735 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); | |
736 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | | |
737 | AVIVO_DC_I2C_DATA_COUNT(current_count) | | |
738 | (prescale << 16))); | |
739 | WREG32(AVIVO_DC_I2C_CONTROL1, reg); | |
740 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); | |
741 | for (j = 0; j < 200; j++) { | |
742 | udelay(50); | |
743 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
744 | if (tmp & AVIVO_DC_I2C_GO) | |
745 | continue; | |
746 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
747 | if (tmp & AVIVO_DC_I2C_DONE) | |
748 | break; | |
749 | else { | |
750 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); | |
751 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); | |
752 | ret = -EIO; | |
753 | goto done; | |
754 | } | |
755 | } | |
756 | remaining -= current_count; | |
757 | buffer_offset += current_count; | |
758 | } | |
759 | } | |
760 | } | |
761 | ||
762 | done: | |
763 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | | |
764 | AVIVO_DC_I2C_NACK | | |
765 | AVIVO_DC_I2C_HALT)); | |
766 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); | |
767 | udelay(1); | |
768 | WREG32(AVIVO_DC_I2C_RESET, 0); | |
769 | ||
770 | WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); | |
771 | WREG32(AVIVO_DC_I2C_CONTROL1, saved1); | |
772 | WREG32(0x494, saved2); | |
773 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); | |
774 | tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; | |
775 | WREG32(RADEON_BIOS_6_SCRATCH, tmp); | |
776 | ||
57fcab62 | 777 | mutex_unlock(&rdev->pm.mutex); |
40bacf16 AD |
778 | mutex_unlock(&rdev->dc_hw_i2c_mutex); |
779 | ||
780 | return ret; | |
781 | } | |
782 | ||
ac1aade6 | 783 | static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, |
40bacf16 | 784 | struct i2c_msg *msgs, int num) |
40bacf16 AD |
785 | { |
786 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |
787 | struct radeon_device *rdev = i2c->dev->dev_private; | |
788 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
ac1aade6 | 789 | int ret = 0; |
40bacf16 AD |
790 | |
791 | switch (rdev->family) { | |
792 | case CHIP_R100: | |
793 | case CHIP_RV100: | |
794 | case CHIP_RS100: | |
795 | case CHIP_RV200: | |
796 | case CHIP_RS200: | |
797 | case CHIP_R200: | |
798 | case CHIP_RV250: | |
799 | case CHIP_RS300: | |
800 | case CHIP_RV280: | |
801 | case CHIP_R300: | |
802 | case CHIP_R350: | |
803 | case CHIP_RV350: | |
804 | case CHIP_RV380: | |
805 | case CHIP_R420: | |
806 | case CHIP_R423: | |
807 | case CHIP_RV410: | |
808 | case CHIP_RS400: | |
809 | case CHIP_RS480: | |
ac1aade6 | 810 | ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); |
40bacf16 AD |
811 | break; |
812 | case CHIP_RS600: | |
813 | case CHIP_RS690: | |
814 | case CHIP_RS740: | |
815 | /* XXX fill in hw i2c implementation */ | |
40bacf16 AD |
816 | break; |
817 | case CHIP_RV515: | |
818 | case CHIP_R520: | |
819 | case CHIP_RV530: | |
820 | case CHIP_RV560: | |
821 | case CHIP_RV570: | |
822 | case CHIP_R580: | |
ac1aade6 AD |
823 | if (rec->mm_i2c) |
824 | ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); | |
825 | else | |
826 | ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); | |
40bacf16 AD |
827 | break; |
828 | case CHIP_R600: | |
829 | case CHIP_RV610: | |
830 | case CHIP_RV630: | |
831 | case CHIP_RV670: | |
832 | /* XXX fill in hw i2c implementation */ | |
40bacf16 AD |
833 | break; |
834 | case CHIP_RV620: | |
835 | case CHIP_RV635: | |
836 | case CHIP_RS780: | |
837 | case CHIP_RS880: | |
838 | case CHIP_RV770: | |
839 | case CHIP_RV730: | |
840 | case CHIP_RV710: | |
841 | case CHIP_RV740: | |
842 | /* XXX fill in hw i2c implementation */ | |
40bacf16 | 843 | break; |
4c36b678 AD |
844 | case CHIP_CEDAR: |
845 | case CHIP_REDWOOD: | |
846 | case CHIP_JUNIPER: | |
847 | case CHIP_CYPRESS: | |
848 | case CHIP_HEMLOCK: | |
849 | /* XXX fill in hw i2c implementation */ | |
4c36b678 | 850 | break; |
40bacf16 AD |
851 | default: |
852 | DRM_ERROR("i2c: unhandled radeon chip\n"); | |
853 | ret = -EIO; | |
854 | break; | |
855 | } | |
856 | ||
857 | return ret; | |
858 | } | |
859 | ||
ac1aade6 | 860 | static u32 radeon_hw_i2c_func(struct i2c_adapter *adap) |
5a6f98f5 AD |
861 | { |
862 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
863 | } | |
864 | ||
865 | static const struct i2c_algorithm radeon_i2c_algo = { | |
ac1aade6 AD |
866 | .master_xfer = radeon_hw_i2c_xfer, |
867 | .functionality = radeon_hw_i2c_func, | |
5a6f98f5 AD |
868 | }; |
869 | ||
771fe6b9 | 870 | struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
ab1e9ea0 AD |
871 | struct radeon_i2c_bus_rec *rec, |
872 | const char *name) | |
771fe6b9 | 873 | { |
ac1aade6 | 874 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
875 | struct radeon_i2c_chan *i2c; |
876 | int ret; | |
877 | ||
9a298b2a | 878 | i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); |
771fe6b9 JG |
879 | if (i2c == NULL) |
880 | return NULL; | |
881 | ||
40bacf16 | 882 | i2c->rec = *rec; |
5a6f98f5 | 883 | i2c->adapter.owner = THIS_MODULE; |
ac1aade6 | 884 | i2c->dev = dev; |
5a6f98f5 | 885 | i2c_set_adapdata(&i2c->adapter, i2c); |
e2b0a8e1 AD |
886 | if (rec->mm_i2c || |
887 | (rec->hw_capable && | |
888 | radeon_hw_i2c && | |
889 | ((rdev->family <= CHIP_RS480) || | |
890 | ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { | |
ac1aade6 AD |
891 | /* set the radeon hw i2c adapter */ |
892 | sprintf(i2c->adapter.name, "Radeon i2c hw bus %s", name); | |
893 | i2c->adapter.algo = &radeon_i2c_algo; | |
894 | ret = i2c_add_adapter(&i2c->adapter); | |
895 | if (ret) { | |
896 | DRM_ERROR("Failed to register hw i2c %s\n", name); | |
897 | goto out_free; | |
898 | } | |
899 | } else { | |
900 | /* set the radeon bit adapter */ | |
901 | sprintf(i2c->adapter.name, "Radeon i2c bit bus %s", name); | |
902 | i2c->adapter.algo_data = &i2c->algo.bit; | |
903 | i2c->algo.bit.pre_xfer = pre_xfer; | |
904 | i2c->algo.bit.post_xfer = post_xfer; | |
905 | i2c->algo.bit.setsda = set_data; | |
906 | i2c->algo.bit.setscl = set_clock; | |
907 | i2c->algo.bit.getsda = get_data; | |
908 | i2c->algo.bit.getscl = get_clock; | |
909 | i2c->algo.bit.udelay = 20; | |
910 | /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always | |
911 | * make this, 2 jiffies is a lot more reliable */ | |
912 | i2c->algo.bit.timeout = 2; | |
913 | i2c->algo.bit.data = i2c; | |
914 | ret = i2c_bit_add_bus(&i2c->adapter); | |
915 | if (ret) { | |
916 | DRM_ERROR("Failed to register bit i2c %s\n", name); | |
917 | goto out_free; | |
918 | } | |
771fe6b9 JG |
919 | } |
920 | ||
921 | return i2c; | |
922 | out_free: | |
9a298b2a | 923 | kfree(i2c); |
771fe6b9 JG |
924 | return NULL; |
925 | ||
926 | } | |
927 | ||
746c1aa4 | 928 | struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, |
6a93cb25 AD |
929 | struct radeon_i2c_bus_rec *rec, |
930 | const char *name) | |
746c1aa4 DA |
931 | { |
932 | struct radeon_i2c_chan *i2c; | |
933 | int ret; | |
934 | ||
935 | i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); | |
936 | if (i2c == NULL) | |
937 | return NULL; | |
938 | ||
6a93cb25 | 939 | i2c->rec = *rec; |
746c1aa4 DA |
940 | i2c->adapter.owner = THIS_MODULE; |
941 | i2c->dev = dev; | |
942 | i2c_set_adapdata(&i2c->adapter, i2c); | |
943 | i2c->adapter.algo_data = &i2c->algo.dp; | |
944 | i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch; | |
945 | i2c->algo.dp.address = 0; | |
946 | ret = i2c_dp_aux_add_bus(&i2c->adapter); | |
947 | if (ret) { | |
948 | DRM_INFO("Failed to register i2c %s\n", name); | |
949 | goto out_free; | |
950 | } | |
951 | ||
952 | return i2c; | |
953 | out_free: | |
954 | kfree(i2c); | |
955 | return NULL; | |
956 | ||
957 | } | |
958 | ||
771fe6b9 | 959 | void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) |
5a6f98f5 AD |
960 | { |
961 | if (!i2c) | |
962 | return; | |
771fe6b9 | 963 | i2c_del_adapter(&i2c->adapter); |
9a298b2a | 964 | kfree(i2c); |
771fe6b9 JG |
965 | } |
966 | ||
f376b94f AD |
967 | /* Add the default buses */ |
968 | void radeon_i2c_init(struct radeon_device *rdev) | |
969 | { | |
970 | if (rdev->is_atom_bios) | |
971 | radeon_atombios_i2c_init(rdev); | |
972 | else | |
973 | radeon_combios_i2c_init(rdev); | |
974 | } | |
975 | ||
976 | /* remove all the buses */ | |
977 | void radeon_i2c_fini(struct radeon_device *rdev) | |
978 | { | |
979 | int i; | |
980 | ||
981 | for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { | |
982 | if (rdev->i2c_bus[i]) { | |
983 | radeon_i2c_destroy(rdev->i2c_bus[i]); | |
984 | rdev->i2c_bus[i] = NULL; | |
985 | } | |
986 | } | |
987 | } | |
988 | ||
989 | /* Add additional buses */ | |
990 | void radeon_i2c_add(struct radeon_device *rdev, | |
991 | struct radeon_i2c_bus_rec *rec, | |
992 | const char *name) | |
993 | { | |
994 | struct drm_device *dev = rdev->ddev; | |
995 | int i; | |
996 | ||
997 | for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { | |
998 | if (!rdev->i2c_bus[i]) { | |
999 | rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); | |
1000 | return; | |
1001 | } | |
1002 | } | |
1003 | } | |
1004 | ||
1005 | /* looks up bus based on id */ | |
1006 | struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, | |
1007 | struct radeon_i2c_bus_rec *i2c_bus) | |
1008 | { | |
1009 | int i; | |
1010 | ||
1011 | for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { | |
1012 | if (rdev->i2c_bus[i] && | |
1013 | (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { | |
1014 | return rdev->i2c_bus[i]; | |
1015 | } | |
1016 | } | |
1017 | return NULL; | |
1018 | } | |
1019 | ||
771fe6b9 JG |
1020 | struct drm_encoder *radeon_best_encoder(struct drm_connector *connector) |
1021 | { | |
1022 | return NULL; | |
1023 | } | |
fcec570b | 1024 | |
5a6f98f5 AD |
1025 | void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
1026 | u8 slave_addr, | |
1027 | u8 addr, | |
1028 | u8 *val) | |
fcec570b AD |
1029 | { |
1030 | u8 out_buf[2]; | |
1031 | u8 in_buf[2]; | |
1032 | struct i2c_msg msgs[] = { | |
1033 | { | |
1034 | .addr = slave_addr, | |
1035 | .flags = 0, | |
1036 | .len = 1, | |
1037 | .buf = out_buf, | |
1038 | }, | |
1039 | { | |
1040 | .addr = slave_addr, | |
1041 | .flags = I2C_M_RD, | |
1042 | .len = 1, | |
1043 | .buf = in_buf, | |
1044 | } | |
1045 | }; | |
1046 | ||
1047 | out_buf[0] = addr; | |
1048 | out_buf[1] = 0; | |
1049 | ||
1050 | if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { | |
1051 | *val = in_buf[0]; | |
1052 | DRM_DEBUG("val = 0x%02x\n", *val); | |
1053 | } else { | |
1054 | DRM_ERROR("i2c 0x%02x 0x%02x read failed\n", | |
1055 | addr, *val); | |
1056 | } | |
1057 | } | |
1058 | ||
5a6f98f5 AD |
1059 | void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, |
1060 | u8 slave_addr, | |
1061 | u8 addr, | |
1062 | u8 val) | |
fcec570b AD |
1063 | { |
1064 | uint8_t out_buf[2]; | |
1065 | struct i2c_msg msg = { | |
1066 | .addr = slave_addr, | |
1067 | .flags = 0, | |
1068 | .len = 2, | |
1069 | .buf = out_buf, | |
1070 | }; | |
1071 | ||
1072 | out_buf[0] = addr; | |
1073 | out_buf[1] = val; | |
1074 | ||
1075 | if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) | |
1076 | DRM_ERROR("i2c 0x%02x 0x%02x write failed\n", | |
1077 | addr, val); | |
1078 | } | |
1079 | ||
26b5bc98 AD |
1080 | /* router switching */ |
1081 | void radeon_router_select_port(struct radeon_connector *radeon_connector) | |
1082 | { | |
1083 | u8 val; | |
1084 | ||
1085 | if (!radeon_connector->router.valid) | |
1086 | return; | |
1087 | ||
1088 | radeon_i2c_get_byte(radeon_connector->router_bus, | |
1089 | radeon_connector->router.i2c_addr, | |
1090 | 0x3, &val); | |
1091 | val &= radeon_connector->router.mux_control_pin; | |
1092 | radeon_i2c_put_byte(radeon_connector->router_bus, | |
1093 | radeon_connector->router.i2c_addr, | |
1094 | 0x3, val); | |
1095 | radeon_i2c_get_byte(radeon_connector->router_bus, | |
1096 | radeon_connector->router.i2c_addr, | |
1097 | 0x1, &val); | |
1098 | val &= radeon_connector->router.mux_control_pin; | |
1099 | val |= radeon_connector->router.mux_state; | |
1100 | radeon_i2c_put_byte(radeon_connector->router_bus, | |
1101 | radeon_connector->router.i2c_addr, | |
1102 | 0x1, val); | |
1103 | } | |
1104 |