Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
30 | #include "radeon.h" |
31 | ||
32 | int radeon_gem_object_init(struct drm_gem_object *obj) | |
33 | { | |
441921d5 DV |
34 | BUG(); |
35 | ||
771fe6b9 JG |
36 | return 0; |
37 | } | |
38 | ||
39 | void radeon_gem_object_free(struct drm_gem_object *gobj) | |
40 | { | |
7e4d15d9 | 41 | struct radeon_bo *robj = gem_to_radeon_bo(gobj); |
771fe6b9 | 42 | |
771fe6b9 | 43 | if (robj) { |
40f5cf99 AD |
44 | if (robj->gem_base.import_attach) |
45 | drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); | |
4c788679 | 46 | radeon_bo_unref(&robj); |
771fe6b9 JG |
47 | } |
48 | } | |
49 | ||
50 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
51 | int alignment, int initial_domain, |
52 | bool discardable, bool kernel, | |
53 | struct drm_gem_object **obj) | |
771fe6b9 | 54 | { |
4c788679 | 55 | struct radeon_bo *robj; |
771fe6b9 JG |
56 | int r; |
57 | ||
58 | *obj = NULL; | |
771fe6b9 JG |
59 | /* At least align on page size */ |
60 | if (alignment < PAGE_SIZE) { | |
61 | alignment = PAGE_SIZE; | |
62 | } | |
40f5cf99 | 63 | r = radeon_bo_create(rdev, size, alignment, kernel, initial_domain, NULL, &robj); |
771fe6b9 | 64 | if (r) { |
ecabd32a DA |
65 | if (r != -ERESTARTSYS) |
66 | DRM_ERROR("Failed to allocate GEM object (%d, %d, %u, %d)\n", | |
67 | size, initial_domain, alignment, r); | |
771fe6b9 JG |
68 | return r; |
69 | } | |
441921d5 DV |
70 | *obj = &robj->gem_base; |
71 | ||
72 | mutex_lock(&rdev->gem.mutex); | |
73 | list_add_tail(&robj->list, &rdev->gem.objects); | |
74 | mutex_unlock(&rdev->gem.mutex); | |
75 | ||
771fe6b9 JG |
76 | return 0; |
77 | } | |
78 | ||
771fe6b9 JG |
79 | int radeon_gem_set_domain(struct drm_gem_object *gobj, |
80 | uint32_t rdomain, uint32_t wdomain) | |
81 | { | |
4c788679 | 82 | struct radeon_bo *robj; |
771fe6b9 JG |
83 | uint32_t domain; |
84 | int r; | |
85 | ||
86 | /* FIXME: reeimplement */ | |
7e4d15d9 | 87 | robj = gem_to_radeon_bo(gobj); |
771fe6b9 JG |
88 | /* work out where to validate the buffer to */ |
89 | domain = wdomain; | |
90 | if (!domain) { | |
91 | domain = rdomain; | |
92 | } | |
93 | if (!domain) { | |
94 | /* Do nothings */ | |
b6cafa27 | 95 | printk(KERN_WARNING "Set domain without domain !\n"); |
771fe6b9 JG |
96 | return 0; |
97 | } | |
98 | if (domain == RADEON_GEM_DOMAIN_CPU) { | |
99 | /* Asking for cpu access wait for object idle */ | |
4c788679 | 100 | r = radeon_bo_wait(robj, NULL, false); |
771fe6b9 JG |
101 | if (r) { |
102 | printk(KERN_ERR "Failed to wait for object !\n"); | |
103 | return r; | |
104 | } | |
105 | } | |
106 | return 0; | |
107 | } | |
108 | ||
109 | int radeon_gem_init(struct radeon_device *rdev) | |
110 | { | |
111 | INIT_LIST_HEAD(&rdev->gem.objects); | |
112 | return 0; | |
113 | } | |
114 | ||
115 | void radeon_gem_fini(struct radeon_device *rdev) | |
116 | { | |
4c788679 | 117 | radeon_bo_force_delete(rdev); |
771fe6b9 JG |
118 | } |
119 | ||
721604a1 JG |
120 | /* |
121 | * Call from drm_gem_handle_create which appear in both new and open ioctl | |
122 | * case. | |
123 | */ | |
124 | int radeon_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) | |
125 | { | |
126 | return 0; | |
127 | } | |
128 | ||
129 | void radeon_gem_object_close(struct drm_gem_object *obj, | |
130 | struct drm_file *file_priv) | |
131 | { | |
132 | struct radeon_bo *rbo = gem_to_radeon_bo(obj); | |
133 | struct radeon_device *rdev = rbo->rdev; | |
134 | struct radeon_fpriv *fpriv = file_priv->driver_priv; | |
135 | struct radeon_vm *vm = &fpriv->vm; | |
721604a1 JG |
136 | |
137 | if (rdev->family < CHIP_CAYMAN) { | |
138 | return; | |
139 | } | |
140 | ||
141 | if (radeon_bo_reserve(rbo, false)) { | |
e43b5ec0 | 142 | dev_err(rdev->dev, "leaking bo va because we fail to reserve bo\n"); |
721604a1 JG |
143 | return; |
144 | } | |
e43b5ec0 | 145 | radeon_vm_bo_rmv(rdev, vm, rbo); |
721604a1 JG |
146 | radeon_bo_unreserve(rbo); |
147 | } | |
148 | ||
6c6f4783 CK |
149 | static int radeon_gem_handle_lockup(struct radeon_device *rdev, int r) |
150 | { | |
151 | if (r == -EDEADLK) { | |
6c6f4783 CK |
152 | r = radeon_gpu_reset(rdev); |
153 | if (!r) | |
154 | r = -EAGAIN; | |
6c6f4783 CK |
155 | } |
156 | return r; | |
157 | } | |
771fe6b9 JG |
158 | |
159 | /* | |
160 | * GEM ioctls. | |
161 | */ | |
162 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
163 | struct drm_file *filp) | |
164 | { | |
165 | struct radeon_device *rdev = dev->dev_private; | |
166 | struct drm_radeon_gem_info *args = data; | |
53595338 | 167 | struct ttm_mem_type_manager *man; |
bf852799 | 168 | unsigned i; |
53595338 DA |
169 | |
170 | man = &rdev->mman.bdev.man[TTM_PL_VRAM]; | |
771fe6b9 | 171 | |
7a50f01a | 172 | args->vram_size = rdev->mc.real_vram_size; |
53595338 | 173 | args->vram_visible = (u64)man->size << PAGE_SHIFT; |
38e14921 | 174 | if (rdev->stollen_vga_memory) |
4c788679 | 175 | args->vram_visible -= radeon_bo_size(rdev->stollen_vga_memory); |
38651674 | 176 | args->vram_visible -= radeon_fbdev_total_size(rdev); |
7b1f2485 | 177 | args->gart_size = rdev->mc.gtt_size - 4096 - RADEON_IB_POOL_SIZE*64*1024; |
bf852799 | 178 | for(i = 0; i < RADEON_NUM_RINGS; ++i) |
e32eb50d | 179 | args->gart_size -= rdev->ring[i].ring_size; |
771fe6b9 JG |
180 | return 0; |
181 | } | |
182 | ||
183 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
184 | struct drm_file *filp) | |
185 | { | |
186 | /* TODO: implement */ | |
187 | DRM_ERROR("unimplemented %s\n", __func__); | |
188 | return -ENOSYS; | |
189 | } | |
190 | ||
191 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
192 | struct drm_file *filp) | |
193 | { | |
194 | /* TODO: implement */ | |
195 | DRM_ERROR("unimplemented %s\n", __func__); | |
196 | return -ENOSYS; | |
197 | } | |
198 | ||
199 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
200 | struct drm_file *filp) | |
201 | { | |
202 | struct radeon_device *rdev = dev->dev_private; | |
203 | struct drm_radeon_gem_create *args = data; | |
204 | struct drm_gem_object *gobj; | |
205 | uint32_t handle; | |
206 | int r; | |
207 | ||
dee53e7f | 208 | down_read(&rdev->exclusive_lock); |
771fe6b9 JG |
209 | /* create a gem object to contain this object in */ |
210 | args->size = roundup(args->size, PAGE_SIZE); | |
211 | r = radeon_gem_object_create(rdev, args->size, args->alignment, | |
4c788679 JG |
212 | args->initial_domain, false, |
213 | false, &gobj); | |
771fe6b9 | 214 | if (r) { |
dee53e7f | 215 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 216 | r = radeon_gem_handle_lockup(rdev, r); |
771fe6b9 JG |
217 | return r; |
218 | } | |
219 | r = drm_gem_handle_create(filp, gobj, &handle); | |
29d08b3e DA |
220 | /* drop reference from allocate - handle holds it now */ |
221 | drm_gem_object_unreference_unlocked(gobj); | |
771fe6b9 | 222 | if (r) { |
dee53e7f | 223 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 224 | r = radeon_gem_handle_lockup(rdev, r); |
771fe6b9 JG |
225 | return r; |
226 | } | |
771fe6b9 | 227 | args->handle = handle; |
dee53e7f | 228 | up_read(&rdev->exclusive_lock); |
771fe6b9 JG |
229 | return 0; |
230 | } | |
231 | ||
232 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
233 | struct drm_file *filp) | |
234 | { | |
235 | /* transition the BO to a domain - | |
236 | * just validate the BO into a certain domain */ | |
dee53e7f | 237 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
238 | struct drm_radeon_gem_set_domain *args = data; |
239 | struct drm_gem_object *gobj; | |
4c788679 | 240 | struct radeon_bo *robj; |
771fe6b9 JG |
241 | int r; |
242 | ||
243 | /* for now if someone requests domain CPU - | |
244 | * just make sure the buffer is finished with */ | |
dee53e7f | 245 | down_read(&rdev->exclusive_lock); |
771fe6b9 JG |
246 | |
247 | /* just do a BO wait for now */ | |
248 | gobj = drm_gem_object_lookup(dev, filp, args->handle); | |
249 | if (gobj == NULL) { | |
dee53e7f | 250 | up_read(&rdev->exclusive_lock); |
bf79cb91 | 251 | return -ENOENT; |
771fe6b9 | 252 | } |
7e4d15d9 | 253 | robj = gem_to_radeon_bo(gobj); |
771fe6b9 JG |
254 | |
255 | r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain); | |
256 | ||
bc9025bd | 257 | drm_gem_object_unreference_unlocked(gobj); |
dee53e7f | 258 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 259 | r = radeon_gem_handle_lockup(robj->rdev, r); |
771fe6b9 JG |
260 | return r; |
261 | } | |
262 | ||
ff72145b DA |
263 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
264 | struct drm_device *dev, | |
265 | uint32_t handle, uint64_t *offset_p) | |
771fe6b9 | 266 | { |
771fe6b9 | 267 | struct drm_gem_object *gobj; |
4c788679 | 268 | struct radeon_bo *robj; |
771fe6b9 | 269 | |
ff72145b | 270 | gobj = drm_gem_object_lookup(dev, filp, handle); |
771fe6b9 | 271 | if (gobj == NULL) { |
bf79cb91 | 272 | return -ENOENT; |
771fe6b9 | 273 | } |
7e4d15d9 | 274 | robj = gem_to_radeon_bo(gobj); |
ff72145b | 275 | *offset_p = radeon_bo_mmap_offset(robj); |
bc9025bd | 276 | drm_gem_object_unreference_unlocked(gobj); |
4c788679 | 277 | return 0; |
771fe6b9 JG |
278 | } |
279 | ||
ff72145b DA |
280 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, |
281 | struct drm_file *filp) | |
282 | { | |
283 | struct drm_radeon_gem_mmap *args = data; | |
284 | ||
285 | return radeon_mode_dumb_mmap(filp, dev, args->handle, &args->addr_ptr); | |
286 | } | |
287 | ||
771fe6b9 JG |
288 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, |
289 | struct drm_file *filp) | |
290 | { | |
1ef5325b | 291 | struct radeon_device *rdev = dev->dev_private; |
cefb87ef DA |
292 | struct drm_radeon_gem_busy *args = data; |
293 | struct drm_gem_object *gobj; | |
4c788679 | 294 | struct radeon_bo *robj; |
cefb87ef | 295 | int r; |
4361e52a | 296 | uint32_t cur_placement = 0; |
cefb87ef DA |
297 | |
298 | gobj = drm_gem_object_lookup(dev, filp, args->handle); | |
299 | if (gobj == NULL) { | |
bf79cb91 | 300 | return -ENOENT; |
cefb87ef | 301 | } |
7e4d15d9 | 302 | robj = gem_to_radeon_bo(gobj); |
4c788679 | 303 | r = radeon_bo_wait(robj, &cur_placement, true); |
9f844e51 MD |
304 | switch (cur_placement) { |
305 | case TTM_PL_VRAM: | |
cefb87ef | 306 | args->domain = RADEON_GEM_DOMAIN_VRAM; |
9f844e51 MD |
307 | break; |
308 | case TTM_PL_TT: | |
cefb87ef | 309 | args->domain = RADEON_GEM_DOMAIN_GTT; |
9f844e51 MD |
310 | break; |
311 | case TTM_PL_SYSTEM: | |
cefb87ef | 312 | args->domain = RADEON_GEM_DOMAIN_CPU; |
9f844e51 MD |
313 | default: |
314 | break; | |
315 | } | |
bc9025bd | 316 | drm_gem_object_unreference_unlocked(gobj); |
1ef5325b | 317 | r = radeon_gem_handle_lockup(rdev, r); |
e3b2415e | 318 | return r; |
771fe6b9 JG |
319 | } |
320 | ||
321 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
322 | struct drm_file *filp) | |
323 | { | |
1ef5325b | 324 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
325 | struct drm_radeon_gem_wait_idle *args = data; |
326 | struct drm_gem_object *gobj; | |
4c788679 | 327 | struct radeon_bo *robj; |
771fe6b9 JG |
328 | int r; |
329 | ||
330 | gobj = drm_gem_object_lookup(dev, filp, args->handle); | |
331 | if (gobj == NULL) { | |
bf79cb91 | 332 | return -ENOENT; |
771fe6b9 | 333 | } |
7e4d15d9 | 334 | robj = gem_to_radeon_bo(gobj); |
4c788679 | 335 | r = radeon_bo_wait(robj, NULL, false); |
062b389c | 336 | /* callback hw specific functions if any */ |
1ef5325b JG |
337 | if (rdev->asic->ioctl_wait_idle) |
338 | robj->rdev->asic->ioctl_wait_idle(rdev, robj); | |
bc9025bd | 339 | drm_gem_object_unreference_unlocked(gobj); |
1ef5325b | 340 | r = radeon_gem_handle_lockup(rdev, r); |
771fe6b9 JG |
341 | return r; |
342 | } | |
e024e110 DA |
343 | |
344 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, | |
345 | struct drm_file *filp) | |
346 | { | |
347 | struct drm_radeon_gem_set_tiling *args = data; | |
348 | struct drm_gem_object *gobj; | |
4c788679 | 349 | struct radeon_bo *robj; |
e024e110 DA |
350 | int r = 0; |
351 | ||
352 | DRM_DEBUG("%d \n", args->handle); | |
353 | gobj = drm_gem_object_lookup(dev, filp, args->handle); | |
354 | if (gobj == NULL) | |
bf79cb91 | 355 | return -ENOENT; |
7e4d15d9 | 356 | robj = gem_to_radeon_bo(gobj); |
4c788679 | 357 | r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); |
bc9025bd | 358 | drm_gem_object_unreference_unlocked(gobj); |
e024e110 DA |
359 | return r; |
360 | } | |
361 | ||
362 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
363 | struct drm_file *filp) | |
364 | { | |
365 | struct drm_radeon_gem_get_tiling *args = data; | |
366 | struct drm_gem_object *gobj; | |
4c788679 | 367 | struct radeon_bo *rbo; |
e024e110 DA |
368 | int r = 0; |
369 | ||
370 | DRM_DEBUG("\n"); | |
371 | gobj = drm_gem_object_lookup(dev, filp, args->handle); | |
372 | if (gobj == NULL) | |
bf79cb91 | 373 | return -ENOENT; |
7e4d15d9 | 374 | rbo = gem_to_radeon_bo(gobj); |
4c788679 JG |
375 | r = radeon_bo_reserve(rbo, false); |
376 | if (unlikely(r != 0)) | |
51f07b7e | 377 | goto out; |
4c788679 JG |
378 | radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); |
379 | radeon_bo_unreserve(rbo); | |
51f07b7e | 380 | out: |
bc9025bd | 381 | drm_gem_object_unreference_unlocked(gobj); |
721604a1 JG |
382 | return r; |
383 | } | |
384 | ||
385 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, | |
386 | struct drm_file *filp) | |
387 | { | |
388 | struct drm_radeon_gem_va *args = data; | |
389 | struct drm_gem_object *gobj; | |
390 | struct radeon_device *rdev = dev->dev_private; | |
391 | struct radeon_fpriv *fpriv = filp->driver_priv; | |
392 | struct radeon_bo *rbo; | |
393 | struct radeon_bo_va *bo_va; | |
394 | u32 invalid_flags; | |
395 | int r = 0; | |
396 | ||
67e915e4 AD |
397 | if (!rdev->vm_manager.enabled) { |
398 | args->operation = RADEON_VA_RESULT_ERROR; | |
399 | return -ENOTTY; | |
400 | } | |
401 | ||
721604a1 JG |
402 | /* !! DONT REMOVE !! |
403 | * We don't support vm_id yet, to be sure we don't have have broken | |
404 | * userspace, reject anyone trying to use non 0 value thus moving | |
405 | * forward we can use those fields without breaking existant userspace | |
406 | */ | |
407 | if (args->vm_id) { | |
408 | args->operation = RADEON_VA_RESULT_ERROR; | |
409 | return -EINVAL; | |
410 | } | |
411 | ||
412 | if (args->offset < RADEON_VA_RESERVED_SIZE) { | |
413 | dev_err(&dev->pdev->dev, | |
414 | "offset 0x%lX is in reserved area 0x%X\n", | |
415 | (unsigned long)args->offset, | |
416 | RADEON_VA_RESERVED_SIZE); | |
417 | args->operation = RADEON_VA_RESULT_ERROR; | |
418 | return -EINVAL; | |
419 | } | |
420 | ||
421 | /* don't remove, we need to enforce userspace to set the snooped flag | |
422 | * otherwise we will endup with broken userspace and we won't be able | |
423 | * to enable this feature without adding new interface | |
424 | */ | |
425 | invalid_flags = RADEON_VM_PAGE_VALID | RADEON_VM_PAGE_SYSTEM; | |
426 | if ((args->flags & invalid_flags)) { | |
427 | dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n", | |
428 | args->flags, invalid_flags); | |
429 | args->operation = RADEON_VA_RESULT_ERROR; | |
430 | return -EINVAL; | |
431 | } | |
432 | if (!(args->flags & RADEON_VM_PAGE_SNOOPED)) { | |
433 | dev_err(&dev->pdev->dev, "only supported snooped mapping for now\n"); | |
434 | args->operation = RADEON_VA_RESULT_ERROR; | |
435 | return -EINVAL; | |
436 | } | |
437 | ||
438 | switch (args->operation) { | |
439 | case RADEON_VA_MAP: | |
440 | case RADEON_VA_UNMAP: | |
441 | break; | |
442 | default: | |
443 | dev_err(&dev->pdev->dev, "unsupported operation %d\n", | |
444 | args->operation); | |
445 | args->operation = RADEON_VA_RESULT_ERROR; | |
446 | return -EINVAL; | |
447 | } | |
448 | ||
449 | gobj = drm_gem_object_lookup(dev, filp, args->handle); | |
450 | if (gobj == NULL) { | |
451 | args->operation = RADEON_VA_RESULT_ERROR; | |
452 | return -ENOENT; | |
453 | } | |
454 | rbo = gem_to_radeon_bo(gobj); | |
455 | r = radeon_bo_reserve(rbo, false); | |
456 | if (r) { | |
457 | args->operation = RADEON_VA_RESULT_ERROR; | |
458 | drm_gem_object_unreference_unlocked(gobj); | |
459 | return r; | |
460 | } | |
461 | switch (args->operation) { | |
462 | case RADEON_VA_MAP: | |
463 | bo_va = radeon_bo_va(rbo, &fpriv->vm); | |
464 | if (bo_va) { | |
465 | args->operation = RADEON_VA_RESULT_VA_EXIST; | |
466 | args->offset = bo_va->soffset; | |
467 | goto out; | |
468 | } | |
469 | r = radeon_vm_bo_add(rdev, &fpriv->vm, rbo, | |
470 | args->offset, args->flags); | |
471 | break; | |
472 | case RADEON_VA_UNMAP: | |
473 | r = radeon_vm_bo_rmv(rdev, &fpriv->vm, rbo); | |
474 | break; | |
475 | default: | |
476 | break; | |
477 | } | |
478 | args->operation = RADEON_VA_RESULT_OK; | |
479 | if (r) { | |
480 | args->operation = RADEON_VA_RESULT_ERROR; | |
481 | } | |
482 | out: | |
483 | radeon_bo_unreserve(rbo); | |
484 | drm_gem_object_unreference_unlocked(gobj); | |
e024e110 DA |
485 | return r; |
486 | } | |
ff72145b DA |
487 | |
488 | int radeon_mode_dumb_create(struct drm_file *file_priv, | |
489 | struct drm_device *dev, | |
490 | struct drm_mode_create_dumb *args) | |
491 | { | |
492 | struct radeon_device *rdev = dev->dev_private; | |
493 | struct drm_gem_object *gobj; | |
c87a8d8d | 494 | uint32_t handle; |
ff72145b DA |
495 | int r; |
496 | ||
497 | args->pitch = radeon_align_pitch(rdev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8); | |
498 | args->size = args->pitch * args->height; | |
499 | args->size = ALIGN(args->size, PAGE_SIZE); | |
500 | ||
501 | r = radeon_gem_object_create(rdev, args->size, 0, | |
502 | RADEON_GEM_DOMAIN_VRAM, | |
503 | false, ttm_bo_type_device, | |
504 | &gobj); | |
505 | if (r) | |
506 | return -ENOMEM; | |
507 | ||
c87a8d8d DA |
508 | r = drm_gem_handle_create(file_priv, gobj, &handle); |
509 | /* drop reference from allocate - handle holds it now */ | |
510 | drm_gem_object_unreference_unlocked(gobj); | |
ff72145b | 511 | if (r) { |
ff72145b DA |
512 | return r; |
513 | } | |
c87a8d8d | 514 | args->handle = handle; |
ff72145b DA |
515 | return 0; |
516 | } | |
517 | ||
518 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, | |
519 | struct drm_device *dev, | |
520 | uint32_t handle) | |
521 | { | |
522 | return drm_gem_handle_delete(file_priv, handle); | |
523 | } |