[linux-block.git] / drivers / gpu / drm / radeon / radeon_gart.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include <drm/drmP.h>
#include <drm/radeon_drm.h>
#ifdef CONFIG_X86
#include <asm/set_memory.h>
#endif
#include "radeon.h"

/*
 * GART
 * The GART (Graphics Aperture Remapping Table) is an aperture
 * in the GPU's address space.  System pages can be mapped into
 * the aperture and look like contiguous pages from the GPU's
 * perspective.  A page table maps the pages in the aperture
 * to the actual backing pages in system memory.
 *
 * Radeon GPUs support both an internal GART, as described above,
 * and AGP.  AGP works similarly, but the GART table is configured
 * and maintained by the northbridge rather than the driver.
 * Radeon hw has a separate AGP aperture that is programmed to
 * point to the AGP aperture provided by the northbridge and the
 * requests are passed through to the northbridge aperture.
 * Both AGP and internal GART can be used at the same time, however
 * that is not currently supported by the driver.
 *
 * This file handles the common internal GART management.
 */

/*
 * Common GART table functions.
 */
/**
 * radeon_gart_table_ram_alloc - allocate system ram for gart page table
 *
 * @rdev: radeon_device pointer
 *
 * Allocate system memory for GART page table
 * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
 * gart table to be in system memory.
 * Returns 0 for success, -ENOMEM for failure.
 */
int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
{
	void *ptr;

	ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
				   &rdev->gart.table_addr);
	if (ptr == NULL) {
		return -ENOMEM;
	}
#ifdef CONFIG_X86
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
	    rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
		set_memory_uc((unsigned long)ptr,
			      rdev->gart.table_size >> PAGE_SHIFT);
	}
#endif
	rdev->gart.ptr = ptr;
	memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size);
	return 0;
}

/**
 * radeon_gart_table_ram_free - free system ram for gart page table
 *
 * @rdev: radeon_device pointer
 *
 * Free system memory for GART page table
 * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
 * gart table to be in system memory.
 */
void radeon_gart_table_ram_free(struct radeon_device *rdev)
{
	if (rdev->gart.ptr == NULL) {
		return;
	}
#ifdef CONFIG_X86
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
	    rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
		set_memory_wb((unsigned long)rdev->gart.ptr,
			      rdev->gart.table_size >> PAGE_SHIFT);
	}
#endif
	pci_free_consistent(rdev->pdev, rdev->gart.table_size,
			    (void *)rdev->gart.ptr,
			    rdev->gart.table_addr);
	rdev->gart.ptr = NULL;
	rdev->gart.table_addr = 0;
}

/**
 * radeon_gart_table_vram_alloc - allocate vram for gart page table
 *
 * @rdev: radeon_device pointer
 *
 * Allocate video memory for GART page table
 * (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
{
	int r;

	if (rdev->gart.robj == NULL) {
		r = radeon_bo_create(rdev, rdev->gart.table_size,
				     PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
				     0, NULL, NULL, &rdev->gart.robj);
		if (r) {
			return r;
		}
	}
	return 0;
}

/**
 * radeon_gart_table_vram_pin - pin gart page table in vram
 *
 * @rdev: radeon_device pointer
 *
 * Pin the GART page table in vram so it will not be moved
 * by the memory manager (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int radeon_gart_table_vram_pin(struct radeon_device *rdev)
{
	uint64_t gpu_addr;
	int r;

	r = radeon_bo_reserve(rdev->gart.robj, false);
	if (unlikely(r != 0))
		return r;
	r = radeon_bo_pin(rdev->gart.robj,
				RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
	if (r) {
		radeon_bo_unreserve(rdev->gart.robj);
		return r;
	}
	r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr);
	if (r)
		radeon_bo_unpin(rdev->gart.robj);
	radeon_bo_unreserve(rdev->gart.robj);
	rdev->gart.table_addr = gpu_addr;

	if (!r) {
		int i;

		/* We might have dropped some GART table updates while it wasn't
		 * mapped, restore all entries
		 */
		for (i = 0; i < rdev->gart.num_gpu_pages; i++)
			radeon_gart_set_page(rdev, i, rdev->gart.pages_entry[i]);
		mb();
		radeon_gart_tlb_flush(rdev);
	}

	return r;
}

/**
 * radeon_gart_table_vram_unpin - unpin gart page table in vram
 *
 * @rdev: radeon_device pointer
 *
 * Unpin the GART page table in vram (pcie r4xx, r5xx+).
 * These asics require the gart table to be in video memory.
 */
void radeon_gart_table_vram_unpin(struct radeon_device *rdev)
{
	int r;

	if (rdev->gart.robj == NULL) {
		return;
	}
	r = radeon_bo_reserve(rdev->gart.robj, false);
	if (likely(r == 0)) {
		radeon_bo_kunmap(rdev->gart.robj);
		radeon_bo_unpin(rdev->gart.robj);
		radeon_bo_unreserve(rdev->gart.robj);
		rdev->gart.ptr = NULL;
	}
}

/**
 * radeon_gart_table_vram_free - free gart page table vram
 *
 * @rdev: radeon_device pointer
 *
 * Free the video memory used for the GART page table
 * (pcie r4xx, r5xx+).  These asics require the gart table to
 * be in video memory.
 */
void radeon_gart_table_vram_free(struct radeon_device *rdev)
{
	if (rdev->gart.robj == NULL) {
		return;
	}
	radeon_bo_unref(&rdev->gart.robj);
}

/*
 * Common gart functions.
 */
/**
 * radeon_gart_unbind - unbind pages from the gart page table
 *
 * @rdev: radeon_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to unbind
 *
 * Unbinds the requested pages from the gart page table and
 * replaces them with the dummy page (all asics).
 */
void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
			int pages)
{
	unsigned t;
	unsigned p;
	int i, j;

	if (!rdev->gart.ready) {
		WARN(1, "trying to unbind memory from uninitialized GART !\n");
		return;
	}
	t = offset / RADEON_GPU_PAGE_SIZE;
	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
	for (i = 0; i < pages; i++, p++) {
		if (rdev->gart.pages[p]) {
			rdev->gart.pages[p] = NULL;
			for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
				rdev->gart.pages_entry[t] = rdev->dummy_page.entry;
				if (rdev->gart.ptr) {
					radeon_gart_set_page(rdev, t,
							     rdev->dummy_page.entry);
				}
			}
		}
	}
	if (rdev->gart.ptr) {
		mb();
		radeon_gart_tlb_flush(rdev);
	}
}

/**
 * radeon_gart_bind - bind pages into the gart page table
 *
 * @rdev: radeon_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to bind
 * @pagelist: pages to bind
 * @dma_addr: DMA addresses of pages
 * @flags: RADEON_GART_PAGE_* flags
 *
 * Binds the requested pages to the gart page table
 * (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
		     int pages, struct page **pagelist, dma_addr_t *dma_addr,
		     uint32_t flags)
{
	unsigned t;
	unsigned p;
	uint64_t page_base, page_entry;
	int i, j;

	if (!rdev->gart.ready) {
		WARN(1, "trying to bind memory to uninitialized GART !\n");
		return -EINVAL;
	}
	t = offset / RADEON_GPU_PAGE_SIZE;
	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);

	for (i = 0; i < pages; i++, p++) {
		rdev->gart.pages[p] = pagelist[i];
		page_base = dma_addr[i];
		for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
			page_entry = radeon_gart_get_page_entry(page_base, flags);
			rdev->gart.pages_entry[t] = page_entry;
			if (rdev->gart.ptr) {
				radeon_gart_set_page(rdev, t, page_entry);
			}
			page_base += RADEON_GPU_PAGE_SIZE;
		}
	}
	if (rdev->gart.ptr) {
		mb();
		radeon_gart_tlb_flush(rdev);
	}
	return 0;
}

/**
 * radeon_gart_init - init the driver info for managing the gart
 *
 * @rdev: radeon_device pointer
 *
 * Allocate the dummy page and init the gart driver info (all asics).
 * Returns 0 for success, error for failure.
 */
int radeon_gart_init(struct radeon_device *rdev)
{
	int r, i;

	if (rdev->gart.pages) {
		return 0;
	}
	/* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
	if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
		DRM_ERROR("Page size is smaller than GPU page size!\n");
		return -EINVAL;
	}
	r = radeon_dummy_page_init(rdev);
	if (r)
		return r;
	/* Compute table size */
	rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
	rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
		 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
	/* Allocate pages table */
	rdev->gart.pages = vzalloc(array_size(sizeof(void *),
				   rdev->gart.num_cpu_pages));
	if (rdev->gart.pages == NULL) {
		radeon_gart_fini(rdev);
		return -ENOMEM;
	}
	rdev->gart.pages_entry = vmalloc(array_size(sizeof(uint64_t),
						    rdev->gart.num_gpu_pages));
	if (rdev->gart.pages_entry == NULL) {
		radeon_gart_fini(rdev);
		return -ENOMEM;
	}
	/* set GART entry to point to the dummy page by default */
	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
		rdev->gart.pages_entry[i] = rdev->dummy_page.entry;
	return 0;
}

/**
 * radeon_gart_fini - tear down the driver info for managing the gart
 *
 * @rdev: radeon_device pointer
 *
 * Tear down the gart driver info and free the dummy page (all asics).
 */
void radeon_gart_fini(struct radeon_device *rdev)
{
	if (rdev->gart.ready) {
		/* unbind pages */
		radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
	}
	rdev->gart.ready = false;
	vfree(rdev->gart.pages);
	vfree(rdev->gart.pages_entry);
	rdev->gart.pages = NULL;
	rdev->gart.pages_entry = NULL;

	radeon_dummy_page_fini(rdev);
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
760285e7 DH	28	#include <drm/drmP.h>
760285e7 DH	29	#include <drm/radeon_drm.h>
ed3ba079 LA	30	#ifdef CONFIG_X86
	31	#include <asm/set_memory.h>
	32	#endif
771fe6b9	33	#include "radeon.h"
771fe6b9	34
03eec93b AD	35	/*
	36	* GART
	37	* The GART (Graphics Aperture Remapping Table) is an aperture
	38	* in the GPU's address space. System pages can be mapped into
	39	* the aperture and look like contiguous pages from the GPU's
	40	* perspective. A page table maps the pages in the aperture
	41	* to the actual backing pages in system memory.
	42	*
	43	* Radeon GPUs support both an internal GART, as described above,
	44	* and AGP. AGP works similarly, but the GART table is configured
	45	* and maintained by the northbridge rather than the driver.
	46	* Radeon hw has a separate AGP aperture that is programmed to
	47	* point to the AGP aperture provided by the northbridge and the
	48	* requests are passed through to the northbridge aperture.
	49	* Both AGP and internal GART can be used at the same time, however
	50	* that is not currently supported by the driver.
	51	*
	52	* This file handles the common internal GART management.
	53	*/
	54
771fe6b9 JG	55	/*
	56	* Common GART table functions.
	57	*/
03eec93b AD	58	/**
	59	* radeon_gart_table_ram_alloc - allocate system ram for gart page table
	60	*
	61	* @rdev: radeon_device pointer
	62	*
	63	* Allocate system memory for GART page table
	64	* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
	65	* gart table to be in system memory.
	66	* Returns 0 for success, -ENOMEM for failure.
	67	*/
771fe6b9 JG	68	int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
	69	{
	70	void *ptr;
	71
	72	ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
	73	&rdev->gart.table_addr);
	74	if (ptr == NULL) {
	75	return -ENOMEM;
	76	}
	77	#ifdef CONFIG_X86
	78	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480 \|\|
	79	rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
	80	set_memory_uc((unsigned long)ptr,
	81	rdev->gart.table_size >> PAGE_SHIFT);
	82	}
	83	#endif
c9a1be96 JG	84	rdev->gart.ptr = ptr;
c9a1be96 JG	85	memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size);
771fe6b9 JG	86	return 0;
	87	}
	88
03eec93b AD	89	/**
	90	* radeon_gart_table_ram_free - free system ram for gart page table
	91	*
	92	* @rdev: radeon_device pointer
	93	*
	94	* Free system memory for GART page table
	95	* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
	96	* gart table to be in system memory.
	97	*/
771fe6b9 JG	98	void radeon_gart_table_ram_free(struct radeon_device *rdev)
771fe6b9 JG	99	{
c9a1be96	100	if (rdev->gart.ptr == NULL) {
771fe6b9 JG	101	return;
	102	}
	103	#ifdef CONFIG_X86
	104	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480 \|\|
	105	rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
c9a1be96	106	set_memory_wb((unsigned long)rdev->gart.ptr,
771fe6b9 JG	107	rdev->gart.table_size >> PAGE_SHIFT);
	108	}
	109	#endif
	110	pci_free_consistent(rdev->pdev, rdev->gart.table_size,
c9a1be96	111	(void *)rdev->gart.ptr,
771fe6b9	112	rdev->gart.table_addr);
c9a1be96	113	rdev->gart.ptr = NULL;
771fe6b9 JG	114	rdev->gart.table_addr = 0;
	115	}
	116
03eec93b AD	117	/**
	118	* radeon_gart_table_vram_alloc - allocate vram for gart page table
	119	*
	120	* @rdev: radeon_device pointer
	121	*
	122	* Allocate video memory for GART page table
	123	* (pcie r4xx, r5xx+). These asics require the
	124	* gart table to be in video memory.
	125	* Returns 0 for success, error for failure.
	126	*/
771fe6b9 JG	127	int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
771fe6b9 JG	128	{
771fe6b9 JG	129	int r;
771fe6b9 JG	130
c9a1be96	131	if (rdev->gart.robj == NULL) {
441921d5	132	r = radeon_bo_create(rdev, rdev->gart.table_size,
268b2510	133	PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
831b6966	134	0, NULL, NULL, &rdev->gart.robj);
771fe6b9 JG	135	if (r) {
	136	return r;
	137	}
	138	}
4aac0473 JG	139	return 0;
	140	}
	141
03eec93b AD	142	/**
	143	* radeon_gart_table_vram_pin - pin gart page table in vram
	144	*
	145	* @rdev: radeon_device pointer
	146	*
	147	* Pin the GART page table in vram so it will not be moved
	148	* by the memory manager (pcie r4xx, r5xx+). These asics require the
	149	* gart table to be in video memory.
	150	* Returns 0 for success, error for failure.
	151	*/
4aac0473 JG	152	int radeon_gart_table_vram_pin(struct radeon_device *rdev)
	153	{
	154	uint64_t gpu_addr;
	155	int r;
	156
c9a1be96	157	r = radeon_bo_reserve(rdev->gart.robj, false);
4c788679	158	if (unlikely(r != 0))
771fe6b9	159	return r;
c9a1be96	160	r = radeon_bo_pin(rdev->gart.robj,
4c788679	161	RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
771fe6b9	162	if (r) {
c9a1be96	163	radeon_bo_unreserve(rdev->gart.robj);
771fe6b9 JG	164	return r;
771fe6b9 JG	165	}
c9a1be96	166	r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr);
4c788679	167	if (r)
c9a1be96 JG	168	radeon_bo_unpin(rdev->gart.robj);
c9a1be96 JG	169	radeon_bo_unreserve(rdev->gart.robj);
771fe6b9	170	rdev->gart.table_addr = gpu_addr;
5636d2f8 MD	171
	172	if (!r) {
	173	int i;
	174
	175	/* We might have dropped some GART table updates while it wasn't
	176	* mapped, restore all entries
	177	*/
	178	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
	179	radeon_gart_set_page(rdev, i, rdev->gart.pages_entry[i]);
	180	mb();
	181	radeon_gart_tlb_flush(rdev);
	182	}
	183
4c788679	184	return r;
771fe6b9 JG	185	}
771fe6b9 JG	186
03eec93b AD	187	/**
	188	* radeon_gart_table_vram_unpin - unpin gart page table in vram
	189	*
	190	* @rdev: radeon_device pointer
	191	*
	192	* Unpin the GART page table in vram (pcie r4xx, r5xx+).
	193	* These asics require the gart table to be in video memory.
	194	*/
c9a1be96	195	void radeon_gart_table_vram_unpin(struct radeon_device *rdev)
771fe6b9	196	{
4c788679 JG	197	int r;
4c788679 JG	198
c9a1be96	199	if (rdev->gart.robj == NULL) {
771fe6b9 JG	200	return;
771fe6b9 JG	201	}
c9a1be96	202	r = radeon_bo_reserve(rdev->gart.robj, false);
4c788679	203	if (likely(r == 0)) {
c9a1be96 JG	204	radeon_bo_kunmap(rdev->gart.robj);
	205	radeon_bo_unpin(rdev->gart.robj);
	206	radeon_bo_unreserve(rdev->gart.robj);
	207	rdev->gart.ptr = NULL;
	208	}
	209	}
	210
03eec93b AD	211	/**
	212	* radeon_gart_table_vram_free - free gart page table vram
	213	*
	214	* @rdev: radeon_device pointer
	215	*
	216	* Free the video memory used for the GART page table
	217	* (pcie r4xx, r5xx+). These asics require the gart table to
	218	* be in video memory.
	219	*/
c9a1be96 JG	220	void radeon_gart_table_vram_free(struct radeon_device *rdev)
	221	{
	222	if (rdev->gart.robj == NULL) {
	223	return;
4c788679	224	}
c9a1be96	225	radeon_bo_unref(&rdev->gart.robj);
771fe6b9 JG	226	}
771fe6b9 JG	227
771fe6b9 JG	228	/*
	229	* Common gart functions.
	230	*/
03eec93b AD	231	/**
	232	* radeon_gart_unbind - unbind pages from the gart page table
	233	*
	234	* @rdev: radeon_device pointer
	235	* @offset: offset into the GPU's gart aperture
	236	* @pages: number of pages to unbind
	237	*
	238	* Unbinds the requested pages from the gart page table and
	239	* replaces them with the dummy page (all asics).
	240	*/
771fe6b9 JG	241	void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
	242	int pages)
	243	{
	244	unsigned t;
	245	unsigned p;
	246	int i, j;
	247
	248	if (!rdev->gart.ready) {
fcf4de5a	249	WARN(1, "trying to unbind memory from uninitialized GART !\n");
771fe6b9 JG	250	return;
771fe6b9 JG	251	}
a77f1718 MT	252	t = offset / RADEON_GPU_PAGE_SIZE;
a77f1718 MT	253	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
771fe6b9 JG	254	for (i = 0; i < pages; i++, p++) {
771fe6b9 JG	255	if (rdev->gart.pages[p]) {
771fe6b9	256	rdev->gart.pages[p] = NULL;
a77f1718	257	for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
cb658906	258	rdev->gart.pages_entry[t] = rdev->dummy_page.entry;
c9a1be96	259	if (rdev->gart.ptr) {
cb658906 MD	260	radeon_gart_set_page(rdev, t,
cb658906 MD	261	rdev->dummy_page.entry);
c9a1be96	262	}
771fe6b9 JG	263	}
	264	}
	265	}
233709d2 MD	266	if (rdev->gart.ptr) {
	267	mb();
	268	radeon_gart_tlb_flush(rdev);
	269	}
771fe6b9 JG	270	}
771fe6b9 JG	271
03eec93b AD	272	/**
	273	* radeon_gart_bind - bind pages into the gart page table
	274	*
	275	* @rdev: radeon_device pointer
	276	* @offset: offset into the GPU's gart aperture
	277	* @pages: number of pages to bind
	278	* @pagelist: pages to bind
	279	* @dma_addr: DMA addresses of pages
77497f27	280	* @flags: RADEON_GART_PAGE_* flags
03eec93b AD	281	*
	282	* Binds the requested pages to the gart page table
	283	* (all asics).
	284	* Returns 0 for success, -EINVAL for failure.
	285	*/
771fe6b9	286	int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
77497f27 MD	287	int pages, struct page *pagelist, dma_addr_t dma_addr,
77497f27 MD	288	uint32_t flags)
771fe6b9 JG	289	{
	290	unsigned t;
	291	unsigned p;
cb658906	292	uint64_t page_base, page_entry;
771fe6b9 JG	293	int i, j;
	294
	295	if (!rdev->gart.ready) {
fcf4de5a	296	WARN(1, "trying to bind memory to uninitialized GART !\n");
771fe6b9 JG	297	return -EINVAL;
771fe6b9 JG	298	}
a77f1718 MT	299	t = offset / RADEON_GPU_PAGE_SIZE;
a77f1718 MT	300	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
771fe6b9 JG	301
771fe6b9 JG	302	for (i = 0; i < pages; i++, p++) {
771fe6b9	303	rdev->gart.pages[p] = pagelist[i];
cb658906 MD	304	page_base = dma_addr[i];
	305	for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
	306	page_entry = radeon_gart_get_page_entry(page_base, flags);
	307	rdev->gart.pages_entry[t] = page_entry;
	308	if (rdev->gart.ptr) {
	309	radeon_gart_set_page(rdev, t, page_entry);
c9a1be96	310	}
cb658906	311	page_base += RADEON_GPU_PAGE_SIZE;
771fe6b9 JG	312	}
771fe6b9 JG	313	}
233709d2 MD	314	if (rdev->gart.ptr) {
	315	mb();
	316	radeon_gart_tlb_flush(rdev);
	317	}
771fe6b9 JG	318	return 0;
	319	}
	320
03eec93b AD	321	/**
	322	* radeon_gart_init - init the driver info for managing the gart
	323	*
	324	* @rdev: radeon_device pointer
	325	*
	326	* Allocate the dummy page and init the gart driver info (all asics).
	327	* Returns 0 for success, error for failure.
	328	*/
771fe6b9 JG	329	int radeon_gart_init(struct radeon_device *rdev)
771fe6b9 JG	330	{
82568565 DA	331	int r, i;
82568565 DA	332
771fe6b9 JG	333	if (rdev->gart.pages) {
	334	return 0;
	335	}
a77f1718 MT	336	/* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
a77f1718 MT	337	if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
771fe6b9 JG	338	DRM_ERROR("Page size is smaller than GPU page size!\n");
	339	return -EINVAL;
	340	}
82568565 DA	341	r = radeon_dummy_page_init(rdev);
	342	if (r)
	343	return r;
771fe6b9 JG	344	/* Compute table size */
771fe6b9 JG	345	rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
a77f1718	346	rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
771fe6b9 JG	347	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
	348	rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
	349	/* Allocate pages table */
fad953ce KC	350	rdev->gart.pages = vzalloc(array_size(sizeof(void *),
fad953ce KC	351	rdev->gart.num_cpu_pages));
771fe6b9 JG	352	if (rdev->gart.pages == NULL) {
	353	radeon_gart_fini(rdev);
	354	return -ENOMEM;
	355	}
42bc47b3 KC	356	rdev->gart.pages_entry = vmalloc(array_size(sizeof(uint64_t),
42bc47b3 KC	357	rdev->gart.num_gpu_pages));
cb658906 MD	358	if (rdev->gart.pages_entry == NULL) {
	359	radeon_gart_fini(rdev);
	360	return -ENOMEM;
	361	}
82568565	362	/* set GART entry to point to the dummy page by default */
cb658906 MD	363	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
cb658906 MD	364	rdev->gart.pages_entry[i] = rdev->dummy_page.entry;
771fe6b9 JG	365	return 0;
	366	}
	367
03eec93b AD	368	/**
	369	* radeon_gart_fini - tear down the driver info for managing the gart
	370	*
	371	* @rdev: radeon_device pointer
	372	*
	373	* Tear down the gart driver info and free the dummy page (all asics).
	374	*/
771fe6b9 JG	375	void radeon_gart_fini(struct radeon_device *rdev)
771fe6b9 JG	376	{
cb658906	377	if (rdev->gart.ready) {
771fe6b9 JG	378	/* unbind pages */
	379	radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
	380	}
	381	rdev->gart.ready = false;
59240ee3	382	vfree(rdev->gart.pages);
cb658906	383	vfree(rdev->gart.pages_entry);
771fe6b9	384	rdev->gart.pages = NULL;
cb658906	385	rdev->gart.pages_entry = NULL;
92656d70 AD	386
92656d70 AD	387	radeon_dummy_page_fini(rdev);
771fe6b9	388	}