Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright © 2007 David Airlie | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * David Airlie | |
25 | */ | |
771fe6b9 | 26 | #include <linux/module.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
771fe6b9 | 28 | #include <linux/fb.h> |
5756b155 | 29 | #include <linux/pm_runtime.h> |
771fe6b9 | 30 | |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
35 | #include "radeon.h" |
36 | ||
760285e7 | 37 | #include <drm/drm_fb_helper.h> |
785b93ef | 38 | |
6a9ee8af DA |
39 | #include <linux/vga_switcheroo.h> |
40 | ||
38651674 | 41 | /* object hierarchy - |
3cf8bb1a JG |
42 | * this contains a helper + a radeon fb |
43 | * the helper contains a pointer to radeon framebuffer baseclass. | |
44 | */ | |
8be48d92 | 45 | struct radeon_fbdev { |
785b93ef | 46 | struct drm_fb_helper helper; |
38651674 | 47 | struct radeon_framebuffer rfb; |
38651674 | 48 | struct radeon_device *rdev; |
771fe6b9 JG |
49 | }; |
50 | ||
5756b155 AD |
51 | static int |
52 | radeonfb_open(struct fb_info *info, int user) | |
53 | { | |
54 | struct radeon_fbdev *rfbdev = info->par; | |
55 | struct radeon_device *rdev = rfbdev->rdev; | |
56 | int ret = pm_runtime_get_sync(rdev->ddev->dev); | |
57 | if (ret < 0 && ret != -EACCES) { | |
58 | pm_runtime_mark_last_busy(rdev->ddev->dev); | |
59 | pm_runtime_put_autosuspend(rdev->ddev->dev); | |
60 | return ret; | |
61 | } | |
62 | return 0; | |
63 | } | |
64 | ||
65 | static int | |
66 | radeonfb_release(struct fb_info *info, int user) | |
67 | { | |
68 | struct radeon_fbdev *rfbdev = info->par; | |
69 | struct radeon_device *rdev = rfbdev->rdev; | |
70 | ||
71 | pm_runtime_mark_last_busy(rdev->ddev->dev); | |
72 | pm_runtime_put_autosuspend(rdev->ddev->dev); | |
73 | return 0; | |
74 | } | |
75 | ||
771fe6b9 JG |
76 | static struct fb_ops radeonfb_ops = { |
77 | .owner = THIS_MODULE, | |
5756b155 AD |
78 | .fb_open = radeonfb_open, |
79 | .fb_release = radeonfb_release, | |
c88f9f0c | 80 | .fb_check_var = drm_fb_helper_check_var, |
0c6dadbe | 81 | .fb_set_par = drm_fb_helper_set_par, |
00450052 AT |
82 | .fb_fillrect = drm_fb_helper_cfb_fillrect, |
83 | .fb_copyarea = drm_fb_helper_cfb_copyarea, | |
84 | .fb_imageblit = drm_fb_helper_cfb_imageblit, | |
785b93ef DA |
85 | .fb_pan_display = drm_fb_helper_pan_display, |
86 | .fb_blank = drm_fb_helper_blank, | |
068143d3 | 87 | .fb_setcmap = drm_fb_helper_setcmap, |
4dd19b0d CB |
88 | .fb_debug_enter = drm_fb_helper_debug_enter, |
89 | .fb_debug_leave = drm_fb_helper_debug_leave, | |
771fe6b9 JG |
90 | }; |
91 | ||
771fe6b9 | 92 | |
ff72145b | 93 | int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled) |
771fe6b9 JG |
94 | { |
95 | int aligned = width; | |
e024e110 | 96 | int align_large = (ASIC_IS_AVIVO(rdev)) || tiled; |
771fe6b9 JG |
97 | int pitch_mask = 0; |
98 | ||
99 | switch (bpp / 8) { | |
100 | case 1: | |
101 | pitch_mask = align_large ? 255 : 127; | |
102 | break; | |
103 | case 2: | |
104 | pitch_mask = align_large ? 127 : 31; | |
105 | break; | |
106 | case 3: | |
107 | case 4: | |
108 | pitch_mask = align_large ? 63 : 15; | |
109 | break; | |
110 | } | |
111 | ||
112 | aligned += pitch_mask; | |
113 | aligned &= ~pitch_mask; | |
114 | return aligned; | |
115 | } | |
116 | ||
8be48d92 | 117 | static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj) |
771fe6b9 | 118 | { |
7e4d15d9 | 119 | struct radeon_bo *rbo = gem_to_radeon_bo(gobj); |
8be48d92 DA |
120 | int ret; |
121 | ||
122 | ret = radeon_bo_reserve(rbo, false); | |
123 | if (likely(ret == 0)) { | |
124 | radeon_bo_kunmap(rbo); | |
29d08b3e | 125 | radeon_bo_unpin(rbo); |
8be48d92 DA |
126 | radeon_bo_unreserve(rbo); |
127 | } | |
128 | drm_gem_object_unreference_unlocked(gobj); | |
129 | } | |
785b93ef | 130 | |
8be48d92 | 131 | static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev, |
308e5bcb | 132 | struct drm_mode_fb_cmd2 *mode_cmd, |
8be48d92 | 133 | struct drm_gem_object **gobj_p) |
771fe6b9 | 134 | { |
8be48d92 | 135 | struct radeon_device *rdev = rfbdev->rdev; |
771fe6b9 | 136 | struct drm_gem_object *gobj = NULL; |
4c788679 | 137 | struct radeon_bo *rbo = NULL; |
e024e110 | 138 | bool fb_tiled = false; /* useful for testing */ |
c88f9f0c | 139 | u32 tiling_flags = 0; |
8be48d92 DA |
140 | int ret; |
141 | int aligned_size, size; | |
e40b6fc8 | 142 | int height = mode_cmd->height; |
308e5bcb JB |
143 | u32 bpp, depth; |
144 | ||
248dbc23 | 145 | drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp); |
771fe6b9 | 146 | |
771fe6b9 | 147 | /* need to align pitch with crtc limits */ |
308e5bcb JB |
148 | mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp, |
149 | fb_tiled) * ((bpp + 1) / 8); | |
771fe6b9 | 150 | |
e40b6fc8 DA |
151 | if (rdev->family >= CHIP_R600) |
152 | height = ALIGN(mode_cmd->height, 8); | |
308e5bcb | 153 | size = mode_cmd->pitches[0] * height; |
771fe6b9 | 154 | aligned_size = ALIGN(size, PAGE_SIZE); |
771fe6b9 | 155 | ret = radeon_gem_object_create(rdev, aligned_size, 0, |
8be48d92 | 156 | RADEON_GEM_DOMAIN_VRAM, |
ed5cb43f | 157 | 0, true, &gobj); |
771fe6b9 | 158 | if (ret) { |
8be48d92 DA |
159 | printk(KERN_ERR "failed to allocate framebuffer (%d)\n", |
160 | aligned_size); | |
161 | return -ENOMEM; | |
771fe6b9 | 162 | } |
7e4d15d9 | 163 | rbo = gem_to_radeon_bo(gobj); |
771fe6b9 | 164 | |
e024e110 | 165 | if (fb_tiled) |
c88f9f0c MD |
166 | tiling_flags = RADEON_TILING_MACRO; |
167 | ||
168 | #ifdef __BIG_ENDIAN | |
435ddd92 | 169 | switch (bpp) { |
c88f9f0c MD |
170 | case 32: |
171 | tiling_flags |= RADEON_TILING_SWAP_32BIT; | |
172 | break; | |
173 | case 16: | |
174 | tiling_flags |= RADEON_TILING_SWAP_16BIT; | |
175 | default: | |
176 | break; | |
177 | } | |
178 | #endif | |
179 | ||
4c788679 JG |
180 | if (tiling_flags) { |
181 | ret = radeon_bo_set_tiling_flags(rbo, | |
8be48d92 | 182 | tiling_flags | RADEON_TILING_SURFACE, |
308e5bcb | 183 | mode_cmd->pitches[0]); |
4c788679 JG |
184 | if (ret) |
185 | dev_err(rdev->dev, "FB failed to set tiling flags\n"); | |
186 | } | |
8be48d92 | 187 | |
38651674 | 188 | |
4c788679 JG |
189 | ret = radeon_bo_reserve(rbo, false); |
190 | if (unlikely(ret != 0)) | |
191 | goto out_unref; | |
0349af70 MD |
192 | /* Only 27 bit offset for legacy CRTC */ |
193 | ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, | |
194 | ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, | |
195 | NULL); | |
4c788679 JG |
196 | if (ret) { |
197 | radeon_bo_unreserve(rbo); | |
198 | goto out_unref; | |
199 | } | |
200 | if (fb_tiled) | |
201 | radeon_bo_check_tiling(rbo, 0, 0); | |
8be48d92 | 202 | ret = radeon_bo_kmap(rbo, NULL); |
4c788679 | 203 | radeon_bo_unreserve(rbo); |
f92e93eb | 204 | if (ret) { |
f92e93eb JG |
205 | goto out_unref; |
206 | } | |
771fe6b9 | 207 | |
8be48d92 DA |
208 | *gobj_p = gobj; |
209 | return 0; | |
210 | out_unref: | |
211 | radeonfb_destroy_pinned_object(gobj); | |
212 | *gobj_p = NULL; | |
213 | return ret; | |
214 | } | |
215 | ||
cd5428a5 | 216 | static int radeonfb_create(struct drm_fb_helper *helper, |
8be48d92 DA |
217 | struct drm_fb_helper_surface_size *sizes) |
218 | { | |
a1d0280e FF |
219 | struct radeon_fbdev *rfbdev = |
220 | container_of(helper, struct radeon_fbdev, helper); | |
8be48d92 DA |
221 | struct radeon_device *rdev = rfbdev->rdev; |
222 | struct fb_info *info; | |
223 | struct drm_framebuffer *fb = NULL; | |
308e5bcb | 224 | struct drm_mode_fb_cmd2 mode_cmd; |
8be48d92 DA |
225 | struct drm_gem_object *gobj = NULL; |
226 | struct radeon_bo *rbo = NULL; | |
8be48d92 DA |
227 | int ret; |
228 | unsigned long tmp; | |
229 | ||
230 | mode_cmd.width = sizes->surface_width; | |
231 | mode_cmd.height = sizes->surface_height; | |
232 | ||
233 | /* avivo can't scanout real 24bpp */ | |
234 | if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev)) | |
235 | sizes->surface_bpp = 32; | |
236 | ||
308e5bcb JB |
237 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, |
238 | sizes->surface_depth); | |
771fe6b9 | 239 | |
8be48d92 | 240 | ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj); |
aaefcd42 DA |
241 | if (ret) { |
242 | DRM_ERROR("failed to create fbcon object %d\n", ret); | |
243 | return ret; | |
244 | } | |
245 | ||
7e4d15d9 | 246 | rbo = gem_to_radeon_bo(gobj); |
771fe6b9 | 247 | |
8be48d92 | 248 | /* okay we have an object now allocate the framebuffer */ |
00450052 AT |
249 | info = drm_fb_helper_alloc_fbi(helper); |
250 | if (IS_ERR(info)) { | |
251 | ret = PTR_ERR(info); | |
771fe6b9 JG |
252 | goto out_unref; |
253 | } | |
785b93ef | 254 | |
8be48d92 | 255 | info->par = rfbdev; |
d57c0edf | 256 | info->skip_vt_switch = true; |
771fe6b9 | 257 | |
aaefcd42 DA |
258 | ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj); |
259 | if (ret) { | |
8b513d0c | 260 | DRM_ERROR("failed to initialize framebuffer %d\n", ret); |
00450052 | 261 | goto out_destroy_fbi; |
aaefcd42 | 262 | } |
8be48d92 | 263 | |
38651674 DA |
264 | fb = &rfbdev->rfb.base; |
265 | ||
266 | /* setup helper */ | |
267 | rfbdev->helper.fb = fb; | |
38651674 | 268 | |
8be48d92 | 269 | memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo)); |
bf8e828b | 270 | |
771fe6b9 | 271 | strcpy(info->fix.id, "radeondrmfb"); |
785b93ef | 272 | |
01f2c773 | 273 | drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth); |
3632ef89 | 274 | |
8fd4bd22 | 275 | info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT; |
771fe6b9 | 276 | info->fbops = &radeonfb_ops; |
785b93ef | 277 | |
8be48d92 | 278 | tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start; |
f92e93eb | 279 | info->fix.smem_start = rdev->mc.aper_base + tmp; |
8be48d92 DA |
280 | info->fix.smem_len = radeon_bo_size(rbo); |
281 | info->screen_base = rbo->kptr; | |
282 | info->screen_size = radeon_bo_size(rbo); | |
785b93ef | 283 | |
38651674 | 284 | drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height); |
ed8f0d9e DA |
285 | |
286 | /* setup aperture base/size for vesafb takeover */ | |
1471ca9a | 287 | info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base; |
68d30596 | 288 | info->apertures->ranges[0].size = rdev->mc.aper_size; |
ed8f0d9e | 289 | |
fb2a99e1 | 290 | /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ |
4abe3520 | 291 | |
771fe6b9 JG |
292 | if (info->screen_base == NULL) { |
293 | ret = -ENOSPC; | |
00450052 | 294 | goto out_destroy_fbi; |
4abe3520 DA |
295 | } |
296 | ||
771fe6b9 JG |
297 | DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); |
298 | DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base); | |
8be48d92 | 299 | DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo)); |
771fe6b9 | 300 | DRM_INFO("fb depth is %d\n", fb->depth); |
01f2c773 | 301 | DRM_INFO(" pitch is %d\n", fb->pitches[0]); |
771fe6b9 | 302 | |
6a9ee8af | 303 | vga_switcheroo_client_fb_set(rdev->ddev->pdev, info); |
771fe6b9 JG |
304 | return 0; |
305 | ||
00450052 AT |
306 | out_destroy_fbi: |
307 | drm_fb_helper_release_fbi(helper); | |
771fe6b9 | 308 | out_unref: |
4c788679 | 309 | if (rbo) { |
8be48d92 | 310 | |
771fe6b9 | 311 | } |
f92e93eb | 312 | if (fb && ret) { |
623fc3b7 | 313 | drm_gem_object_unreference_unlocked(gobj); |
36206361 | 314 | drm_framebuffer_unregister_private(fb); |
771fe6b9 JG |
315 | drm_framebuffer_cleanup(fb); |
316 | kfree(fb); | |
317 | } | |
771fe6b9 JG |
318 | return ret; |
319 | } | |
320 | ||
eb1f8e4f | 321 | void radeon_fb_output_poll_changed(struct radeon_device *rdev) |
771fe6b9 | 322 | { |
e5f243bd AD |
323 | if (rdev->mode_info.rfbdev) |
324 | drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper); | |
771fe6b9 | 325 | } |
771fe6b9 | 326 | |
8be48d92 | 327 | static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev) |
771fe6b9 | 328 | { |
38651674 | 329 | struct radeon_framebuffer *rfb = &rfbdev->rfb; |
771fe6b9 | 330 | |
00450052 AT |
331 | drm_fb_helper_unregister_fbi(&rfbdev->helper); |
332 | drm_fb_helper_release_fbi(&rfbdev->helper); | |
771fe6b9 | 333 | |
8be48d92 | 334 | if (rfb->obj) { |
29d08b3e DA |
335 | radeonfb_destroy_pinned_object(rfb->obj); |
336 | rfb->obj = NULL; | |
771fe6b9 | 337 | } |
4abe3520 | 338 | drm_fb_helper_fini(&rfbdev->helper); |
36206361 | 339 | drm_framebuffer_unregister_private(&rfb->base); |
38651674 | 340 | drm_framebuffer_cleanup(&rfb->base); |
771fe6b9 | 341 | |
771fe6b9 JG |
342 | return 0; |
343 | } | |
785b93ef | 344 | |
3a493879 | 345 | static const struct drm_fb_helper_funcs radeon_fb_helper_funcs = { |
4abe3520 DA |
346 | .gamma_set = radeon_crtc_fb_gamma_set, |
347 | .gamma_get = radeon_crtc_fb_gamma_get, | |
cd5428a5 | 348 | .fb_probe = radeonfb_create, |
4abe3520 | 349 | }; |
38651674 DA |
350 | |
351 | int radeon_fbdev_init(struct radeon_device *rdev) | |
352 | { | |
8be48d92 | 353 | struct radeon_fbdev *rfbdev; |
4abe3520 | 354 | int bpp_sel = 32; |
5a79395b | 355 | int ret; |
4abe3520 | 356 | |
e5f243bd AD |
357 | /* don't enable fbdev if no connectors */ |
358 | if (list_empty(&rdev->ddev->mode_config.connector_list)) | |
359 | return 0; | |
360 | ||
4abe3520 DA |
361 | /* select 8 bpp console on RN50 or 16MB cards */ |
362 | if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024)) | |
363 | bpp_sel = 8; | |
8be48d92 DA |
364 | |
365 | rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL); | |
366 | if (!rfbdev) | |
367 | return -ENOMEM; | |
368 | ||
369 | rfbdev->rdev = rdev; | |
370 | rdev->mode_info.rfbdev = rfbdev; | |
10a23102 TR |
371 | |
372 | drm_fb_helper_prepare(rdev->ddev, &rfbdev->helper, | |
373 | &radeon_fb_helper_funcs); | |
8be48d92 | 374 | |
5a79395b CW |
375 | ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper, |
376 | rdev->num_crtc, | |
377 | RADEONFB_CONN_LIMIT); | |
01934c2a TR |
378 | if (ret) |
379 | goto free; | |
5a79395b | 380 | |
01934c2a TR |
381 | ret = drm_fb_helper_single_add_all_connectors(&rfbdev->helper); |
382 | if (ret) | |
383 | goto fini; | |
76a39dbf DV |
384 | |
385 | /* disable all the possible outputs/crtcs before entering KMS mode */ | |
386 | drm_helper_disable_unused_functions(rdev->ddev); | |
387 | ||
01934c2a TR |
388 | ret = drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); |
389 | if (ret) | |
390 | goto fini; | |
391 | ||
771fe6b9 | 392 | return 0; |
01934c2a TR |
393 | |
394 | fini: | |
395 | drm_fb_helper_fini(&rfbdev->helper); | |
396 | free: | |
397 | kfree(rfbdev); | |
398 | return ret; | |
38651674 DA |
399 | } |
400 | ||
401 | void radeon_fbdev_fini(struct radeon_device *rdev) | |
402 | { | |
8be48d92 DA |
403 | if (!rdev->mode_info.rfbdev) |
404 | return; | |
405 | ||
38651674 | 406 | radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev); |
8be48d92 | 407 | kfree(rdev->mode_info.rfbdev); |
38651674 DA |
408 | rdev->mode_info.rfbdev = NULL; |
409 | } | |
410 | ||
411 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state) | |
412 | { | |
e5f243bd AD |
413 | if (rdev->mode_info.rfbdev) |
414 | fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state); | |
38651674 DA |
415 | } |
416 | ||
38651674 DA |
417 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj) |
418 | { | |
e5f243bd AD |
419 | if (!rdev->mode_info.rfbdev) |
420 | return false; | |
421 | ||
7e4d15d9 | 422 | if (robj == gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj)) |
38651674 DA |
423 | return true; |
424 | return false; | |
771fe6b9 | 425 | } |
bb26270e DA |
426 | |
427 | void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector) | |
428 | { | |
e5f243bd AD |
429 | if (rdev->mode_info.rfbdev) |
430 | drm_fb_helper_add_one_connector(&rdev->mode_info.rfbdev->helper, connector); | |
bb26270e DA |
431 | } |
432 | ||
433 | void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector) | |
434 | { | |
e5f243bd AD |
435 | if (rdev->mode_info.rfbdev) |
436 | drm_fb_helper_remove_one_connector(&rdev->mode_info.rfbdev->helper, connector); | |
bb26270e | 437 | } |
8c70e1cd AD |
438 | |
439 | void radeon_fbdev_restore_mode(struct radeon_device *rdev) | |
440 | { | |
441 | struct radeon_fbdev *rfbdev = rdev->mode_info.rfbdev; | |
442 | struct drm_fb_helper *fb_helper; | |
443 | int ret; | |
444 | ||
445 | if (!rfbdev) | |
446 | return; | |
447 | ||
448 | fb_helper = &rfbdev->helper; | |
449 | ||
450 | ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper); | |
451 | if (ret) | |
452 | DRM_DEBUG("failed to restore crtc mode\n"); | |
453 | } |