[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>

#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/radeon_drm.h>
#include "radeon.h"

#include <drm/drm_fb_helper.h>

#include <linux/vga_switcheroo.h>

/* object hierarchy -
 * this contains a helper + a radeon fb
 * the helper contains a pointer to radeon framebuffer baseclass.
 */
struct radeon_fbdev {
	struct drm_fb_helper helper;
	struct radeon_framebuffer rfb;
	struct radeon_device *rdev;
};

static int
radeonfb_open(struct fb_info *info, int user)
{
	struct radeon_fbdev *rfbdev = info->par;
	struct radeon_device *rdev = rfbdev->rdev;
	int ret = pm_runtime_get_sync(rdev->ddev->dev);
	if (ret < 0 && ret != -EACCES) {
		pm_runtime_mark_last_busy(rdev->ddev->dev);
		pm_runtime_put_autosuspend(rdev->ddev->dev);
		return ret;
	}
	return 0;
}

static int
radeonfb_release(struct fb_info *info, int user)
{
	struct radeon_fbdev *rfbdev = info->par;
	struct radeon_device *rdev = rfbdev->rdev;

	pm_runtime_mark_last_busy(rdev->ddev->dev);
	pm_runtime_put_autosuspend(rdev->ddev->dev);
	return 0;
}

static struct fb_ops radeonfb_ops = {
	.owner = THIS_MODULE,
	.fb_open = radeonfb_open,
	.fb_release = radeonfb_release,
	.fb_check_var = drm_fb_helper_check_var,
	.fb_set_par = drm_fb_helper_set_par,
	.fb_fillrect = drm_fb_helper_cfb_fillrect,
	.fb_copyarea = drm_fb_helper_cfb_copyarea,
	.fb_imageblit = drm_fb_helper_cfb_imageblit,
	.fb_pan_display = drm_fb_helper_pan_display,
	.fb_blank = drm_fb_helper_blank,
	.fb_setcmap = drm_fb_helper_setcmap,
	.fb_debug_enter = drm_fb_helper_debug_enter,
	.fb_debug_leave = drm_fb_helper_debug_leave,
};


int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
{
	int aligned = width;
	int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
	int pitch_mask = 0;

	switch (bpp / 8) {
	case 1:
		pitch_mask = align_large ? 255 : 127;
		break;
	case 2:
		pitch_mask = align_large ? 127 : 31;
		break;
	case 3:
	case 4:
		pitch_mask = align_large ? 63 : 15;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned;
}

static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
{
	struct radeon_bo *rbo = gem_to_radeon_bo(gobj);
	int ret;

	ret = radeon_bo_reserve(rbo, false);
	if (likely(ret == 0)) {
		radeon_bo_kunmap(rbo);
		radeon_bo_unpin(rbo);
		radeon_bo_unreserve(rbo);
	}
	drm_gem_object_unreference_unlocked(gobj);
}

static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
					 struct drm_mode_fb_cmd2 *mode_cmd,
					 struct drm_gem_object **gobj_p)
{
	struct radeon_device *rdev = rfbdev->rdev;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0;
	int ret;
	int aligned_size, size;
	int height = mode_cmd->height;
	u32 bpp, depth;

	drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);

	/* need to align pitch with crtc limits */
	mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp,
						  fb_tiled) * ((bpp + 1) / 8);

	if (rdev->family >= CHIP_R600)
		height = ALIGN(mode_cmd->height, 8);
	size = mode_cmd->pitches[0] * height;
	aligned_size = ALIGN(size, PAGE_SIZE);
	ret = radeon_gem_object_create(rdev, aligned_size, 0,
				       RADEON_GEM_DOMAIN_VRAM,
				       0, true, &gobj);
	if (ret) {
		printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
		       aligned_size);
		return -ENOMEM;
	}
	rbo = gem_to_radeon_bo(gobj);

	if (fb_tiled)
		tiling_flags = RADEON_TILING_MACRO;

#ifdef __BIG_ENDIAN
	switch (bpp) {
	case 32:
		tiling_flags |= RADEON_TILING_SWAP_32BIT;
		break;
	case 16:
		tiling_flags |= RADEON_TILING_SWAP_16BIT;
	default:
		break;
	}
#endif

	if (tiling_flags) {
		ret = radeon_bo_set_tiling_flags(rbo,
						 tiling_flags | RADEON_TILING_SURFACE,
						 mode_cmd->pitches[0]);
		if (ret)
			dev_err(rdev->dev, "FB failed to set tiling flags\n");
	}


	ret = radeon_bo_reserve(rbo, false);
	if (unlikely(ret != 0))
		goto out_unref;
	/* Only 27 bit offset for legacy CRTC */
	ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
				       ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
				       NULL);
	if (ret) {
		radeon_bo_unreserve(rbo);
		goto out_unref;
	}
	if (fb_tiled)
		radeon_bo_check_tiling(rbo, 0, 0);
	ret = radeon_bo_kmap(rbo, NULL);
	radeon_bo_unreserve(rbo);
	if (ret) {
		goto out_unref;
	}

	*gobj_p = gobj;
	return 0;
out_unref:
	radeonfb_destroy_pinned_object(gobj);
	*gobj_p = NULL;
	return ret;
}

static int radeonfb_create(struct drm_fb_helper *helper,
			   struct drm_fb_helper_surface_size *sizes)
{
	struct radeon_fbdev *rfbdev =
		container_of(helper, struct radeon_fbdev, helper);
	struct radeon_device *rdev = rfbdev->rdev;
	struct fb_info *info;
	struct drm_framebuffer *fb = NULL;
	struct drm_mode_fb_cmd2 mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	int ret;
	unsigned long tmp;

	mode_cmd.width = sizes->surface_width;
	mode_cmd.height = sizes->surface_height;

	/* avivo can't scanout real 24bpp */
	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
		sizes->surface_bpp = 32;

	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
							  sizes->surface_depth);

	ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	if (ret) {
		DRM_ERROR("failed to create fbcon object %d\n", ret);
		return ret;
	}

	rbo = gem_to_radeon_bo(gobj);

	/* okay we have an object now allocate the framebuffer */
	info = drm_fb_helper_alloc_fbi(helper);
	if (IS_ERR(info)) {
		ret = PTR_ERR(info);
		goto out_unref;
	}

	info->par = rfbdev;
	info->skip_vt_switch = true;

	ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
	if (ret) {
		DRM_ERROR("failed to initialize framebuffer %d\n", ret);
		goto out_destroy_fbi;
	}

	fb = &rfbdev->rfb.base;

	/* setup helper */
	rfbdev->helper.fb = fb;

	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));

	strcpy(info->fix.id, "radeondrmfb");

	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);

	info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
	info->fbops = &radeonfb_ops;

	tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
	info->fix.smem_start = rdev->mc.aper_base + tmp;
	info->fix.smem_len = radeon_bo_size(rbo);
	info->screen_base = rbo->kptr;
	info->screen_size = radeon_bo_size(rbo);

	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
	info->apertures->ranges[0].size = rdev->mc.aper_size;

	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */

	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out_destroy_fbi;
	}

	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)rdev->mc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
	DRM_INFO("fb depth is %d\n", fb->depth);
	DRM_INFO("   pitch is %d\n", fb->pitches[0]);

	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
	return 0;

out_destroy_fbi:
	drm_fb_helper_release_fbi(helper);
out_unref:
	if (rbo) {

	}
	if (fb && ret) {
		drm_gem_object_unreference_unlocked(gobj);
		drm_framebuffer_unregister_private(fb);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	return ret;
}

void radeon_fb_output_poll_changed(struct radeon_device *rdev)
{
	if (rdev->mode_info.rfbdev)
		drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper);
}

static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev)
{
	struct radeon_framebuffer *rfb = &rfbdev->rfb;

	drm_fb_helper_unregister_fbi(&rfbdev->helper);
	drm_fb_helper_release_fbi(&rfbdev->helper);

	if (rfb->obj) {
		radeonfb_destroy_pinned_object(rfb->obj);
		rfb->obj = NULL;
	}
	drm_fb_helper_fini(&rfbdev->helper);
	drm_framebuffer_unregister_private(&rfb->base);
	drm_framebuffer_cleanup(&rfb->base);

	return 0;
}

static const struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	.gamma_set = radeon_crtc_fb_gamma_set,
	.gamma_get = radeon_crtc_fb_gamma_get,
	.fb_probe = radeonfb_create,
};

int radeon_fbdev_init(struct radeon_device *rdev)
{
	struct radeon_fbdev *rfbdev;
	int bpp_sel = 32;
	int ret;

	/* don't enable fbdev if no connectors */
	if (list_empty(&rdev->ddev->mode_config.connector_list))
		return 0;

	/* select 8 bpp console on RN50 or 16MB cards */
	if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
		bpp_sel = 8;

	rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
	if (!rfbdev)
		return -ENOMEM;

	rfbdev->rdev = rdev;
	rdev->mode_info.rfbdev = rfbdev;

	drm_fb_helper_prepare(rdev->ddev, &rfbdev->helper,
			      &radeon_fb_helper_funcs);

	ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
				 rdev->num_crtc,
				 RADEONFB_CONN_LIMIT);
	if (ret)
		goto free;

	ret = drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
	if (ret)
		goto fini;

	/* disable all the possible outputs/crtcs before entering KMS mode */
	drm_helper_disable_unused_functions(rdev->ddev);

	ret = drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	if (ret)
		goto fini;

	return 0;

fini:
	drm_fb_helper_fini(&rfbdev->helper);
free:
	kfree(rfbdev);
	return ret;
}

void radeon_fbdev_fini(struct radeon_device *rdev)
{
	if (!rdev->mode_info.rfbdev)
		return;

	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
	kfree(rdev->mode_info.rfbdev);
	rdev->mode_info.rfbdev = NULL;
}

void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
{
	if (rdev->mode_info.rfbdev)
		drm_fb_helper_set_suspend(&rdev->mode_info.rfbdev->helper, state);
}

bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
{
	if (!rdev->mode_info.rfbdev)
		return false;

	if (robj == gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj))
		return true;
	return false;
}

void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector)
{
	if (rdev->mode_info.rfbdev)
		drm_fb_helper_add_one_connector(&rdev->mode_info.rfbdev->helper, connector);
}

void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector)
{
	if (rdev->mode_info.rfbdev)
		drm_fb_helper_remove_one_connector(&rdev->mode_info.rfbdev->helper, connector);
}

void radeon_fbdev_restore_mode(struct radeon_device *rdev)
{
	struct radeon_fbdev *rfbdev = rdev->mode_info.rfbdev;
	struct drm_fb_helper *fb_helper;
	int ret;

	if (!rfbdev)
		return;

	fb_helper = &rfbdev->helper;

	ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
	if (ret)
		DRM_DEBUG("failed to restore crtc mode\n");
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
771fe6b9	26	#include <linux/module.h>
5a0e3ad6	27	#include <linux/slab.h>
5756b155	28	#include <linux/pm_runtime.h>
771fe6b9	29
760285e7 DH	30	#include <drm/drmP.h>
	31	#include <drm/drm_crtc.h>
	32	#include <drm/drm_crtc_helper.h>
	33	#include <drm/radeon_drm.h>
771fe6b9 JG	34	#include "radeon.h"
771fe6b9 JG	35
760285e7	36	#include <drm/drm_fb_helper.h>
785b93ef	37
6a9ee8af DA	38	#include <linux/vga_switcheroo.h>
6a9ee8af DA	39
38651674	40	/* object hierarchy -
3cf8bb1a JG	41	* this contains a helper + a radeon fb
	42	* the helper contains a pointer to radeon framebuffer baseclass.
	43	*/
8be48d92	44	struct radeon_fbdev {
785b93ef	45	struct drm_fb_helper helper;
38651674	46	struct radeon_framebuffer rfb;
38651674	47	struct radeon_device *rdev;
771fe6b9 JG	48	};
771fe6b9 JG	49
5756b155 AD	50	static int
	51	radeonfb_open(struct fb_info *info, int user)
	52	{
	53	struct radeon_fbdev *rfbdev = info->par;
	54	struct radeon_device *rdev = rfbdev->rdev;
	55	int ret = pm_runtime_get_sync(rdev->ddev->dev);
	56	if (ret < 0 && ret != -EACCES) {
	57	pm_runtime_mark_last_busy(rdev->ddev->dev);
	58	pm_runtime_put_autosuspend(rdev->ddev->dev);
	59	return ret;
	60	}
	61	return 0;
	62	}
	63
	64	static int
	65	radeonfb_release(struct fb_info *info, int user)
	66	{
	67	struct radeon_fbdev *rfbdev = info->par;
	68	struct radeon_device *rdev = rfbdev->rdev;
	69
	70	pm_runtime_mark_last_busy(rdev->ddev->dev);
	71	pm_runtime_put_autosuspend(rdev->ddev->dev);
	72	return 0;
	73	}
	74
771fe6b9 JG	75	static struct fb_ops radeonfb_ops = {
771fe6b9 JG	76	.owner = THIS_MODULE,
5756b155 AD	77	.fb_open = radeonfb_open,
5756b155 AD	78	.fb_release = radeonfb_release,
c88f9f0c	79	.fb_check_var = drm_fb_helper_check_var,
0c6dadbe	80	.fb_set_par = drm_fb_helper_set_par,
00450052 AT	81	.fb_fillrect = drm_fb_helper_cfb_fillrect,
	82	.fb_copyarea = drm_fb_helper_cfb_copyarea,
	83	.fb_imageblit = drm_fb_helper_cfb_imageblit,
785b93ef DA	84	.fb_pan_display = drm_fb_helper_pan_display,
785b93ef DA	85	.fb_blank = drm_fb_helper_blank,
068143d3	86	.fb_setcmap = drm_fb_helper_setcmap,
4dd19b0d CB	87	.fb_debug_enter = drm_fb_helper_debug_enter,
4dd19b0d CB	88	.fb_debug_leave = drm_fb_helper_debug_leave,
771fe6b9 JG	89	};
771fe6b9 JG	90
771fe6b9	91
ff72145b	92	int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
771fe6b9 JG	93	{
771fe6b9 JG	94	int aligned = width;
e024e110	95	int align_large = (ASIC_IS_AVIVO(rdev)) \|\| tiled;
771fe6b9 JG	96	int pitch_mask = 0;
	97
	98	switch (bpp / 8) {
	99	case 1:
	100	pitch_mask = align_large ? 255 : 127;
	101	break;
	102	case 2:
	103	pitch_mask = align_large ? 127 : 31;
	104	break;
	105	case 3:
	106	case 4:
	107	pitch_mask = align_large ? 63 : 15;
	108	break;
	109	}
	110
	111	aligned += pitch_mask;
	112	aligned &= ~pitch_mask;
	113	return aligned;
	114	}
	115
8be48d92	116	static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
771fe6b9	117	{
7e4d15d9	118	struct radeon_bo *rbo = gem_to_radeon_bo(gobj);
8be48d92 DA	119	int ret;
	120
	121	ret = radeon_bo_reserve(rbo, false);
	122	if (likely(ret == 0)) {
	123	radeon_bo_kunmap(rbo);
29d08b3e	124	radeon_bo_unpin(rbo);
8be48d92 DA	125	radeon_bo_unreserve(rbo);
	126	}
	127	drm_gem_object_unreference_unlocked(gobj);
	128	}
785b93ef	129
8be48d92	130	static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
308e5bcb	131	struct drm_mode_fb_cmd2 *mode_cmd,
8be48d92	132	struct drm_gem_object **gobj_p)
771fe6b9	133	{
8be48d92	134	struct radeon_device *rdev = rfbdev->rdev;
771fe6b9	135	struct drm_gem_object *gobj = NULL;
4c788679	136	struct radeon_bo *rbo = NULL;
e024e110	137	bool fb_tiled = false; /* useful for testing */
c88f9f0c	138	u32 tiling_flags = 0;
8be48d92 DA	139	int ret;
8be48d92 DA	140	int aligned_size, size;
e40b6fc8	141	int height = mode_cmd->height;
308e5bcb JB	142	u32 bpp, depth;
308e5bcb JB	143
248dbc23	144	drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);
771fe6b9	145
771fe6b9	146	/* need to align pitch with crtc limits */
308e5bcb JB	147	mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp,
308e5bcb JB	148	fb_tiled) * ((bpp + 1) / 8);
771fe6b9	149
e40b6fc8 DA	150	if (rdev->family >= CHIP_R600)
e40b6fc8 DA	151	height = ALIGN(mode_cmd->height, 8);
308e5bcb	152	size = mode_cmd->pitches[0] * height;
771fe6b9	153	aligned_size = ALIGN(size, PAGE_SIZE);
771fe6b9	154	ret = radeon_gem_object_create(rdev, aligned_size, 0,
8be48d92	155	RADEON_GEM_DOMAIN_VRAM,
ed5cb43f	156	0, true, &gobj);
771fe6b9	157	if (ret) {
8be48d92 DA	158	printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
	159	aligned_size);
	160	return -ENOMEM;
771fe6b9	161	}
7e4d15d9	162	rbo = gem_to_radeon_bo(gobj);
771fe6b9	163
e024e110	164	if (fb_tiled)
c88f9f0c MD	165	tiling_flags = RADEON_TILING_MACRO;
	166
	167	#ifdef __BIG_ENDIAN
435ddd92	168	switch (bpp) {
c88f9f0c MD	169	case 32:
	170	tiling_flags \|= RADEON_TILING_SWAP_32BIT;
	171	break;
	172	case 16:
	173	tiling_flags \|= RADEON_TILING_SWAP_16BIT;
	174	default:
	175	break;
	176	}
	177	#endif
	178
4c788679 JG	179	if (tiling_flags) {
4c788679 JG	180	ret = radeon_bo_set_tiling_flags(rbo,
8be48d92	181	tiling_flags \| RADEON_TILING_SURFACE,
308e5bcb	182	mode_cmd->pitches[0]);
4c788679 JG	183	if (ret)
	184	dev_err(rdev->dev, "FB failed to set tiling flags\n");
	185	}
8be48d92	186
38651674	187
4c788679 JG	188	ret = radeon_bo_reserve(rbo, false);
	189	if (unlikely(ret != 0))
	190	goto out_unref;
0349af70 MD	191	/* Only 27 bit offset for legacy CRTC */
	192	ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
	193	ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
	194	NULL);
4c788679 JG	195	if (ret) {
	196	radeon_bo_unreserve(rbo);
	197	goto out_unref;
	198	}
	199	if (fb_tiled)
	200	radeon_bo_check_tiling(rbo, 0, 0);
8be48d92	201	ret = radeon_bo_kmap(rbo, NULL);
4c788679	202	radeon_bo_unreserve(rbo);
f92e93eb	203	if (ret) {
f92e93eb JG	204	goto out_unref;
f92e93eb JG	205	}
771fe6b9	206
8be48d92 DA	207	*gobj_p = gobj;
	208	return 0;
	209	out_unref:
	210	radeonfb_destroy_pinned_object(gobj);
	211	*gobj_p = NULL;
	212	return ret;
	213	}
	214
cd5428a5	215	static int radeonfb_create(struct drm_fb_helper *helper,
8be48d92 DA	216	struct drm_fb_helper_surface_size *sizes)
8be48d92 DA	217	{
a1d0280e FF	218	struct radeon_fbdev *rfbdev =
a1d0280e FF	219	container_of(helper, struct radeon_fbdev, helper);
8be48d92 DA	220	struct radeon_device *rdev = rfbdev->rdev;
	221	struct fb_info *info;
	222	struct drm_framebuffer *fb = NULL;
308e5bcb	223	struct drm_mode_fb_cmd2 mode_cmd;
8be48d92 DA	224	struct drm_gem_object *gobj = NULL;
8be48d92 DA	225	struct radeon_bo *rbo = NULL;
8be48d92 DA	226	int ret;
	227	unsigned long tmp;
	228
	229	mode_cmd.width = sizes->surface_width;
	230	mode_cmd.height = sizes->surface_height;
	231
	232	/* avivo can't scanout real 24bpp */
	233	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
	234	sizes->surface_bpp = 32;
	235
308e5bcb JB	236	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
308e5bcb JB	237	sizes->surface_depth);
771fe6b9	238
8be48d92	239	ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
aaefcd42 DA	240	if (ret) {
	241	DRM_ERROR("failed to create fbcon object %d\n", ret);
	242	return ret;
	243	}
	244
7e4d15d9	245	rbo = gem_to_radeon_bo(gobj);
771fe6b9	246
8be48d92	247	/* okay we have an object now allocate the framebuffer */
00450052 AT	248	info = drm_fb_helper_alloc_fbi(helper);
	249	if (IS_ERR(info)) {
	250	ret = PTR_ERR(info);
771fe6b9 JG	251	goto out_unref;
771fe6b9 JG	252	}
785b93ef	253
8be48d92	254	info->par = rfbdev;
d57c0edf	255	info->skip_vt_switch = true;
771fe6b9	256
aaefcd42 DA	257	ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
aaefcd42 DA	258	if (ret) {
8b513d0c	259	DRM_ERROR("failed to initialize framebuffer %d\n", ret);
00450052	260	goto out_destroy_fbi;
aaefcd42	261	}
8be48d92	262
38651674 DA	263	fb = &rfbdev->rfb.base;
	264
	265	/* setup helper */
	266	rfbdev->helper.fb = fb;
38651674	267
8be48d92	268	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));
bf8e828b	269
771fe6b9	270	strcpy(info->fix.id, "radeondrmfb");
785b93ef	271
01f2c773	272	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
3632ef89	273
8fd4bd22	274	info->flags = FBINFO_DEFAULT \| FBINFO_CAN_FORCE_OUTPUT;
771fe6b9	275	info->fbops = &radeonfb_ops;
785b93ef	276
8be48d92	277	tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
f92e93eb	278	info->fix.smem_start = rdev->mc.aper_base + tmp;
8be48d92 DA	279	info->fix.smem_len = radeon_bo_size(rbo);
	280	info->screen_base = rbo->kptr;
	281	info->screen_size = radeon_bo_size(rbo);
785b93ef	282
38651674	283	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
ed8f0d9e DA	284
ed8f0d9e DA	285	/* setup aperture base/size for vesafb takeover */
1471ca9a	286	info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
68d30596	287	info->apertures->ranges[0].size = rdev->mc.aper_size;
ed8f0d9e	288
fb2a99e1	289	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
4abe3520	290
771fe6b9 JG	291	if (info->screen_base == NULL) {
771fe6b9 JG	292	ret = -ENOSPC;
00450052	293	goto out_destroy_fbi;
4abe3520 DA	294	}
4abe3520 DA	295
771fe6b9 JG	296	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
771fe6b9 JG	297	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
8be48d92	298	DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
771fe6b9	299	DRM_INFO("fb depth is %d\n", fb->depth);
01f2c773	300	DRM_INFO(" pitch is %d\n", fb->pitches[0]);
771fe6b9	301
6a9ee8af	302	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
771fe6b9 JG	303	return 0;
771fe6b9 JG	304
00450052 AT	305	out_destroy_fbi:
00450052 AT	306	drm_fb_helper_release_fbi(helper);
771fe6b9	307	out_unref:
4c788679	308	if (rbo) {
8be48d92	309
771fe6b9	310	}
f92e93eb	311	if (fb && ret) {
623fc3b7	312	drm_gem_object_unreference_unlocked(gobj);
36206361	313	drm_framebuffer_unregister_private(fb);
771fe6b9 JG	314	drm_framebuffer_cleanup(fb);
	315	kfree(fb);
	316	}
771fe6b9 JG	317	return ret;
	318	}
	319
eb1f8e4f	320	void radeon_fb_output_poll_changed(struct radeon_device *rdev)
771fe6b9	321	{
e5f243bd AD	322	if (rdev->mode_info.rfbdev)
e5f243bd AD	323	drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper);
771fe6b9	324	}
771fe6b9	325
8be48d92	326	static int radeon_fbdev_destroy(struct drm_device dev, struct radeon_fbdev rfbdev)
771fe6b9	327	{
38651674	328	struct radeon_framebuffer *rfb = &rfbdev->rfb;
771fe6b9	329
00450052 AT	330	drm_fb_helper_unregister_fbi(&rfbdev->helper);
00450052 AT	331	drm_fb_helper_release_fbi(&rfbdev->helper);
771fe6b9	332
8be48d92	333	if (rfb->obj) {
29d08b3e DA	334	radeonfb_destroy_pinned_object(rfb->obj);
29d08b3e DA	335	rfb->obj = NULL;
771fe6b9	336	}
4abe3520	337	drm_fb_helper_fini(&rfbdev->helper);
36206361	338	drm_framebuffer_unregister_private(&rfb->base);
38651674	339	drm_framebuffer_cleanup(&rfb->base);
771fe6b9	340
771fe6b9 JG	341	return 0;
771fe6b9 JG	342	}
785b93ef	343
3a493879	344	static const struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
4abe3520 DA	345	.gamma_set = radeon_crtc_fb_gamma_set,
4abe3520 DA	346	.gamma_get = radeon_crtc_fb_gamma_get,
cd5428a5	347	.fb_probe = radeonfb_create,
4abe3520	348	};
38651674 DA	349
	350	int radeon_fbdev_init(struct radeon_device *rdev)
	351	{
8be48d92	352	struct radeon_fbdev *rfbdev;
4abe3520	353	int bpp_sel = 32;
5a79395b	354	int ret;
4abe3520	355
e5f243bd AD	356	/* don't enable fbdev if no connectors */
	357	if (list_empty(&rdev->ddev->mode_config.connector_list))
	358	return 0;
	359
4abe3520 DA	360	/* select 8 bpp console on RN50 or 16MB cards */
	361	if (ASIC_IS_RN50(rdev) \|\| rdev->mc.real_vram_size <= (3210241024))
	362	bpp_sel = 8;
8be48d92 DA	363
	364	rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
	365	if (!rfbdev)
	366	return -ENOMEM;
	367
	368	rfbdev->rdev = rdev;
	369	rdev->mode_info.rfbdev = rfbdev;
10a23102 TR	370
	371	drm_fb_helper_prepare(rdev->ddev, &rfbdev->helper,
	372	&radeon_fb_helper_funcs);
8be48d92	373
5a79395b CW	374	ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
	375	rdev->num_crtc,
	376	RADEONFB_CONN_LIMIT);
01934c2a TR	377	if (ret)
01934c2a TR	378	goto free;
5a79395b	379
01934c2a TR	380	ret = drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
	381	if (ret)
	382	goto fini;
76a39dbf DV	383
	384	/* disable all the possible outputs/crtcs before entering KMS mode */
	385	drm_helper_disable_unused_functions(rdev->ddev);
	386
01934c2a TR	387	ret = drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	388	if (ret)
	389	goto fini;
	390
771fe6b9	391	return 0;
01934c2a TR	392
	393	fini:
	394	drm_fb_helper_fini(&rfbdev->helper);
	395	free:
	396	kfree(rfbdev);
	397	return ret;
38651674 DA	398	}
	399
	400	void radeon_fbdev_fini(struct radeon_device *rdev)
	401	{
8be48d92 DA	402	if (!rdev->mode_info.rfbdev)
	403	return;
	404
38651674	405	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
8be48d92	406	kfree(rdev->mode_info.rfbdev);
38651674 DA	407	rdev->mode_info.rfbdev = NULL;
	408	}
	409
	410	void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
	411	{
e5f243bd	412	if (rdev->mode_info.rfbdev)
9db7d2b2	413	drm_fb_helper_set_suspend(&rdev->mode_info.rfbdev->helper, state);
38651674 DA	414	}
38651674 DA	415
38651674 DA	416	bool radeon_fbdev_robj_is_fb(struct radeon_device rdev, struct radeon_bo robj)
38651674 DA	417	{
e5f243bd AD	418	if (!rdev->mode_info.rfbdev)
	419	return false;
	420
7e4d15d9	421	if (robj == gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj))
38651674 DA	422	return true;
38651674 DA	423	return false;
771fe6b9	424	}
bb26270e DA	425
	426	void radeon_fb_add_connector(struct radeon_device rdev, struct drm_connector connector)
	427	{
e5f243bd AD	428	if (rdev->mode_info.rfbdev)
e5f243bd AD	429	drm_fb_helper_add_one_connector(&rdev->mode_info.rfbdev->helper, connector);
bb26270e DA	430	}
	431
	432	void radeon_fb_remove_connector(struct radeon_device rdev, struct drm_connector connector)
	433	{
e5f243bd AD	434	if (rdev->mode_info.rfbdev)
e5f243bd AD	435	drm_fb_helper_remove_one_connector(&rdev->mode_info.rfbdev->helper, connector);
bb26270e	436	}
8c70e1cd AD	437
	438	void radeon_fbdev_restore_mode(struct radeon_device *rdev)
	439	{
	440	struct radeon_fbdev *rfbdev = rdev->mode_info.rfbdev;
	441	struct drm_fb_helper *fb_helper;
	442	int ret;
	443
	444	if (!rfbdev)
	445	return;
	446
	447	fb_helper = &rfbdev->helper;
	448
	449	ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
	450	if (ret)
	451	DRM_DEBUG("failed to restore crtc mode\n");
	452	}