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1da177e4 LT |
1 | /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- |
2 | * | |
3 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
5 | * All rights reserved. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the "Software"), | |
9 | * to deal in the Software without restriction, including without limitation | |
10 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
11 | * and/or sell copies of the Software, and to permit persons to whom the | |
12 | * Software is furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the next | |
15 | * paragraph) shall be included in all copies or substantial portions of the | |
16 | * Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
24 | * DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | * Authors: | |
27 | * Kevin E. Martin <martin@valinux.com> | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | */ | |
30 | ||
31 | #ifndef __RADEON_DRV_H__ | |
32 | #define __RADEON_DRV_H__ | |
33 | ||
34 | /* General customization: | |
35 | */ | |
36 | ||
37 | #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." | |
38 | ||
39 | #define DRIVER_NAME "radeon" | |
40 | #define DRIVER_DESC "ATI Radeon" | |
c0beb2a7 | 41 | #define DRIVER_DATE "20080528" |
1da177e4 LT |
42 | |
43 | /* Interface history: | |
44 | * | |
45 | * 1.1 - ?? | |
46 | * 1.2 - Add vertex2 ioctl (keith) | |
47 | * - Add stencil capability to clear ioctl (gareth, keith) | |
48 | * - Increase MAX_TEXTURE_LEVELS (brian) | |
49 | * 1.3 - Add cmdbuf ioctl (keith) | |
50 | * - Add support for new radeon packets (keith) | |
51 | * - Add getparam ioctl (keith) | |
52 | * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). | |
53 | * 1.4 - Add scratch registers to get_param ioctl. | |
54 | * 1.5 - Add r200 packets to cmdbuf ioctl | |
55 | * - Add r200 function to init ioctl | |
56 | * - Add 'scalar2' instruction to cmdbuf | |
57 | * 1.6 - Add static GART memory manager | |
58 | * Add irq handler (won't be turned on unless X server knows to) | |
59 | * Add irq ioctls and irq_active getparam. | |
60 | * Add wait command for cmdbuf ioctl | |
61 | * Add GART offset query for getparam | |
62 | * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] | |
63 | * and R200_PP_CUBIC_OFFSET_F1_[0..5]. | |
64 | * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and | |
65 | * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) | |
66 | * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) | |
67 | * Add 'GET' queries for starting additional clients on different VT's. | |
68 | * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. | |
69 | * Add texture rectangle support for r100. | |
70 | * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which | |
b5e89ed5 | 71 | * clients use to tell the DRM where they think the framebuffer is |
1da177e4 LT |
72 | * located in the card's address space |
73 | * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color | |
74 | * and GL_EXT_blend_[func|equation]_separate on r200 | |
75 | * 1.12- Add R300 CP microcode support - this just loads the CP on r300 | |
d985c108 | 76 | * (No 3D support yet - just microcode loading). |
1da177e4 LT |
77 | * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters |
78 | * - Add hyperz support, add hyperz flags to clear ioctl. | |
79 | * 1.14- Add support for color tiling | |
80 | * - Add R100/R200 surface allocation/free support | |
81 | * 1.15- Add support for texture micro tiling | |
82 | * - Add support for r100 cube maps | |
83 | * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear | |
84 | * texture filtering on r200 | |
414ed537 | 85 | * 1.17- Add initial support for R300 (3D). |
9d17601c DA |
86 | * 1.18- Add support for GL_ATI_fragment_shader, new packets |
87 | * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces | |
88 | * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR | |
89 | * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) | |
ea98a92f | 90 | * 1.19- Add support for gart table in FB memory and PCIE r300 |
d985c108 DA |
91 | * 1.20- Add support for r300 texrect |
92 | * 1.21- Add support for card type getparam | |
4e5e2e25 | 93 | * 1.22- Add support for texture cache flushes (R300_TX_CNTL) |
d5ea702f | 94 | * 1.23- Add new radeon memory map work from benh |
ee4621f0 | 95 | * 1.24- Add general-purpose packet for manipulating scratch registers (r300) |
d6fece05 DA |
96 | * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, |
97 | * new packet type) | |
f2b04cd2 DA |
98 | * 1.26- Add support for variable size PCI(E) gart aperture |
99 | * 1.27- Add support for IGP GART | |
ddbee333 | 100 | * 1.28- Add support for VBL on CRTC2 |
c0beb2a7 | 101 | * 1.29- R500 3D cmd buffer support |
1da177e4 LT |
102 | */ |
103 | #define DRIVER_MAJOR 1 | |
c0beb2a7 | 104 | #define DRIVER_MINOR 29 |
1da177e4 LT |
105 | #define DRIVER_PATCHLEVEL 0 |
106 | ||
1da177e4 LT |
107 | /* |
108 | * Radeon chip families | |
109 | */ | |
110 | enum radeon_family { | |
111 | CHIP_R100, | |
1da177e4 | 112 | CHIP_RV100, |
dfab1154 | 113 | CHIP_RS100, |
1da177e4 LT |
114 | CHIP_RV200, |
115 | CHIP_RS200, | |
dfab1154 | 116 | CHIP_R200, |
1da177e4 | 117 | CHIP_RV250, |
dfab1154 | 118 | CHIP_RS300, |
1da177e4 LT |
119 | CHIP_RV280, |
120 | CHIP_R300, | |
414ed537 | 121 | CHIP_R350, |
1da177e4 | 122 | CHIP_RV350, |
dfab1154 | 123 | CHIP_RV380, |
414ed537 | 124 | CHIP_R420, |
edc6f389 | 125 | CHIP_R423, |
dfab1154 | 126 | CHIP_RV410, |
b2ceddfa | 127 | CHIP_RS400, |
45e51905 | 128 | CHIP_RS480, |
60f92683 | 129 | CHIP_RS690, |
f0738e92 | 130 | CHIP_RS740, |
3d5e2c13 DA |
131 | CHIP_RV515, |
132 | CHIP_R520, | |
133 | CHIP_RV530, | |
134 | CHIP_RV560, | |
135 | CHIP_RV570, | |
136 | CHIP_R580, | |
1da177e4 LT |
137 | CHIP_LAST, |
138 | }; | |
139 | ||
140 | enum radeon_cp_microcode_version { | |
141 | UCODE_R100, | |
142 | UCODE_R200, | |
143 | UCODE_R300, | |
144 | }; | |
145 | ||
146 | /* | |
147 | * Chip flags | |
148 | */ | |
149 | enum radeon_chip_flags { | |
54a56ac5 DA |
150 | RADEON_FAMILY_MASK = 0x0000ffffUL, |
151 | RADEON_FLAGS_MASK = 0xffff0000UL, | |
152 | RADEON_IS_MOBILITY = 0x00010000UL, | |
153 | RADEON_IS_IGP = 0x00020000UL, | |
154 | RADEON_SINGLE_CRTC = 0x00040000UL, | |
155 | RADEON_IS_AGP = 0x00080000UL, | |
156 | RADEON_HAS_HIERZ = 0x00100000UL, | |
157 | RADEON_IS_PCIE = 0x00200000UL, | |
158 | RADEON_NEW_MEMMAP = 0x00400000UL, | |
159 | RADEON_IS_PCI = 0x00800000UL, | |
f2b04cd2 | 160 | RADEON_IS_IGPGART = 0x01000000UL, |
1da177e4 LT |
161 | }; |
162 | ||
d5ea702f DA |
163 | #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ |
164 | DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR)) | |
d985c108 DA |
165 | #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) |
166 | ||
1da177e4 | 167 | typedef struct drm_radeon_freelist { |
b5e89ed5 | 168 | unsigned int age; |
056219e2 | 169 | struct drm_buf *buf; |
b5e89ed5 DA |
170 | struct drm_radeon_freelist *next; |
171 | struct drm_radeon_freelist *prev; | |
1da177e4 LT |
172 | } drm_radeon_freelist_t; |
173 | ||
174 | typedef struct drm_radeon_ring_buffer { | |
175 | u32 *start; | |
176 | u32 *end; | |
177 | int size; | |
178 | int size_l2qw; | |
179 | ||
576cc458 RS |
180 | int rptr_update; /* Double Words */ |
181 | int rptr_update_l2qw; /* log2 Quad Words */ | |
182 | ||
183 | int fetch_size; /* Double Words */ | |
184 | int fetch_size_l2ow; /* log2 Oct Words */ | |
185 | ||
1da177e4 LT |
186 | u32 tail; |
187 | u32 tail_mask; | |
188 | int space; | |
189 | ||
190 | int high_mark; | |
191 | } drm_radeon_ring_buffer_t; | |
192 | ||
193 | typedef struct drm_radeon_depth_clear_t { | |
194 | u32 rb3d_cntl; | |
195 | u32 rb3d_zstencilcntl; | |
196 | u32 se_cntl; | |
197 | } drm_radeon_depth_clear_t; | |
198 | ||
199 | struct drm_radeon_driver_file_fields { | |
200 | int64_t radeon_fb_delta; | |
201 | }; | |
202 | ||
203 | struct mem_block { | |
204 | struct mem_block *next; | |
205 | struct mem_block *prev; | |
206 | int start; | |
207 | int size; | |
6c340eac | 208 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
209 | }; |
210 | ||
211 | struct radeon_surface { | |
212 | int refcount; | |
213 | u32 lower; | |
214 | u32 upper; | |
215 | u32 flags; | |
216 | }; | |
217 | ||
218 | struct radeon_virt_surface { | |
219 | int surface_index; | |
220 | u32 lower; | |
221 | u32 upper; | |
222 | u32 flags; | |
6c340eac | 223 | struct drm_file *file_priv; |
1da177e4 LT |
224 | }; |
225 | ||
54f961a6 JG |
226 | #define RADEON_FLUSH_EMITED (1 < 0) |
227 | #define RADEON_PURGE_EMITED (1 < 1) | |
228 | ||
1da177e4 LT |
229 | typedef struct drm_radeon_private { |
230 | drm_radeon_ring_buffer_t ring; | |
231 | drm_radeon_sarea_t *sarea_priv; | |
232 | ||
233 | u32 fb_location; | |
d5ea702f DA |
234 | u32 fb_size; |
235 | int new_memmap; | |
1da177e4 LT |
236 | |
237 | int gart_size; | |
238 | u32 gart_vm_start; | |
239 | unsigned long gart_buffers_offset; | |
240 | ||
241 | int cp_mode; | |
242 | int cp_running; | |
243 | ||
b5e89ed5 DA |
244 | drm_radeon_freelist_t *head; |
245 | drm_radeon_freelist_t *tail; | |
1da177e4 LT |
246 | int last_buf; |
247 | volatile u32 *scratch; | |
248 | int writeback_works; | |
249 | ||
250 | int usec_timeout; | |
251 | ||
252 | int microcode_version; | |
253 | ||
1da177e4 LT |
254 | struct { |
255 | u32 boxes; | |
256 | int freelist_timeouts; | |
257 | int freelist_loops; | |
258 | int requested_bufs; | |
259 | int last_frame_reads; | |
260 | int last_clear_reads; | |
261 | int clears; | |
262 | int texture_uploads; | |
263 | } stats; | |
264 | ||
265 | int do_boxes; | |
266 | int page_flipping; | |
1da177e4 LT |
267 | |
268 | u32 color_fmt; | |
269 | unsigned int front_offset; | |
270 | unsigned int front_pitch; | |
271 | unsigned int back_offset; | |
272 | unsigned int back_pitch; | |
273 | ||
274 | u32 depth_fmt; | |
275 | unsigned int depth_offset; | |
276 | unsigned int depth_pitch; | |
277 | ||
278 | u32 front_pitch_offset; | |
279 | u32 back_pitch_offset; | |
280 | u32 depth_pitch_offset; | |
281 | ||
282 | drm_radeon_depth_clear_t depth_clear; | |
b5e89ed5 | 283 | |
1da177e4 LT |
284 | unsigned long ring_offset; |
285 | unsigned long ring_rptr_offset; | |
286 | unsigned long buffers_offset; | |
287 | unsigned long gart_textures_offset; | |
288 | ||
289 | drm_local_map_t *sarea; | |
290 | drm_local_map_t *mmio; | |
291 | drm_local_map_t *cp_ring; | |
292 | drm_local_map_t *ring_rptr; | |
293 | drm_local_map_t *gart_textures; | |
294 | ||
295 | struct mem_block *gart_heap; | |
296 | struct mem_block *fb_heap; | |
297 | ||
298 | /* SW interrupt */ | |
b5e89ed5 DA |
299 | wait_queue_head_t swi_queue; |
300 | atomic_t swi_emitted; | |
ddbee333 DA |
301 | int vblank_crtc; |
302 | uint32_t irq_enable_reg; | |
303 | int irq_enabled; | |
c0beb2a7 | 304 | uint32_t r500_disp_irq_reg; |
1da177e4 LT |
305 | |
306 | struct radeon_surface surfaces[RADEON_MAX_SURFACES]; | |
b5e89ed5 | 307 | struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; |
1da177e4 | 308 | |
b5e89ed5 | 309 | unsigned long pcigart_offset; |
f2b04cd2 | 310 | unsigned int pcigart_offset_set; |
55910517 | 311 | struct drm_ati_pcigart_info gart_info; |
ea98a92f | 312 | |
ee4621f0 DA |
313 | u32 scratch_ages[5]; |
314 | ||
1da177e4 LT |
315 | /* starting from here on, data is preserved accross an open */ |
316 | uint32_t flags; /* see radeon_chip_flags */ | |
7fc86860 | 317 | unsigned long fb_aper_offset; |
5b92c404 AD |
318 | |
319 | int num_gb_pipes; | |
54f961a6 | 320 | int track_flush; |
1da177e4 LT |
321 | } drm_radeon_private_t; |
322 | ||
323 | typedef struct drm_radeon_buf_priv { | |
324 | u32 age; | |
325 | } drm_radeon_buf_priv_t; | |
326 | ||
b3a83639 DA |
327 | typedef struct drm_radeon_kcmd_buffer { |
328 | int bufsz; | |
329 | char *buf; | |
330 | int nbox; | |
c60ce623 | 331 | struct drm_clip_rect __user *boxes; |
b3a83639 DA |
332 | } drm_radeon_kcmd_buffer_t; |
333 | ||
689b9d74 | 334 | extern int radeon_no_wb; |
c153f45f | 335 | extern struct drm_ioctl_desc radeon_ioctls[]; |
b3a83639 DA |
336 | extern int radeon_max_ioctl; |
337 | ||
1d6bb8e5 MCA |
338 | /* Check whether the given hardware address is inside the framebuffer or the |
339 | * GART area. | |
340 | */ | |
341 | static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, | |
342 | u64 off) | |
343 | { | |
344 | u32 fb_start = dev_priv->fb_location; | |
345 | u32 fb_end = fb_start + dev_priv->fb_size - 1; | |
346 | u32 gart_start = dev_priv->gart_vm_start; | |
347 | u32 gart_end = gart_start + dev_priv->gart_size - 1; | |
348 | ||
349 | return ((off >= fb_start && off <= fb_end) || | |
350 | (off >= gart_start && off <= gart_end)); | |
351 | } | |
352 | ||
1da177e4 | 353 | /* radeon_cp.c */ |
c153f45f EA |
354 | extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); |
355 | extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); | |
356 | extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); | |
357 | extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); | |
358 | extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); | |
359 | extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); | |
360 | extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); | |
361 | extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); | |
362 | extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); | |
3d5e2c13 | 363 | extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); |
1da177e4 | 364 | |
84b1fd10 | 365 | extern void radeon_freelist_reset(struct drm_device * dev); |
056219e2 | 366 | extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); |
1da177e4 | 367 | |
b5e89ed5 | 368 | extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); |
1da177e4 | 369 | |
b5e89ed5 | 370 | extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); |
1da177e4 LT |
371 | |
372 | extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); | |
836cf046 | 373 | extern int radeon_presetup(struct drm_device *dev); |
1da177e4 LT |
374 | extern int radeon_driver_postcleanup(struct drm_device *dev); |
375 | ||
c153f45f EA |
376 | extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); |
377 | extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); | |
378 | extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); | |
b5e89ed5 | 379 | extern void radeon_mem_takedown(struct mem_block **heap); |
6c340eac EA |
380 | extern void radeon_mem_release(struct drm_file *file_priv, |
381 | struct mem_block *heap); | |
1da177e4 LT |
382 | |
383 | /* radeon_irq.c */ | |
0a3e67a4 | 384 | extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); |
c153f45f EA |
385 | extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); |
386 | extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); | |
b5e89ed5 | 387 | |
84b1fd10 | 388 | extern void radeon_do_release(struct drm_device * dev); |
0a3e67a4 JB |
389 | extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); |
390 | extern int radeon_enable_vblank(struct drm_device *dev, int crtc); | |
391 | extern void radeon_disable_vblank(struct drm_device *dev, int crtc); | |
b5e89ed5 | 392 | extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); |
84b1fd10 | 393 | extern void radeon_driver_irq_preinstall(struct drm_device * dev); |
0a3e67a4 | 394 | extern int radeon_driver_irq_postinstall(struct drm_device *dev); |
84b1fd10 | 395 | extern void radeon_driver_irq_uninstall(struct drm_device * dev); |
7ecabc53 | 396 | extern void radeon_enable_interrupt(struct drm_device *dev); |
84b1fd10 DA |
397 | extern int radeon_vblank_crtc_get(struct drm_device *dev); |
398 | extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); | |
1da177e4 | 399 | |
22eae947 DA |
400 | extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); |
401 | extern int radeon_driver_unload(struct drm_device *dev); | |
402 | extern int radeon_driver_firstopen(struct drm_device *dev); | |
0a3e67a4 JB |
403 | extern void radeon_driver_preclose(struct drm_device *dev, |
404 | struct drm_file *file_priv); | |
405 | extern void radeon_driver_postclose(struct drm_device *dev, | |
406 | struct drm_file *file_priv); | |
84b1fd10 | 407 | extern void radeon_driver_lastclose(struct drm_device * dev); |
0a3e67a4 JB |
408 | extern int radeon_driver_open(struct drm_device *dev, |
409 | struct drm_file *file_priv); | |
9a186645 DA |
410 | extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, |
411 | unsigned long arg); | |
412 | ||
414ed537 | 413 | /* r300_cmdbuf.c */ |
3d5e2c13 | 414 | extern void r300_init_reg_flags(struct drm_device *dev); |
414ed537 | 415 | |
0a3e67a4 | 416 | extern int r300_do_cp_cmdbuf(struct drm_device *dev, |
6c340eac | 417 | struct drm_file *file_priv, |
0a3e67a4 | 418 | drm_radeon_kcmd_buffer_t *cmdbuf); |
414ed537 | 419 | |
1da177e4 LT |
420 | /* Flags for stats.boxes |
421 | */ | |
422 | #define RADEON_BOX_DMA_IDLE 0x1 | |
423 | #define RADEON_BOX_RING_FULL 0x2 | |
424 | #define RADEON_BOX_FLIP 0x4 | |
425 | #define RADEON_BOX_WAIT_IDLE 0x8 | |
426 | #define RADEON_BOX_TEXTURE_LOAD 0x10 | |
427 | ||
1da177e4 LT |
428 | /* Register definitions, register access macros and drmAddMap constants |
429 | * for Radeon kernel driver. | |
430 | */ | |
431 | ||
432 | #define RADEON_AGP_COMMAND 0x0f60 | |
d985c108 DA |
433 | #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ |
434 | # define RADEON_AGP_ENABLE (1<<8) | |
1da177e4 LT |
435 | #define RADEON_AUX_SCISSOR_CNTL 0x26f0 |
436 | # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) | |
437 | # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) | |
438 | # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) | |
439 | # define RADEON_SCISSOR_0_ENABLE (1 << 28) | |
440 | # define RADEON_SCISSOR_1_ENABLE (1 << 29) | |
441 | # define RADEON_SCISSOR_2_ENABLE (1 << 30) | |
442 | ||
edc6f389 AD |
443 | /* |
444 | * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) | |
445 | * don't have an explicit bus mastering disable bit. It's handled | |
446 | * by the PCI D-states. PMI_BM_DIS disables D-state bus master | |
447 | * handling, not bus mastering itself. | |
448 | */ | |
1da177e4 | 449 | #define RADEON_BUS_CNTL 0x0030 |
4e270e9b | 450 | /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ |
1da177e4 | 451 | # define RADEON_BUS_MASTER_DIS (1 << 6) |
4e270e9b AD |
452 | /* rs600/rs690/rs740 */ |
453 | # define RS600_BUS_MASTER_DIS (1 << 14) | |
454 | # define RS600_MSI_REARM (1 << 20) | |
455 | /* see RS400_MSI_REARM in AIC_CNTL for rs480 */ | |
edc6f389 AD |
456 | |
457 | #define RADEON_BUS_CNTL1 0x0034 | |
458 | # define RADEON_PMI_BM_DIS (1 << 2) | |
459 | # define RADEON_PMI_INT_DIS (1 << 3) | |
460 | ||
461 | #define RV370_BUS_CNTL 0x004c | |
462 | # define RV370_PMI_BM_DIS (1 << 5) | |
463 | # define RV370_PMI_INT_DIS (1 << 6) | |
464 | ||
465 | #define RADEON_MSI_REARM_EN 0x0160 | |
466 | /* rv370/rv380, rv410, r423/r430/r480, r5xx */ | |
467 | # define RV370_MSI_REARM_EN (1 << 0) | |
1da177e4 LT |
468 | |
469 | #define RADEON_CLOCK_CNTL_DATA 0x000c | |
470 | # define RADEON_PLL_WR_EN (1 << 7) | |
471 | #define RADEON_CLOCK_CNTL_INDEX 0x0008 | |
472 | #define RADEON_CONFIG_APER_SIZE 0x0108 | |
d985c108 | 473 | #define RADEON_CONFIG_MEMSIZE 0x00f8 |
1da177e4 LT |
474 | #define RADEON_CRTC_OFFSET 0x0224 |
475 | #define RADEON_CRTC_OFFSET_CNTL 0x0228 | |
476 | # define RADEON_CRTC_TILE_EN (1 << 15) | |
477 | # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) | |
478 | #define RADEON_CRTC2_OFFSET 0x0324 | |
479 | #define RADEON_CRTC2_OFFSET_CNTL 0x0328 | |
480 | ||
ea98a92f DA |
481 | #define RADEON_PCIE_INDEX 0x0030 |
482 | #define RADEON_PCIE_DATA 0x0034 | |
483 | #define RADEON_PCIE_TX_GART_CNTL 0x10 | |
bc5f4523 | 484 | # define RADEON_PCIE_TX_GART_EN (1 << 0) |
2735977b AD |
485 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) |
486 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) | |
487 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) | |
488 | # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) | |
489 | # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) | |
490 | # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) | |
491 | # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) | |
ea98a92f DA |
492 | #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 |
493 | #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 | |
bc5f4523 | 494 | #define RADEON_PCIE_TX_GART_BASE 0x13 |
ea98a92f DA |
495 | #define RADEON_PCIE_TX_GART_START_LO 0x14 |
496 | #define RADEON_PCIE_TX_GART_START_HI 0x15 | |
497 | #define RADEON_PCIE_TX_GART_END_LO 0x16 | |
498 | #define RADEON_PCIE_TX_GART_END_HI 0x17 | |
499 | ||
45e51905 AD |
500 | #define RS480_NB_MC_INDEX 0x168 |
501 | # define RS480_NB_MC_IND_WR_EN (1 << 8) | |
502 | #define RS480_NB_MC_DATA 0x16c | |
f2b04cd2 | 503 | |
60f92683 MC |
504 | #define RS690_MC_INDEX 0x78 |
505 | # define RS690_MC_INDEX_MASK 0x1ff | |
506 | # define RS690_MC_INDEX_WR_EN (1 << 9) | |
507 | # define RS690_MC_INDEX_WR_ACK 0x7f | |
508 | #define RS690_MC_DATA 0x7c | |
509 | ||
2735977b | 510 | /* MC indirect registers */ |
45e51905 AD |
511 | #define RS480_MC_MISC_CNTL 0x18 |
512 | # define RS480_DISABLE_GTW (1 << 1) | |
2735977b | 513 | /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ |
45e51905 | 514 | # define RS480_GART_INDEX_REG_EN (1 << 12) |
2735977b | 515 | # define RS690_BLOCK_GFX_D3_EN (1 << 14) |
45e51905 AD |
516 | #define RS480_K8_FB_LOCATION 0x1e |
517 | #define RS480_GART_FEATURE_ID 0x2b | |
518 | # define RS480_HANG_EN (1 << 11) | |
519 | # define RS480_TLB_ENABLE (1 << 18) | |
520 | # define RS480_P2P_ENABLE (1 << 19) | |
521 | # define RS480_GTW_LAC_EN (1 << 25) | |
522 | # define RS480_2LEVEL_GART (0 << 30) | |
523 | # define RS480_1LEVEL_GART (1 << 30) | |
524 | # define RS480_PDC_EN (1 << 31) | |
525 | #define RS480_GART_BASE 0x2c | |
526 | #define RS480_GART_CACHE_CNTRL 0x2e | |
527 | # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ | |
528 | #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 | |
529 | # define RS480_GART_EN (1 << 0) | |
530 | # define RS480_VA_SIZE_32MB (0 << 1) | |
531 | # define RS480_VA_SIZE_64MB (1 << 1) | |
532 | # define RS480_VA_SIZE_128MB (2 << 1) | |
533 | # define RS480_VA_SIZE_256MB (3 << 1) | |
534 | # define RS480_VA_SIZE_512MB (4 << 1) | |
535 | # define RS480_VA_SIZE_1GB (5 << 1) | |
536 | # define RS480_VA_SIZE_2GB (6 << 1) | |
537 | #define RS480_AGP_MODE_CNTL 0x39 | |
538 | # define RS480_POST_GART_Q_SIZE (1 << 18) | |
539 | # define RS480_NONGART_SNOOP (1 << 19) | |
540 | # define RS480_AGP_RD_BUF_SIZE (1 << 20) | |
541 | # define RS480_REQ_TYPE_SNOOP_SHIFT 22 | |
542 | # define RS480_REQ_TYPE_SNOOP_MASK 0x3 | |
543 | # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) | |
544 | #define RS480_MC_MISC_UMA_CNTL 0x5f | |
545 | #define RS480_MC_MCLK_CNTL 0x7a | |
546 | #define RS480_MC_UMA_DUALCH_CNTL 0x86 | |
2735977b | 547 | |
60f92683 MC |
548 | #define RS690_MC_FB_LOCATION 0x100 |
549 | #define RS690_MC_AGP_LOCATION 0x101 | |
550 | #define RS690_MC_AGP_BASE 0x102 | |
3722bfc6 | 551 | #define RS690_MC_AGP_BASE_2 0x103 |
60f92683 | 552 | |
3d5e2c13 | 553 | #define R520_MC_IND_INDEX 0x70 |
2735977b | 554 | #define R520_MC_IND_WR_EN (1 << 24) |
3d5e2c13 DA |
555 | #define R520_MC_IND_DATA 0x74 |
556 | ||
557 | #define RV515_MC_FB_LOCATION 0x01 | |
558 | #define RV515_MC_AGP_LOCATION 0x02 | |
70b13d51 DA |
559 | #define RV515_MC_AGP_BASE 0x03 |
560 | #define RV515_MC_AGP_BASE_2 0x04 | |
3d5e2c13 DA |
561 | |
562 | #define R520_MC_FB_LOCATION 0x04 | |
563 | #define R520_MC_AGP_LOCATION 0x05 | |
70b13d51 DA |
564 | #define R520_MC_AGP_BASE 0x06 |
565 | #define R520_MC_AGP_BASE_2 0x07 | |
3d5e2c13 | 566 | |
414ed537 DA |
567 | #define RADEON_MPP_TB_CONFIG 0x01c0 |
568 | #define RADEON_MEM_CNTL 0x0140 | |
569 | #define RADEON_MEM_SDRAM_MODE_REG 0x0158 | |
45e51905 AD |
570 | #define RADEON_AGP_BASE_2 0x015c /* r200+ only */ |
571 | #define RS480_AGP_BASE_2 0x0164 | |
414ed537 DA |
572 | #define RADEON_AGP_BASE 0x0170 |
573 | ||
5b92c404 AD |
574 | /* pipe config regs */ |
575 | #define R400_GB_PIPE_SELECT 0x402c | |
576 | #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ | |
577 | #define R500_SU_REG_DEST 0x42c8 | |
578 | #define R300_GB_TILE_CONFIG 0x4018 | |
579 | # define R300_ENABLE_TILING (1 << 0) | |
580 | # define R300_PIPE_COUNT_RV350 (0 << 1) | |
581 | # define R300_PIPE_COUNT_R300 (3 << 1) | |
582 | # define R300_PIPE_COUNT_R420_3P (6 << 1) | |
583 | # define R300_PIPE_COUNT_R420 (7 << 1) | |
584 | # define R300_TILE_SIZE_8 (0 << 4) | |
585 | # define R300_TILE_SIZE_16 (1 << 4) | |
586 | # define R300_TILE_SIZE_32 (2 << 4) | |
587 | # define R300_SUBPIXEL_1_12 (0 << 16) | |
588 | # define R300_SUBPIXEL_1_16 (1 << 16) | |
589 | #define R300_DST_PIPE_CONFIG 0x170c | |
590 | # define R300_PIPE_AUTO_CONFIG (1 << 31) | |
591 | #define R300_RB2D_DSTCACHE_MODE 0x3428 | |
592 | # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) | |
593 | # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) | |
594 | ||
1da177e4 LT |
595 | #define RADEON_RB3D_COLOROFFSET 0x1c40 |
596 | #define RADEON_RB3D_COLORPITCH 0x1c48 | |
597 | ||
3e14a286 MD |
598 | #define RADEON_SRC_X_Y 0x1590 |
599 | ||
1da177e4 LT |
600 | #define RADEON_DP_GUI_MASTER_CNTL 0x146c |
601 | # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) | |
602 | # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) | |
603 | # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) | |
604 | # define RADEON_GMC_BRUSH_NONE (15 << 4) | |
605 | # define RADEON_GMC_DST_16BPP (4 << 8) | |
606 | # define RADEON_GMC_DST_24BPP (5 << 8) | |
607 | # define RADEON_GMC_DST_32BPP (6 << 8) | |
608 | # define RADEON_GMC_DST_DATATYPE_SHIFT 8 | |
609 | # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) | |
610 | # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) | |
611 | # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) | |
612 | # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) | |
613 | # define RADEON_GMC_WR_MSK_DIS (1 << 30) | |
614 | # define RADEON_ROP3_S 0x00cc0000 | |
615 | # define RADEON_ROP3_P 0x00f00000 | |
616 | #define RADEON_DP_WRITE_MASK 0x16cc | |
3e14a286 | 617 | #define RADEON_SRC_PITCH_OFFSET 0x1428 |
1da177e4 LT |
618 | #define RADEON_DST_PITCH_OFFSET 0x142c |
619 | #define RADEON_DST_PITCH_OFFSET_C 0x1c80 | |
620 | # define RADEON_DST_TILE_LINEAR (0 << 30) | |
621 | # define RADEON_DST_TILE_MACRO (1 << 30) | |
622 | # define RADEON_DST_TILE_MICRO (2 << 30) | |
623 | # define RADEON_DST_TILE_BOTH (3 << 30) | |
624 | ||
625 | #define RADEON_SCRATCH_REG0 0x15e0 | |
626 | #define RADEON_SCRATCH_REG1 0x15e4 | |
627 | #define RADEON_SCRATCH_REG2 0x15e8 | |
628 | #define RADEON_SCRATCH_REG3 0x15ec | |
629 | #define RADEON_SCRATCH_REG4 0x15f0 | |
630 | #define RADEON_SCRATCH_REG5 0x15f4 | |
631 | #define RADEON_SCRATCH_UMSK 0x0770 | |
632 | #define RADEON_SCRATCH_ADDR 0x0774 | |
633 | ||
634 | #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) | |
635 | ||
636 | #define GET_SCRATCH( x ) (dev_priv->writeback_works \ | |
637 | ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ | |
638 | : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) | |
639 | ||
1da177e4 LT |
640 | #define RADEON_GEN_INT_CNTL 0x0040 |
641 | # define RADEON_CRTC_VBLANK_MASK (1 << 0) | |
ddbee333 | 642 | # define RADEON_CRTC2_VBLANK_MASK (1 << 9) |
1da177e4 LT |
643 | # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) |
644 | # define RADEON_SW_INT_ENABLE (1 << 25) | |
645 | ||
646 | #define RADEON_GEN_INT_STATUS 0x0044 | |
647 | # define RADEON_CRTC_VBLANK_STAT (1 << 0) | |
bc5f4523 | 648 | # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) |
ddbee333 | 649 | # define RADEON_CRTC2_VBLANK_STAT (1 << 9) |
bc5f4523 | 650 | # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) |
1da177e4 LT |
651 | # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) |
652 | # define RADEON_SW_INT_TEST (1 << 25) | |
bc5f4523 | 653 | # define RADEON_SW_INT_TEST_ACK (1 << 25) |
1da177e4 | 654 | # define RADEON_SW_INT_FIRE (1 << 26) |
0a3e67a4 | 655 | # define R500_DISPLAY_INT_STATUS (1 << 0) |
1da177e4 LT |
656 | |
657 | #define RADEON_HOST_PATH_CNTL 0x0130 | |
658 | # define RADEON_HDP_SOFT_RESET (1 << 26) | |
659 | # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) | |
660 | # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) | |
661 | ||
662 | #define RADEON_ISYNC_CNTL 0x1724 | |
663 | # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) | |
664 | # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) | |
665 | # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) | |
666 | # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) | |
667 | # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) | |
668 | # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) | |
669 | ||
670 | #define RADEON_RBBM_GUICNTL 0x172c | |
671 | # define RADEON_HOST_DATA_SWAP_NONE (0 << 0) | |
672 | # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) | |
673 | # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) | |
674 | # define RADEON_HOST_DATA_SWAP_HDW (3 << 0) | |
675 | ||
676 | #define RADEON_MC_AGP_LOCATION 0x014c | |
677 | #define RADEON_MC_FB_LOCATION 0x0148 | |
678 | #define RADEON_MCLK_CNTL 0x0012 | |
679 | # define RADEON_FORCEON_MCLKA (1 << 16) | |
680 | # define RADEON_FORCEON_MCLKB (1 << 17) | |
681 | # define RADEON_FORCEON_YCLKA (1 << 18) | |
682 | # define RADEON_FORCEON_YCLKB (1 << 19) | |
683 | # define RADEON_FORCEON_MC (1 << 20) | |
684 | # define RADEON_FORCEON_AIC (1 << 21) | |
685 | ||
686 | #define RADEON_PP_BORDER_COLOR_0 0x1d40 | |
687 | #define RADEON_PP_BORDER_COLOR_1 0x1d44 | |
688 | #define RADEON_PP_BORDER_COLOR_2 0x1d48 | |
689 | #define RADEON_PP_CNTL 0x1c38 | |
690 | # define RADEON_SCISSOR_ENABLE (1 << 1) | |
691 | #define RADEON_PP_LUM_MATRIX 0x1d00 | |
692 | #define RADEON_PP_MISC 0x1c14 | |
693 | #define RADEON_PP_ROT_MATRIX_0 0x1d58 | |
694 | #define RADEON_PP_TXFILTER_0 0x1c54 | |
695 | #define RADEON_PP_TXOFFSET_0 0x1c5c | |
696 | #define RADEON_PP_TXFILTER_1 0x1c6c | |
697 | #define RADEON_PP_TXFILTER_2 0x1c84 | |
698 | ||
5e35eff1 AD |
699 | #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ |
700 | #define R300_DSTCACHE_CTLSTAT 0x1714 | |
701 | # define R300_RB2D_DC_FLUSH (3 << 0) | |
702 | # define R300_RB2D_DC_FREE (3 << 2) | |
703 | # define R300_RB2D_DC_FLUSH_ALL 0xf | |
704 | # define R300_RB2D_DC_BUSY (1 << 31) | |
1da177e4 LT |
705 | #define RADEON_RB3D_CNTL 0x1c3c |
706 | # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) | |
707 | # define RADEON_PLANE_MASK_ENABLE (1 << 1) | |
708 | # define RADEON_DITHER_ENABLE (1 << 2) | |
709 | # define RADEON_ROUND_ENABLE (1 << 3) | |
710 | # define RADEON_SCALE_DITHER_ENABLE (1 << 4) | |
711 | # define RADEON_DITHER_INIT (1 << 5) | |
712 | # define RADEON_ROP_ENABLE (1 << 6) | |
713 | # define RADEON_STENCIL_ENABLE (1 << 7) | |
714 | # define RADEON_Z_ENABLE (1 << 8) | |
715 | # define RADEON_ZBLOCK16 (1 << 15) | |
716 | #define RADEON_RB3D_DEPTHOFFSET 0x1c24 | |
717 | #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 | |
718 | #define RADEON_RB3D_DEPTHPITCH 0x1c28 | |
719 | #define RADEON_RB3D_PLANEMASK 0x1d84 | |
720 | #define RADEON_RB3D_STENCILREFMASK 0x1d7c | |
721 | #define RADEON_RB3D_ZCACHE_MODE 0x3250 | |
722 | #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 | |
723 | # define RADEON_RB3D_ZC_FLUSH (1 << 0) | |
724 | # define RADEON_RB3D_ZC_FREE (1 << 2) | |
725 | # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 | |
726 | # define RADEON_RB3D_ZC_BUSY (1 << 31) | |
259434ac AD |
727 | #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 |
728 | # define R300_ZC_FLUSH (1 << 0) | |
729 | # define R300_ZC_FREE (1 << 1) | |
259434ac | 730 | # define R300_ZC_BUSY (1 << 31) |
b9b603dd MD |
731 | #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c |
732 | # define RADEON_RB3D_DC_FLUSH (3 << 0) | |
733 | # define RADEON_RB3D_DC_FREE (3 << 2) | |
734 | # define RADEON_RB3D_DC_FLUSH_ALL 0xf | |
735 | # define RADEON_RB3D_DC_BUSY (1 << 31) | |
259434ac | 736 | #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c |
54f961a6 JG |
737 | # define R300_RB3D_DC_FLUSH (2 << 0) |
738 | # define R300_RB3D_DC_FREE (2 << 2) | |
259434ac | 739 | # define R300_RB3D_DC_FINISH (1 << 4) |
1da177e4 LT |
740 | #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c |
741 | # define RADEON_Z_TEST_MASK (7 << 4) | |
742 | # define RADEON_Z_TEST_ALWAYS (7 << 4) | |
743 | # define RADEON_Z_HIERARCHY_ENABLE (1 << 8) | |
744 | # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) | |
745 | # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) | |
746 | # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) | |
747 | # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) | |
748 | # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) | |
749 | # define RADEON_FORCE_Z_DIRTY (1 << 29) | |
750 | # define RADEON_Z_WRITE_ENABLE (1 << 30) | |
751 | # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) | |
752 | #define RADEON_RBBM_SOFT_RESET 0x00f0 | |
753 | # define RADEON_SOFT_RESET_CP (1 << 0) | |
754 | # define RADEON_SOFT_RESET_HI (1 << 1) | |
755 | # define RADEON_SOFT_RESET_SE (1 << 2) | |
756 | # define RADEON_SOFT_RESET_RE (1 << 3) | |
757 | # define RADEON_SOFT_RESET_PP (1 << 4) | |
758 | # define RADEON_SOFT_RESET_E2 (1 << 5) | |
759 | # define RADEON_SOFT_RESET_RB (1 << 6) | |
760 | # define RADEON_SOFT_RESET_HDP (1 << 7) | |
576cc458 RS |
761 | /* |
762 | * 6:0 Available slots in the FIFO | |
763 | * 8 Host Interface active | |
764 | * 9 CP request active | |
765 | * 10 FIFO request active | |
766 | * 11 Host Interface retry active | |
767 | * 12 CP retry active | |
768 | * 13 FIFO retry active | |
769 | * 14 FIFO pipeline busy | |
770 | * 15 Event engine busy | |
771 | * 16 CP command stream busy | |
772 | * 17 2D engine busy | |
773 | * 18 2D portion of render backend busy | |
774 | * 20 3D setup engine busy | |
775 | * 26 GA engine busy | |
776 | * 27 CBA 2D engine busy | |
777 | * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or | |
778 | * command stream queue not empty or Ring Buffer not empty | |
779 | */ | |
1da177e4 | 780 | #define RADEON_RBBM_STATUS 0x0e40 |
576cc458 RS |
781 | /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ |
782 | /* #define RADEON_RBBM_STATUS 0x1740 */ | |
783 | /* bits 6:0 are dword slots available in the cmd fifo */ | |
1da177e4 | 784 | # define RADEON_RBBM_FIFOCNT_MASK 0x007f |
576cc458 RS |
785 | # define RADEON_HIRQ_ON_RBB (1 << 8) |
786 | # define RADEON_CPRQ_ON_RBB (1 << 9) | |
787 | # define RADEON_CFRQ_ON_RBB (1 << 10) | |
788 | # define RADEON_HIRQ_IN_RTBUF (1 << 11) | |
789 | # define RADEON_CPRQ_IN_RTBUF (1 << 12) | |
790 | # define RADEON_CFRQ_IN_RTBUF (1 << 13) | |
791 | # define RADEON_PIPE_BUSY (1 << 14) | |
792 | # define RADEON_ENG_EV_BUSY (1 << 15) | |
793 | # define RADEON_CP_CMDSTRM_BUSY (1 << 16) | |
794 | # define RADEON_E2_BUSY (1 << 17) | |
795 | # define RADEON_RB2D_BUSY (1 << 18) | |
796 | # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ | |
797 | # define RADEON_VAP_BUSY (1 << 20) | |
798 | # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ | |
799 | # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ | |
800 | # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ | |
801 | # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ | |
802 | # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ | |
803 | # define RADEON_GA_BUSY (1 << 26) | |
804 | # define RADEON_CBA2D_BUSY (1 << 27) | |
805 | # define RADEON_RBBM_ACTIVE (1 << 31) | |
1da177e4 LT |
806 | #define RADEON_RE_LINE_PATTERN 0x1cd0 |
807 | #define RADEON_RE_MISC 0x26c4 | |
808 | #define RADEON_RE_TOP_LEFT 0x26c0 | |
809 | #define RADEON_RE_WIDTH_HEIGHT 0x1c44 | |
810 | #define RADEON_RE_STIPPLE_ADDR 0x1cc8 | |
811 | #define RADEON_RE_STIPPLE_DATA 0x1ccc | |
812 | ||
813 | #define RADEON_SCISSOR_TL_0 0x1cd8 | |
814 | #define RADEON_SCISSOR_BR_0 0x1cdc | |
815 | #define RADEON_SCISSOR_TL_1 0x1ce0 | |
816 | #define RADEON_SCISSOR_BR_1 0x1ce4 | |
817 | #define RADEON_SCISSOR_TL_2 0x1ce8 | |
818 | #define RADEON_SCISSOR_BR_2 0x1cec | |
819 | #define RADEON_SE_COORD_FMT 0x1c50 | |
820 | #define RADEON_SE_CNTL 0x1c4c | |
821 | # define RADEON_FFACE_CULL_CW (0 << 0) | |
822 | # define RADEON_BFACE_SOLID (3 << 1) | |
823 | # define RADEON_FFACE_SOLID (3 << 3) | |
824 | # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) | |
825 | # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) | |
826 | # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) | |
827 | # define RADEON_ALPHA_SHADE_FLAT (1 << 10) | |
828 | # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) | |
829 | # define RADEON_SPECULAR_SHADE_FLAT (1 << 12) | |
830 | # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) | |
831 | # define RADEON_FOG_SHADE_FLAT (1 << 14) | |
832 | # define RADEON_FOG_SHADE_GOURAUD (2 << 14) | |
833 | # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) | |
834 | # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) | |
835 | # define RADEON_VTX_PIX_CENTER_OGL (1 << 27) | |
836 | # define RADEON_ROUND_MODE_TRUNC (0 << 28) | |
837 | # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) | |
838 | #define RADEON_SE_CNTL_STATUS 0x2140 | |
839 | #define RADEON_SE_LINE_WIDTH 0x1db8 | |
840 | #define RADEON_SE_VPORT_XSCALE 0x1d98 | |
841 | #define RADEON_SE_ZBIAS_FACTOR 0x1db0 | |
842 | #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 | |
843 | #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 | |
844 | #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 | |
845 | # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 | |
846 | # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 | |
847 | #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 | |
848 | #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 | |
849 | # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 | |
850 | #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C | |
851 | #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 | |
852 | #define RADEON_SURFACE_ACCESS_CLR 0x0bfc | |
853 | #define RADEON_SURFACE_CNTL 0x0b00 | |
854 | # define RADEON_SURF_TRANSLATION_DIS (1 << 8) | |
855 | # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) | |
856 | # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) | |
857 | # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) | |
858 | # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) | |
859 | # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) | |
860 | # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) | |
861 | # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) | |
862 | # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) | |
863 | #define RADEON_SURFACE0_INFO 0x0b0c | |
864 | # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) | |
865 | # define RADEON_SURF_TILE_MODE_MASK (3 << 16) | |
866 | # define RADEON_SURF_TILE_MODE_MACRO (0 << 16) | |
867 | # define RADEON_SURF_TILE_MODE_MICRO (1 << 16) | |
868 | # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) | |
869 | # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) | |
870 | #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 | |
871 | #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 | |
872 | # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) | |
873 | #define RADEON_SURFACE1_INFO 0x0b1c | |
874 | #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 | |
875 | #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 | |
876 | #define RADEON_SURFACE2_INFO 0x0b2c | |
877 | #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 | |
878 | #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 | |
879 | #define RADEON_SURFACE3_INFO 0x0b3c | |
880 | #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 | |
881 | #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 | |
882 | #define RADEON_SURFACE4_INFO 0x0b4c | |
883 | #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 | |
884 | #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 | |
885 | #define RADEON_SURFACE5_INFO 0x0b5c | |
886 | #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 | |
887 | #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 | |
888 | #define RADEON_SURFACE6_INFO 0x0b6c | |
889 | #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 | |
890 | #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 | |
891 | #define RADEON_SURFACE7_INFO 0x0b7c | |
892 | #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 | |
893 | #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 | |
894 | #define RADEON_SW_SEMAPHORE 0x013c | |
895 | ||
896 | #define RADEON_WAIT_UNTIL 0x1720 | |
897 | # define RADEON_WAIT_CRTC_PFLIP (1 << 0) | |
d985c108 DA |
898 | # define RADEON_WAIT_2D_IDLE (1 << 14) |
899 | # define RADEON_WAIT_3D_IDLE (1 << 15) | |
1da177e4 LT |
900 | # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) |
901 | # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) | |
902 | # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) | |
903 | ||
904 | #define RADEON_RB3D_ZMASKOFFSET 0x3234 | |
905 | #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c | |
906 | # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) | |
907 | # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) | |
908 | ||
1da177e4 LT |
909 | /* CP registers */ |
910 | #define RADEON_CP_ME_RAM_ADDR 0x07d4 | |
911 | #define RADEON_CP_ME_RAM_RADDR 0x07d8 | |
912 | #define RADEON_CP_ME_RAM_DATAH 0x07dc | |
913 | #define RADEON_CP_ME_RAM_DATAL 0x07e0 | |
914 | ||
915 | #define RADEON_CP_RB_BASE 0x0700 | |
916 | #define RADEON_CP_RB_CNTL 0x0704 | |
917 | # define RADEON_BUF_SWAP_32BIT (2 << 16) | |
ae1b1a48 | 918 | # define RADEON_RB_NO_UPDATE (1 << 27) |
1da177e4 LT |
919 | #define RADEON_CP_RB_RPTR_ADDR 0x070c |
920 | #define RADEON_CP_RB_RPTR 0x0710 | |
921 | #define RADEON_CP_RB_WPTR 0x0714 | |
922 | ||
923 | #define RADEON_CP_RB_WPTR_DELAY 0x0718 | |
924 | # define RADEON_PRE_WRITE_TIMER_SHIFT 0 | |
925 | # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 | |
926 | ||
927 | #define RADEON_CP_IB_BASE 0x0738 | |
928 | ||
929 | #define RADEON_CP_CSQ_CNTL 0x0740 | |
930 | # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) | |
931 | # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) | |
932 | # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) | |
933 | # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) | |
934 | # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) | |
935 | # define RADEON_CSQ_PRIBM_INDBM (4 << 28) | |
936 | # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) | |
937 | ||
938 | #define RADEON_AIC_CNTL 0x01d0 | |
939 | # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) | |
4e270e9b | 940 | # define RS400_MSI_REARM (1 << 3) |
1da177e4 LT |
941 | #define RADEON_AIC_STAT 0x01d4 |
942 | #define RADEON_AIC_PT_BASE 0x01d8 | |
943 | #define RADEON_AIC_LO_ADDR 0x01dc | |
944 | #define RADEON_AIC_HI_ADDR 0x01e0 | |
945 | #define RADEON_AIC_TLB_ADDR 0x01e4 | |
946 | #define RADEON_AIC_TLB_DATA 0x01e8 | |
947 | ||
948 | /* CP command packets */ | |
949 | #define RADEON_CP_PACKET0 0x00000000 | |
950 | # define RADEON_ONE_REG_WR (1 << 15) | |
951 | #define RADEON_CP_PACKET1 0x40000000 | |
952 | #define RADEON_CP_PACKET2 0x80000000 | |
953 | #define RADEON_CP_PACKET3 0xC0000000 | |
414ed537 DA |
954 | # define RADEON_CP_NOP 0x00001000 |
955 | # define RADEON_CP_NEXT_CHAR 0x00001900 | |
956 | # define RADEON_CP_PLY_NEXTSCAN 0x00001D00 | |
957 | # define RADEON_CP_SET_SCISSORS 0x00001E00 | |
b5e89ed5 | 958 | /* GEN_INDX_PRIM is unsupported starting with R300 */ |
1da177e4 LT |
959 | # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 |
960 | # define RADEON_WAIT_FOR_IDLE 0x00002600 | |
961 | # define RADEON_3D_DRAW_VBUF 0x00002800 | |
962 | # define RADEON_3D_DRAW_IMMD 0x00002900 | |
963 | # define RADEON_3D_DRAW_INDX 0x00002A00 | |
414ed537 | 964 | # define RADEON_CP_LOAD_PALETTE 0x00002C00 |
1da177e4 LT |
965 | # define RADEON_3D_LOAD_VBPNTR 0x00002F00 |
966 | # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 | |
967 | # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 | |
968 | # define RADEON_3D_CLEAR_ZMASK 0x00003200 | |
414ed537 DA |
969 | # define RADEON_CP_INDX_BUFFER 0x00003300 |
970 | # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 | |
971 | # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 | |
972 | # define RADEON_CP_3D_DRAW_INDX_2 0x00003600 | |
1da177e4 | 973 | # define RADEON_3D_CLEAR_HIZ 0x00003700 |
414ed537 | 974 | # define RADEON_CP_3D_CLEAR_CMASK 0x00003802 |
1da177e4 LT |
975 | # define RADEON_CNTL_HOSTDATA_BLT 0x00009400 |
976 | # define RADEON_CNTL_PAINT_MULTI 0x00009A00 | |
977 | # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 | |
978 | # define RADEON_CNTL_SET_SCISSORS 0xC0001E00 | |
979 | ||
980 | #define RADEON_CP_PACKET_MASK 0xC0000000 | |
981 | #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 | |
982 | #define RADEON_CP_PACKET0_REG_MASK 0x000007ff | |
983 | #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff | |
984 | #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 | |
985 | ||
986 | #define RADEON_VTX_Z_PRESENT (1 << 31) | |
987 | #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) | |
988 | ||
989 | #define RADEON_PRIM_TYPE_NONE (0 << 0) | |
990 | #define RADEON_PRIM_TYPE_POINT (1 << 0) | |
991 | #define RADEON_PRIM_TYPE_LINE (2 << 0) | |
992 | #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) | |
993 | #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) | |
994 | #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) | |
995 | #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) | |
996 | #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) | |
997 | #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) | |
998 | #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) | |
999 | #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) | |
1000 | #define RADEON_PRIM_TYPE_MASK 0xf | |
1001 | #define RADEON_PRIM_WALK_IND (1 << 4) | |
1002 | #define RADEON_PRIM_WALK_LIST (2 << 4) | |
1003 | #define RADEON_PRIM_WALK_RING (3 << 4) | |
1004 | #define RADEON_COLOR_ORDER_BGRA (0 << 6) | |
1005 | #define RADEON_COLOR_ORDER_RGBA (1 << 6) | |
1006 | #define RADEON_MAOS_ENABLE (1 << 7) | |
1007 | #define RADEON_VTX_FMT_R128_MODE (0 << 8) | |
1008 | #define RADEON_VTX_FMT_RADEON_MODE (1 << 8) | |
1009 | #define RADEON_NUM_VERTICES_SHIFT 16 | |
1010 | ||
1011 | #define RADEON_COLOR_FORMAT_CI8 2 | |
1012 | #define RADEON_COLOR_FORMAT_ARGB1555 3 | |
1013 | #define RADEON_COLOR_FORMAT_RGB565 4 | |
1014 | #define RADEON_COLOR_FORMAT_ARGB8888 6 | |
1015 | #define RADEON_COLOR_FORMAT_RGB332 7 | |
1016 | #define RADEON_COLOR_FORMAT_RGB8 9 | |
1017 | #define RADEON_COLOR_FORMAT_ARGB4444 15 | |
1018 | ||
1019 | #define RADEON_TXFORMAT_I8 0 | |
1020 | #define RADEON_TXFORMAT_AI88 1 | |
1021 | #define RADEON_TXFORMAT_RGB332 2 | |
1022 | #define RADEON_TXFORMAT_ARGB1555 3 | |
1023 | #define RADEON_TXFORMAT_RGB565 4 | |
1024 | #define RADEON_TXFORMAT_ARGB4444 5 | |
1025 | #define RADEON_TXFORMAT_ARGB8888 6 | |
1026 | #define RADEON_TXFORMAT_RGBA8888 7 | |
1027 | #define RADEON_TXFORMAT_Y8 8 | |
1028 | #define RADEON_TXFORMAT_VYUY422 10 | |
1029 | #define RADEON_TXFORMAT_YVYU422 11 | |
1030 | #define RADEON_TXFORMAT_DXT1 12 | |
1031 | #define RADEON_TXFORMAT_DXT23 14 | |
1032 | #define RADEON_TXFORMAT_DXT45 15 | |
1033 | ||
1034 | #define R200_PP_TXCBLEND_0 0x2f00 | |
1035 | #define R200_PP_TXCBLEND_1 0x2f10 | |
1036 | #define R200_PP_TXCBLEND_2 0x2f20 | |
1037 | #define R200_PP_TXCBLEND_3 0x2f30 | |
1038 | #define R200_PP_TXCBLEND_4 0x2f40 | |
1039 | #define R200_PP_TXCBLEND_5 0x2f50 | |
1040 | #define R200_PP_TXCBLEND_6 0x2f60 | |
1041 | #define R200_PP_TXCBLEND_7 0x2f70 | |
b5e89ed5 | 1042 | #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 |
1da177e4 LT |
1043 | #define R200_PP_TFACTOR_0 0x2ee0 |
1044 | #define R200_SE_VTX_FMT_0 0x2088 | |
1045 | #define R200_SE_VAP_CNTL 0x2080 | |
1046 | #define R200_SE_TCL_MATRIX_SEL_0 0x2230 | |
b5e89ed5 DA |
1047 | #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 |
1048 | #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 | |
1049 | #define R200_PP_TXFILTER_5 0x2ca0 | |
1050 | #define R200_PP_TXFILTER_4 0x2c80 | |
1051 | #define R200_PP_TXFILTER_3 0x2c60 | |
1052 | #define R200_PP_TXFILTER_2 0x2c40 | |
1053 | #define R200_PP_TXFILTER_1 0x2c20 | |
1054 | #define R200_PP_TXFILTER_0 0x2c00 | |
1da177e4 LT |
1055 | #define R200_PP_TXOFFSET_5 0x2d78 |
1056 | #define R200_PP_TXOFFSET_4 0x2d60 | |
1057 | #define R200_PP_TXOFFSET_3 0x2d48 | |
1058 | #define R200_PP_TXOFFSET_2 0x2d30 | |
1059 | #define R200_PP_TXOFFSET_1 0x2d18 | |
1060 | #define R200_PP_TXOFFSET_0 0x2d00 | |
1061 | ||
1062 | #define R200_PP_CUBIC_FACES_0 0x2c18 | |
1063 | #define R200_PP_CUBIC_FACES_1 0x2c38 | |
1064 | #define R200_PP_CUBIC_FACES_2 0x2c58 | |
1065 | #define R200_PP_CUBIC_FACES_3 0x2c78 | |
1066 | #define R200_PP_CUBIC_FACES_4 0x2c98 | |
1067 | #define R200_PP_CUBIC_FACES_5 0x2cb8 | |
1068 | #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 | |
1069 | #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 | |
1070 | #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c | |
1071 | #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 | |
1072 | #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 | |
1073 | #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c | |
1074 | #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 | |
1075 | #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 | |
1076 | #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 | |
1077 | #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c | |
1078 | #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 | |
1079 | #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 | |
1080 | #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c | |
1081 | #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 | |
1082 | #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 | |
1083 | #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c | |
1084 | #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 | |
1085 | #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 | |
1086 | #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 | |
1087 | #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c | |
1088 | #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 | |
1089 | #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 | |
1090 | #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c | |
1091 | #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 | |
1092 | #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 | |
1093 | #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c | |
1094 | #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 | |
1095 | #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 | |
1096 | #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 | |
1097 | #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c | |
1098 | ||
1099 | #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 | |
1100 | #define R200_SE_VTE_CNTL 0x20b0 | |
1101 | #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 | |
1102 | #define R200_PP_TAM_DEBUG3 0x2d9c | |
1103 | #define R200_PP_CNTL_X 0x2cc4 | |
1104 | #define R200_SE_VAP_CNTL_STATUS 0x2140 | |
1105 | #define R200_RE_SCISSOR_TL_0 0x1cd8 | |
1106 | #define R200_RE_SCISSOR_TL_1 0x1ce0 | |
1107 | #define R200_RE_SCISSOR_TL_2 0x1ce8 | |
b5e89ed5 | 1108 | #define R200_RB3D_DEPTHXY_OFFSET 0x1d60 |
1da177e4 LT |
1109 | #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 |
1110 | #define R200_SE_VTX_STATE_CNTL 0x2180 | |
1111 | #define R200_RE_POINTSIZE 0x2648 | |
1112 | #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 | |
1113 | ||
b5e89ed5 | 1114 | #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ |
1da177e4 LT |
1115 | #define RADEON_PP_TEX_SIZE_1 0x1d0c |
1116 | #define RADEON_PP_TEX_SIZE_2 0x1d14 | |
1117 | ||
1118 | #define RADEON_PP_CUBIC_FACES_0 0x1d24 | |
1119 | #define RADEON_PP_CUBIC_FACES_1 0x1d28 | |
1120 | #define RADEON_PP_CUBIC_FACES_2 0x1d2c | |
1121 | #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ | |
1122 | #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 | |
1123 | #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 | |
1124 | ||
f2a2279f DA |
1125 | #define RADEON_SE_TCL_STATE_FLUSH 0x2284 |
1126 | ||
1da177e4 LT |
1127 | #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 |
1128 | #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 | |
1129 | #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 | |
1130 | #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 | |
1131 | #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 | |
1132 | #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 | |
1133 | #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 | |
1134 | #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b | |
1135 | #define R200_3D_DRAW_IMMD_2 0xC0003500 | |
1136 | #define R200_SE_VTX_FMT_1 0x208c | |
b5e89ed5 | 1137 | #define R200_RE_CNTL 0x1c50 |
1da177e4 LT |
1138 | |
1139 | #define R200_RB3D_BLENDCOLOR 0x3218 | |
1140 | ||
1141 | #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 | |
1142 | ||
1143 | #define R200_PP_TRI_PERF 0x2cf8 | |
1144 | ||
9d17601c | 1145 | #define R200_PP_AFS_0 0x2f80 |
b5e89ed5 | 1146 | #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ |
9d17601c | 1147 | |
d6fece05 DA |
1148 | #define R200_VAP_PVS_CNTL_1 0x22D0 |
1149 | ||
0a3e67a4 JB |
1150 | #define RADEON_CRTC_CRNT_FRAME 0x0214 |
1151 | #define RADEON_CRTC2_CRNT_FRAME 0x0314 | |
1152 | ||
c0beb2a7 DA |
1153 | #define R500_D1CRTC_STATUS 0x609c |
1154 | #define R500_D2CRTC_STATUS 0x689c | |
1155 | #define R500_CRTC_V_BLANK (1<<0) | |
1156 | ||
1157 | #define R500_D1CRTC_FRAME_COUNT 0x60a4 | |
1158 | #define R500_D2CRTC_FRAME_COUNT 0x68a4 | |
1159 | ||
1160 | #define R500_D1MODE_V_COUNTER 0x6530 | |
1161 | #define R500_D2MODE_V_COUNTER 0x6d30 | |
1162 | ||
1163 | #define R500_D1MODE_VBLANK_STATUS 0x6534 | |
1164 | #define R500_D2MODE_VBLANK_STATUS 0x6d34 | |
1165 | #define R500_VBLANK_OCCURED (1<<0) | |
1166 | #define R500_VBLANK_ACK (1<<4) | |
1167 | #define R500_VBLANK_STAT (1<<12) | |
1168 | #define R500_VBLANK_INT (1<<16) | |
1169 | ||
1170 | #define R500_DxMODE_INT_MASK 0x6540 | |
1171 | #define R500_D1MODE_INT_MASK (1<<0) | |
1172 | #define R500_D2MODE_INT_MASK (1<<8) | |
1173 | ||
1174 | #define R500_DISP_INTERRUPT_STATUS 0x7edc | |
1175 | #define R500_D1_VBLANK_INTERRUPT (1 << 4) | |
1176 | #define R500_D2_VBLANK_INTERRUPT (1 << 5) | |
1177 | ||
1da177e4 LT |
1178 | /* Constants */ |
1179 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | |
1180 | ||
1181 | #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 | |
1182 | #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 | |
1183 | #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 | |
1184 | #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 | |
1185 | #define RADEON_LAST_DISPATCH 1 | |
1186 | ||
1187 | #define RADEON_MAX_VB_AGE 0x7fffffff | |
1188 | #define RADEON_MAX_VB_VERTS (0xffff) | |
1189 | ||
1190 | #define RADEON_RING_HIGH_MARK 128 | |
1191 | ||
ea98a92f DA |
1192 | #define RADEON_PCIGART_TABLE_SIZE (32*1024) |
1193 | ||
1da177e4 LT |
1194 | #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) |
1195 | #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) | |
1196 | #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) | |
1197 | #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) | |
1198 | ||
2735977b | 1199 | #define RADEON_WRITE_PLL(addr, val) \ |
1da177e4 | 1200 | do { \ |
2735977b | 1201 | RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ |
1da177e4 | 1202 | ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ |
2735977b | 1203 | RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ |
1da177e4 LT |
1204 | } while (0) |
1205 | ||
2735977b | 1206 | #define RADEON_WRITE_PCIE(addr, val) \ |
ea98a92f | 1207 | do { \ |
2735977b | 1208 | RADEON_WRITE8(RADEON_PCIE_INDEX, \ |
ea98a92f | 1209 | ((addr) & 0xff)); \ |
2735977b | 1210 | RADEON_WRITE(RADEON_PCIE_DATA, (val)); \ |
ea98a92f DA |
1211 | } while (0) |
1212 | ||
45e51905 AD |
1213 | #define R500_WRITE_MCIND(addr, val) \ |
1214 | do { \ | |
1215 | RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ | |
1216 | RADEON_WRITE(R520_MC_IND_DATA, (val)); \ | |
1217 | RADEON_WRITE(R520_MC_IND_INDEX, 0); \ | |
1218 | } while (0) | |
1219 | ||
1220 | #define RS480_WRITE_MCIND(addr, val) \ | |
1221 | do { \ | |
1222 | RADEON_WRITE(RS480_NB_MC_INDEX, \ | |
1223 | ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ | |
1224 | RADEON_WRITE(RS480_NB_MC_DATA, (val)); \ | |
1225 | RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \ | |
1226 | } while (0) | |
3d5e2c13 | 1227 | |
2735977b | 1228 | #define RS690_WRITE_MCIND(addr, val) \ |
60f92683 MC |
1229 | do { \ |
1230 | RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ | |
1231 | RADEON_WRITE(RS690_MC_DATA, val); \ | |
1232 | RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ | |
1233 | } while (0) | |
1234 | ||
45e51905 AD |
1235 | #define IGP_WRITE_MCIND(addr, val) \ |
1236 | do { \ | |
f0738e92 AD |
1237 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ |
1238 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ | |
45e51905 AD |
1239 | RS690_WRITE_MCIND(addr, val); \ |
1240 | else \ | |
1241 | RS480_WRITE_MCIND(addr, val); \ | |
1242 | } while (0) | |
1243 | ||
1da177e4 LT |
1244 | #define CP_PACKET0( reg, n ) \ |
1245 | (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) | |
1246 | #define CP_PACKET0_TABLE( reg, n ) \ | |
1247 | (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) | |
1248 | #define CP_PACKET1( reg0, reg1 ) \ | |
1249 | (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) | |
1250 | #define CP_PACKET2() \ | |
1251 | (RADEON_CP_PACKET2) | |
1252 | #define CP_PACKET3( pkt, n ) \ | |
1253 | (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) | |
1254 | ||
1da177e4 LT |
1255 | /* ================================================================ |
1256 | * Engine control helper macros | |
1257 | */ | |
1258 | ||
1259 | #define RADEON_WAIT_UNTIL_2D_IDLE() do { \ | |
1260 | OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ | |
1261 | OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ | |
1262 | RADEON_WAIT_HOST_IDLECLEAN) ); \ | |
1263 | } while (0) | |
1264 | ||
1265 | #define RADEON_WAIT_UNTIL_3D_IDLE() do { \ | |
1266 | OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ | |
1267 | OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ | |
1268 | RADEON_WAIT_HOST_IDLECLEAN) ); \ | |
1269 | } while (0) | |
1270 | ||
1271 | #define RADEON_WAIT_UNTIL_IDLE() do { \ | |
1272 | OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ | |
1273 | OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ | |
1274 | RADEON_WAIT_3D_IDLECLEAN | \ | |
1275 | RADEON_WAIT_HOST_IDLECLEAN) ); \ | |
1276 | } while (0) | |
1277 | ||
1278 | #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ | |
1279 | OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ | |
1280 | OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ | |
1281 | } while (0) | |
1282 | ||
1283 | #define RADEON_FLUSH_CACHE() do { \ | |
259434ac AD |
1284 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1285 | OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ | |
1286 | OUT_RING(RADEON_RB3D_DC_FLUSH); \ | |
1287 | } else { \ | |
1288 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ | |
54f961a6 | 1289 | OUT_RING(R300_RB3D_DC_FLUSH); \ |
259434ac | 1290 | } \ |
1da177e4 LT |
1291 | } while (0) |
1292 | ||
1293 | #define RADEON_PURGE_CACHE() do { \ | |
259434ac AD |
1294 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1295 | OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ | |
54f961a6 | 1296 | OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ |
259434ac AD |
1297 | } else { \ |
1298 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ | |
54f961a6 | 1299 | OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \ |
259434ac | 1300 | } \ |
1da177e4 LT |
1301 | } while (0) |
1302 | ||
1303 | #define RADEON_FLUSH_ZCACHE() do { \ | |
259434ac AD |
1304 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1305 | OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ | |
1306 | OUT_RING(RADEON_RB3D_ZC_FLUSH); \ | |
1307 | } else { \ | |
1308 | OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ | |
1309 | OUT_RING(R300_ZC_FLUSH); \ | |
1310 | } \ | |
1da177e4 LT |
1311 | } while (0) |
1312 | ||
1313 | #define RADEON_PURGE_ZCACHE() do { \ | |
259434ac AD |
1314 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1315 | OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ | |
54f961a6 | 1316 | OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ |
259434ac | 1317 | } else { \ |
54f961a6 JG |
1318 | OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ |
1319 | OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ | |
259434ac | 1320 | } \ |
1da177e4 LT |
1321 | } while (0) |
1322 | ||
1da177e4 LT |
1323 | /* ================================================================ |
1324 | * Misc helper macros | |
1325 | */ | |
1326 | ||
b5e89ed5 | 1327 | /* Perfbox functionality only. |
1da177e4 LT |
1328 | */ |
1329 | #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ | |
1330 | do { \ | |
1331 | if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ | |
1332 | u32 head = GET_RING_HEAD( dev_priv ); \ | |
1333 | if (head == dev_priv->ring.tail) \ | |
1334 | dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ | |
1335 | } \ | |
1336 | } while (0) | |
1337 | ||
1338 | #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ | |
1339 | do { \ | |
1340 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ | |
1341 | if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ | |
1342 | int __ret = radeon_do_cp_idle( dev_priv ); \ | |
1343 | if ( __ret ) return __ret; \ | |
1344 | sarea_priv->last_dispatch = 0; \ | |
1345 | radeon_freelist_reset( dev ); \ | |
1346 | } \ | |
1347 | } while (0) | |
1348 | ||
1349 | #define RADEON_DISPATCH_AGE( age ) do { \ | |
1350 | OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ | |
1351 | OUT_RING( age ); \ | |
1352 | } while (0) | |
1353 | ||
1354 | #define RADEON_FRAME_AGE( age ) do { \ | |
1355 | OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ | |
1356 | OUT_RING( age ); \ | |
1357 | } while (0) | |
1358 | ||
1359 | #define RADEON_CLEAR_AGE( age ) do { \ | |
1360 | OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ | |
1361 | OUT_RING( age ); \ | |
1362 | } while (0) | |
1363 | ||
1da177e4 LT |
1364 | /* ================================================================ |
1365 | * Ring control | |
1366 | */ | |
1367 | ||
1368 | #define RADEON_VERBOSE 0 | |
1369 | ||
1370 | #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; | |
1371 | ||
1372 | #define BEGIN_RING( n ) do { \ | |
1373 | if ( RADEON_VERBOSE ) { \ | |
3e684eae | 1374 | DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ |
1da177e4 LT |
1375 | } \ |
1376 | if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ | |
1377 | COMMIT_RING(); \ | |
1378 | radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ | |
1379 | } \ | |
1380 | _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ | |
1381 | ring = dev_priv->ring.start; \ | |
1382 | write = dev_priv->ring.tail; \ | |
1383 | mask = dev_priv->ring.tail_mask; \ | |
1384 | } while (0) | |
1385 | ||
1386 | #define ADVANCE_RING() do { \ | |
1387 | if ( RADEON_VERBOSE ) { \ | |
1388 | DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ | |
1389 | write, dev_priv->ring.tail ); \ | |
1390 | } \ | |
1391 | if (((dev_priv->ring.tail + _nr) & mask) != write) { \ | |
bc5f4523 | 1392 | DRM_ERROR( \ |
1da177e4 LT |
1393 | "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ |
1394 | ((dev_priv->ring.tail + _nr) & mask), \ | |
1395 | write, __LINE__); \ | |
1396 | } else \ | |
1397 | dev_priv->ring.tail = write; \ | |
1398 | } while (0) | |
1399 | ||
1400 | #define COMMIT_RING() do { \ | |
1401 | /* Flush writes to ring */ \ | |
1402 | DRM_MEMORYBARRIER(); \ | |
1403 | GET_RING_HEAD( dev_priv ); \ | |
1404 | RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ | |
1405 | /* read from PCI bus to ensure correct posting */ \ | |
1406 | RADEON_READ( RADEON_CP_RB_RPTR ); \ | |
1407 | } while (0) | |
1408 | ||
1409 | #define OUT_RING( x ) do { \ | |
1410 | if ( RADEON_VERBOSE ) { \ | |
1411 | DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ | |
1412 | (unsigned int)(x), write ); \ | |
1413 | } \ | |
1414 | ring[write++] = (x); \ | |
1415 | write &= mask; \ | |
1416 | } while (0) | |
1417 | ||
1418 | #define OUT_RING_REG( reg, val ) do { \ | |
1419 | OUT_RING( CP_PACKET0( reg, 0 ) ); \ | |
1420 | OUT_RING( val ); \ | |
1421 | } while (0) | |
1422 | ||
1da177e4 LT |
1423 | #define OUT_RING_TABLE( tab, sz ) do { \ |
1424 | int _size = (sz); \ | |
1425 | int *_tab = (int *)(tab); \ | |
1426 | \ | |
1427 | if (write + _size > mask) { \ | |
1428 | int _i = (mask+1) - write; \ | |
1429 | _size -= _i; \ | |
1430 | while (_i > 0 ) { \ | |
1431 | *(int *)(ring + write) = *_tab++; \ | |
1432 | write++; \ | |
1433 | _i--; \ | |
1434 | } \ | |
1435 | write = 0; \ | |
1436 | _tab += _i; \ | |
1437 | } \ | |
1da177e4 LT |
1438 | while (_size > 0) { \ |
1439 | *(ring + write) = *_tab++; \ | |
1440 | write++; \ | |
1441 | _size--; \ | |
1442 | } \ | |
1443 | write &= mask; \ | |
1444 | } while (0) | |
1445 | ||
b5e89ed5 | 1446 | #endif /* __RADEON_DRV_H__ */ |