Commit | Line | Data |
---|---|---|
6d587203 | 1 | /* |
1da177e4 LT |
2 | * \file radeon_drv.c |
3 | * ATI Radeon driver | |
4 | * | |
5 | * \author Gareth Hughes <gareth@valinux.com> | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
10 | * All Rights Reserved. | |
11 | * | |
12 | * Permission is hereby granted, free of charge, to any person obtaining a | |
13 | * copy of this software and associated documentation files (the "Software"), | |
14 | * to deal in the Software without restriction, including without limitation | |
15 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
16 | * and/or sell copies of the Software, and to permit persons to whom the | |
17 | * Software is furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice (including the next | |
20 | * paragraph) shall be included in all copies or substantial portions of the | |
21 | * Software. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
24 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
25 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
26 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
27 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
28 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
29 | * OTHER DEALINGS IN THE SOFTWARE. | |
30 | */ | |
31 | ||
1da177e4 | 32 | |
f9183127 | 33 | #include <linux/compat.h> |
e0cd3608 | 34 | #include <linux/module.h> |
10ebc0bc DA |
35 | #include <linux/pm_runtime.h> |
36 | #include <linux/vga_switcheroo.h> | |
534e5f84 | 37 | #include <linux/mmu_notifier.h> |
625c18d7 | 38 | #include <linux/pci.h> |
d9fc9413 | 39 | |
6848c291 | 40 | #include <drm/drm_aperture.h> |
f9183127 | 41 | #include <drm/drm_drv.h> |
f9183127 SR |
42 | #include <drm/drm_file.h> |
43 | #include <drm/drm_gem.h> | |
44 | #include <drm/drm_ioctl.h> | |
f9183127 | 45 | #include <drm/drm_pciids.h> |
fcd70cd3 | 46 | #include <drm/drm_probe_helper.h> |
f9183127 SR |
47 | #include <drm/drm_vblank.h> |
48 | #include <drm/radeon_drm.h> | |
49 | ||
50 | #include "radeon_drv.h" | |
384bc5e0 | 51 | #include "radeon.h" |
f3723ad1 | 52 | #include "radeon_kms.h" |
0a2e8d51 | 53 | #include "radeon_ttm.h" |
4d3efadd | 54 | #include "radeon_device.h" |
4138b62b | 55 | #include "radeon_prime.h" |
e28740ec | 56 | |
771fe6b9 JG |
57 | /* |
58 | * KMS wrapper. | |
0de1a57b DA |
59 | * - 2.0.0 - initial interface |
60 | * - 2.1.0 - add square tiling interface | |
fdb43528 | 61 | * - 2.2.0 - add r6xx/r7xx const buffer support |
cae94b0a | 62 | * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs |
bc35afdb | 63 | * - 2.4.0 - add crtc id query |
148a03bc | 64 | * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen |
ab9e1f59 | 65 | * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) |
71901cc4 | 66 | * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs |
58bbf018 | 67 | * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query |
486af189 | 68 | * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query |
b8709894 AD |
69 | * 2.10.0 - fusion 2D tiling |
70 | * 2.11.0 - backend map, initial compute support for the CS checker | |
e70f224c | 71 | * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS |
dd220a00 | 72 | * 2.13.0 - virtual memory support, streamout |
285484e2 | 73 | * 2.14.0 - add evergreen tiling informations |
609c1e15 | 74 | * 2.15.0 - add max_pipes query |
d2609875 | 75 | * 2.16.0 - fix evergreen 2D tiled surface calculation |
7c77bf2a | 76 | * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx |
0f457e48 | 77 | * 2.18.0 - r600-eg: allow "invalid" DB formats |
b51ad12a | 78 | * 2.19.0 - r600-eg: MSAA textures |
6759a0a7 | 79 | * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query |
c116cc94 | 80 | * 2.21.0 - r600-r700: FMASK and CMASK |
523885de | 81 | * 2.22.0 - r600 only: RESOLVE_BOX allowed |
46fc8781 | 82 | * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 |
61051afd | 83 | * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures |
71bfe916 | 84 | * 2.25.0 - eg+: new info request for num SE and num SH |
4ac0533a | 85 | * 2.26.0 - r600-eg: fix htile size computation |
8696e33f | 86 | * 2.27.0 - r600-SI: Add CS ioctl support for async DMA |
4613ca14 | 87 | * 2.28.0 - r600-eg: Add MEM_WRITE packet support |
c18b1170 | 88 | * 2.29.0 - R500 FP16 color clear registers |
774c389f | 89 | * 2.30.0 - fix for FMASK texturing |
a0a53aa8 | 90 | * 2.31.0 - Add fastfb support for rs690 |
902aaef6 | 91 | * 2.32.0 - new info request for rings working |
64d7b8be | 92 | * 2.33.0 - Add SI tiling mode array query |
39aee490 | 93 | * 2.34.0 - Add CIK tiling mode array query |
32f79a8a | 94 | * 2.35.0 - Add CIK macrotile mode array query |
9482d0d3 | 95 | * 2.36.0 - Fix CIK DCE tiling setup |
7c4c62a0 | 96 | * 2.37.0 - allow GS ring setup on r6xx/r7xx |
020ff546 MO |
97 | * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), |
98 | * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG | |
65fcf668 | 99 | * 2.39.0 - Add INFO query for number of active CUs |
72a9987e | 100 | * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting |
897eba82 | 101 | * CS to GPU on >= r600 |
16613743 | 102 | * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support |
1957d6be | 103 | * 2.42.0 - Add VCE/VUI (Video Usability Information) support |
72b9076b | 104 | * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER |
8c4f2bbd | 105 | * 2.44.0 - SET_APPEND_CNT packet3 support |
3d02b7fe | 106 | * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI |
662ce7bc | 107 | * 2.46.0 - Add PFP_SYNC_ME support on evergreen |
4d6bdbad | 108 | * 2.47.0 - Add UVD_NO_OP register support |
113d0f9d | 109 | * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI |
51964e9e | 110 | * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values |
75cb00dc | 111 | * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) |
771fe6b9 JG |
112 | */ |
113 | #define KMS_DRIVER_MAJOR 2 | |
75cb00dc | 114 | #define KMS_DRIVER_MINOR 50 |
771fe6b9 | 115 | #define KMS_DRIVER_PATCHLEVEL 0 |
1da177e4 | 116 | |
689b9d74 | 117 | int radeon_no_wb; |
e9ced8e0 | 118 | int radeon_modeset = -1; |
771fe6b9 | 119 | int radeon_dynclks = -1; |
803d411b | 120 | int radeon_r4xx_atom; |
037d1a66 | 121 | int radeon_agpmode = -1; |
803d411b | 122 | int radeon_vram_limit; |
edcd26e8 | 123 | int radeon_gart_size = -1; /* auto */ |
803d411b SS |
124 | int radeon_benchmarking; |
125 | int radeon_testing; | |
126 | int radeon_connector_table; | |
4ce001ab | 127 | int radeon_tv = 1; |
108dc8e8 | 128 | int radeon_audio = -1; |
803d411b SS |
129 | int radeon_disp_priority; |
130 | int radeon_hw_i2c; | |
197bbb3d | 131 | int radeon_pcie_gen2 = -1; |
a18cee15 | 132 | int radeon_msi = -1; |
3368ff0c | 133 | int radeon_lockup_timeout = 10000; |
803d411b | 134 | int radeon_fastfb; |
da321c8a | 135 | int radeon_dpm = -1; |
1294d4a3 | 136 | int radeon_aspm = -1; |
10ebc0bc | 137 | int radeon_runtime_pm = -1; |
803d411b | 138 | int radeon_hard_reset; |
dfc230f9 CK |
139 | int radeon_vm_size = 8; |
140 | int radeon_vm_block_size = -1; | |
803d411b | 141 | int radeon_deep_color; |
39dc5454 | 142 | int radeon_use_pflipirq = 2; |
6e909f74 | 143 | int radeon_bapm = -1; |
bc13018b | 144 | int radeon_backlight = -1; |
875711f0 | 145 | int radeon_auxch = -1; |
f1a0a67a | 146 | int radeon_uvd = 1; |
fabb5935 | 147 | int radeon_vce = 1; |
689b9d74 | 148 | |
61a2d07d | 149 | MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); |
689b9d74 DA |
150 | module_param_named(no_wb, radeon_no_wb, int, 0444); |
151 | ||
771fe6b9 JG |
152 | MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); |
153 | module_param_named(modeset, radeon_modeset, int, 0400); | |
154 | ||
155 | MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); | |
156 | module_param_named(dynclks, radeon_dynclks, int, 0444); | |
157 | ||
158 | MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); | |
159 | module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); | |
160 | ||
8902e6f2 | 161 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); |
771fe6b9 JG |
162 | module_param_named(vramlimit, radeon_vram_limit, int, 0600); |
163 | ||
164 | MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); | |
165 | module_param_named(agpmode, radeon_agpmode, int, 0444); | |
166 | ||
edcd26e8 | 167 | MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); |
771fe6b9 JG |
168 | module_param_named(gartsize, radeon_gart_size, int, 0600); |
169 | ||
170 | MODULE_PARM_DESC(benchmark, "Run benchmark"); | |
171 | module_param_named(benchmark, radeon_benchmarking, int, 0444); | |
172 | ||
ecc0b326 MD |
173 | MODULE_PARM_DESC(test, "Run tests"); |
174 | module_param_named(test, radeon_testing, int, 0444); | |
175 | ||
771fe6b9 JG |
176 | MODULE_PARM_DESC(connector_table, "Force connector table"); |
177 | module_param_named(connector_table, radeon_connector_table, int, 0444); | |
4ce001ab DA |
178 | |
179 | MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); | |
180 | module_param_named(tv, radeon_tv, int, 0444); | |
771fe6b9 | 181 | |
108dc8e8 | 182 | MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); |
dafc3bd5 CK |
183 | module_param_named(audio, radeon_audio, int, 0444); |
184 | ||
f46c0120 AD |
185 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); |
186 | module_param_named(disp_priority, radeon_disp_priority, int, 0444); | |
187 | ||
e2b0a8e1 AD |
188 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); |
189 | module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); | |
190 | ||
197bbb3d | 191 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); |
d42dd579 AD |
192 | module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); |
193 | ||
a18cee15 AD |
194 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); |
195 | module_param_named(msi, radeon_msi, int, 0444); | |
196 | ||
b5c9ecab | 197 | MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); |
3368ff0c CK |
198 | module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); |
199 | ||
a0a53aa8 SL |
200 | MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); |
201 | module_param_named(fastfb, radeon_fastfb, int, 0444); | |
202 | ||
da321c8a AD |
203 | MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); |
204 | module_param_named(dpm, radeon_dpm, int, 0444); | |
205 | ||
1294d4a3 AD |
206 | MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); |
207 | module_param_named(aspm, radeon_aspm, int, 0444); | |
208 | ||
10ebc0bc DA |
209 | MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); |
210 | module_param_named(runpm, radeon_runtime_pm, int, 0444); | |
211 | ||
363eb0b4 AD |
212 | MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); |
213 | module_param_named(hard_reset, radeon_hard_reset, int, 0444); | |
214 | ||
20b2656d | 215 | MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); |
c1c44132 CK |
216 | module_param_named(vm_size, radeon_vm_size, int, 0444); |
217 | ||
dfc230f9 | 218 | MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); |
4510fb98 CK |
219 | module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); |
220 | ||
a624f429 AD |
221 | MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); |
222 | module_param_named(deep_color, radeon_deep_color, int, 0444); | |
223 | ||
39dc5454 MK |
224 | MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); |
225 | module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); | |
226 | ||
6e909f74 AD |
227 | MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); |
228 | module_param_named(bapm, radeon_bapm, int, 0444); | |
229 | ||
bc13018b AD |
230 | MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); |
231 | module_param_named(backlight, radeon_backlight, int, 0444); | |
232 | ||
875711f0 DA |
233 | MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); |
234 | module_param_named(auxch, radeon_auxch, int, 0444); | |
235 | ||
f1a0a67a JG |
236 | MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); |
237 | module_param_named(uvd, radeon_uvd, int, 0444); | |
238 | ||
fabb5935 JG |
239 | MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); |
240 | module_param_named(vce, radeon_vce, int, 0444); | |
241 | ||
36ffce0a FK |
242 | int radeon_si_support = 1; |
243 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); | |
244 | module_param_named(si_support, radeon_si_support, int, 0444); | |
36ffce0a | 245 | |
2b059658 MD |
246 | int radeon_cik_support = 1; |
247 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); | |
e7f78b69 | 248 | module_param_named(cik_support, radeon_cik_support, int, 0444); |
e7f78b69 | 249 | |
14adc892 CK |
250 | static struct pci_device_id pciidlist[] = { |
251 | radeon_PCI_IDS | |
252 | }; | |
253 | ||
254 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
255 | ||
70a59dd8 | 256 | static const struct drm_driver kms_driver; |
771fe6b9 | 257 | |
56550d94 GKH |
258 | static int radeon_pci_probe(struct pci_dev *pdev, |
259 | const struct pci_device_id *ent) | |
771fe6b9 | 260 | { |
9dbc88d0 | 261 | unsigned long flags = 0; |
b8076b5e | 262 | struct drm_device *dev; |
30238151 TR |
263 | int ret; |
264 | ||
9dbc88d0 HG |
265 | if (!ent) |
266 | return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */ | |
267 | ||
268 | flags = ent->driver_data; | |
269 | ||
270 | if (!radeon_si_support) { | |
271 | switch (flags & RADEON_FAMILY_MASK) { | |
272 | case CHIP_TAHITI: | |
273 | case CHIP_PITCAIRN: | |
274 | case CHIP_VERDE: | |
275 | case CHIP_OLAND: | |
276 | case CHIP_HAINAN: | |
277 | dev_info(&pdev->dev, | |
278 | "SI support disabled by module param\n"); | |
279 | return -ENODEV; | |
280 | } | |
281 | } | |
282 | if (!radeon_cik_support) { | |
283 | switch (flags & RADEON_FAMILY_MASK) { | |
284 | case CHIP_KAVERI: | |
285 | case CHIP_BONAIRE: | |
286 | case CHIP_HAWAII: | |
287 | case CHIP_KABINI: | |
288 | case CHIP_MULLINS: | |
289 | dev_info(&pdev->dev, | |
290 | "CIK support disabled by module param\n"); | |
291 | return -ENODEV; | |
292 | } | |
293 | } | |
294 | ||
b00e5334 | 295 | if (vga_switcheroo_client_probe_defer(pdev)) |
14d20001 LW |
296 | return -EPROBE_DEFER; |
297 | ||
a56f7428 | 298 | /* Get rid of things like offb */ |
97c9bfe3 | 299 | ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &kms_driver); |
30238151 TR |
300 | if (ret) |
301 | return ret; | |
a56f7428 | 302 | |
b8076b5e DV |
303 | dev = drm_dev_alloc(&kms_driver, &pdev->dev); |
304 | if (IS_ERR(dev)) | |
305 | return PTR_ERR(dev); | |
306 | ||
307 | ret = pci_enable_device(pdev); | |
308 | if (ret) | |
309 | goto err_free; | |
310 | ||
b8076b5e DV |
311 | pci_set_drvdata(pdev, dev); |
312 | ||
b8076b5e DV |
313 | ret = drm_dev_register(dev, ent->driver_data); |
314 | if (ret) | |
315 | goto err_agp; | |
316 | ||
e317a69f TZ |
317 | radeon_fbdev_setup(dev->dev_private); |
318 | ||
b8076b5e DV |
319 | return 0; |
320 | ||
321 | err_agp: | |
b8076b5e DV |
322 | pci_disable_device(pdev); |
323 | err_free: | |
324 | drm_dev_put(dev); | |
325 | return ret; | |
771fe6b9 JG |
326 | } |
327 | ||
328 | static void | |
329 | radeon_pci_remove(struct pci_dev *pdev) | |
330 | { | |
331 | struct drm_device *dev = pci_get_drvdata(pdev); | |
332 | ||
333 | drm_put_dev(dev); | |
334 | } | |
335 | ||
a801abe4 AD |
336 | static void |
337 | radeon_pci_shutdown(struct pci_dev *pdev) | |
338 | { | |
339 | /* if we are running in a VM, make sure the device | |
b9b487e4 | 340 | * torn down properly on reboot/shutdown |
a801abe4 | 341 | */ |
b9b487e4 AD |
342 | if (radeon_device_is_virtual()) |
343 | radeon_pci_remove(pdev); | |
d02f5aab | 344 | |
c1bfd74b | 345 | #if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64) |
4cae34d0 K |
346 | /* |
347 | * Some adapters need to be suspended before a | |
d02f5aab | 348 | * shutdown occurs in order to prevent an error |
c1bfd74b TY |
349 | * during kexec, shutdown or reboot. |
350 | * Make this power and Loongson specific because | |
351 | * it breaks some other boards. | |
d02f5aab | 352 | */ |
4cae34d0 | 353 | radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false); |
d02f5aab | 354 | #endif |
a801abe4 AD |
355 | } |
356 | ||
7473e830 | 357 | static int radeon_pmops_suspend(struct device *dev) |
771fe6b9 | 358 | { |
59d788b1 | 359 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
803d411b | 360 | |
274ad65c | 361 | return radeon_suspend_kms(drm_dev, true, true, false); |
771fe6b9 JG |
362 | } |
363 | ||
7473e830 | 364 | static int radeon_pmops_resume(struct device *dev) |
771fe6b9 | 365 | { |
59d788b1 | 366 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
103917b3 AD |
367 | |
368 | /* GPU comes up enabled by the bios on resume */ | |
369 | if (radeon_is_px(drm_dev)) { | |
370 | pm_runtime_disable(dev); | |
371 | pm_runtime_set_active(dev); | |
372 | pm_runtime_enable(dev); | |
373 | } | |
374 | ||
10ebc0bc | 375 | return radeon_resume_kms(drm_dev, true, true); |
7473e830 DA |
376 | } |
377 | ||
378 | static int radeon_pmops_freeze(struct device *dev) | |
379 | { | |
59d788b1 | 380 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
803d411b | 381 | |
274ad65c | 382 | return radeon_suspend_kms(drm_dev, false, true, true); |
771fe6b9 JG |
383 | } |
384 | ||
7473e830 DA |
385 | static int radeon_pmops_thaw(struct device *dev) |
386 | { | |
59d788b1 | 387 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
803d411b | 388 | |
10ebc0bc DA |
389 | return radeon_resume_kms(drm_dev, false, true); |
390 | } | |
391 | ||
392 | static int radeon_pmops_runtime_suspend(struct device *dev) | |
393 | { | |
394 | struct pci_dev *pdev = to_pci_dev(dev); | |
395 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
10ebc0bc | 396 | |
90c4cde9 | 397 | if (!radeon_is_px(drm_dev)) { |
1d8eec8b DA |
398 | pm_runtime_forbid(dev); |
399 | return -EBUSY; | |
400 | } | |
9babd35a | 401 | |
10ebc0bc DA |
402 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
403 | drm_kms_helper_poll_disable(drm_dev); | |
10ebc0bc | 404 | |
3655d1a6 | 405 | radeon_suspend_kms(drm_dev, false, false, false); |
10ebc0bc DA |
406 | pci_save_state(pdev); |
407 | pci_disable_device(pdev); | |
b440bde7 | 408 | pci_ignore_hotplug(pdev); |
31764c1e AD |
409 | if (radeon_is_atpx_hybrid()) |
410 | pci_set_power_state(pdev, PCI_D3cold); | |
84919992 | 411 | else if (!radeon_has_atpx_dgpu_power_cntl()) |
f7ea4189 | 412 | pci_set_power_state(pdev, PCI_D3hot); |
10ebc0bc DA |
413 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; |
414 | ||
415 | return 0; | |
416 | } | |
417 | ||
418 | static int radeon_pmops_runtime_resume(struct device *dev) | |
419 | { | |
420 | struct pci_dev *pdev = to_pci_dev(dev); | |
421 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
422 | int ret; | |
423 | ||
90c4cde9 | 424 | if (!radeon_is_px(drm_dev)) |
9babd35a AD |
425 | return -EINVAL; |
426 | ||
10ebc0bc DA |
427 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
428 | ||
84919992 AD |
429 | if (radeon_is_atpx_hybrid() || |
430 | !radeon_has_atpx_dgpu_power_cntl()) | |
431 | pci_set_power_state(pdev, PCI_D0); | |
10ebc0bc DA |
432 | pci_restore_state(pdev); |
433 | ret = pci_enable_device(pdev); | |
434 | if (ret) | |
435 | return ret; | |
436 | pci_set_master(pdev); | |
437 | ||
438 | ret = radeon_resume_kms(drm_dev, false, false); | |
439 | drm_kms_helper_poll_enable(drm_dev); | |
10ebc0bc DA |
440 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; |
441 | return 0; | |
442 | } | |
443 | ||
444 | static int radeon_pmops_runtime_idle(struct device *dev) | |
445 | { | |
59d788b1 | 446 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
10ebc0bc DA |
447 | struct drm_crtc *crtc; |
448 | ||
90c4cde9 | 449 | if (!radeon_is_px(drm_dev)) { |
1d8eec8b | 450 | pm_runtime_forbid(dev); |
10ebc0bc DA |
451 | return -EBUSY; |
452 | } | |
453 | ||
454 | list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { | |
455 | if (crtc->enabled) { | |
456 | DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); | |
457 | return -EBUSY; | |
458 | } | |
459 | } | |
460 | ||
461 | pm_runtime_mark_last_busy(dev); | |
462 | pm_runtime_autosuspend(dev); | |
463 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ | |
464 | return 1; | |
465 | } | |
466 | ||
467 | long radeon_drm_ioctl(struct file *filp, | |
468 | unsigned int cmd, unsigned long arg) | |
469 | { | |
470 | struct drm_file *file_priv = filp->private_data; | |
471 | struct drm_device *dev; | |
472 | long ret; | |
803d411b | 473 | |
10ebc0bc DA |
474 | dev = file_priv->minor->dev; |
475 | ret = pm_runtime_get_sync(dev->dev); | |
9fb10671 AP |
476 | if (ret < 0) { |
477 | pm_runtime_put_autosuspend(dev->dev); | |
10ebc0bc | 478 | return ret; |
9fb10671 | 479 | } |
10ebc0bc DA |
480 | |
481 | ret = drm_ioctl(filp, cmd, arg); | |
552f9d60 | 482 | |
10ebc0bc DA |
483 | pm_runtime_mark_last_busy(dev->dev); |
484 | pm_runtime_put_autosuspend(dev->dev); | |
485 | return ret; | |
7473e830 DA |
486 | } |
487 | ||
ff32d39b AV |
488 | #ifdef CONFIG_COMPAT |
489 | static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) | |
490 | { | |
491 | unsigned int nr = DRM_IOCTL_NR(cmd); | |
ff32d39b AV |
492 | |
493 | if (nr < DRM_COMMAND_BASE) | |
494 | return drm_compat_ioctl(filp, cmd, arg); | |
495 | ||
d4242216 | 496 | return radeon_drm_ioctl(filp, cmd, arg); |
ff32d39b AV |
497 | } |
498 | #endif | |
499 | ||
7473e830 DA |
500 | static const struct dev_pm_ops radeon_pm_ops = { |
501 | .suspend = radeon_pmops_suspend, | |
502 | .resume = radeon_pmops_resume, | |
503 | .freeze = radeon_pmops_freeze, | |
504 | .thaw = radeon_pmops_thaw, | |
505 | .poweroff = radeon_pmops_freeze, | |
506 | .restore = radeon_pmops_resume, | |
10ebc0bc DA |
507 | .runtime_suspend = radeon_pmops_runtime_suspend, |
508 | .runtime_resume = radeon_pmops_runtime_resume, | |
509 | .runtime_idle = radeon_pmops_runtime_idle, | |
7473e830 DA |
510 | }; |
511 | ||
e08e96de AV |
512 | static const struct file_operations radeon_driver_kms_fops = { |
513 | .owner = THIS_MODULE, | |
514 | .open = drm_open, | |
515 | .release = drm_release, | |
10ebc0bc | 516 | .unlocked_ioctl = radeon_drm_ioctl, |
645e9541 | 517 | .mmap = drm_gem_mmap, |
e08e96de | 518 | .poll = drm_poll, |
e08e96de AV |
519 | .read = drm_read, |
520 | #ifdef CONFIG_COMPAT | |
521 | .compat_ioctl = radeon_kms_compat_ioctl, | |
522 | #endif | |
523 | }; | |
524 | ||
384bc5e0 DV |
525 | static const struct drm_ioctl_desc radeon_ioctls_kms[] = { |
526 | DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
527 | DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
528 | DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
529 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
530 | DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), | |
531 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), | |
532 | DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), | |
533 | DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), | |
534 | DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), | |
535 | DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), | |
536 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), | |
537 | DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), | |
538 | DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), | |
539 | DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), | |
540 | DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
541 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), | |
542 | DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), | |
543 | DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), | |
544 | DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), | |
545 | DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), | |
546 | DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), | |
547 | DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
548 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), | |
549 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), | |
550 | DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), | |
551 | DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), | |
552 | DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), | |
553 | /* KMS */ | |
554 | DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
555 | DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
556 | DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
557 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
384bc5e0 DV |
558 | DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
559 | DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
560 | DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
561 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
562 | DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
563 | DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
564 | DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
565 | DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
566 | DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
567 | }; | |
568 | ||
70a59dd8 | 569 | static const struct drm_driver kms_driver = { |
771fe6b9 | 570 | .driver_features = |
384bc5e0 | 571 | DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET, |
771fe6b9 | 572 | .load = radeon_driver_load_kms, |
771fe6b9 | 573 | .open = radeon_driver_open_kms, |
771fe6b9 | 574 | .postclose = radeon_driver_postclose_kms, |
771fe6b9 | 575 | .unload = radeon_driver_unload_kms, |
771fe6b9 | 576 | .ioctls = radeon_ioctls_kms, |
384bc5e0 | 577 | .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms), |
ff72145b DA |
578 | .dumb_create = radeon_mode_dumb_create, |
579 | .dumb_map_offset = radeon_mode_dumb_mmap, | |
e08e96de | 580 | .fops = &radeon_driver_kms_fops, |
40f5cf99 | 581 | |
1e6d17a5 | 582 | .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, |
40f5cf99 | 583 | |
771fe6b9 JG |
584 | .name = DRIVER_NAME, |
585 | .desc = DRIVER_DESC, | |
586 | .date = DRIVER_DATE, | |
587 | .major = KMS_DRIVER_MAJOR, | |
588 | .minor = KMS_DRIVER_MINOR, | |
589 | .patchlevel = KMS_DRIVER_PATCHLEVEL, | |
590 | }; | |
771fe6b9 | 591 | |
8410ea3b DA |
592 | static struct pci_driver radeon_kms_pci_driver = { |
593 | .name = DRIVER_NAME, | |
594 | .id_table = pciidlist, | |
595 | .probe = radeon_pci_probe, | |
596 | .remove = radeon_pci_remove, | |
a801abe4 | 597 | .shutdown = radeon_pci_shutdown, |
7473e830 | 598 | .driver.pm = &radeon_pm_ops, |
8410ea3b | 599 | }; |
771fe6b9 | 600 | |
384bc5e0 | 601 | static int __init radeon_module_init(void) |
1da177e4 | 602 | { |
6a2d2ddf | 603 | if (drm_firmware_drivers_only() && radeon_modeset == -1) |
e9ced8e0 | 604 | radeon_modeset = 0; |
384bc5e0 | 605 | |
35f7775f | 606 | if (radeon_modeset == 0) |
14adc892 | 607 | return -EINVAL; |
14adc892 | 608 | |
384bc5e0 DV |
609 | DRM_INFO("radeon kernel modesetting enabled.\n"); |
610 | radeon_register_atpx_handler(); | |
611 | ||
612 | return pci_register_driver(&radeon_kms_pci_driver); | |
1da177e4 LT |
613 | } |
614 | ||
384bc5e0 | 615 | static void __exit radeon_module_exit(void) |
1da177e4 | 616 | { |
384bc5e0 | 617 | pci_unregister_driver(&radeon_kms_pci_driver); |
6a9ee8af | 618 | radeon_unregister_atpx_handler(); |
534e5f84 | 619 | mmu_notifier_synchronize(); |
1da177e4 LT |
620 | } |
621 | ||
384bc5e0 DV |
622 | module_init(radeon_module_init); |
623 | module_exit(radeon_module_exit); | |
1da177e4 | 624 | |
b5e89ed5 DA |
625 | MODULE_AUTHOR(DRIVER_AUTHOR); |
626 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 627 | MODULE_LICENSE("GPL and additional rights"); |