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Merge tag 'mm-hotfixes-stable-2025-07-11-16-16' of git://git.kernel.org/pub/scm/linux...
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
6d587203 1/*
1da177e4
LT		 2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
fea5d61b 32#include <linux/aperture.h>
f9183127 33#include <linux/compat.h>
e0cd3608 34#include <linux/module.h>
10ebc0bc
DA		 35#include <linux/pm_runtime.h>
36#include <linux/vga_switcheroo.h>
534e5f84 37#include <linux/mmu_notifier.h>
625c18d7 38#include <linux/pci.h>
d9fc9413 39
b86711c6 40#include <drm/clients/drm_client_setup.h>
f9183127 41#include <drm/drm_drv.h>
f9183127 42#include <drm/drm_file.h>
41d48e55 43#include <drm/drm_fourcc.h>
f9183127
SR		 44#include <drm/drm_gem.h>
45#include <drm/drm_ioctl.h>
f9183127 46#include <drm/drm_pciids.h>
fcd70cd3 47#include <drm/drm_probe_helper.h>
f9183127
SR		 48#include <drm/drm_vblank.h>
49#include <drm/radeon_drm.h>
50
51#include "radeon_drv.h"
384bc5e0 52#include "radeon.h"
f3723ad1 53#include "radeon_kms.h"
0a2e8d51 54#include "radeon_ttm.h"
4d3efadd 55#include "radeon_device.h"
4138b62b 56#include "radeon_prime.h"
e28740ec 57
771fe6b9
JG		 58/*
59 * KMS wrapper.
0de1a57b
DA		 60 * - 2.0.0 - initial interface
61 * - 2.1.0 - add square tiling interface
fdb43528 62 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 63 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 64 * - 2.4.0 - add crtc id query
148a03bc 65 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 66 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 67 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 68 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 69 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD		 70 * 2.10.0 - fusion 2D tiling
71 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 72 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 73 * 2.13.0 - virtual memory support, streamout
285484e2 74 * 2.14.0 - add evergreen tiling informations
609c1e15 75 * 2.15.0 - add max_pipes query
d2609875 76 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 77 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 78 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 79 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 80 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 81 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 82 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 83 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 84 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 85 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 86 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 87 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 88 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 89 * 2.29.0 - R500 FP16 color clear registers
774c389f 90 * 2.30.0 - fix for FMASK texturing
a0a53aa8 91 * 2.31.0 - Add fastfb support for rs690
902aaef6 92 * 2.32.0 - new info request for rings working
64d7b8be 93 * 2.33.0 - Add SI tiling mode array query
39aee490 94 * 2.34.0 - Add CIK tiling mode array query
32f79a8a 95 * 2.35.0 - Add CIK macrotile mode array query
9482d0d3 96 * 2.36.0 - Fix CIK DCE tiling setup
7c4c62a0 97 * 2.37.0 - allow GS ring setup on r6xx/r7xx
020ff546
MO		 98 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
99 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
65fcf668 100 * 2.39.0 - Add INFO query for number of active CUs
72a9987e 101 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
897eba82 102 * CS to GPU on >= r600
16613743 103 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
1957d6be 104 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
72b9076b 105 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
8c4f2bbd 106 * 2.44.0 - SET_APPEND_CNT packet3 support
3d02b7fe 107 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
662ce7bc 108 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
4d6bdbad 109 * 2.47.0 - Add UVD_NO_OP register support
113d0f9d 110 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
51964e9e 111 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
75cb00dc 112 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
771fe6b9
JG		 113 */
114#define KMS_DRIVER_MAJOR 2
75cb00dc 115#define KMS_DRIVER_MINOR 50
771fe6b9 116#define KMS_DRIVER_PATCHLEVEL 0
1da177e4 117
689b9d74 118int radeon_no_wb;
e9ced8e0 119int radeon_modeset = -1;
771fe6b9 120int radeon_dynclks = -1;
803d411b 121int radeon_r4xx_atom;
037d1a66 122int radeon_agpmode = -1;
803d411b 123int radeon_vram_limit;
edcd26e8 124int radeon_gart_size = -1; /* auto */
803d411b
SS		 125int radeon_benchmarking;
126int radeon_testing;
127int radeon_connector_table;
4ce001ab 128int radeon_tv = 1;
108dc8e8 129int radeon_audio = -1;
803d411b
SS		 130int radeon_disp_priority;
131int radeon_hw_i2c;
197bbb3d 132int radeon_pcie_gen2 = -1;
a18cee15 133int radeon_msi = -1;
3368ff0c 134int radeon_lockup_timeout = 10000;
803d411b 135int radeon_fastfb;
da321c8a 136int radeon_dpm = -1;
1294d4a3 137int radeon_aspm = -1;
10ebc0bc 138int radeon_runtime_pm = -1;
803d411b 139int radeon_hard_reset;
dfc230f9
CK		 140int radeon_vm_size = 8;
141int radeon_vm_block_size = -1;
803d411b 142int radeon_deep_color;
39dc5454 143int radeon_use_pflipirq = 2;
6e909f74 144int radeon_bapm = -1;
bc13018b 145int radeon_backlight = -1;
875711f0 146int radeon_auxch = -1;
f1a0a67a 147int radeon_uvd = 1;
fabb5935 148int radeon_vce = 1;
689b9d74 149
61a2d07d 150MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA		 151module_param_named(no_wb, radeon_no_wb, int, 0444);
152
771fe6b9
JG		 153MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
154module_param_named(modeset, radeon_modeset, int, 0400);
155
156MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
157module_param_named(dynclks, radeon_dynclks, int, 0444);
158
159MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
160module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
161
8902e6f2 162MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
771fe6b9
JG		 163module_param_named(vramlimit, radeon_vram_limit, int, 0600);
164
165MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
166module_param_named(agpmode, radeon_agpmode, int, 0444);
167
edcd26e8 168MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
771fe6b9
JG		 169module_param_named(gartsize, radeon_gart_size, int, 0600);
170
171MODULE_PARM_DESC(benchmark, "Run benchmark");
172module_param_named(benchmark, radeon_benchmarking, int, 0444);
173
ecc0b326
MD		 174MODULE_PARM_DESC(test, "Run tests");
175module_param_named(test, radeon_testing, int, 0444);
176
771fe6b9
JG		 177MODULE_PARM_DESC(connector_table, "Force connector table");
178module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA		 179
180MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
181module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 182
108dc8e8 183MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
dafc3bd5
CK		 184module_param_named(audio, radeon_audio, int, 0444);
185
f46c0120
AD		 186MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
187module_param_named(disp_priority, radeon_disp_priority, int, 0444);
188
e2b0a8e1
AD		 189MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
190module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
191
197bbb3d 192MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD		 193module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
194
a18cee15
AD		 195MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
196module_param_named(msi, radeon_msi, int, 0444);
197
b5c9ecab 198MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
3368ff0c
CK		 199module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
200
a0a53aa8
SL		 201MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
202module_param_named(fastfb, radeon_fastfb, int, 0444);
203
da321c8a
AD		 204MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
205module_param_named(dpm, radeon_dpm, int, 0444);
206
1294d4a3
AD		 207MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
208module_param_named(aspm, radeon_aspm, int, 0444);
209
10ebc0bc
DA		 210MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
211module_param_named(runpm, radeon_runtime_pm, int, 0444);
212
363eb0b4
AD		 213MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
214module_param_named(hard_reset, radeon_hard_reset, int, 0444);
215
20b2656d 216MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
c1c44132
CK		 217module_param_named(vm_size, radeon_vm_size, int, 0444);
218
dfc230f9 219MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
4510fb98
CK		 220module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
221
a624f429
AD		 222MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
223module_param_named(deep_color, radeon_deep_color, int, 0444);
224
39dc5454
MK		 225MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
226module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
227
6e909f74
AD		 228MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
229module_param_named(bapm, radeon_bapm, int, 0444);
230
bc13018b
AD		 231MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
232module_param_named(backlight, radeon_backlight, int, 0444);
233
875711f0
DA		 234MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
235module_param_named(auxch, radeon_auxch, int, 0444);
236
f1a0a67a
JG		 237MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
238module_param_named(uvd, radeon_uvd, int, 0444);
239
fabb5935
JG		 240MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
241module_param_named(vce, radeon_vce, int, 0444);
242
36ffce0a
FK		 243int radeon_si_support = 1;
244MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
245module_param_named(si_support, radeon_si_support, int, 0444);
36ffce0a 246
2b059658
MD		 247int radeon_cik_support = 1;
248MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
e7f78b69 249module_param_named(cik_support, radeon_cik_support, int, 0444);
e7f78b69 250
c3e3c1aa 251static const struct pci_device_id pciidlist[] = {
14adc892
CK		 252 radeon_PCI_IDS
253};
14adc892
CK		 254MODULE_DEVICE_TABLE(pci, pciidlist);
255
70a59dd8 256static const struct drm_driver kms_driver;
771fe6b9 257
56550d94
GKH		 258static int radeon_pci_probe(struct pci_dev *pdev,
259 const struct pci_device_id *ent)
771fe6b9 260{
9dbc88d0 261 unsigned long flags = 0;
60a9472c 262 struct drm_device *ddev;
a9ed2f05 263 struct radeon_device *rdev;
41d48e55 264 const struct drm_format_info *format;
30238151
TR		 265 int ret;
266
9dbc88d0
HG		 267 if (!ent)
268 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */
269
270 flags = ent->driver_data;
271
272 if (!radeon_si_support) {
273 switch (flags & RADEON_FAMILY_MASK) {
274 case CHIP_TAHITI:
275 case CHIP_PITCAIRN:
276 case CHIP_VERDE:
277 case CHIP_OLAND:
278 case CHIP_HAINAN:
279 dev_info(&pdev->dev,
280 "SI support disabled by module param\n");
281 return -ENODEV;
282 }
283 }
284 if (!radeon_cik_support) {
285 switch (flags & RADEON_FAMILY_MASK) {
286 case CHIP_KAVERI:
287 case CHIP_BONAIRE:
288 case CHIP_HAWAII:
289 case CHIP_KABINI:
290 case CHIP_MULLINS:
291 dev_info(&pdev->dev,
292 "CIK support disabled by module param\n");
293 return -ENODEV;
294 }
295 }
296
b00e5334 297 if (vga_switcheroo_client_probe_defer(pdev))
14d20001
LW		 298 return -EPROBE_DEFER;
299
a56f7428 300 /* Get rid of things like offb */
fea5d61b 301 ret = aperture_remove_conflicting_pci_devices(pdev, kms_driver.name);
30238151
TR		 302 if (ret)
303 return ret;
a56f7428 304
a9ed2f05
WHP		 305 rdev = devm_drm_dev_alloc(&pdev->dev, &kms_driver, typeof(*rdev), ddev);
306 if (IS_ERR(rdev))
307 return PTR_ERR(rdev);
308
309 rdev->dev = &pdev->dev;
310 rdev->pdev = pdev;
311 ddev = rdev_to_drm(rdev);
312 ddev->dev_private = rdev;
b8076b5e
DV		 313
314 ret = pci_enable_device(pdev);
315 if (ret)
316 goto err_free;
317
60a9472c 318 pci_set_drvdata(pdev, ddev);
b8076b5e 319
90985660
WHP		 320 ret = radeon_driver_load_kms(ddev, flags);
321 if (ret)
322 goto err_agp;
323
78dd6a8d 324 ret = drm_dev_register(ddev, flags);
b8076b5e
DV		 325 if (ret)
326 goto err_agp;
327
41d48e55
TZ		 328 if (rdev->mc.real_vram_size <= (8 * 1024 * 1024))
329 format = drm_format_info(DRM_FORMAT_C8);
330 else if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32 * 1024 * 1024))
331 format = drm_format_info(DRM_FORMAT_RGB565);
332 else
333 format = NULL;
334
335 drm_client_setup(ddev, format);
e317a69f 336
b8076b5e
DV		 337 return 0;
338
339err_agp:
b8076b5e
DV		 340 pci_disable_device(pdev);
341err_free:
60a9472c 342 drm_dev_put(ddev);
b8076b5e 343 return ret;
771fe6b9
JG		 344}
345
346static void
347radeon_pci_remove(struct pci_dev *pdev)
348{
349 struct drm_device *dev = pci_get_drvdata(pdev);
350
351 drm_put_dev(dev);
352}
353
a801abe4
AD		 354static void
355radeon_pci_shutdown(struct pci_dev *pdev)
356{
357 /* if we are running in a VM, make sure the device
b9b487e4 358 * torn down properly on reboot/shutdown
a801abe4 359 */
b9b487e4
AD		 360 if (radeon_device_is_virtual())
361 radeon_pci_remove(pdev);
d02f5aab 362
c1bfd74b 363#if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64)
4cae34d0
K		 364 /*
365 * Some adapters need to be suspended before a
d02f5aab 366 * shutdown occurs in order to prevent an error
c1bfd74b
TY		 367 * during kexec, shutdown or reboot.
368 * Make this power and Loongson specific because
369 * it breaks some other boards.
d02f5aab 370 */
4cae34d0 371 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
d02f5aab 372#endif
a801abe4
AD		 373}
374
7473e830 375static int radeon_pmops_suspend(struct device *dev)
771fe6b9 376{
59d788b1 377 struct drm_device *drm_dev = dev_get_drvdata(dev);
803d411b 378
274ad65c 379 return radeon_suspend_kms(drm_dev, true, true, false);
771fe6b9
JG		 380}
381
7473e830 382static int radeon_pmops_resume(struct device *dev)
771fe6b9 383{
59d788b1 384 struct drm_device *drm_dev = dev_get_drvdata(dev);
103917b3
AD		 385
386 /* GPU comes up enabled by the bios on resume */
387 if (radeon_is_px(drm_dev)) {
388 pm_runtime_disable(dev);
389 pm_runtime_set_active(dev);
390 pm_runtime_enable(dev);
391 }
392
10ebc0bc 393 return radeon_resume_kms(drm_dev, true, true);
7473e830
DA		 394}
395
396static int radeon_pmops_freeze(struct device *dev)
397{
59d788b1 398 struct drm_device *drm_dev = dev_get_drvdata(dev);
803d411b 399
274ad65c 400 return radeon_suspend_kms(drm_dev, false, true, true);
771fe6b9
JG		 401}
402
7473e830
DA		 403static int radeon_pmops_thaw(struct device *dev)
404{
59d788b1 405 struct drm_device *drm_dev = dev_get_drvdata(dev);
803d411b 406
10ebc0bc
DA		 407 return radeon_resume_kms(drm_dev, false, true);
408}
409
410static int radeon_pmops_runtime_suspend(struct device *dev)
411{
412 struct pci_dev *pdev = to_pci_dev(dev);
413 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 414
90c4cde9 415 if (!radeon_is_px(drm_dev)) {
1d8eec8b
DA		 416 pm_runtime_forbid(dev);
417 return -EBUSY;
418 }
9babd35a 419
10ebc0bc
DA		 420 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
421 drm_kms_helper_poll_disable(drm_dev);
10ebc0bc 422
3655d1a6 423 radeon_suspend_kms(drm_dev, false, false, false);
10ebc0bc
DA		 424 pci_save_state(pdev);
425 pci_disable_device(pdev);
b440bde7 426 pci_ignore_hotplug(pdev);
31764c1e
AD		 427 if (radeon_is_atpx_hybrid())
428 pci_set_power_state(pdev, PCI_D3cold);
84919992 429 else if (!radeon_has_atpx_dgpu_power_cntl())
f7ea4189 430 pci_set_power_state(pdev, PCI_D3hot);
10ebc0bc
DA		 431 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
432
433 return 0;
434}
435
436static int radeon_pmops_runtime_resume(struct device *dev)
437{
438 struct pci_dev *pdev = to_pci_dev(dev);
439 struct drm_device *drm_dev = pci_get_drvdata(pdev);
440 int ret;
441
90c4cde9 442 if (!radeon_is_px(drm_dev))
9babd35a
AD		 443 return -EINVAL;
444
10ebc0bc
DA		 445 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
446
84919992
AD		 447 if (radeon_is_atpx_hybrid() ||
448 !radeon_has_atpx_dgpu_power_cntl())
449 pci_set_power_state(pdev, PCI_D0);
10ebc0bc
DA		 450 pci_restore_state(pdev);
451 ret = pci_enable_device(pdev);
452 if (ret)
453 return ret;
454 pci_set_master(pdev);
455
456 ret = radeon_resume_kms(drm_dev, false, false);
457 drm_kms_helper_poll_enable(drm_dev);
10ebc0bc
DA		 458 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
459 return 0;
460}
461
462static int radeon_pmops_runtime_idle(struct device *dev)
463{
59d788b1 464 struct drm_device *drm_dev = dev_get_drvdata(dev);
10ebc0bc
DA		 465 struct drm_crtc *crtc;
466
90c4cde9 467 if (!radeon_is_px(drm_dev)) {
1d8eec8b 468 pm_runtime_forbid(dev);
10ebc0bc
DA		 469 return -EBUSY;
470 }
471
472 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
473 if (crtc->enabled) {
474 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
475 return -EBUSY;
476 }
477 }
478
479 pm_runtime_mark_last_busy(dev);
480 pm_runtime_autosuspend(dev);
481 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
482 return 1;
483}
484
485long radeon_drm_ioctl(struct file *filp,
486 unsigned int cmd, unsigned long arg)
487{
488 struct drm_file *file_priv = filp->private_data;
489 struct drm_device *dev;
490 long ret;
803d411b 491
10ebc0bc
DA		 492 dev = file_priv->minor->dev;
493 ret = pm_runtime_get_sync(dev->dev);
9fb10671
AP		 494 if (ret < 0) {
495 pm_runtime_put_autosuspend(dev->dev);
10ebc0bc 496 return ret;
9fb10671 497 }
10ebc0bc
DA		 498
499 ret = drm_ioctl(filp, cmd, arg);
552f9d60 500
10ebc0bc
DA		 501 pm_runtime_mark_last_busy(dev->dev);
502 pm_runtime_put_autosuspend(dev->dev);
503 return ret;
7473e830
DA		 504}
505
ff32d39b
AV		 506#ifdef CONFIG_COMPAT
507static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
508{
509 unsigned int nr = DRM_IOCTL_NR(cmd);
ff32d39b
AV		 510
511 if (nr < DRM_COMMAND_BASE)
512 return drm_compat_ioctl(filp, cmd, arg);
513
d4242216 514 return radeon_drm_ioctl(filp, cmd, arg);
ff32d39b
AV		 515}
516#endif
517
7473e830
DA		 518static const struct dev_pm_ops radeon_pm_ops = {
519 .suspend = radeon_pmops_suspend,
520 .resume = radeon_pmops_resume,
521 .freeze = radeon_pmops_freeze,
522 .thaw = radeon_pmops_thaw,
523 .poweroff = radeon_pmops_freeze,
524 .restore = radeon_pmops_resume,
10ebc0bc
DA		 525 .runtime_suspend = radeon_pmops_runtime_suspend,
526 .runtime_resume = radeon_pmops_runtime_resume,
527 .runtime_idle = radeon_pmops_runtime_idle,
7473e830
DA		 528};
529
e08e96de
AV		 530static const struct file_operations radeon_driver_kms_fops = {
531 .owner = THIS_MODULE,
532 .open = drm_open,
533 .release = drm_release,
10ebc0bc 534 .unlocked_ioctl = radeon_drm_ioctl,
645e9541 535 .mmap = drm_gem_mmap,
e08e96de 536 .poll = drm_poll,
e08e96de
AV		 537 .read = drm_read,
538#ifdef CONFIG_COMPAT
539 .compat_ioctl = radeon_kms_compat_ioctl,
540#endif
641bb439 541 .fop_flags = FOP_UNSIGNED_OFFSET,
e08e96de
AV		 542};
543
384bc5e0
DV		 544static const struct drm_ioctl_desc radeon_ioctls_kms[] = {
545 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
546 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
547 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
548 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
549 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
550 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
551 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
552 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
553 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
554 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
555 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
556 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
557 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
558 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
559 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
560 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
561 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
562 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
563 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
564 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
565 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
566 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
567 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
568 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
569 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
570 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
571 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
572 /* KMS */
573 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
574 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
575 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
576 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
384bc5e0
DV		 577 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
578 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
579 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
580 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
581 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
582 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
583 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
584 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
585 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
586};
587
70a59dd8 588static const struct drm_driver kms_driver = {
771fe6b9 589 .driver_features =
384bc5e0 590 DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET,
771fe6b9 591 .open = radeon_driver_open_kms,
771fe6b9 592 .postclose = radeon_driver_postclose_kms,
771fe6b9 593 .unload = radeon_driver_unload_kms,
771fe6b9 594 .ioctls = radeon_ioctls_kms,
384bc5e0 595 .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms),
ff72145b
DA		 596 .dumb_create = radeon_mode_dumb_create,
597 .dumb_map_offset = radeon_mode_dumb_mmap,
e08e96de 598 .fops = &radeon_driver_kms_fops,
40f5cf99 599
1e6d17a5 600 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
40f5cf99 601
41d48e55
TZ		 602 RADEON_FBDEV_DRIVER_OPS,
603
771fe6b9
JG		 604 .name = DRIVER_NAME,
605 .desc = DRIVER_DESC,
771fe6b9
JG		 606 .major = KMS_DRIVER_MAJOR,
607 .minor = KMS_DRIVER_MINOR,
608 .patchlevel = KMS_DRIVER_PATCHLEVEL,
609};
771fe6b9 610
8410ea3b
DA		 611static struct pci_driver radeon_kms_pci_driver = {
612 .name = DRIVER_NAME,
613 .id_table = pciidlist,
614 .probe = radeon_pci_probe,
615 .remove = radeon_pci_remove,
a801abe4 616 .shutdown = radeon_pci_shutdown,
7473e830 617 .driver.pm = &radeon_pm_ops,
8410ea3b 618};
771fe6b9 619
384bc5e0 620static int __init radeon_module_init(void)
1da177e4 621{
6a2d2ddf 622 if (drm_firmware_drivers_only() && radeon_modeset == -1)
e9ced8e0 623 radeon_modeset = 0;
384bc5e0 624
35f7775f 625 if (radeon_modeset == 0)
14adc892 626 return -EINVAL;
14adc892 627
384bc5e0
DV		 628 DRM_INFO("radeon kernel modesetting enabled.\n");
629 radeon_register_atpx_handler();
630
631 return pci_register_driver(&radeon_kms_pci_driver);
1da177e4
LT		 632}
633
384bc5e0 634static void __exit radeon_module_exit(void)
1da177e4 635{
384bc5e0 636 pci_unregister_driver(&radeon_kms_pci_driver);
6a9ee8af 637 radeon_unregister_atpx_handler();
534e5f84 638 mmu_notifier_synchronize();
1da177e4
LT		 639}
640
384bc5e0
DV		 641module_init(radeon_module_init);
642module_exit(radeon_module_exit);
1da177e4 643
b5e89ed5
DA		 644MODULE_AUTHOR(DRIVER_AUTHOR);
645MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 646MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)