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Merge greybus driver tree into 4.8-rc6
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
1da177e4
LT		 1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
1da177e4
LT		 34#include "radeon_drv.h"
35
760285e7 36#include <drm/drm_pciids.h>
771fe6b9 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
10ebc0bc
DA		 39#include <linux/pm_runtime.h>
40#include <linux/vga_switcheroo.h>
d9fc9413
DV		 41#include <drm/drm_gem.h>
42
10ebc0bc 43#include "drm_crtc_helper.h"
e28740ec
OG		 44#include "radeon_kfd.h"
45
771fe6b9
JG		 46/*
47 * KMS wrapper.
0de1a57b
DA		 48 * - 2.0.0 - initial interface
49 * - 2.1.0 - add square tiling interface
fdb43528 50 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 51 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 52 * - 2.4.0 - add crtc id query
148a03bc 53 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 54 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 55 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 56 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 57 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD		 58 * 2.10.0 - fusion 2D tiling
59 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 60 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 61 * 2.13.0 - virtual memory support, streamout
285484e2 62 * 2.14.0 - add evergreen tiling informations
609c1e15 63 * 2.15.0 - add max_pipes query
d2609875 64 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 65 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 66 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 67 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 68 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 69 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 70 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 71 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 72 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 73 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 74 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 75 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 76 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 77 * 2.29.0 - R500 FP16 color clear registers
774c389f 78 * 2.30.0 - fix for FMASK texturing
a0a53aa8 79 * 2.31.0 - Add fastfb support for rs690
902aaef6 80 * 2.32.0 - new info request for rings working
64d7b8be 81 * 2.33.0 - Add SI tiling mode array query
39aee490 82 * 2.34.0 - Add CIK tiling mode array query
32f79a8a 83 * 2.35.0 - Add CIK macrotile mode array query
9482d0d3 84 * 2.36.0 - Fix CIK DCE tiling setup
7c4c62a0 85 * 2.37.0 - allow GS ring setup on r6xx/r7xx
020ff546
MO		 86 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
87 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
65fcf668 88 * 2.39.0 - Add INFO query for number of active CUs
72a9987e 89 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
897eba82 90 * CS to GPU on >= r600
16613743 91 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
1957d6be 92 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
72b9076b 93 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
8c4f2bbd 94 * 2.44.0 - SET_APPEND_CNT packet3 support
3d02b7fe 95 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
662ce7bc 96 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
771fe6b9
JG		 97 */
98#define KMS_DRIVER_MAJOR 2
662ce7bc 99#define KMS_DRIVER_MINOR 46
771fe6b9
JG		 100#define KMS_DRIVER_PATCHLEVEL 0
101int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
102int radeon_driver_unload_kms(struct drm_device *dev);
771fe6b9
JG		 103void radeon_driver_lastclose_kms(struct drm_device *dev);
104int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
105void radeon_driver_postclose_kms(struct drm_device *dev,
106 struct drm_file *file_priv);
107void radeon_driver_preclose_kms(struct drm_device *dev,
108 struct drm_file *file_priv);
274ad65c
JG		 109int radeon_suspend_kms(struct drm_device *dev, bool suspend,
110 bool fbcon, bool freeze);
10ebc0bc 111int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 112u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
113int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
114void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
115int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
f5a80209
MK		 116 int *max_error,
117 struct timeval *vblank_time,
118 unsigned flags);
771fe6b9
JG		 119void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
120int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
121void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
e9f0d76f 122irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
771fe6b9 123void radeon_gem_object_free(struct drm_gem_object *obj);
721604a1
JG		 124int radeon_gem_object_open(struct drm_gem_object *obj,
125 struct drm_file *file_priv);
126void radeon_gem_object_close(struct drm_gem_object *obj,
127 struct drm_file *file_priv);
f72a113a
CK		 128struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
129 struct drm_gem_object *gobj,
130 int flags);
88e72717
TR		 131extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
132 unsigned int flags, int *vpos, int *hpos,
3bb403bf
VS		 133 ktime_t *stime, ktime_t *etime,
134 const struct drm_display_mode *mode);
90c4cde9 135extern bool radeon_is_px(struct drm_device *dev);
baa70943 136extern const struct drm_ioctl_desc radeon_ioctls_kms[];
771fe6b9
JG		 137extern int radeon_max_kms_ioctl;
138int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
ff72145b
DA		 139int radeon_mode_dumb_mmap(struct drm_file *filp,
140 struct drm_device *dev,
141 uint32_t handle, uint64_t *offset_p);
142int radeon_mode_dumb_create(struct drm_file *file_priv,
143 struct drm_device *dev,
144 struct drm_mode_create_dumb *args);
1e6d17a5
AP		 145struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
146struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
b5e9c1a2 147 struct dma_buf_attachment *,
1e6d17a5
AP		 148 struct sg_table *sg);
149int radeon_gem_prime_pin(struct drm_gem_object *obj);
280cf211 150void radeon_gem_prime_unpin(struct drm_gem_object *obj);
3aac4502 151struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
1e6d17a5
AP		 152void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
153void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
14adc892
CK		 154extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
155 unsigned long arg);
ff72145b 156
771fe6b9
JG		 157#if defined(CONFIG_DEBUG_FS)
158int radeon_debugfs_init(struct drm_minor *minor);
159void radeon_debugfs_cleanup(struct drm_minor *minor);
160#endif
771fe6b9 161
14adc892
CK		 162/* atpx handler */
163#if defined(CONFIG_VGA_SWITCHEROO)
164void radeon_register_atpx_handler(void);
165void radeon_unregister_atpx_handler(void);
e1052b35 166bool radeon_has_atpx_dgpu_power_cntl(void);
b8c9fd5a 167bool radeon_is_atpx_hybrid(void);
14adc892
CK		 168#else
169static inline void radeon_register_atpx_handler(void) {}
170static inline void radeon_unregister_atpx_handler(void) {}
e1052b35 171static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
b8c9fd5a 172static inline bool radeon_is_atpx_hybrid(void) { return false; }
14adc892 173#endif
1da177e4 174
689b9d74 175int radeon_no_wb;
e9ced8e0 176int radeon_modeset = -1;
771fe6b9
JG		 177int radeon_dynclks = -1;
178int radeon_r4xx_atom = 0;
179int radeon_agpmode = 0;
180int radeon_vram_limit = 0;
edcd26e8 181int radeon_gart_size = -1; /* auto */
771fe6b9 182int radeon_benchmarking = 0;
ecc0b326 183int radeon_testing = 0;
771fe6b9 184int radeon_connector_table = 0;
4ce001ab 185int radeon_tv = 1;
108dc8e8 186int radeon_audio = -1;
f46c0120 187int radeon_disp_priority = 0;
e2b0a8e1 188int radeon_hw_i2c = 0;
197bbb3d 189int radeon_pcie_gen2 = -1;
a18cee15 190int radeon_msi = -1;
3368ff0c 191int radeon_lockup_timeout = 10000;
a0a53aa8 192int radeon_fastfb = 0;
da321c8a 193int radeon_dpm = -1;
1294d4a3 194int radeon_aspm = -1;
10ebc0bc 195int radeon_runtime_pm = -1;
363eb0b4 196int radeon_hard_reset = 0;
dfc230f9
CK		 197int radeon_vm_size = 8;
198int radeon_vm_block_size = -1;
a624f429 199int radeon_deep_color = 0;
39dc5454 200int radeon_use_pflipirq = 2;
6e909f74 201int radeon_bapm = -1;
bc13018b 202int radeon_backlight = -1;
875711f0 203int radeon_auxch = -1;
9843ead0 204int radeon_mst = 0;
f1a0a67a 205int radeon_uvd = 1;
fabb5935 206int radeon_vce = 1;
689b9d74 207
61a2d07d 208MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA		 209module_param_named(no_wb, radeon_no_wb, int, 0444);
210
771fe6b9
JG		 211MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
212module_param_named(modeset, radeon_modeset, int, 0400);
213
214MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
215module_param_named(dynclks, radeon_dynclks, int, 0444);
216
217MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
218module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
219
8902e6f2 220MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
771fe6b9
JG		 221module_param_named(vramlimit, radeon_vram_limit, int, 0600);
222
223MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
224module_param_named(agpmode, radeon_agpmode, int, 0444);
225
edcd26e8 226MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
771fe6b9
JG		 227module_param_named(gartsize, radeon_gart_size, int, 0600);
228
229MODULE_PARM_DESC(benchmark, "Run benchmark");
230module_param_named(benchmark, radeon_benchmarking, int, 0444);
231
ecc0b326
MD		 232MODULE_PARM_DESC(test, "Run tests");
233module_param_named(test, radeon_testing, int, 0444);
234
771fe6b9
JG		 235MODULE_PARM_DESC(connector_table, "Force connector table");
236module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA		 237
238MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
239module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 240
108dc8e8 241MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
dafc3bd5
CK		 242module_param_named(audio, radeon_audio, int, 0444);
243
f46c0120
AD		 244MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
245module_param_named(disp_priority, radeon_disp_priority, int, 0444);
246
e2b0a8e1
AD		 247MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
248module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
249
197bbb3d 250MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD		 251module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
252
a18cee15
AD		 253MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
254module_param_named(msi, radeon_msi, int, 0444);
255
b5c9ecab 256MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
3368ff0c
CK		 257module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
258
a0a53aa8
SL		 259MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
260module_param_named(fastfb, radeon_fastfb, int, 0444);
261
da321c8a
AD		 262MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
263module_param_named(dpm, radeon_dpm, int, 0444);
264
1294d4a3
AD		 265MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
266module_param_named(aspm, radeon_aspm, int, 0444);
267
10ebc0bc
DA		 268MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
269module_param_named(runpm, radeon_runtime_pm, int, 0444);
270
363eb0b4
AD		 271MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
272module_param_named(hard_reset, radeon_hard_reset, int, 0444);
273
20b2656d 274MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
c1c44132
CK		 275module_param_named(vm_size, radeon_vm_size, int, 0444);
276
dfc230f9 277MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
4510fb98
CK		 278module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
279
a624f429
AD		 280MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
281module_param_named(deep_color, radeon_deep_color, int, 0444);
282
39dc5454
MK		 283MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
284module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
285
6e909f74
AD		 286MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
287module_param_named(bapm, radeon_bapm, int, 0444);
288
bc13018b
AD		 289MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
290module_param_named(backlight, radeon_backlight, int, 0444);
291
875711f0
DA		 292MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
293module_param_named(auxch, radeon_auxch, int, 0444);
294
9843ead0
DA		 295MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
296module_param_named(mst, radeon_mst, int, 0444);
297
f1a0a67a
JG		 298MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
299module_param_named(uvd, radeon_uvd, int, 0444);
300
fabb5935
JG		 301MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
302module_param_named(vce, radeon_vce, int, 0444);
303
14adc892
CK		 304static struct pci_device_id pciidlist[] = {
305 radeon_PCI_IDS
306};
307
308MODULE_DEVICE_TABLE(pci, pciidlist);
309
771fe6b9
JG		 310static struct drm_driver kms_driver;
311
30238151 312static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
a56f7428
BH		 313{
314 struct apertures_struct *ap;
315 bool primary = false;
316
317 ap = alloc_apertures(1);
30238151
TR		 318 if (!ap)
319 return -ENOMEM;
320
a56f7428
BH		 321 ap->ranges[0].base = pci_resource_start(pdev, 0);
322 ap->ranges[0].size = pci_resource_len(pdev, 0);
323
324#ifdef CONFIG_X86
325 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
326#endif
327 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
328 kfree(ap);
30238151
TR		 329
330 return 0;
a56f7428
BH		 331}
332
56550d94
GKH		 333static int radeon_pci_probe(struct pci_dev *pdev,
334 const struct pci_device_id *ent)
771fe6b9 335{
30238151
TR		 336 int ret;
337
412c8f7d
OG		 338 /*
339 * Initialize amdkfd before starting radeon. If it was not loaded yet,
340 * defer radeon probing
341 */
342 ret = radeon_kfd_init();
343 if (ret == -EPROBE_DEFER)
344 return ret;
345
b00e5334 346 if (vga_switcheroo_client_probe_defer(pdev))
14d20001
LW		 347 return -EPROBE_DEFER;
348
a56f7428 349 /* Get rid of things like offb */
30238151
TR		 350 ret = radeon_kick_out_firmware_fb(pdev);
351 if (ret)
352 return ret;
a56f7428 353
dcdb1674 354 return drm_get_pci_dev(pdev, ent, &kms_driver);
771fe6b9
JG		 355}
356
357static void
358radeon_pci_remove(struct pci_dev *pdev)
359{
360 struct drm_device *dev = pci_get_drvdata(pdev);
361
362 drm_put_dev(dev);
363}
364
7473e830 365static int radeon_pmops_suspend(struct device *dev)
771fe6b9 366{
7473e830
DA		 367 struct pci_dev *pdev = to_pci_dev(dev);
368 struct drm_device *drm_dev = pci_get_drvdata(pdev);
274ad65c 369 return radeon_suspend_kms(drm_dev, true, true, false);
771fe6b9
JG		 370}
371
7473e830 372static int radeon_pmops_resume(struct device *dev)
771fe6b9 373{
7473e830
DA		 374 struct pci_dev *pdev = to_pci_dev(dev);
375 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 376 return radeon_resume_kms(drm_dev, true, true);
7473e830
DA		 377}
378
379static int radeon_pmops_freeze(struct device *dev)
380{
381 struct pci_dev *pdev = to_pci_dev(dev);
382 struct drm_device *drm_dev = pci_get_drvdata(pdev);
274ad65c 383 return radeon_suspend_kms(drm_dev, false, true, true);
771fe6b9
JG		 384}
385
7473e830
DA		 386static int radeon_pmops_thaw(struct device *dev)
387{
388 struct pci_dev *pdev = to_pci_dev(dev);
389 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc
DA		 390 return radeon_resume_kms(drm_dev, false, true);
391}
392
393static int radeon_pmops_runtime_suspend(struct device *dev)
394{
395 struct pci_dev *pdev = to_pci_dev(dev);
396 struct drm_device *drm_dev = pci_get_drvdata(pdev);
397 int ret;
398
90c4cde9 399 if (!radeon_is_px(drm_dev)) {
1d8eec8b
DA		 400 pm_runtime_forbid(dev);
401 return -EBUSY;
402 }
9babd35a 403
10ebc0bc
DA		 404 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
405 drm_kms_helper_poll_disable(drm_dev);
406 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
407
274ad65c 408 ret = radeon_suspend_kms(drm_dev, false, false, false);
10ebc0bc
DA		 409 pci_save_state(pdev);
410 pci_disable_device(pdev);
b440bde7 411 pci_ignore_hotplug(pdev);
31764c1e
AD		 412 if (radeon_is_atpx_hybrid())
413 pci_set_power_state(pdev, PCI_D3cold);
84919992 414 else if (!radeon_has_atpx_dgpu_power_cntl())
f7ea4189 415 pci_set_power_state(pdev, PCI_D3hot);
10ebc0bc
DA		 416 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
417
418 return 0;
419}
420
421static int radeon_pmops_runtime_resume(struct device *dev)
422{
423 struct pci_dev *pdev = to_pci_dev(dev);
424 struct drm_device *drm_dev = pci_get_drvdata(pdev);
425 int ret;
426
90c4cde9 427 if (!radeon_is_px(drm_dev))
9babd35a
AD		 428 return -EINVAL;
429
10ebc0bc
DA		 430 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
431
84919992
AD		 432 if (radeon_is_atpx_hybrid() ||
433 !radeon_has_atpx_dgpu_power_cntl())
434 pci_set_power_state(pdev, PCI_D0);
10ebc0bc
DA		 435 pci_restore_state(pdev);
436 ret = pci_enable_device(pdev);
437 if (ret)
438 return ret;
439 pci_set_master(pdev);
440
441 ret = radeon_resume_kms(drm_dev, false, false);
442 drm_kms_helper_poll_enable(drm_dev);
443 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
444 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
445 return 0;
446}
447
448static int radeon_pmops_runtime_idle(struct device *dev)
449{
450 struct pci_dev *pdev = to_pci_dev(dev);
451 struct drm_device *drm_dev = pci_get_drvdata(pdev);
452 struct drm_crtc *crtc;
453
90c4cde9 454 if (!radeon_is_px(drm_dev)) {
1d8eec8b 455 pm_runtime_forbid(dev);
10ebc0bc
DA		 456 return -EBUSY;
457 }
458
459 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
460 if (crtc->enabled) {
461 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
462 return -EBUSY;
463 }
464 }
465
466 pm_runtime_mark_last_busy(dev);
467 pm_runtime_autosuspend(dev);
468 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
469 return 1;
470}
471
472long radeon_drm_ioctl(struct file *filp,
473 unsigned int cmd, unsigned long arg)
474{
475 struct drm_file *file_priv = filp->private_data;
476 struct drm_device *dev;
477 long ret;
478 dev = file_priv->minor->dev;
479 ret = pm_runtime_get_sync(dev->dev);
480 if (ret < 0)
481 return ret;
482
483 ret = drm_ioctl(filp, cmd, arg);
484
485 pm_runtime_mark_last_busy(dev->dev);
486 pm_runtime_put_autosuspend(dev->dev);
487 return ret;
7473e830
DA		 488}
489
490static const struct dev_pm_ops radeon_pm_ops = {
491 .suspend = radeon_pmops_suspend,
492 .resume = radeon_pmops_resume,
493 .freeze = radeon_pmops_freeze,
494 .thaw = radeon_pmops_thaw,
495 .poweroff = radeon_pmops_freeze,
496 .restore = radeon_pmops_resume,
10ebc0bc
DA		 497 .runtime_suspend = radeon_pmops_runtime_suspend,
498 .runtime_resume = radeon_pmops_runtime_resume,
499 .runtime_idle = radeon_pmops_runtime_idle,
7473e830
DA		 500};
501
e08e96de
AV		 502static const struct file_operations radeon_driver_kms_fops = {
503 .owner = THIS_MODULE,
504 .open = drm_open,
505 .release = drm_release,
10ebc0bc 506 .unlocked_ioctl = radeon_drm_ioctl,
e08e96de
AV		 507 .mmap = radeon_mmap,
508 .poll = drm_poll,
e08e96de
AV		 509 .read = drm_read,
510#ifdef CONFIG_COMPAT
511 .compat_ioctl = radeon_kms_compat_ioctl,
512#endif
513};
514
771fe6b9
JG		 515static struct drm_driver kms_driver = {
516 .driver_features =
28185647 517 DRIVER_USE_AGP |
81e95697 518 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
f33bcab9 519 DRIVER_PRIME | DRIVER_RENDER,
771fe6b9 520 .load = radeon_driver_load_kms,
771fe6b9
JG		 521 .open = radeon_driver_open_kms,
522 .preclose = radeon_driver_preclose_kms,
523 .postclose = radeon_driver_postclose_kms,
524 .lastclose = radeon_driver_lastclose_kms,
915b4d11 525 .set_busid = drm_pci_set_busid,
771fe6b9 526 .unload = radeon_driver_unload_kms,
771fe6b9
JG		 527 .get_vblank_counter = radeon_get_vblank_counter_kms,
528 .enable_vblank = radeon_enable_vblank_kms,
529 .disable_vblank = radeon_disable_vblank_kms,
f5a80209
MK		 530 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
531 .get_scanout_position = radeon_get_crtc_scanoutpos,
771fe6b9
JG		 532#if defined(CONFIG_DEBUG_FS)
533 .debugfs_init = radeon_debugfs_init,
534 .debugfs_cleanup = radeon_debugfs_cleanup,
535#endif
536 .irq_preinstall = radeon_driver_irq_preinstall_kms,
537 .irq_postinstall = radeon_driver_irq_postinstall_kms,
538 .irq_uninstall = radeon_driver_irq_uninstall_kms,
539 .irq_handler = radeon_driver_irq_handler_kms,
771fe6b9 540 .ioctls = radeon_ioctls_kms,
71cbf451 541 .gem_free_object_unlocked = radeon_gem_object_free,
721604a1
JG		 542 .gem_open_object = radeon_gem_object_open,
543 .gem_close_object = radeon_gem_object_close,
ff72145b
DA		 544 .dumb_create = radeon_mode_dumb_create,
545 .dumb_map_offset = radeon_mode_dumb_mmap,
43387b37 546 .dumb_destroy = drm_gem_dumb_destroy,
e08e96de 547 .fops = &radeon_driver_kms_fops,
40f5cf99
AD		 548
549 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
550 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
f72a113a 551 .gem_prime_export = radeon_gem_prime_export,
1e6d17a5
AP		 552 .gem_prime_import = drm_gem_prime_import,
553 .gem_prime_pin = radeon_gem_prime_pin,
280cf211 554 .gem_prime_unpin = radeon_gem_prime_unpin,
3aac4502 555 .gem_prime_res_obj = radeon_gem_prime_res_obj,
1e6d17a5
AP		 556 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
557 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
558 .gem_prime_vmap = radeon_gem_prime_vmap,
559 .gem_prime_vunmap = radeon_gem_prime_vunmap,
40f5cf99 560
771fe6b9
JG		 561 .name = DRIVER_NAME,
562 .desc = DRIVER_DESC,
563 .date = DRIVER_DATE,
564 .major = KMS_DRIVER_MAJOR,
565 .minor = KMS_DRIVER_MINOR,
566 .patchlevel = KMS_DRIVER_PATCHLEVEL,
567};
771fe6b9
JG		 568
569static struct drm_driver *driver;
8410ea3b
DA		 570static struct pci_driver *pdriver;
571
8410ea3b
DA		 572static struct pci_driver radeon_kms_pci_driver = {
573 .name = DRIVER_NAME,
574 .id_table = pciidlist,
575 .probe = radeon_pci_probe,
576 .remove = radeon_pci_remove,
7473e830 577 .driver.pm = &radeon_pm_ops,
8410ea3b 578};
771fe6b9 579
1da177e4
LT		 580static int __init radeon_init(void)
581{
e9ced8e0
DA		 582 if (vgacon_text_force() && radeon_modeset == -1) {
583 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
584 radeon_modeset = 0;
585 }
e9ced8e0
DA		 586 /* set to modesetting by default if not nomodeset */
587 if (radeon_modeset == -1)
588 radeon_modeset = 1;
589
771fe6b9
JG		 590 if (radeon_modeset == 1) {
591 DRM_INFO("radeon kernel modesetting enabled.\n");
592 driver = &kms_driver;
8410ea3b 593 pdriver = &radeon_kms_pci_driver;
771fe6b9
JG		 594 driver->driver_features |= DRIVER_MODESET;
595 driver->num_ioctls = radeon_max_kms_ioctl;
6a9ee8af 596 radeon_register_atpx_handler();
14adc892
CK		 597
598 } else {
14adc892
CK		 599 DRM_ERROR("No UMS support in radeon module!\n");
600 return -EINVAL;
771fe6b9 601 }
14adc892
CK		 602
603 /* let modprobe override vga console setting */
8410ea3b 604 return drm_pci_init(driver, pdriver);
1da177e4
LT		 605}
606
607static void __exit radeon_exit(void)
608{
e28740ec 609 radeon_kfd_fini();
8410ea3b 610 drm_pci_exit(driver, pdriver);
6a9ee8af 611 radeon_unregister_atpx_handler();
1da177e4
LT		 612}
613
176f613e 614module_init(radeon_init);
1da177e4
LT		 615module_exit(radeon_exit);
616
b5e89ed5
DA		 617MODULE_AUTHOR(DRIVER_AUTHOR);
618MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 619MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)