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hmm: use mmu_notifier_get/put for 'struct hmm'
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
1da177e4
LT		 1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
1da177e4 32
f9183127 33#include <linux/compat.h>
771fe6b9 34#include <linux/console.h>
e0cd3608 35#include <linux/module.h>
10ebc0bc
DA		 36#include <linux/pm_runtime.h>
37#include <linux/vga_switcheroo.h>
d9fc9413 38
64a9dfc4 39#include <drm/drm_crtc_helper.h>
f9183127
SR		 40#include <drm/drm_drv.h>
41#include <drm/drm_fb_helper.h>
42#include <drm/drm_file.h>
43#include <drm/drm_gem.h>
44#include <drm/drm_ioctl.h>
45#include <drm/drm_pci.h>
46#include <drm/drm_pciids.h>
fcd70cd3 47#include <drm/drm_probe_helper.h>
f9183127
SR		 48#include <drm/drm_vblank.h>
49#include <drm/radeon_drm.h>
50
51#include "radeon_drv.h"
e28740ec 52
771fe6b9
JG		 53/*
54 * KMS wrapper.
0de1a57b
DA		 55 * - 2.0.0 - initial interface
56 * - 2.1.0 - add square tiling interface
fdb43528 57 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 58 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 59 * - 2.4.0 - add crtc id query
148a03bc 60 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 61 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 62 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 63 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 64 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD		 65 * 2.10.0 - fusion 2D tiling
66 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 67 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 68 * 2.13.0 - virtual memory support, streamout
285484e2 69 * 2.14.0 - add evergreen tiling informations
609c1e15 70 * 2.15.0 - add max_pipes query
d2609875 71 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 72 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 73 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 74 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 75 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 76 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 77 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 78 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 79 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 80 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 81 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 82 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 83 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 84 * 2.29.0 - R500 FP16 color clear registers
774c389f 85 * 2.30.0 - fix for FMASK texturing
a0a53aa8 86 * 2.31.0 - Add fastfb support for rs690
902aaef6 87 * 2.32.0 - new info request for rings working
64d7b8be 88 * 2.33.0 - Add SI tiling mode array query
39aee490 89 * 2.34.0 - Add CIK tiling mode array query
32f79a8a 90 * 2.35.0 - Add CIK macrotile mode array query
9482d0d3 91 * 2.36.0 - Fix CIK DCE tiling setup
7c4c62a0 92 * 2.37.0 - allow GS ring setup on r6xx/r7xx
020ff546
MO		 93 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
94 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
65fcf668 95 * 2.39.0 - Add INFO query for number of active CUs
72a9987e 96 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
897eba82 97 * CS to GPU on >= r600
16613743 98 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
1957d6be 99 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
72b9076b 100 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
8c4f2bbd 101 * 2.44.0 - SET_APPEND_CNT packet3 support
3d02b7fe 102 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
662ce7bc 103 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
4d6bdbad 104 * 2.47.0 - Add UVD_NO_OP register support
113d0f9d 105 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
51964e9e 106 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
75cb00dc 107 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
771fe6b9
JG		 108 */
109#define KMS_DRIVER_MAJOR 2
75cb00dc 110#define KMS_DRIVER_MINOR 50
771fe6b9
JG		 111#define KMS_DRIVER_PATCHLEVEL 0
112int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 113void radeon_driver_unload_kms(struct drm_device *dev);
771fe6b9
JG		 114void radeon_driver_lastclose_kms(struct drm_device *dev);
115int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
116void radeon_driver_postclose_kms(struct drm_device *dev,
117 struct drm_file *file_priv);
274ad65c
JG		 118int radeon_suspend_kms(struct drm_device *dev, bool suspend,
119 bool fbcon, bool freeze);
10ebc0bc 120int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 121u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
122int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
123void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
771fe6b9
JG		 124void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
125int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
126void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
e9f0d76f 127irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
771fe6b9 128void radeon_gem_object_free(struct drm_gem_object *obj);
721604a1
JG		 129int radeon_gem_object_open(struct drm_gem_object *obj,
130 struct drm_file *file_priv);
131void radeon_gem_object_close(struct drm_gem_object *obj,
132 struct drm_file *file_priv);
f72a113a
CK		 133struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
134 struct drm_gem_object *gobj,
135 int flags);
88e72717
TR		 136extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
137 unsigned int flags, int *vpos, int *hpos,
3bb403bf
VS		 138 ktime_t *stime, ktime_t *etime,
139 const struct drm_display_mode *mode);
90c4cde9 140extern bool radeon_is_px(struct drm_device *dev);
baa70943 141extern const struct drm_ioctl_desc radeon_ioctls_kms[];
771fe6b9
JG		 142extern int radeon_max_kms_ioctl;
143int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
ff72145b
DA		 144int radeon_mode_dumb_mmap(struct drm_file *filp,
145 struct drm_device *dev,
146 uint32_t handle, uint64_t *offset_p);
147int radeon_mode_dumb_create(struct drm_file *file_priv,
148 struct drm_device *dev,
149 struct drm_mode_create_dumb *args);
1e6d17a5
AP		 150struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
151struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
b5e9c1a2 152 struct dma_buf_attachment *,
1e6d17a5
AP		 153 struct sg_table *sg);
154int radeon_gem_prime_pin(struct drm_gem_object *obj);
280cf211 155void radeon_gem_prime_unpin(struct drm_gem_object *obj);
3aac4502 156struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
1e6d17a5
AP		 157void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
158void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
ff72145b 159
14adc892
CK		 160/* atpx handler */
161#if defined(CONFIG_VGA_SWITCHEROO)
162void radeon_register_atpx_handler(void);
163void radeon_unregister_atpx_handler(void);
e1052b35 164bool radeon_has_atpx_dgpu_power_cntl(void);
b8c9fd5a 165bool radeon_is_atpx_hybrid(void);
14adc892
CK		 166#else
167static inline void radeon_register_atpx_handler(void) {}
168static inline void radeon_unregister_atpx_handler(void) {}
e1052b35 169static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
b8c9fd5a 170static inline bool radeon_is_atpx_hybrid(void) { return false; }
14adc892 171#endif
1da177e4 172
689b9d74 173int radeon_no_wb;
e9ced8e0 174int radeon_modeset = -1;
771fe6b9
JG		 175int radeon_dynclks = -1;
176int radeon_r4xx_atom = 0;
037d1a66
MM		 177#ifdef __powerpc__
178/* Default to PCI on PowerPC (fdo #95017) */
179int radeon_agpmode = -1;
180#else
771fe6b9 181int radeon_agpmode = 0;
037d1a66 182#endif
771fe6b9 183int radeon_vram_limit = 0;
edcd26e8 184int radeon_gart_size = -1; /* auto */
771fe6b9 185int radeon_benchmarking = 0;
ecc0b326 186int radeon_testing = 0;
771fe6b9 187int radeon_connector_table = 0;
4ce001ab 188int radeon_tv = 1;
108dc8e8 189int radeon_audio = -1;
f46c0120 190int radeon_disp_priority = 0;
e2b0a8e1 191int radeon_hw_i2c = 0;
197bbb3d 192int radeon_pcie_gen2 = -1;
a18cee15 193int radeon_msi = -1;
3368ff0c 194int radeon_lockup_timeout = 10000;
a0a53aa8 195int radeon_fastfb = 0;
da321c8a 196int radeon_dpm = -1;
1294d4a3 197int radeon_aspm = -1;
10ebc0bc 198int radeon_runtime_pm = -1;
363eb0b4 199int radeon_hard_reset = 0;
dfc230f9
CK		 200int radeon_vm_size = 8;
201int radeon_vm_block_size = -1;
a624f429 202int radeon_deep_color = 0;
39dc5454 203int radeon_use_pflipirq = 2;
6e909f74 204int radeon_bapm = -1;
bc13018b 205int radeon_backlight = -1;
875711f0 206int radeon_auxch = -1;
9843ead0 207int radeon_mst = 0;
f1a0a67a 208int radeon_uvd = 1;
fabb5935 209int radeon_vce = 1;
689b9d74 210
61a2d07d 211MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA		 212module_param_named(no_wb, radeon_no_wb, int, 0444);
213
771fe6b9
JG		 214MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
215module_param_named(modeset, radeon_modeset, int, 0400);
216
217MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
218module_param_named(dynclks, radeon_dynclks, int, 0444);
219
220MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
221module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
222
8902e6f2 223MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
771fe6b9
JG		 224module_param_named(vramlimit, radeon_vram_limit, int, 0600);
225
226MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
227module_param_named(agpmode, radeon_agpmode, int, 0444);
228
edcd26e8 229MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
771fe6b9
JG		 230module_param_named(gartsize, radeon_gart_size, int, 0600);
231
232MODULE_PARM_DESC(benchmark, "Run benchmark");
233module_param_named(benchmark, radeon_benchmarking, int, 0444);
234
ecc0b326
MD		 235MODULE_PARM_DESC(test, "Run tests");
236module_param_named(test, radeon_testing, int, 0444);
237
771fe6b9
JG		 238MODULE_PARM_DESC(connector_table, "Force connector table");
239module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA		 240
241MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
242module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 243
108dc8e8 244MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
dafc3bd5
CK		 245module_param_named(audio, radeon_audio, int, 0444);
246
f46c0120
AD		 247MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
248module_param_named(disp_priority, radeon_disp_priority, int, 0444);
249
e2b0a8e1
AD		 250MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
251module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
252
197bbb3d 253MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD		 254module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
255
a18cee15
AD		 256MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
257module_param_named(msi, radeon_msi, int, 0444);
258
b5c9ecab 259MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
3368ff0c
CK		 260module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
261
a0a53aa8
SL		 262MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
263module_param_named(fastfb, radeon_fastfb, int, 0444);
264
da321c8a
AD		 265MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
266module_param_named(dpm, radeon_dpm, int, 0444);
267
1294d4a3
AD		 268MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
269module_param_named(aspm, radeon_aspm, int, 0444);
270
10ebc0bc
DA		 271MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
272module_param_named(runpm, radeon_runtime_pm, int, 0444);
273
363eb0b4
AD		 274MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
275module_param_named(hard_reset, radeon_hard_reset, int, 0444);
276
20b2656d 277MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
c1c44132
CK		 278module_param_named(vm_size, radeon_vm_size, int, 0444);
279
dfc230f9 280MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
4510fb98
CK		 281module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
282
a624f429
AD		 283MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
284module_param_named(deep_color, radeon_deep_color, int, 0444);
285
39dc5454
MK		 286MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
287module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
288
6e909f74
AD		 289MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
290module_param_named(bapm, radeon_bapm, int, 0444);
291
bc13018b
AD		 292MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
293module_param_named(backlight, radeon_backlight, int, 0444);
294
875711f0
DA		 295MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
296module_param_named(auxch, radeon_auxch, int, 0444);
297
9843ead0
DA		 298MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
299module_param_named(mst, radeon_mst, int, 0444);
300
f1a0a67a
JG		 301MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
302module_param_named(uvd, radeon_uvd, int, 0444);
303
fabb5935
JG		 304MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
305module_param_named(vce, radeon_vce, int, 0444);
306
36ffce0a
FK		 307int radeon_si_support = 1;
308MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
309module_param_named(si_support, radeon_si_support, int, 0444);
36ffce0a 310
2b059658
MD		 311int radeon_cik_support = 1;
312MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
e7f78b69 313module_param_named(cik_support, radeon_cik_support, int, 0444);
e7f78b69 314
14adc892
CK		 315static struct pci_device_id pciidlist[] = {
316 radeon_PCI_IDS
317};
318
319MODULE_DEVICE_TABLE(pci, pciidlist);
320
771fe6b9
JG		 321static struct drm_driver kms_driver;
322
a801abe4
AD		 323bool radeon_device_is_virtual(void);
324
56550d94
GKH		 325static int radeon_pci_probe(struct pci_dev *pdev,
326 const struct pci_device_id *ent)
771fe6b9 327{
30238151
TR		 328 int ret;
329
b00e5334 330 if (vga_switcheroo_client_probe_defer(pdev))
14d20001
LW		 331 return -EPROBE_DEFER;
332
a56f7428 333 /* Get rid of things like offb */
39a3043a 334 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "radeondrmfb");
30238151
TR		 335 if (ret)
336 return ret;
a56f7428 337
dcdb1674 338 return drm_get_pci_dev(pdev, ent, &kms_driver);
771fe6b9
JG		 339}
340
341static void
342radeon_pci_remove(struct pci_dev *pdev)
343{
344 struct drm_device *dev = pci_get_drvdata(pdev);
345
346 drm_put_dev(dev);
347}
348
a801abe4
AD		 349static void
350radeon_pci_shutdown(struct pci_dev *pdev)
351{
352 /* if we are running in a VM, make sure the device
b9b487e4 353 * torn down properly on reboot/shutdown
a801abe4 354 */
b9b487e4
AD		 355 if (radeon_device_is_virtual())
356 radeon_pci_remove(pdev);
a801abe4
AD		 357}
358
7473e830 359static int radeon_pmops_suspend(struct device *dev)
771fe6b9 360{
7473e830
DA		 361 struct pci_dev *pdev = to_pci_dev(dev);
362 struct drm_device *drm_dev = pci_get_drvdata(pdev);
274ad65c 363 return radeon_suspend_kms(drm_dev, true, true, false);
771fe6b9
JG		 364}
365
7473e830 366static int radeon_pmops_resume(struct device *dev)
771fe6b9 367{
7473e830
DA		 368 struct pci_dev *pdev = to_pci_dev(dev);
369 struct drm_device *drm_dev = pci_get_drvdata(pdev);
103917b3
AD		 370
371 /* GPU comes up enabled by the bios on resume */
372 if (radeon_is_px(drm_dev)) {
373 pm_runtime_disable(dev);
374 pm_runtime_set_active(dev);
375 pm_runtime_enable(dev);
376 }
377
10ebc0bc 378 return radeon_resume_kms(drm_dev, true, true);
7473e830
DA		 379}
380
381static int radeon_pmops_freeze(struct device *dev)
382{
383 struct pci_dev *pdev = to_pci_dev(dev);
384 struct drm_device *drm_dev = pci_get_drvdata(pdev);
274ad65c 385 return radeon_suspend_kms(drm_dev, false, true, true);
771fe6b9
JG		 386}
387
7473e830
DA		 388static int radeon_pmops_thaw(struct device *dev)
389{
390 struct pci_dev *pdev = to_pci_dev(dev);
391 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc
DA		 392 return radeon_resume_kms(drm_dev, false, true);
393}
394
395static int radeon_pmops_runtime_suspend(struct device *dev)
396{
397 struct pci_dev *pdev = to_pci_dev(dev);
398 struct drm_device *drm_dev = pci_get_drvdata(pdev);
399 int ret;
400
90c4cde9 401 if (!radeon_is_px(drm_dev)) {
1d8eec8b
DA		 402 pm_runtime_forbid(dev);
403 return -EBUSY;
404 }
9babd35a 405
10ebc0bc
DA		 406 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
407 drm_kms_helper_poll_disable(drm_dev);
10ebc0bc 408
274ad65c 409 ret = radeon_suspend_kms(drm_dev, false, false, false);
10ebc0bc
DA		 410 pci_save_state(pdev);
411 pci_disable_device(pdev);
b440bde7 412 pci_ignore_hotplug(pdev);
31764c1e
AD		 413 if (radeon_is_atpx_hybrid())
414 pci_set_power_state(pdev, PCI_D3cold);
84919992 415 else if (!radeon_has_atpx_dgpu_power_cntl())
f7ea4189 416 pci_set_power_state(pdev, PCI_D3hot);
10ebc0bc
DA		 417 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
418
419 return 0;
420}
421
422static int radeon_pmops_runtime_resume(struct device *dev)
423{
424 struct pci_dev *pdev = to_pci_dev(dev);
425 struct drm_device *drm_dev = pci_get_drvdata(pdev);
426 int ret;
427
90c4cde9 428 if (!radeon_is_px(drm_dev))
9babd35a
AD		 429 return -EINVAL;
430
10ebc0bc
DA		 431 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
432
84919992
AD		 433 if (radeon_is_atpx_hybrid() ||
434 !radeon_has_atpx_dgpu_power_cntl())
435 pci_set_power_state(pdev, PCI_D0);
10ebc0bc
DA		 436 pci_restore_state(pdev);
437 ret = pci_enable_device(pdev);
438 if (ret)
439 return ret;
440 pci_set_master(pdev);
441
442 ret = radeon_resume_kms(drm_dev, false, false);
443 drm_kms_helper_poll_enable(drm_dev);
10ebc0bc
DA		 444 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
445 return 0;
446}
447
448static int radeon_pmops_runtime_idle(struct device *dev)
449{
450 struct pci_dev *pdev = to_pci_dev(dev);
451 struct drm_device *drm_dev = pci_get_drvdata(pdev);
452 struct drm_crtc *crtc;
453
90c4cde9 454 if (!radeon_is_px(drm_dev)) {
1d8eec8b 455 pm_runtime_forbid(dev);
10ebc0bc
DA		 456 return -EBUSY;
457 }
458
459 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
460 if (crtc->enabled) {
461 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
462 return -EBUSY;
463 }
464 }
465
466 pm_runtime_mark_last_busy(dev);
467 pm_runtime_autosuspend(dev);
468 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
469 return 1;
470}
471
472long radeon_drm_ioctl(struct file *filp,
473 unsigned int cmd, unsigned long arg)
474{
475 struct drm_file *file_priv = filp->private_data;
476 struct drm_device *dev;
477 long ret;
478 dev = file_priv->minor->dev;
479 ret = pm_runtime_get_sync(dev->dev);
480 if (ret < 0)
481 return ret;
482
483 ret = drm_ioctl(filp, cmd, arg);
484
485 pm_runtime_mark_last_busy(dev->dev);
486 pm_runtime_put_autosuspend(dev->dev);
487 return ret;
7473e830
DA		 488}
489
ff32d39b
AV		 490#ifdef CONFIG_COMPAT
491static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
492{
493 unsigned int nr = DRM_IOCTL_NR(cmd);
494 int ret;
495
496 if (nr < DRM_COMMAND_BASE)
497 return drm_compat_ioctl(filp, cmd, arg);
498
499 ret = radeon_drm_ioctl(filp, cmd, arg);
500
501 return ret;
502}
503#endif
504
7473e830
DA		 505static const struct dev_pm_ops radeon_pm_ops = {
506 .suspend = radeon_pmops_suspend,
507 .resume = radeon_pmops_resume,
508 .freeze = radeon_pmops_freeze,
509 .thaw = radeon_pmops_thaw,
510 .poweroff = radeon_pmops_freeze,
511 .restore = radeon_pmops_resume,
10ebc0bc
DA		 512 .runtime_suspend = radeon_pmops_runtime_suspend,
513 .runtime_resume = radeon_pmops_runtime_resume,
514 .runtime_idle = radeon_pmops_runtime_idle,
7473e830
DA		 515};
516
e08e96de
AV		 517static const struct file_operations radeon_driver_kms_fops = {
518 .owner = THIS_MODULE,
519 .open = drm_open,
520 .release = drm_release,
10ebc0bc 521 .unlocked_ioctl = radeon_drm_ioctl,
e08e96de
AV		 522 .mmap = radeon_mmap,
523 .poll = drm_poll,
e08e96de
AV		 524 .read = drm_read,
525#ifdef CONFIG_COMPAT
526 .compat_ioctl = radeon_kms_compat_ioctl,
527#endif
528};
529
1bf6ad62
DV		 530static bool
531radeon_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
532 bool in_vblank_irq, int *vpos, int *hpos,
533 ktime_t *stime, ktime_t *etime,
534 const struct drm_display_mode *mode)
535{
536 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
537 stime, etime, mode);
538}
539
771fe6b9
JG		 540static struct drm_driver kms_driver = {
541 .driver_features =
1ff49481 542 DRIVER_USE_AGP | DRIVER_GEM | DRIVER_PRIME | DRIVER_RENDER,
771fe6b9 543 .load = radeon_driver_load_kms,
771fe6b9 544 .open = radeon_driver_open_kms,
771fe6b9
JG		 545 .postclose = radeon_driver_postclose_kms,
546 .lastclose = radeon_driver_lastclose_kms,
547 .unload = radeon_driver_unload_kms,
771fe6b9
JG		 548 .get_vblank_counter = radeon_get_vblank_counter_kms,
549 .enable_vblank = radeon_enable_vblank_kms,
550 .disable_vblank = radeon_disable_vblank_kms,
1bf6ad62
DV		 551 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
552 .get_scanout_position = radeon_get_crtc_scanout_position,
771fe6b9
JG		 553 .irq_preinstall = radeon_driver_irq_preinstall_kms,
554 .irq_postinstall = radeon_driver_irq_postinstall_kms,
555 .irq_uninstall = radeon_driver_irq_uninstall_kms,
556 .irq_handler = radeon_driver_irq_handler_kms,
771fe6b9 557 .ioctls = radeon_ioctls_kms,
71cbf451 558 .gem_free_object_unlocked = radeon_gem_object_free,
721604a1
JG		 559 .gem_open_object = radeon_gem_object_open,
560 .gem_close_object = radeon_gem_object_close,
ff72145b
DA		 561 .dumb_create = radeon_mode_dumb_create,
562 .dumb_map_offset = radeon_mode_dumb_mmap,
e08e96de 563 .fops = &radeon_driver_kms_fops,
40f5cf99
AD		 564
565 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
566 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
f72a113a 567 .gem_prime_export = radeon_gem_prime_export,
1e6d17a5
AP		 568 .gem_prime_import = drm_gem_prime_import,
569 .gem_prime_pin = radeon_gem_prime_pin,
280cf211 570 .gem_prime_unpin = radeon_gem_prime_unpin,
3aac4502 571 .gem_prime_res_obj = radeon_gem_prime_res_obj,
1e6d17a5
AP		 572 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
573 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
574 .gem_prime_vmap = radeon_gem_prime_vmap,
575 .gem_prime_vunmap = radeon_gem_prime_vunmap,
40f5cf99 576
771fe6b9
JG		 577 .name = DRIVER_NAME,
578 .desc = DRIVER_DESC,
579 .date = DRIVER_DATE,
580 .major = KMS_DRIVER_MAJOR,
581 .minor = KMS_DRIVER_MINOR,
582 .patchlevel = KMS_DRIVER_PATCHLEVEL,
583};
771fe6b9
JG		 584
585static struct drm_driver *driver;
8410ea3b
DA		 586static struct pci_driver *pdriver;
587
8410ea3b
DA		 588static struct pci_driver radeon_kms_pci_driver = {
589 .name = DRIVER_NAME,
590 .id_table = pciidlist,
591 .probe = radeon_pci_probe,
592 .remove = radeon_pci_remove,
a801abe4 593 .shutdown = radeon_pci_shutdown,
7473e830 594 .driver.pm = &radeon_pm_ops,
8410ea3b 595};
771fe6b9 596
1da177e4
LT		 597static int __init radeon_init(void)
598{
e9ced8e0
DA		 599 if (vgacon_text_force() && radeon_modeset == -1) {
600 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
601 radeon_modeset = 0;
602 }
e9ced8e0
DA		 603 /* set to modesetting by default if not nomodeset */
604 if (radeon_modeset == -1)
605 radeon_modeset = 1;
606
771fe6b9
JG		 607 if (radeon_modeset == 1) {
608 DRM_INFO("radeon kernel modesetting enabled.\n");
609 driver = &kms_driver;
8410ea3b 610 pdriver = &radeon_kms_pci_driver;
771fe6b9
JG		 611 driver->driver_features |= DRIVER_MODESET;
612 driver->num_ioctls = radeon_max_kms_ioctl;
6a9ee8af 613 radeon_register_atpx_handler();
14adc892
CK		 614
615 } else {
14adc892
CK		 616 DRM_ERROR("No UMS support in radeon module!\n");
617 return -EINVAL;
771fe6b9 618 }
14adc892 619
10631d72 620 return pci_register_driver(pdriver);
1da177e4
LT		 621}
622
623static void __exit radeon_exit(void)
624{
10631d72 625 pci_unregister_driver(pdriver);
6a9ee8af 626 radeon_unregister_atpx_handler();
1da177e4
LT		 627}
628
176f613e 629module_init(radeon_init);
1da177e4
LT		 630module_exit(radeon_exit);
631
b5e89ed5
DA		 632MODULE_AUTHOR(DRIVER_AUTHOR);
633MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 634MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)