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drm/radeon: add query for number of active CUs
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
1da177e4
LT		 1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
1da177e4
LT		 34#include "radeon_drv.h"
35
760285e7 36#include <drm/drm_pciids.h>
771fe6b9 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
10ebc0bc
DA		 39#include <linux/pm_runtime.h>
40#include <linux/vga_switcheroo.h>
41#include "drm_crtc_helper.h"
771fe6b9
JG		 42/*
43 * KMS wrapper.
0de1a57b
DA		 44 * - 2.0.0 - initial interface
45 * - 2.1.0 - add square tiling interface
fdb43528 46 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 47 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 48 * - 2.4.0 - add crtc id query
148a03bc 49 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 50 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 51 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 52 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 53 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD		 54 * 2.10.0 - fusion 2D tiling
55 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 56 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 57 * 2.13.0 - virtual memory support, streamout
285484e2 58 * 2.14.0 - add evergreen tiling informations
609c1e15 59 * 2.15.0 - add max_pipes query
d2609875 60 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 61 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 62 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 63 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 64 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 65 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 66 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 67 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 68 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 69 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 70 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 71 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 72 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 73 * 2.29.0 - R500 FP16 color clear registers
774c389f 74 * 2.30.0 - fix for FMASK texturing
a0a53aa8 75 * 2.31.0 - Add fastfb support for rs690
902aaef6 76 * 2.32.0 - new info request for rings working
64d7b8be 77 * 2.33.0 - Add SI tiling mode array query
39aee490 78 * 2.34.0 - Add CIK tiling mode array query
32f79a8a 79 * 2.35.0 - Add CIK macrotile mode array query
9482d0d3 80 * 2.36.0 - Fix CIK DCE tiling setup
7c4c62a0 81 * 2.37.0 - allow GS ring setup on r6xx/r7xx
020ff546
MO		 82 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
83 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
65fcf668 84 * 2.39.0 - Add INFO query for number of active CUs
771fe6b9
JG		 85 */
86#define KMS_DRIVER_MAJOR 2
65fcf668 87#define KMS_DRIVER_MINOR 39
771fe6b9
JG		 88#define KMS_DRIVER_PATCHLEVEL 0
89int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
90int radeon_driver_unload_kms(struct drm_device *dev);
771fe6b9
JG		 91void radeon_driver_lastclose_kms(struct drm_device *dev);
92int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
93void radeon_driver_postclose_kms(struct drm_device *dev,
94 struct drm_file *file_priv);
95void radeon_driver_preclose_kms(struct drm_device *dev,
96 struct drm_file *file_priv);
10ebc0bc
DA		 97int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
98int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
771fe6b9
JG		 99u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
100int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
101void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
f5a80209
MK		 102int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
103 int *max_error,
104 struct timeval *vblank_time,
105 unsigned flags);
771fe6b9
JG		 106void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
107int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
108void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
e9f0d76f 109irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
771fe6b9 110void radeon_gem_object_free(struct drm_gem_object *obj);
721604a1
JG		 111int radeon_gem_object_open(struct drm_gem_object *obj,
112 struct drm_file *file_priv);
113void radeon_gem_object_close(struct drm_gem_object *obj,
114 struct drm_file *file_priv);
f5a80209 115extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
abca9e45 116 unsigned int flags,
d47abc58
MK		 117 int *vpos, int *hpos, ktime_t *stime,
118 ktime_t *etime);
90c4cde9 119extern bool radeon_is_px(struct drm_device *dev);
baa70943 120extern const struct drm_ioctl_desc radeon_ioctls_kms[];
771fe6b9
JG		 121extern int radeon_max_kms_ioctl;
122int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
ff72145b
DA		 123int radeon_mode_dumb_mmap(struct drm_file *filp,
124 struct drm_device *dev,
125 uint32_t handle, uint64_t *offset_p);
126int radeon_mode_dumb_create(struct drm_file *file_priv,
127 struct drm_device *dev,
128 struct drm_mode_create_dumb *args);
1e6d17a5
AP		 129struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
130struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
131 size_t size,
132 struct sg_table *sg);
133int radeon_gem_prime_pin(struct drm_gem_object *obj);
280cf211 134void radeon_gem_prime_unpin(struct drm_gem_object *obj);
1e6d17a5
AP		 135void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
136void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
14adc892
CK		 137extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
138 unsigned long arg);
ff72145b 139
771fe6b9
JG		 140#if defined(CONFIG_DEBUG_FS)
141int radeon_debugfs_init(struct drm_minor *minor);
142void radeon_debugfs_cleanup(struct drm_minor *minor);
143#endif
771fe6b9 144
14adc892
CK		 145/* atpx handler */
146#if defined(CONFIG_VGA_SWITCHEROO)
147void radeon_register_atpx_handler(void);
148void radeon_unregister_atpx_handler(void);
149#else
150static inline void radeon_register_atpx_handler(void) {}
151static inline void radeon_unregister_atpx_handler(void) {}
152#endif
1da177e4 153
689b9d74 154int radeon_no_wb;
e9ced8e0 155int radeon_modeset = -1;
771fe6b9
JG		 156int radeon_dynclks = -1;
157int radeon_r4xx_atom = 0;
158int radeon_agpmode = 0;
159int radeon_vram_limit = 0;
edcd26e8 160int radeon_gart_size = -1; /* auto */
771fe6b9 161int radeon_benchmarking = 0;
ecc0b326 162int radeon_testing = 0;
771fe6b9 163int radeon_connector_table = 0;
4ce001ab 164int radeon_tv = 1;
108dc8e8 165int radeon_audio = -1;
f46c0120 166int radeon_disp_priority = 0;
e2b0a8e1 167int radeon_hw_i2c = 0;
197bbb3d 168int radeon_pcie_gen2 = -1;
a18cee15 169int radeon_msi = -1;
3368ff0c 170int radeon_lockup_timeout = 10000;
a0a53aa8 171int radeon_fastfb = 0;
da321c8a 172int radeon_dpm = -1;
1294d4a3 173int radeon_aspm = -1;
10ebc0bc 174int radeon_runtime_pm = -1;
363eb0b4 175int radeon_hard_reset = 0;
c1c44132 176int radeon_vm_size = 4096;
4510fb98 177int radeon_vm_block_size = 9;
689b9d74 178
61a2d07d 179MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA		 180module_param_named(no_wb, radeon_no_wb, int, 0444);
181
771fe6b9
JG		 182MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
183module_param_named(modeset, radeon_modeset, int, 0400);
184
185MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
186module_param_named(dynclks, radeon_dynclks, int, 0444);
187
188MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
189module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
190
8902e6f2 191MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
771fe6b9
JG		 192module_param_named(vramlimit, radeon_vram_limit, int, 0600);
193
194MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
195module_param_named(agpmode, radeon_agpmode, int, 0444);
196
edcd26e8 197MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
771fe6b9
JG		 198module_param_named(gartsize, radeon_gart_size, int, 0600);
199
200MODULE_PARM_DESC(benchmark, "Run benchmark");
201module_param_named(benchmark, radeon_benchmarking, int, 0444);
202
ecc0b326
MD		 203MODULE_PARM_DESC(test, "Run tests");
204module_param_named(test, radeon_testing, int, 0444);
205
771fe6b9
JG		 206MODULE_PARM_DESC(connector_table, "Force connector table");
207module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA		 208
209MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
210module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 211
108dc8e8 212MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
dafc3bd5
CK		 213module_param_named(audio, radeon_audio, int, 0444);
214
f46c0120
AD		 215MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
216module_param_named(disp_priority, radeon_disp_priority, int, 0444);
217
e2b0a8e1
AD		 218MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
219module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
220
197bbb3d 221MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD		 222module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
223
a18cee15
AD		 224MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
225module_param_named(msi, radeon_msi, int, 0444);
226
3368ff0c
CK		 227MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
228module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
229
a0a53aa8
SL		 230MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
231module_param_named(fastfb, radeon_fastfb, int, 0444);
232
da321c8a
AD		 233MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
234module_param_named(dpm, radeon_dpm, int, 0444);
235
1294d4a3
AD		 236MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
237module_param_named(aspm, radeon_aspm, int, 0444);
238
10ebc0bc
DA		 239MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
240module_param_named(runpm, radeon_runtime_pm, int, 0444);
241
363eb0b4
AD		 242MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
243module_param_named(hard_reset, radeon_hard_reset, int, 0444);
244
c1c44132
CK		 245MODULE_PARM_DESC(vm_size, "VM address space size in megabytes (default 4GB)");
246module_param_named(vm_size, radeon_vm_size, int, 0444);
247
4510fb98
CK		 248MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default 9)");
249module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
250
14adc892
CK		 251static struct pci_device_id pciidlist[] = {
252 radeon_PCI_IDS
253};
254
255MODULE_DEVICE_TABLE(pci, pciidlist);
256
257#ifdef CONFIG_DRM_RADEON_UMS
258
0a3e67a4
JB		 259static int radeon_suspend(struct drm_device *dev, pm_message_t state)
260{
261 drm_radeon_private_t *dev_priv = dev->dev_private;
262
03efb885
DA		 263 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
264 return 0;
265
0a3e67a4 266 /* Disable *all* interrupts */
800b6995 267 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
0a3e67a4
JB		 268 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
269 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
270 return 0;
271}
272
273static int radeon_resume(struct drm_device *dev)
274{
275 drm_radeon_private_t *dev_priv = dev->dev_private;
276
03efb885
DA		 277 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
278 return 0;
279
0a3e67a4 280 /* Restore interrupt registers */
800b6995 281 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
0a3e67a4
JB		 282 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
283 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
284 return 0;
285}
286
10ebc0bc 287
e08e96de
AV		 288static const struct file_operations radeon_driver_old_fops = {
289 .owner = THIS_MODULE,
290 .open = drm_open,
291 .release = drm_release,
292 .unlocked_ioctl = drm_ioctl,
293 .mmap = drm_mmap,
294 .poll = drm_poll,
e08e96de
AV		 295 .read = drm_read,
296#ifdef CONFIG_COMPAT
297 .compat_ioctl = radeon_compat_ioctl,
298#endif
299 .llseek = noop_llseek,
300};
301
771fe6b9 302static struct drm_driver driver_old = {
b5e89ed5 303 .driver_features =
28185647 304 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
0a3e67a4 305 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
1da177e4 306 .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
22eae947
DA		 307 .load = radeon_driver_load,
308 .firstopen = radeon_driver_firstopen,
309 .open = radeon_driver_open,
310 .preclose = radeon_driver_preclose,
311 .postclose = radeon_driver_postclose,
312 .lastclose = radeon_driver_lastclose,
313 .unload = radeon_driver_unload,
0a3e67a4
JB		 314 .suspend = radeon_suspend,
315 .resume = radeon_resume,
316 .get_vblank_counter = radeon_get_vblank_counter,
317 .enable_vblank = radeon_enable_vblank,
318 .disable_vblank = radeon_disable_vblank,
60f2ee0b
DA		 319 .master_create = radeon_master_create,
320 .master_destroy = radeon_master_destroy,
1da177e4
LT		 321 .irq_preinstall = radeon_driver_irq_preinstall,
322 .irq_postinstall = radeon_driver_irq_postinstall,
323 .irq_uninstall = radeon_driver_irq_uninstall,
324 .irq_handler = radeon_driver_irq_handler,
1da177e4
LT		 325 .ioctls = radeon_ioctls,
326 .dma_ioctl = radeon_cp_buffers,
e08e96de 327 .fops = &radeon_driver_old_fops,
22eae947
DA		 328 .name = DRIVER_NAME,
329 .desc = DRIVER_DESC,
330 .date = DRIVER_DATE,
331 .major = DRIVER_MAJOR,
332 .minor = DRIVER_MINOR,
333 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT		 334};
335
14adc892
CK		 336#endif
337
771fe6b9
JG		 338static struct drm_driver kms_driver;
339
30238151 340static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
a56f7428
BH		 341{
342 struct apertures_struct *ap;
343 bool primary = false;
344
345 ap = alloc_apertures(1);
30238151
TR		 346 if (!ap)
347 return -ENOMEM;
348
a56f7428
BH		 349 ap->ranges[0].base = pci_resource_start(pdev, 0);
350 ap->ranges[0].size = pci_resource_len(pdev, 0);
351
352#ifdef CONFIG_X86
353 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
354#endif
355 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
356 kfree(ap);
30238151
TR		 357
358 return 0;
a56f7428
BH		 359}
360
56550d94
GKH		 361static int radeon_pci_probe(struct pci_dev *pdev,
362 const struct pci_device_id *ent)
771fe6b9 363{
30238151
TR		 364 int ret;
365
a56f7428 366 /* Get rid of things like offb */
30238151
TR		 367 ret = radeon_kick_out_firmware_fb(pdev);
368 if (ret)
369 return ret;
a56f7428 370
dcdb1674 371 return drm_get_pci_dev(pdev, ent, &kms_driver);
771fe6b9
JG		 372}
373
374static void
375radeon_pci_remove(struct pci_dev *pdev)
376{
377 struct drm_device *dev = pci_get_drvdata(pdev);
378
379 drm_put_dev(dev);
380}
381
7473e830 382static int radeon_pmops_suspend(struct device *dev)
771fe6b9 383{
7473e830
DA		 384 struct pci_dev *pdev = to_pci_dev(dev);
385 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 386 return radeon_suspend_kms(drm_dev, true, true);
771fe6b9
JG		 387}
388
7473e830 389static int radeon_pmops_resume(struct device *dev)
771fe6b9 390{
7473e830
DA		 391 struct pci_dev *pdev = to_pci_dev(dev);
392 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 393 return radeon_resume_kms(drm_dev, true, true);
7473e830
DA		 394}
395
396static int radeon_pmops_freeze(struct device *dev)
397{
398 struct pci_dev *pdev = to_pci_dev(dev);
399 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 400 return radeon_suspend_kms(drm_dev, false, true);
771fe6b9
JG		 401}
402
7473e830
DA		 403static int radeon_pmops_thaw(struct device *dev)
404{
405 struct pci_dev *pdev = to_pci_dev(dev);
406 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc
DA		 407 return radeon_resume_kms(drm_dev, false, true);
408}
409
410static int radeon_pmops_runtime_suspend(struct device *dev)
411{
412 struct pci_dev *pdev = to_pci_dev(dev);
413 struct drm_device *drm_dev = pci_get_drvdata(pdev);
414 int ret;
415
90c4cde9 416 if (!radeon_is_px(drm_dev)) {
1d8eec8b
DA		 417 pm_runtime_forbid(dev);
418 return -EBUSY;
419 }
9babd35a 420
10ebc0bc
DA		 421 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
422 drm_kms_helper_poll_disable(drm_dev);
423 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
424
425 ret = radeon_suspend_kms(drm_dev, false, false);
426 pci_save_state(pdev);
427 pci_disable_device(pdev);
428 pci_set_power_state(pdev, PCI_D3cold);
429 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
430
431 return 0;
432}
433
434static int radeon_pmops_runtime_resume(struct device *dev)
435{
436 struct pci_dev *pdev = to_pci_dev(dev);
437 struct drm_device *drm_dev = pci_get_drvdata(pdev);
438 int ret;
439
90c4cde9 440 if (!radeon_is_px(drm_dev))
9babd35a
AD		 441 return -EINVAL;
442
10ebc0bc
DA		 443 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
444
445 pci_set_power_state(pdev, PCI_D0);
446 pci_restore_state(pdev);
447 ret = pci_enable_device(pdev);
448 if (ret)
449 return ret;
450 pci_set_master(pdev);
451
452 ret = radeon_resume_kms(drm_dev, false, false);
453 drm_kms_helper_poll_enable(drm_dev);
454 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
455 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
456 return 0;
457}
458
459static int radeon_pmops_runtime_idle(struct device *dev)
460{
461 struct pci_dev *pdev = to_pci_dev(dev);
462 struct drm_device *drm_dev = pci_get_drvdata(pdev);
463 struct drm_crtc *crtc;
464
90c4cde9 465 if (!radeon_is_px(drm_dev)) {
1d8eec8b 466 pm_runtime_forbid(dev);
10ebc0bc
DA		 467 return -EBUSY;
468 }
469
470 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
471 if (crtc->enabled) {
472 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
473 return -EBUSY;
474 }
475 }
476
477 pm_runtime_mark_last_busy(dev);
478 pm_runtime_autosuspend(dev);
479 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
480 return 1;
481}
482
483long radeon_drm_ioctl(struct file *filp,
484 unsigned int cmd, unsigned long arg)
485{
486 struct drm_file *file_priv = filp->private_data;
487 struct drm_device *dev;
488 long ret;
489 dev = file_priv->minor->dev;
490 ret = pm_runtime_get_sync(dev->dev);
491 if (ret < 0)
492 return ret;
493
494 ret = drm_ioctl(filp, cmd, arg);
495
496 pm_runtime_mark_last_busy(dev->dev);
497 pm_runtime_put_autosuspend(dev->dev);
498 return ret;
7473e830
DA		 499}
500
501static const struct dev_pm_ops radeon_pm_ops = {
502 .suspend = radeon_pmops_suspend,
503 .resume = radeon_pmops_resume,
504 .freeze = radeon_pmops_freeze,
505 .thaw = radeon_pmops_thaw,
506 .poweroff = radeon_pmops_freeze,
507 .restore = radeon_pmops_resume,
10ebc0bc
DA		 508 .runtime_suspend = radeon_pmops_runtime_suspend,
509 .runtime_resume = radeon_pmops_runtime_resume,
510 .runtime_idle = radeon_pmops_runtime_idle,
7473e830
DA		 511};
512
e08e96de
AV		 513static const struct file_operations radeon_driver_kms_fops = {
514 .owner = THIS_MODULE,
515 .open = drm_open,
516 .release = drm_release,
10ebc0bc 517 .unlocked_ioctl = radeon_drm_ioctl,
e08e96de
AV		 518 .mmap = radeon_mmap,
519 .poll = drm_poll,
e08e96de
AV		 520 .read = drm_read,
521#ifdef CONFIG_COMPAT
522 .compat_ioctl = radeon_kms_compat_ioctl,
523#endif
524};
525
771fe6b9
JG		 526static struct drm_driver kms_driver = {
527 .driver_features =
28185647 528 DRIVER_USE_AGP |
81e95697 529 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
f33bcab9 530 DRIVER_PRIME | DRIVER_RENDER,
771fe6b9 531 .load = radeon_driver_load_kms,
771fe6b9
JG		 532 .open = radeon_driver_open_kms,
533 .preclose = radeon_driver_preclose_kms,
534 .postclose = radeon_driver_postclose_kms,
535 .lastclose = radeon_driver_lastclose_kms,
536 .unload = radeon_driver_unload_kms,
771fe6b9
JG		 537 .get_vblank_counter = radeon_get_vblank_counter_kms,
538 .enable_vblank = radeon_enable_vblank_kms,
539 .disable_vblank = radeon_disable_vblank_kms,
f5a80209
MK		 540 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
541 .get_scanout_position = radeon_get_crtc_scanoutpos,
771fe6b9
JG		 542#if defined(CONFIG_DEBUG_FS)
543 .debugfs_init = radeon_debugfs_init,
544 .debugfs_cleanup = radeon_debugfs_cleanup,
545#endif
546 .irq_preinstall = radeon_driver_irq_preinstall_kms,
547 .irq_postinstall = radeon_driver_irq_postinstall_kms,
548 .irq_uninstall = radeon_driver_irq_uninstall_kms,
549 .irq_handler = radeon_driver_irq_handler_kms,
771fe6b9 550 .ioctls = radeon_ioctls_kms,
771fe6b9 551 .gem_free_object = radeon_gem_object_free,
721604a1
JG		 552 .gem_open_object = radeon_gem_object_open,
553 .gem_close_object = radeon_gem_object_close,
ff72145b
DA		 554 .dumb_create = radeon_mode_dumb_create,
555 .dumb_map_offset = radeon_mode_dumb_mmap,
43387b37 556 .dumb_destroy = drm_gem_dumb_destroy,
e08e96de 557 .fops = &radeon_driver_kms_fops,
40f5cf99
AD		 558
559 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
560 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1e6d17a5
AP		 561 .gem_prime_export = drm_gem_prime_export,
562 .gem_prime_import = drm_gem_prime_import,
563 .gem_prime_pin = radeon_gem_prime_pin,
280cf211 564 .gem_prime_unpin = radeon_gem_prime_unpin,
1e6d17a5
AP		 565 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
566 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
567 .gem_prime_vmap = radeon_gem_prime_vmap,
568 .gem_prime_vunmap = radeon_gem_prime_vunmap,
40f5cf99 569
771fe6b9
JG		 570 .name = DRIVER_NAME,
571 .desc = DRIVER_DESC,
572 .date = DRIVER_DATE,
573 .major = KMS_DRIVER_MAJOR,
574 .minor = KMS_DRIVER_MINOR,
575 .patchlevel = KMS_DRIVER_PATCHLEVEL,
576};
771fe6b9
JG		 577
578static struct drm_driver *driver;
8410ea3b
DA		 579static struct pci_driver *pdriver;
580
14adc892 581#ifdef CONFIG_DRM_RADEON_UMS
8410ea3b
DA		 582static struct pci_driver radeon_pci_driver = {
583 .name = DRIVER_NAME,
584 .id_table = pciidlist,
585};
14adc892 586#endif
8410ea3b
DA		 587
588static struct pci_driver radeon_kms_pci_driver = {
589 .name = DRIVER_NAME,
590 .id_table = pciidlist,
591 .probe = radeon_pci_probe,
592 .remove = radeon_pci_remove,
7473e830 593 .driver.pm = &radeon_pm_ops,
8410ea3b 594};
771fe6b9 595
1da177e4
LT		 596static int __init radeon_init(void)
597{
e9ced8e0
DA		 598#ifdef CONFIG_VGA_CONSOLE
599 if (vgacon_text_force() && radeon_modeset == -1) {
600 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
601 radeon_modeset = 0;
602 }
603#endif
604 /* set to modesetting by default if not nomodeset */
605 if (radeon_modeset == -1)
606 radeon_modeset = 1;
607
771fe6b9
JG		 608 if (radeon_modeset == 1) {
609 DRM_INFO("radeon kernel modesetting enabled.\n");
610 driver = &kms_driver;
8410ea3b 611 pdriver = &radeon_kms_pci_driver;
771fe6b9
JG		 612 driver->driver_features |= DRIVER_MODESET;
613 driver->num_ioctls = radeon_max_kms_ioctl;
6a9ee8af 614 radeon_register_atpx_handler();
14adc892
CK		 615
616 } else {
617#ifdef CONFIG_DRM_RADEON_UMS
618 DRM_INFO("radeon userspace modesetting enabled.\n");
619 driver = &driver_old;
620 pdriver = &radeon_pci_driver;
621 driver->driver_features &= ~DRIVER_MODESET;
622 driver->num_ioctls = radeon_max_ioctl;
623#else
624 DRM_ERROR("No UMS support in radeon module!\n");
625 return -EINVAL;
626#endif
771fe6b9 627 }
14adc892
CK		 628
629 /* let modprobe override vga console setting */
8410ea3b 630 return drm_pci_init(driver, pdriver);
1da177e4
LT		 631}
632
633static void __exit radeon_exit(void)
634{
8410ea3b 635 drm_pci_exit(driver, pdriver);
6a9ee8af 636 radeon_unregister_atpx_handler();
1da177e4
LT		 637}
638
176f613e 639module_init(radeon_init);
1da177e4
LT		 640module_exit(radeon_exit);
641
b5e89ed5
DA		 642MODULE_AUTHOR(DRIVER_AUTHOR);
643MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 644MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)