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drm/radeon/atombios_encoders: Move 'radeon_atom_get_tv_timings()'s prototype into...
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
6d587203 1/*
1da177e4
LT		 2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
1da177e4 32
f9183127 33#include <linux/compat.h>
771fe6b9 34#include <linux/console.h>
e0cd3608 35#include <linux/module.h>
10ebc0bc
DA		 36#include <linux/pm_runtime.h>
37#include <linux/vga_switcheroo.h>
534e5f84 38#include <linux/mmu_notifier.h>
625c18d7 39#include <linux/pci.h>
d9fc9413 40
b8076b5e 41#include <drm/drm_agpsupport.h>
64a9dfc4 42#include <drm/drm_crtc_helper.h>
f9183127
SR		 43#include <drm/drm_drv.h>
44#include <drm/drm_fb_helper.h>
45#include <drm/drm_file.h>
46#include <drm/drm_gem.h>
47#include <drm/drm_ioctl.h>
f9183127 48#include <drm/drm_pciids.h>
fcd70cd3 49#include <drm/drm_probe_helper.h>
f9183127
SR		 50#include <drm/drm_vblank.h>
51#include <drm/radeon_drm.h>
52
53#include "radeon_drv.h"
e28740ec 54
771fe6b9
JG		 55/*
56 * KMS wrapper.
0de1a57b
DA		 57 * - 2.0.0 - initial interface
58 * - 2.1.0 - add square tiling interface
fdb43528 59 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 60 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 61 * - 2.4.0 - add crtc id query
148a03bc 62 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 63 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 64 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 65 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 66 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD		 67 * 2.10.0 - fusion 2D tiling
68 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 69 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 70 * 2.13.0 - virtual memory support, streamout
285484e2 71 * 2.14.0 - add evergreen tiling informations
609c1e15 72 * 2.15.0 - add max_pipes query
d2609875 73 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 74 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 75 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 76 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 77 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 78 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 79 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 80 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 81 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 82 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 83 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 84 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 85 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 86 * 2.29.0 - R500 FP16 color clear registers
774c389f 87 * 2.30.0 - fix for FMASK texturing
a0a53aa8 88 * 2.31.0 - Add fastfb support for rs690
902aaef6 89 * 2.32.0 - new info request for rings working
64d7b8be 90 * 2.33.0 - Add SI tiling mode array query
39aee490 91 * 2.34.0 - Add CIK tiling mode array query
32f79a8a 92 * 2.35.0 - Add CIK macrotile mode array query
9482d0d3 93 * 2.36.0 - Fix CIK DCE tiling setup
7c4c62a0 94 * 2.37.0 - allow GS ring setup on r6xx/r7xx
020ff546
MO		 95 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
96 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
65fcf668 97 * 2.39.0 - Add INFO query for number of active CUs
72a9987e 98 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
897eba82 99 * CS to GPU on >= r600
16613743 100 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
1957d6be 101 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
72b9076b 102 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
8c4f2bbd 103 * 2.44.0 - SET_APPEND_CNT packet3 support
3d02b7fe 104 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
662ce7bc 105 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
4d6bdbad 106 * 2.47.0 - Add UVD_NO_OP register support
113d0f9d 107 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
51964e9e 108 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
75cb00dc 109 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
771fe6b9
JG		 110 */
111#define KMS_DRIVER_MAJOR 2
75cb00dc 112#define KMS_DRIVER_MINOR 50
771fe6b9 113#define KMS_DRIVER_PATCHLEVEL 0
274ad65c
JG		 114int radeon_suspend_kms(struct drm_device *dev, bool suspend,
115 bool fbcon, bool freeze);
10ebc0bc 116int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
771fe6b9
JG		 117void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
118int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
119void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
e9f0d76f 120irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
88e72717
TR		 121extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
122 unsigned int flags, int *vpos, int *hpos,
3bb403bf
VS		 123 ktime_t *stime, ktime_t *etime,
124 const struct drm_display_mode *mode);
90c4cde9 125extern bool radeon_is_px(struct drm_device *dev);
baa70943 126extern const struct drm_ioctl_desc radeon_ioctls_kms[];
771fe6b9
JG		 127extern int radeon_max_kms_ioctl;
128int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
ff72145b
DA		 129int radeon_mode_dumb_mmap(struct drm_file *filp,
130 struct drm_device *dev,
131 uint32_t handle, uint64_t *offset_p);
132int radeon_mode_dumb_create(struct drm_file *file_priv,
133 struct drm_device *dev,
134 struct drm_mode_create_dumb *args);
1e6d17a5 135struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
b5e9c1a2 136 struct dma_buf_attachment *,
1e6d17a5 137 struct sg_table *sg);
ff72145b 138
14adc892
CK		 139/* atpx handler */
140#if defined(CONFIG_VGA_SWITCHEROO)
141void radeon_register_atpx_handler(void);
142void radeon_unregister_atpx_handler(void);
e1052b35 143bool radeon_has_atpx_dgpu_power_cntl(void);
b8c9fd5a 144bool radeon_is_atpx_hybrid(void);
14adc892
CK		 145#else
146static inline void radeon_register_atpx_handler(void) {}
147static inline void radeon_unregister_atpx_handler(void) {}
e1052b35 148static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
b8c9fd5a 149static inline bool radeon_is_atpx_hybrid(void) { return false; }
14adc892 150#endif
1da177e4 151
689b9d74 152int radeon_no_wb;
e9ced8e0 153int radeon_modeset = -1;
771fe6b9
JG		 154int radeon_dynclks = -1;
155int radeon_r4xx_atom = 0;
037d1a66 156int radeon_agpmode = -1;
771fe6b9 157int radeon_vram_limit = 0;
edcd26e8 158int radeon_gart_size = -1; /* auto */
771fe6b9 159int radeon_benchmarking = 0;
ecc0b326 160int radeon_testing = 0;
771fe6b9 161int radeon_connector_table = 0;
4ce001ab 162int radeon_tv = 1;
108dc8e8 163int radeon_audio = -1;
f46c0120 164int radeon_disp_priority = 0;
e2b0a8e1 165int radeon_hw_i2c = 0;
197bbb3d 166int radeon_pcie_gen2 = -1;
a18cee15 167int radeon_msi = -1;
3368ff0c 168int radeon_lockup_timeout = 10000;
a0a53aa8 169int radeon_fastfb = 0;
da321c8a 170int radeon_dpm = -1;
1294d4a3 171int radeon_aspm = -1;
10ebc0bc 172int radeon_runtime_pm = -1;
363eb0b4 173int radeon_hard_reset = 0;
dfc230f9
CK		 174int radeon_vm_size = 8;
175int radeon_vm_block_size = -1;
a624f429 176int radeon_deep_color = 0;
39dc5454 177int radeon_use_pflipirq = 2;
6e909f74 178int radeon_bapm = -1;
bc13018b 179int radeon_backlight = -1;
875711f0 180int radeon_auxch = -1;
9843ead0 181int radeon_mst = 0;
f1a0a67a 182int radeon_uvd = 1;
fabb5935 183int radeon_vce = 1;
689b9d74 184
61a2d07d 185MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA		 186module_param_named(no_wb, radeon_no_wb, int, 0444);
187
771fe6b9
JG		 188MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
189module_param_named(modeset, radeon_modeset, int, 0400);
190
191MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
192module_param_named(dynclks, radeon_dynclks, int, 0444);
193
194MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
195module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
196
8902e6f2 197MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
771fe6b9
JG		 198module_param_named(vramlimit, radeon_vram_limit, int, 0600);
199
200MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
201module_param_named(agpmode, radeon_agpmode, int, 0444);
202
edcd26e8 203MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
771fe6b9
JG		 204module_param_named(gartsize, radeon_gart_size, int, 0600);
205
206MODULE_PARM_DESC(benchmark, "Run benchmark");
207module_param_named(benchmark, radeon_benchmarking, int, 0444);
208
ecc0b326
MD		 209MODULE_PARM_DESC(test, "Run tests");
210module_param_named(test, radeon_testing, int, 0444);
211
771fe6b9
JG		 212MODULE_PARM_DESC(connector_table, "Force connector table");
213module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA		 214
215MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
216module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 217
108dc8e8 218MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
dafc3bd5
CK		 219module_param_named(audio, radeon_audio, int, 0444);
220
f46c0120
AD		 221MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
222module_param_named(disp_priority, radeon_disp_priority, int, 0444);
223
e2b0a8e1
AD		 224MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
225module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
226
197bbb3d 227MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD		 228module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
229
a18cee15
AD		 230MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
231module_param_named(msi, radeon_msi, int, 0444);
232
b5c9ecab 233MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
3368ff0c
CK		 234module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
235
a0a53aa8
SL		 236MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
237module_param_named(fastfb, radeon_fastfb, int, 0444);
238
da321c8a
AD		 239MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
240module_param_named(dpm, radeon_dpm, int, 0444);
241
1294d4a3
AD		 242MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
243module_param_named(aspm, radeon_aspm, int, 0444);
244
10ebc0bc
DA		 245MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
246module_param_named(runpm, radeon_runtime_pm, int, 0444);
247
363eb0b4
AD		 248MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
249module_param_named(hard_reset, radeon_hard_reset, int, 0444);
250
20b2656d 251MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
c1c44132
CK		 252module_param_named(vm_size, radeon_vm_size, int, 0444);
253
dfc230f9 254MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
4510fb98
CK		 255module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
256
a624f429
AD		 257MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
258module_param_named(deep_color, radeon_deep_color, int, 0444);
259
39dc5454
MK		 260MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
261module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
262
6e909f74
AD		 263MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
264module_param_named(bapm, radeon_bapm, int, 0444);
265
bc13018b
AD		 266MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
267module_param_named(backlight, radeon_backlight, int, 0444);
268
875711f0
DA		 269MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
270module_param_named(auxch, radeon_auxch, int, 0444);
271
9843ead0
DA		 272MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
273module_param_named(mst, radeon_mst, int, 0444);
274
f1a0a67a
JG		 275MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
276module_param_named(uvd, radeon_uvd, int, 0444);
277
fabb5935
JG		 278MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
279module_param_named(vce, radeon_vce, int, 0444);
280
36ffce0a
FK		 281int radeon_si_support = 1;
282MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
283module_param_named(si_support, radeon_si_support, int, 0444);
36ffce0a 284
2b059658
MD		 285int radeon_cik_support = 1;
286MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
e7f78b69 287module_param_named(cik_support, radeon_cik_support, int, 0444);
e7f78b69 288
14adc892
CK		 289static struct pci_device_id pciidlist[] = {
290 radeon_PCI_IDS
291};
292
293MODULE_DEVICE_TABLE(pci, pciidlist);
294
771fe6b9
JG		 295static struct drm_driver kms_driver;
296
a801abe4
AD		 297bool radeon_device_is_virtual(void);
298
56550d94
GKH		 299static int radeon_pci_probe(struct pci_dev *pdev,
300 const struct pci_device_id *ent)
771fe6b9 301{
9dbc88d0 302 unsigned long flags = 0;
b8076b5e 303 struct drm_device *dev;
30238151
TR		 304 int ret;
305
9dbc88d0
HG		 306 if (!ent)
307 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */
308
309 flags = ent->driver_data;
310
311 if (!radeon_si_support) {
312 switch (flags & RADEON_FAMILY_MASK) {
313 case CHIP_TAHITI:
314 case CHIP_PITCAIRN:
315 case CHIP_VERDE:
316 case CHIP_OLAND:
317 case CHIP_HAINAN:
318 dev_info(&pdev->dev,
319 "SI support disabled by module param\n");
320 return -ENODEV;
321 }
322 }
323 if (!radeon_cik_support) {
324 switch (flags & RADEON_FAMILY_MASK) {
325 case CHIP_KAVERI:
326 case CHIP_BONAIRE:
327 case CHIP_HAWAII:
328 case CHIP_KABINI:
329 case CHIP_MULLINS:
330 dev_info(&pdev->dev,
331 "CIK support disabled by module param\n");
332 return -ENODEV;
333 }
334 }
335
b00e5334 336 if (vga_switcheroo_client_probe_defer(pdev))
14d20001
LW		 337 return -EPROBE_DEFER;
338
a56f7428 339 /* Get rid of things like offb */
35616a4a 340 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "radeondrmfb");
30238151
TR		 341 if (ret)
342 return ret;
a56f7428 343
b8076b5e
DV		 344 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
345 if (IS_ERR(dev))
346 return PTR_ERR(dev);
347
348 ret = pci_enable_device(pdev);
349 if (ret)
350 goto err_free;
351
352 dev->pdev = pdev;
353#ifdef __alpha__
354 dev->hose = pdev->sysdata;
355#endif
356
357 pci_set_drvdata(pdev, dev);
358
359 if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP))
360 dev->agp = drm_agp_init(dev);
361 if (dev->agp) {
362 dev->agp->agp_mtrr = arch_phys_wc_add(
363 dev->agp->agp_info.aper_base,
364 dev->agp->agp_info.aper_size *
365 1024 * 1024);
366 }
367
368 ret = drm_dev_register(dev, ent->driver_data);
369 if (ret)
370 goto err_agp;
371
372 return 0;
373
374err_agp:
375 if (dev->agp)
376 arch_phys_wc_del(dev->agp->agp_mtrr);
377 kfree(dev->agp);
378 pci_disable_device(pdev);
379err_free:
380 drm_dev_put(dev);
381 return ret;
771fe6b9
JG		 382}
383
384static void
385radeon_pci_remove(struct pci_dev *pdev)
386{
387 struct drm_device *dev = pci_get_drvdata(pdev);
388
389 drm_put_dev(dev);
390}
391
a801abe4
AD		 392static void
393radeon_pci_shutdown(struct pci_dev *pdev)
394{
395 /* if we are running in a VM, make sure the device
b9b487e4 396 * torn down properly on reboot/shutdown
a801abe4 397 */
b9b487e4
AD		 398 if (radeon_device_is_virtual())
399 radeon_pci_remove(pdev);
d02f5aab
KM		 400
401#ifdef CONFIG_PPC64
4cae34d0
K		 402 /*
403 * Some adapters need to be suspended before a
d02f5aab
KM		 404 * shutdown occurs in order to prevent an error
405 * during kexec.
406 * Make this power specific becauase it breaks
407 * some non-power boards.
408 */
4cae34d0 409 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
d02f5aab 410#endif
a801abe4
AD		 411}
412
7473e830 413static int radeon_pmops_suspend(struct device *dev)
771fe6b9 414{
59d788b1 415 struct drm_device *drm_dev = dev_get_drvdata(dev);
274ad65c 416 return radeon_suspend_kms(drm_dev, true, true, false);
771fe6b9
JG		 417}
418
7473e830 419static int radeon_pmops_resume(struct device *dev)
771fe6b9 420{
59d788b1 421 struct drm_device *drm_dev = dev_get_drvdata(dev);
103917b3
AD		 422
423 /* GPU comes up enabled by the bios on resume */
424 if (radeon_is_px(drm_dev)) {
425 pm_runtime_disable(dev);
426 pm_runtime_set_active(dev);
427 pm_runtime_enable(dev);
428 }
429
10ebc0bc 430 return radeon_resume_kms(drm_dev, true, true);
7473e830
DA		 431}
432
433static int radeon_pmops_freeze(struct device *dev)
434{
59d788b1 435 struct drm_device *drm_dev = dev_get_drvdata(dev);
274ad65c 436 return radeon_suspend_kms(drm_dev, false, true, true);
771fe6b9
JG		 437}
438
7473e830
DA		 439static int radeon_pmops_thaw(struct device *dev)
440{
59d788b1 441 struct drm_device *drm_dev = dev_get_drvdata(dev);
10ebc0bc
DA		 442 return radeon_resume_kms(drm_dev, false, true);
443}
444
445static int radeon_pmops_runtime_suspend(struct device *dev)
446{
447 struct pci_dev *pdev = to_pci_dev(dev);
448 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 449
90c4cde9 450 if (!radeon_is_px(drm_dev)) {
1d8eec8b
DA		 451 pm_runtime_forbid(dev);
452 return -EBUSY;
453 }
9babd35a 454
10ebc0bc
DA		 455 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
456 drm_kms_helper_poll_disable(drm_dev);
10ebc0bc 457
3655d1a6 458 radeon_suspend_kms(drm_dev, false, false, false);
10ebc0bc
DA		 459 pci_save_state(pdev);
460 pci_disable_device(pdev);
b440bde7 461 pci_ignore_hotplug(pdev);
31764c1e
AD		 462 if (radeon_is_atpx_hybrid())
463 pci_set_power_state(pdev, PCI_D3cold);
84919992 464 else if (!radeon_has_atpx_dgpu_power_cntl())
f7ea4189 465 pci_set_power_state(pdev, PCI_D3hot);
10ebc0bc
DA		 466 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
467
468 return 0;
469}
470
471static int radeon_pmops_runtime_resume(struct device *dev)
472{
473 struct pci_dev *pdev = to_pci_dev(dev);
474 struct drm_device *drm_dev = pci_get_drvdata(pdev);
475 int ret;
476
90c4cde9 477 if (!radeon_is_px(drm_dev))
9babd35a
AD		 478 return -EINVAL;
479
10ebc0bc
DA		 480 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
481
84919992
AD		 482 if (radeon_is_atpx_hybrid() ||
483 !radeon_has_atpx_dgpu_power_cntl())
484 pci_set_power_state(pdev, PCI_D0);
10ebc0bc
DA		 485 pci_restore_state(pdev);
486 ret = pci_enable_device(pdev);
487 if (ret)
488 return ret;
489 pci_set_master(pdev);
490
491 ret = radeon_resume_kms(drm_dev, false, false);
492 drm_kms_helper_poll_enable(drm_dev);
10ebc0bc
DA		 493 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
494 return 0;
495}
496
497static int radeon_pmops_runtime_idle(struct device *dev)
498{
59d788b1 499 struct drm_device *drm_dev = dev_get_drvdata(dev);
10ebc0bc
DA		 500 struct drm_crtc *crtc;
501
90c4cde9 502 if (!radeon_is_px(drm_dev)) {
1d8eec8b 503 pm_runtime_forbid(dev);
10ebc0bc
DA		 504 return -EBUSY;
505 }
506
507 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
508 if (crtc->enabled) {
509 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
510 return -EBUSY;
511 }
512 }
513
514 pm_runtime_mark_last_busy(dev);
515 pm_runtime_autosuspend(dev);
516 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
517 return 1;
518}
519
520long radeon_drm_ioctl(struct file *filp,
521 unsigned int cmd, unsigned long arg)
522{
523 struct drm_file *file_priv = filp->private_data;
524 struct drm_device *dev;
525 long ret;
526 dev = file_priv->minor->dev;
527 ret = pm_runtime_get_sync(dev->dev);
9fb10671
AP		 528 if (ret < 0) {
529 pm_runtime_put_autosuspend(dev->dev);
10ebc0bc 530 return ret;
9fb10671 531 }
10ebc0bc
DA		 532
533 ret = drm_ioctl(filp, cmd, arg);
552f9d60 534
10ebc0bc
DA		 535 pm_runtime_mark_last_busy(dev->dev);
536 pm_runtime_put_autosuspend(dev->dev);
537 return ret;
7473e830
DA		 538}
539
ff32d39b
AV		 540#ifdef CONFIG_COMPAT
541static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
542{
543 unsigned int nr = DRM_IOCTL_NR(cmd);
544 int ret;
545
546 if (nr < DRM_COMMAND_BASE)
547 return drm_compat_ioctl(filp, cmd, arg);
548
549 ret = radeon_drm_ioctl(filp, cmd, arg);
550
551 return ret;
552}
553#endif
554
7473e830
DA		 555static const struct dev_pm_ops radeon_pm_ops = {
556 .suspend = radeon_pmops_suspend,
557 .resume = radeon_pmops_resume,
558 .freeze = radeon_pmops_freeze,
559 .thaw = radeon_pmops_thaw,
560 .poweroff = radeon_pmops_freeze,
561 .restore = radeon_pmops_resume,
10ebc0bc
DA		 562 .runtime_suspend = radeon_pmops_runtime_suspend,
563 .runtime_resume = radeon_pmops_runtime_resume,
564 .runtime_idle = radeon_pmops_runtime_idle,
7473e830
DA		 565};
566
e08e96de
AV		 567static const struct file_operations radeon_driver_kms_fops = {
568 .owner = THIS_MODULE,
569 .open = drm_open,
570 .release = drm_release,
10ebc0bc 571 .unlocked_ioctl = radeon_drm_ioctl,
e08e96de
AV		 572 .mmap = radeon_mmap,
573 .poll = drm_poll,
e08e96de
AV		 574 .read = drm_read,
575#ifdef CONFIG_COMPAT
576 .compat_ioctl = radeon_kms_compat_ioctl,
577#endif
578};
579
771fe6b9
JG		 580static struct drm_driver kms_driver = {
581 .driver_features =
b8076b5e 582 DRIVER_GEM | DRIVER_RENDER,
771fe6b9 583 .load = radeon_driver_load_kms,
771fe6b9 584 .open = radeon_driver_open_kms,
771fe6b9
JG		 585 .postclose = radeon_driver_postclose_kms,
586 .lastclose = radeon_driver_lastclose_kms,
587 .unload = radeon_driver_unload_kms,
771fe6b9
JG		 588 .irq_preinstall = radeon_driver_irq_preinstall_kms,
589 .irq_postinstall = radeon_driver_irq_postinstall_kms,
590 .irq_uninstall = radeon_driver_irq_uninstall_kms,
591 .irq_handler = radeon_driver_irq_handler_kms,
771fe6b9 592 .ioctls = radeon_ioctls_kms,
ff72145b
DA		 593 .dumb_create = radeon_mode_dumb_create,
594 .dumb_map_offset = radeon_mode_dumb_mmap,
e08e96de 595 .fops = &radeon_driver_kms_fops,
40f5cf99
AD		 596
597 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
598 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1e6d17a5 599 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
40f5cf99 600
771fe6b9
JG		 601 .name = DRIVER_NAME,
602 .desc = DRIVER_DESC,
603 .date = DRIVER_DATE,
604 .major = KMS_DRIVER_MAJOR,
605 .minor = KMS_DRIVER_MINOR,
606 .patchlevel = KMS_DRIVER_PATCHLEVEL,
607};
771fe6b9
JG		 608
609static struct drm_driver *driver;
8410ea3b
DA		 610static struct pci_driver *pdriver;
611
8410ea3b
DA		 612static struct pci_driver radeon_kms_pci_driver = {
613 .name = DRIVER_NAME,
614 .id_table = pciidlist,
615 .probe = radeon_pci_probe,
616 .remove = radeon_pci_remove,
a801abe4 617 .shutdown = radeon_pci_shutdown,
7473e830 618 .driver.pm = &radeon_pm_ops,
8410ea3b 619};
771fe6b9 620
1da177e4
LT		 621static int __init radeon_init(void)
622{
e9ced8e0
DA		 623 if (vgacon_text_force() && radeon_modeset == -1) {
624 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
625 radeon_modeset = 0;
626 }
e9ced8e0
DA		 627 /* set to modesetting by default if not nomodeset */
628 if (radeon_modeset == -1)
629 radeon_modeset = 1;
630
771fe6b9
JG		 631 if (radeon_modeset == 1) {
632 DRM_INFO("radeon kernel modesetting enabled.\n");
633 driver = &kms_driver;
8410ea3b 634 pdriver = &radeon_kms_pci_driver;
771fe6b9
JG		 635 driver->driver_features |= DRIVER_MODESET;
636 driver->num_ioctls = radeon_max_kms_ioctl;
6a9ee8af 637 radeon_register_atpx_handler();
14adc892
CK		 638
639 } else {
14adc892
CK		 640 DRM_ERROR("No UMS support in radeon module!\n");
641 return -EINVAL;
771fe6b9 642 }
14adc892 643
10631d72 644 return pci_register_driver(pdriver);
1da177e4
LT		 645}
646
647static void __exit radeon_exit(void)
648{
10631d72 649 pci_unregister_driver(pdriver);
6a9ee8af 650 radeon_unregister_atpx_handler();
534e5f84 651 mmu_notifier_synchronize();
1da177e4
LT		 652}
653
176f613e 654module_init(radeon_init);
1da177e4
LT		 655module_exit(radeon_exit);
656
b5e89ed5
DA		 657MODULE_AUTHOR(DRIVER_AUTHOR);
658MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 659MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)