projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon: Allow setting shader registers using DMA/COPY packet3 on SI.
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
1da177e4
LT		 1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
1da177e4
LT		 34#include "radeon_drv.h"
35
760285e7 36#include <drm/drm_pciids.h>
14d20001 37#include <linux/apple-gmux.h>
771fe6b9 38#include <linux/console.h>
e0cd3608 39#include <linux/module.h>
10ebc0bc 40#include <linux/pm_runtime.h>
14d20001 41#include <linux/vgaarb.h>
10ebc0bc 42#include <linux/vga_switcheroo.h>
d9fc9413
DV		 43#include <drm/drm_gem.h>
44
10ebc0bc 45#include "drm_crtc_helper.h"
e28740ec
OG		 46#include "radeon_kfd.h"
47
771fe6b9
JG		 48/*
49 * KMS wrapper.
0de1a57b
DA		 50 * - 2.0.0 - initial interface
51 * - 2.1.0 - add square tiling interface
fdb43528 52 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 53 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 54 * - 2.4.0 - add crtc id query
148a03bc 55 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 56 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 57 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 58 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 59 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD		 60 * 2.10.0 - fusion 2D tiling
61 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 62 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 63 * 2.13.0 - virtual memory support, streamout
285484e2 64 * 2.14.0 - add evergreen tiling informations
609c1e15 65 * 2.15.0 - add max_pipes query
d2609875 66 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 67 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 68 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 69 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 70 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 71 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 72 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 73 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 74 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 75 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 76 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 77 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 78 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 79 * 2.29.0 - R500 FP16 color clear registers
774c389f 80 * 2.30.0 - fix for FMASK texturing
a0a53aa8 81 * 2.31.0 - Add fastfb support for rs690
902aaef6 82 * 2.32.0 - new info request for rings working
64d7b8be 83 * 2.33.0 - Add SI tiling mode array query
39aee490 84 * 2.34.0 - Add CIK tiling mode array query
32f79a8a 85 * 2.35.0 - Add CIK macrotile mode array query
9482d0d3 86 * 2.36.0 - Fix CIK DCE tiling setup
7c4c62a0 87 * 2.37.0 - allow GS ring setup on r6xx/r7xx
020ff546
MO		 88 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
89 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
65fcf668 90 * 2.39.0 - Add INFO query for number of active CUs
72a9987e 91 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
897eba82 92 * CS to GPU on >= r600
16613743 93 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
1957d6be 94 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
72b9076b 95 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
8c4f2bbd 96 * 2.44.0 - SET_APPEND_CNT packet3 support
3d02b7fe 97 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
771fe6b9
JG		 98 */
99#define KMS_DRIVER_MAJOR 2
3d02b7fe 100#define KMS_DRIVER_MINOR 45
771fe6b9
JG		 101#define KMS_DRIVER_PATCHLEVEL 0
102int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
103int radeon_driver_unload_kms(struct drm_device *dev);
771fe6b9
JG		 104void radeon_driver_lastclose_kms(struct drm_device *dev);
105int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
106void radeon_driver_postclose_kms(struct drm_device *dev,
107 struct drm_file *file_priv);
108void radeon_driver_preclose_kms(struct drm_device *dev,
109 struct drm_file *file_priv);
274ad65c
JG		 110int radeon_suspend_kms(struct drm_device *dev, bool suspend,
111 bool fbcon, bool freeze);
10ebc0bc 112int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 113u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
114int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
115void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
116int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
f5a80209
MK		 117 int *max_error,
118 struct timeval *vblank_time,
119 unsigned flags);
771fe6b9
JG		 120void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
121int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
122void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
e9f0d76f 123irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
771fe6b9 124void radeon_gem_object_free(struct drm_gem_object *obj);
721604a1
JG		 125int radeon_gem_object_open(struct drm_gem_object *obj,
126 struct drm_file *file_priv);
127void radeon_gem_object_close(struct drm_gem_object *obj,
128 struct drm_file *file_priv);
f72a113a
CK		 129struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
130 struct drm_gem_object *gobj,
131 int flags);
88e72717
TR		 132extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
133 unsigned int flags, int *vpos, int *hpos,
3bb403bf
VS		 134 ktime_t *stime, ktime_t *etime,
135 const struct drm_display_mode *mode);
90c4cde9 136extern bool radeon_is_px(struct drm_device *dev);
baa70943 137extern const struct drm_ioctl_desc radeon_ioctls_kms[];
771fe6b9
JG		 138extern int radeon_max_kms_ioctl;
139int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
ff72145b
DA		 140int radeon_mode_dumb_mmap(struct drm_file *filp,
141 struct drm_device *dev,
142 uint32_t handle, uint64_t *offset_p);
143int radeon_mode_dumb_create(struct drm_file *file_priv,
144 struct drm_device *dev,
145 struct drm_mode_create_dumb *args);
1e6d17a5
AP		 146struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
147struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
b5e9c1a2 148 struct dma_buf_attachment *,
1e6d17a5
AP		 149 struct sg_table *sg);
150int radeon_gem_prime_pin(struct drm_gem_object *obj);
280cf211 151void radeon_gem_prime_unpin(struct drm_gem_object *obj);
3aac4502 152struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
1e6d17a5
AP		 153void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
154void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
14adc892
CK		 155extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
156 unsigned long arg);
ff72145b 157
771fe6b9
JG		 158#if defined(CONFIG_DEBUG_FS)
159int radeon_debugfs_init(struct drm_minor *minor);
160void radeon_debugfs_cleanup(struct drm_minor *minor);
161#endif
771fe6b9 162
14adc892
CK		 163/* atpx handler */
164#if defined(CONFIG_VGA_SWITCHEROO)
165void radeon_register_atpx_handler(void);
166void radeon_unregister_atpx_handler(void);
167#else
168static inline void radeon_register_atpx_handler(void) {}
169static inline void radeon_unregister_atpx_handler(void) {}
170#endif
1da177e4 171
689b9d74 172int radeon_no_wb;
e9ced8e0 173int radeon_modeset = -1;
771fe6b9
JG		 174int radeon_dynclks = -1;
175int radeon_r4xx_atom = 0;
176int radeon_agpmode = 0;
177int radeon_vram_limit = 0;
edcd26e8 178int radeon_gart_size = -1; /* auto */
771fe6b9 179int radeon_benchmarking = 0;
ecc0b326 180int radeon_testing = 0;
771fe6b9 181int radeon_connector_table = 0;
4ce001ab 182int radeon_tv = 1;
108dc8e8 183int radeon_audio = -1;
f46c0120 184int radeon_disp_priority = 0;
e2b0a8e1 185int radeon_hw_i2c = 0;
197bbb3d 186int radeon_pcie_gen2 = -1;
a18cee15 187int radeon_msi = -1;
3368ff0c 188int radeon_lockup_timeout = 10000;
a0a53aa8 189int radeon_fastfb = 0;
da321c8a 190int radeon_dpm = -1;
1294d4a3 191int radeon_aspm = -1;
10ebc0bc 192int radeon_runtime_pm = -1;
363eb0b4 193int radeon_hard_reset = 0;
dfc230f9
CK		 194int radeon_vm_size = 8;
195int radeon_vm_block_size = -1;
a624f429 196int radeon_deep_color = 0;
39dc5454 197int radeon_use_pflipirq = 2;
6e909f74 198int radeon_bapm = -1;
bc13018b 199int radeon_backlight = -1;
875711f0 200int radeon_auxch = -1;
9843ead0 201int radeon_mst = 0;
f1a0a67a 202int radeon_uvd = 1;
fabb5935 203int radeon_vce = 1;
689b9d74 204
61a2d07d 205MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA		 206module_param_named(no_wb, radeon_no_wb, int, 0444);
207
771fe6b9
JG		 208MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
209module_param_named(modeset, radeon_modeset, int, 0400);
210
211MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
212module_param_named(dynclks, radeon_dynclks, int, 0444);
213
214MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
215module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
216
8902e6f2 217MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
771fe6b9
JG		 218module_param_named(vramlimit, radeon_vram_limit, int, 0600);
219
220MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
221module_param_named(agpmode, radeon_agpmode, int, 0444);
222
edcd26e8 223MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
771fe6b9
JG		 224module_param_named(gartsize, radeon_gart_size, int, 0600);
225
226MODULE_PARM_DESC(benchmark, "Run benchmark");
227module_param_named(benchmark, radeon_benchmarking, int, 0444);
228
ecc0b326
MD		 229MODULE_PARM_DESC(test, "Run tests");
230module_param_named(test, radeon_testing, int, 0444);
231
771fe6b9
JG		 232MODULE_PARM_DESC(connector_table, "Force connector table");
233module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA		 234
235MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
236module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 237
108dc8e8 238MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
dafc3bd5
CK		 239module_param_named(audio, radeon_audio, int, 0444);
240
f46c0120
AD		 241MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
242module_param_named(disp_priority, radeon_disp_priority, int, 0444);
243
e2b0a8e1
AD		 244MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
245module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
246
197bbb3d 247MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD		 248module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
249
a18cee15
AD		 250MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
251module_param_named(msi, radeon_msi, int, 0444);
252
b5c9ecab 253MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
3368ff0c
CK		 254module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
255
a0a53aa8
SL		 256MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
257module_param_named(fastfb, radeon_fastfb, int, 0444);
258
da321c8a
AD		 259MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
260module_param_named(dpm, radeon_dpm, int, 0444);
261
1294d4a3
AD		 262MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
263module_param_named(aspm, radeon_aspm, int, 0444);
264
10ebc0bc
DA		 265MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
266module_param_named(runpm, radeon_runtime_pm, int, 0444);
267
363eb0b4
AD		 268MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
269module_param_named(hard_reset, radeon_hard_reset, int, 0444);
270
20b2656d 271MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
c1c44132
CK		 272module_param_named(vm_size, radeon_vm_size, int, 0444);
273
dfc230f9 274MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
4510fb98
CK		 275module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
276
a624f429
AD		 277MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
278module_param_named(deep_color, radeon_deep_color, int, 0444);
279
39dc5454
MK		 280MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
281module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
282
6e909f74
AD		 283MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
284module_param_named(bapm, radeon_bapm, int, 0444);
285
bc13018b
AD		 286MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
287module_param_named(backlight, radeon_backlight, int, 0444);
288
875711f0
DA		 289MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
290module_param_named(auxch, radeon_auxch, int, 0444);
291
9843ead0
DA		 292MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
293module_param_named(mst, radeon_mst, int, 0444);
294
f1a0a67a
JG		 295MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
296module_param_named(uvd, radeon_uvd, int, 0444);
297
fabb5935
JG		 298MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
299module_param_named(vce, radeon_vce, int, 0444);
300
14adc892
CK		 301static struct pci_device_id pciidlist[] = {
302 radeon_PCI_IDS
303};
304
305MODULE_DEVICE_TABLE(pci, pciidlist);
306
771fe6b9
JG		 307static struct drm_driver kms_driver;
308
30238151 309static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
a56f7428
BH		 310{
311 struct apertures_struct *ap;
312 bool primary = false;
313
314 ap = alloc_apertures(1);
30238151
TR		 315 if (!ap)
316 return -ENOMEM;
317
a56f7428
BH		 318 ap->ranges[0].base = pci_resource_start(pdev, 0);
319 ap->ranges[0].size = pci_resource_len(pdev, 0);
320
321#ifdef CONFIG_X86
322 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
323#endif
324 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
325 kfree(ap);
30238151
TR		 326
327 return 0;
a56f7428
BH		 328}
329
56550d94
GKH		 330static int radeon_pci_probe(struct pci_dev *pdev,
331 const struct pci_device_id *ent)
771fe6b9 332{
30238151
TR		 333 int ret;
334
412c8f7d
OG		 335 /*
336 * Initialize amdkfd before starting radeon. If it was not loaded yet,
337 * defer radeon probing
338 */
339 ret = radeon_kfd_init();
340 if (ret == -EPROBE_DEFER)
341 return ret;
342
14d20001
LW		 343 /*
344 * apple-gmux is needed on dual GPU MacBook Pro
345 * to probe the panel if we're the inactive GPU.
346 */
347 if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) &&
348 apple_gmux_present() && pdev != vga_default_device() &&
349 !vga_switcheroo_handler_flags())
350 return -EPROBE_DEFER;
351
a56f7428 352 /* Get rid of things like offb */
30238151
TR		 353 ret = radeon_kick_out_firmware_fb(pdev);
354 if (ret)
355 return ret;
a56f7428 356
dcdb1674 357 return drm_get_pci_dev(pdev, ent, &kms_driver);
771fe6b9
JG		 358}
359
360static void
361radeon_pci_remove(struct pci_dev *pdev)
362{
363 struct drm_device *dev = pci_get_drvdata(pdev);
364
365 drm_put_dev(dev);
366}
367
7473e830 368static int radeon_pmops_suspend(struct device *dev)
771fe6b9 369{
7473e830
DA		 370 struct pci_dev *pdev = to_pci_dev(dev);
371 struct drm_device *drm_dev = pci_get_drvdata(pdev);
274ad65c 372 return radeon_suspend_kms(drm_dev, true, true, false);
771fe6b9
JG		 373}
374
7473e830 375static int radeon_pmops_resume(struct device *dev)
771fe6b9 376{
7473e830
DA		 377 struct pci_dev *pdev = to_pci_dev(dev);
378 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 379 return radeon_resume_kms(drm_dev, true, true);
7473e830
DA		 380}
381
382static int radeon_pmops_freeze(struct device *dev)
383{
384 struct pci_dev *pdev = to_pci_dev(dev);
385 struct drm_device *drm_dev = pci_get_drvdata(pdev);
274ad65c 386 return radeon_suspend_kms(drm_dev, false, true, true);
771fe6b9
JG		 387}
388
7473e830
DA		 389static int radeon_pmops_thaw(struct device *dev)
390{
391 struct pci_dev *pdev = to_pci_dev(dev);
392 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc
DA		 393 return radeon_resume_kms(drm_dev, false, true);
394}
395
396static int radeon_pmops_runtime_suspend(struct device *dev)
397{
398 struct pci_dev *pdev = to_pci_dev(dev);
399 struct drm_device *drm_dev = pci_get_drvdata(pdev);
400 int ret;
401
90c4cde9 402 if (!radeon_is_px(drm_dev)) {
1d8eec8b
DA		 403 pm_runtime_forbid(dev);
404 return -EBUSY;
405 }
9babd35a 406
10ebc0bc
DA		 407 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
408 drm_kms_helper_poll_disable(drm_dev);
409 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
410
274ad65c 411 ret = radeon_suspend_kms(drm_dev, false, false, false);
10ebc0bc
DA		 412 pci_save_state(pdev);
413 pci_disable_device(pdev);
b440bde7 414 pci_ignore_hotplug(pdev);
10ebc0bc
DA		 415 pci_set_power_state(pdev, PCI_D3cold);
416 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
417
418 return 0;
419}
420
421static int radeon_pmops_runtime_resume(struct device *dev)
422{
423 struct pci_dev *pdev = to_pci_dev(dev);
424 struct drm_device *drm_dev = pci_get_drvdata(pdev);
425 int ret;
426
90c4cde9 427 if (!radeon_is_px(drm_dev))
9babd35a
AD		 428 return -EINVAL;
429
10ebc0bc
DA		 430 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
431
432 pci_set_power_state(pdev, PCI_D0);
433 pci_restore_state(pdev);
434 ret = pci_enable_device(pdev);
435 if (ret)
436 return ret;
437 pci_set_master(pdev);
438
439 ret = radeon_resume_kms(drm_dev, false, false);
440 drm_kms_helper_poll_enable(drm_dev);
441 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
442 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
443 return 0;
444}
445
446static int radeon_pmops_runtime_idle(struct device *dev)
447{
448 struct pci_dev *pdev = to_pci_dev(dev);
449 struct drm_device *drm_dev = pci_get_drvdata(pdev);
450 struct drm_crtc *crtc;
451
90c4cde9 452 if (!radeon_is_px(drm_dev)) {
1d8eec8b 453 pm_runtime_forbid(dev);
10ebc0bc
DA		 454 return -EBUSY;
455 }
456
457 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
458 if (crtc->enabled) {
459 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
460 return -EBUSY;
461 }
462 }
463
464 pm_runtime_mark_last_busy(dev);
465 pm_runtime_autosuspend(dev);
466 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
467 return 1;
468}
469
470long radeon_drm_ioctl(struct file *filp,
471 unsigned int cmd, unsigned long arg)
472{
473 struct drm_file *file_priv = filp->private_data;
474 struct drm_device *dev;
475 long ret;
476 dev = file_priv->minor->dev;
477 ret = pm_runtime_get_sync(dev->dev);
478 if (ret < 0)
479 return ret;
480
481 ret = drm_ioctl(filp, cmd, arg);
482
483 pm_runtime_mark_last_busy(dev->dev);
484 pm_runtime_put_autosuspend(dev->dev);
485 return ret;
7473e830
DA		 486}
487
488static const struct dev_pm_ops radeon_pm_ops = {
489 .suspend = radeon_pmops_suspend,
490 .resume = radeon_pmops_resume,
491 .freeze = radeon_pmops_freeze,
492 .thaw = radeon_pmops_thaw,
493 .poweroff = radeon_pmops_freeze,
494 .restore = radeon_pmops_resume,
10ebc0bc
DA		 495 .runtime_suspend = radeon_pmops_runtime_suspend,
496 .runtime_resume = radeon_pmops_runtime_resume,
497 .runtime_idle = radeon_pmops_runtime_idle,
7473e830
DA		 498};
499
e08e96de
AV		 500static const struct file_operations radeon_driver_kms_fops = {
501 .owner = THIS_MODULE,
502 .open = drm_open,
503 .release = drm_release,
10ebc0bc 504 .unlocked_ioctl = radeon_drm_ioctl,
e08e96de
AV		 505 .mmap = radeon_mmap,
506 .poll = drm_poll,
e08e96de
AV		 507 .read = drm_read,
508#ifdef CONFIG_COMPAT
509 .compat_ioctl = radeon_kms_compat_ioctl,
510#endif
511};
512
771fe6b9
JG		 513static struct drm_driver kms_driver = {
514 .driver_features =
28185647 515 DRIVER_USE_AGP |
81e95697 516 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
f33bcab9 517 DRIVER_PRIME | DRIVER_RENDER,
771fe6b9 518 .load = radeon_driver_load_kms,
771fe6b9
JG		 519 .open = radeon_driver_open_kms,
520 .preclose = radeon_driver_preclose_kms,
521 .postclose = radeon_driver_postclose_kms,
522 .lastclose = radeon_driver_lastclose_kms,
915b4d11 523 .set_busid = drm_pci_set_busid,
771fe6b9 524 .unload = radeon_driver_unload_kms,
771fe6b9
JG		 525 .get_vblank_counter = radeon_get_vblank_counter_kms,
526 .enable_vblank = radeon_enable_vblank_kms,
527 .disable_vblank = radeon_disable_vblank_kms,
f5a80209
MK		 528 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
529 .get_scanout_position = radeon_get_crtc_scanoutpos,
771fe6b9
JG		 530#if defined(CONFIG_DEBUG_FS)
531 .debugfs_init = radeon_debugfs_init,
532 .debugfs_cleanup = radeon_debugfs_cleanup,
533#endif
534 .irq_preinstall = radeon_driver_irq_preinstall_kms,
535 .irq_postinstall = radeon_driver_irq_postinstall_kms,
536 .irq_uninstall = radeon_driver_irq_uninstall_kms,
537 .irq_handler = radeon_driver_irq_handler_kms,
771fe6b9 538 .ioctls = radeon_ioctls_kms,
771fe6b9 539 .gem_free_object = radeon_gem_object_free,
721604a1
JG		 540 .gem_open_object = radeon_gem_object_open,
541 .gem_close_object = radeon_gem_object_close,
ff72145b
DA		 542 .dumb_create = radeon_mode_dumb_create,
543 .dumb_map_offset = radeon_mode_dumb_mmap,
43387b37 544 .dumb_destroy = drm_gem_dumb_destroy,
e08e96de 545 .fops = &radeon_driver_kms_fops,
40f5cf99
AD		 546
547 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
548 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
f72a113a 549 .gem_prime_export = radeon_gem_prime_export,
1e6d17a5
AP		 550 .gem_prime_import = drm_gem_prime_import,
551 .gem_prime_pin = radeon_gem_prime_pin,
280cf211 552 .gem_prime_unpin = radeon_gem_prime_unpin,
3aac4502 553 .gem_prime_res_obj = radeon_gem_prime_res_obj,
1e6d17a5
AP		 554 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
555 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
556 .gem_prime_vmap = radeon_gem_prime_vmap,
557 .gem_prime_vunmap = radeon_gem_prime_vunmap,
40f5cf99 558
771fe6b9
JG		 559 .name = DRIVER_NAME,
560 .desc = DRIVER_DESC,
561 .date = DRIVER_DATE,
562 .major = KMS_DRIVER_MAJOR,
563 .minor = KMS_DRIVER_MINOR,
564 .patchlevel = KMS_DRIVER_PATCHLEVEL,
565};
771fe6b9
JG		 566
567static struct drm_driver *driver;
8410ea3b
DA		 568static struct pci_driver *pdriver;
569
8410ea3b
DA		 570static struct pci_driver radeon_kms_pci_driver = {
571 .name = DRIVER_NAME,
572 .id_table = pciidlist,
573 .probe = radeon_pci_probe,
574 .remove = radeon_pci_remove,
7473e830 575 .driver.pm = &radeon_pm_ops,
8410ea3b 576};
771fe6b9 577
1da177e4
LT		 578static int __init radeon_init(void)
579{
e9ced8e0
DA		 580 if (vgacon_text_force() && radeon_modeset == -1) {
581 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
582 radeon_modeset = 0;
583 }
e9ced8e0
DA		 584 /* set to modesetting by default if not nomodeset */
585 if (radeon_modeset == -1)
586 radeon_modeset = 1;
587
771fe6b9
JG		 588 if (radeon_modeset == 1) {
589 DRM_INFO("radeon kernel modesetting enabled.\n");
590 driver = &kms_driver;
8410ea3b 591 pdriver = &radeon_kms_pci_driver;
771fe6b9
JG		 592 driver->driver_features |= DRIVER_MODESET;
593 driver->num_ioctls = radeon_max_kms_ioctl;
6a9ee8af 594 radeon_register_atpx_handler();
14adc892
CK		 595
596 } else {
14adc892
CK		 597 DRM_ERROR("No UMS support in radeon module!\n");
598 return -EINVAL;
771fe6b9 599 }
14adc892
CK		 600
601 /* let modprobe override vga console setting */
8410ea3b 602 return drm_pci_init(driver, pdriver);
1da177e4
LT		 603}
604
605static void __exit radeon_exit(void)
606{
e28740ec 607 radeon_kfd_fini();
8410ea3b 608 drm_pci_exit(driver, pdriver);
6a9ee8af 609 radeon_unregister_atpx_handler();
1da177e4
LT		 610}
611
176f613e 612module_init(radeon_init);
1da177e4
LT		 613module_exit(radeon_exit);
614
b5e89ed5
DA		 615MODULE_AUTHOR(DRIVER_AUTHOR);
616MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 617MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)