Commit | Line | Data |
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1da177e4 LT |
1 | /** |
2 | * \file radeon_drv.c | |
3 | * ATI Radeon driver | |
4 | * | |
5 | * \author Gareth Hughes <gareth@valinux.com> | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
10 | * All Rights Reserved. | |
11 | * | |
12 | * Permission is hereby granted, free of charge, to any person obtaining a | |
13 | * copy of this software and associated documentation files (the "Software"), | |
14 | * to deal in the Software without restriction, including without limitation | |
15 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
16 | * and/or sell copies of the Software, and to permit persons to whom the | |
17 | * Software is furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice (including the next | |
20 | * paragraph) shall be included in all copies or substantial portions of the | |
21 | * Software. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
24 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
25 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
26 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
27 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
28 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
29 | * OTHER DEALINGS IN THE SOFTWARE. | |
30 | */ | |
31 | ||
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/radeon_drm.h> | |
1da177e4 LT |
34 | #include "radeon_drv.h" |
35 | ||
760285e7 | 36 | #include <drm/drm_pciids.h> |
771fe6b9 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
10ebc0bc DA |
39 | #include <linux/pm_runtime.h> |
40 | #include <linux/vga_switcheroo.h> | |
d9fc9413 | 41 | #include <drm/drm_gem.h> |
44adece5 | 42 | #include <drm/drm_fb_helper.h> |
d9fc9413 | 43 | |
10ebc0bc | 44 | #include "drm_crtc_helper.h" |
e28740ec OG |
45 | #include "radeon_kfd.h" |
46 | ||
771fe6b9 JG |
47 | /* |
48 | * KMS wrapper. | |
0de1a57b DA |
49 | * - 2.0.0 - initial interface |
50 | * - 2.1.0 - add square tiling interface | |
fdb43528 | 51 | * - 2.2.0 - add r6xx/r7xx const buffer support |
cae94b0a | 52 | * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs |
bc35afdb | 53 | * - 2.4.0 - add crtc id query |
148a03bc | 54 | * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen |
ab9e1f59 | 55 | * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) |
71901cc4 | 56 | * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs |
58bbf018 | 57 | * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query |
486af189 | 58 | * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query |
b8709894 AD |
59 | * 2.10.0 - fusion 2D tiling |
60 | * 2.11.0 - backend map, initial compute support for the CS checker | |
e70f224c | 61 | * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS |
dd220a00 | 62 | * 2.13.0 - virtual memory support, streamout |
285484e2 | 63 | * 2.14.0 - add evergreen tiling informations |
609c1e15 | 64 | * 2.15.0 - add max_pipes query |
d2609875 | 65 | * 2.16.0 - fix evergreen 2D tiled surface calculation |
7c77bf2a | 66 | * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx |
0f457e48 | 67 | * 2.18.0 - r600-eg: allow "invalid" DB formats |
b51ad12a | 68 | * 2.19.0 - r600-eg: MSAA textures |
6759a0a7 | 69 | * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query |
c116cc94 | 70 | * 2.21.0 - r600-r700: FMASK and CMASK |
523885de | 71 | * 2.22.0 - r600 only: RESOLVE_BOX allowed |
46fc8781 | 72 | * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 |
61051afd | 73 | * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures |
71bfe916 | 74 | * 2.25.0 - eg+: new info request for num SE and num SH |
4ac0533a | 75 | * 2.26.0 - r600-eg: fix htile size computation |
8696e33f | 76 | * 2.27.0 - r600-SI: Add CS ioctl support for async DMA |
4613ca14 | 77 | * 2.28.0 - r600-eg: Add MEM_WRITE packet support |
c18b1170 | 78 | * 2.29.0 - R500 FP16 color clear registers |
774c389f | 79 | * 2.30.0 - fix for FMASK texturing |
a0a53aa8 | 80 | * 2.31.0 - Add fastfb support for rs690 |
902aaef6 | 81 | * 2.32.0 - new info request for rings working |
64d7b8be | 82 | * 2.33.0 - Add SI tiling mode array query |
39aee490 | 83 | * 2.34.0 - Add CIK tiling mode array query |
32f79a8a | 84 | * 2.35.0 - Add CIK macrotile mode array query |
9482d0d3 | 85 | * 2.36.0 - Fix CIK DCE tiling setup |
7c4c62a0 | 86 | * 2.37.0 - allow GS ring setup on r6xx/r7xx |
020ff546 MO |
87 | * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), |
88 | * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG | |
65fcf668 | 89 | * 2.39.0 - Add INFO query for number of active CUs |
72a9987e | 90 | * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting |
897eba82 | 91 | * CS to GPU on >= r600 |
16613743 | 92 | * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support |
1957d6be | 93 | * 2.42.0 - Add VCE/VUI (Video Usability Information) support |
72b9076b | 94 | * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER |
8c4f2bbd | 95 | * 2.44.0 - SET_APPEND_CNT packet3 support |
3d02b7fe | 96 | * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI |
662ce7bc | 97 | * 2.46.0 - Add PFP_SYNC_ME support on evergreen |
4d6bdbad | 98 | * 2.47.0 - Add UVD_NO_OP register support |
771fe6b9 JG |
99 | */ |
100 | #define KMS_DRIVER_MAJOR 2 | |
4d6bdbad | 101 | #define KMS_DRIVER_MINOR 47 |
771fe6b9 JG |
102 | #define KMS_DRIVER_PATCHLEVEL 0 |
103 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); | |
104 | int radeon_driver_unload_kms(struct drm_device *dev); | |
771fe6b9 JG |
105 | void radeon_driver_lastclose_kms(struct drm_device *dev); |
106 | int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); | |
107 | void radeon_driver_postclose_kms(struct drm_device *dev, | |
108 | struct drm_file *file_priv); | |
109 | void radeon_driver_preclose_kms(struct drm_device *dev, | |
110 | struct drm_file *file_priv); | |
274ad65c JG |
111 | int radeon_suspend_kms(struct drm_device *dev, bool suspend, |
112 | bool fbcon, bool freeze); | |
10ebc0bc | 113 | int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); |
88e72717 TR |
114 | u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); |
115 | int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); | |
116 | void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); | |
117 | int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, | |
f5a80209 MK |
118 | int *max_error, |
119 | struct timeval *vblank_time, | |
120 | unsigned flags); | |
771fe6b9 JG |
121 | void radeon_driver_irq_preinstall_kms(struct drm_device *dev); |
122 | int radeon_driver_irq_postinstall_kms(struct drm_device *dev); | |
123 | void radeon_driver_irq_uninstall_kms(struct drm_device *dev); | |
e9f0d76f | 124 | irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); |
771fe6b9 | 125 | void radeon_gem_object_free(struct drm_gem_object *obj); |
721604a1 JG |
126 | int radeon_gem_object_open(struct drm_gem_object *obj, |
127 | struct drm_file *file_priv); | |
128 | void radeon_gem_object_close(struct drm_gem_object *obj, | |
129 | struct drm_file *file_priv); | |
f72a113a CK |
130 | struct dma_buf *radeon_gem_prime_export(struct drm_device *dev, |
131 | struct drm_gem_object *gobj, | |
132 | int flags); | |
88e72717 TR |
133 | extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, |
134 | unsigned int flags, int *vpos, int *hpos, | |
3bb403bf VS |
135 | ktime_t *stime, ktime_t *etime, |
136 | const struct drm_display_mode *mode); | |
90c4cde9 | 137 | extern bool radeon_is_px(struct drm_device *dev); |
baa70943 | 138 | extern const struct drm_ioctl_desc radeon_ioctls_kms[]; |
771fe6b9 JG |
139 | extern int radeon_max_kms_ioctl; |
140 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma); | |
ff72145b DA |
141 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
142 | struct drm_device *dev, | |
143 | uint32_t handle, uint64_t *offset_p); | |
144 | int radeon_mode_dumb_create(struct drm_file *file_priv, | |
145 | struct drm_device *dev, | |
146 | struct drm_mode_create_dumb *args); | |
1e6d17a5 AP |
147 | struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); |
148 | struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, | |
b5e9c1a2 | 149 | struct dma_buf_attachment *, |
1e6d17a5 AP |
150 | struct sg_table *sg); |
151 | int radeon_gem_prime_pin(struct drm_gem_object *obj); | |
280cf211 | 152 | void radeon_gem_prime_unpin(struct drm_gem_object *obj); |
3aac4502 | 153 | struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *); |
1e6d17a5 AP |
154 | void *radeon_gem_prime_vmap(struct drm_gem_object *obj); |
155 | void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); | |
14adc892 CK |
156 | extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, |
157 | unsigned long arg); | |
ff72145b | 158 | |
14adc892 CK |
159 | /* atpx handler */ |
160 | #if defined(CONFIG_VGA_SWITCHEROO) | |
161 | void radeon_register_atpx_handler(void); | |
162 | void radeon_unregister_atpx_handler(void); | |
e1052b35 | 163 | bool radeon_has_atpx_dgpu_power_cntl(void); |
b8c9fd5a | 164 | bool radeon_is_atpx_hybrid(void); |
14adc892 CK |
165 | #else |
166 | static inline void radeon_register_atpx_handler(void) {} | |
167 | static inline void radeon_unregister_atpx_handler(void) {} | |
e1052b35 | 168 | static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } |
b8c9fd5a | 169 | static inline bool radeon_is_atpx_hybrid(void) { return false; } |
14adc892 | 170 | #endif |
1da177e4 | 171 | |
689b9d74 | 172 | int radeon_no_wb; |
e9ced8e0 | 173 | int radeon_modeset = -1; |
771fe6b9 JG |
174 | int radeon_dynclks = -1; |
175 | int radeon_r4xx_atom = 0; | |
176 | int radeon_agpmode = 0; | |
177 | int radeon_vram_limit = 0; | |
edcd26e8 | 178 | int radeon_gart_size = -1; /* auto */ |
771fe6b9 | 179 | int radeon_benchmarking = 0; |
ecc0b326 | 180 | int radeon_testing = 0; |
771fe6b9 | 181 | int radeon_connector_table = 0; |
4ce001ab | 182 | int radeon_tv = 1; |
108dc8e8 | 183 | int radeon_audio = -1; |
f46c0120 | 184 | int radeon_disp_priority = 0; |
e2b0a8e1 | 185 | int radeon_hw_i2c = 0; |
197bbb3d | 186 | int radeon_pcie_gen2 = -1; |
a18cee15 | 187 | int radeon_msi = -1; |
3368ff0c | 188 | int radeon_lockup_timeout = 10000; |
a0a53aa8 | 189 | int radeon_fastfb = 0; |
da321c8a | 190 | int radeon_dpm = -1; |
1294d4a3 | 191 | int radeon_aspm = -1; |
10ebc0bc | 192 | int radeon_runtime_pm = -1; |
363eb0b4 | 193 | int radeon_hard_reset = 0; |
dfc230f9 CK |
194 | int radeon_vm_size = 8; |
195 | int radeon_vm_block_size = -1; | |
a624f429 | 196 | int radeon_deep_color = 0; |
39dc5454 | 197 | int radeon_use_pflipirq = 2; |
6e909f74 | 198 | int radeon_bapm = -1; |
bc13018b | 199 | int radeon_backlight = -1; |
875711f0 | 200 | int radeon_auxch = -1; |
9843ead0 | 201 | int radeon_mst = 0; |
f1a0a67a | 202 | int radeon_uvd = 1; |
fabb5935 | 203 | int radeon_vce = 1; |
689b9d74 | 204 | |
61a2d07d | 205 | MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); |
689b9d74 DA |
206 | module_param_named(no_wb, radeon_no_wb, int, 0444); |
207 | ||
771fe6b9 JG |
208 | MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); |
209 | module_param_named(modeset, radeon_modeset, int, 0400); | |
210 | ||
211 | MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); | |
212 | module_param_named(dynclks, radeon_dynclks, int, 0444); | |
213 | ||
214 | MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); | |
215 | module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); | |
216 | ||
8902e6f2 | 217 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); |
771fe6b9 JG |
218 | module_param_named(vramlimit, radeon_vram_limit, int, 0600); |
219 | ||
220 | MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); | |
221 | module_param_named(agpmode, radeon_agpmode, int, 0444); | |
222 | ||
edcd26e8 | 223 | MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); |
771fe6b9 JG |
224 | module_param_named(gartsize, radeon_gart_size, int, 0600); |
225 | ||
226 | MODULE_PARM_DESC(benchmark, "Run benchmark"); | |
227 | module_param_named(benchmark, radeon_benchmarking, int, 0444); | |
228 | ||
ecc0b326 MD |
229 | MODULE_PARM_DESC(test, "Run tests"); |
230 | module_param_named(test, radeon_testing, int, 0444); | |
231 | ||
771fe6b9 JG |
232 | MODULE_PARM_DESC(connector_table, "Force connector table"); |
233 | module_param_named(connector_table, radeon_connector_table, int, 0444); | |
4ce001ab DA |
234 | |
235 | MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); | |
236 | module_param_named(tv, radeon_tv, int, 0444); | |
771fe6b9 | 237 | |
108dc8e8 | 238 | MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); |
dafc3bd5 CK |
239 | module_param_named(audio, radeon_audio, int, 0444); |
240 | ||
f46c0120 AD |
241 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); |
242 | module_param_named(disp_priority, radeon_disp_priority, int, 0444); | |
243 | ||
e2b0a8e1 AD |
244 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); |
245 | module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); | |
246 | ||
197bbb3d | 247 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); |
d42dd579 AD |
248 | module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); |
249 | ||
a18cee15 AD |
250 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); |
251 | module_param_named(msi, radeon_msi, int, 0444); | |
252 | ||
b5c9ecab | 253 | MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); |
3368ff0c CK |
254 | module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); |
255 | ||
a0a53aa8 SL |
256 | MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); |
257 | module_param_named(fastfb, radeon_fastfb, int, 0444); | |
258 | ||
da321c8a AD |
259 | MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); |
260 | module_param_named(dpm, radeon_dpm, int, 0444); | |
261 | ||
1294d4a3 AD |
262 | MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); |
263 | module_param_named(aspm, radeon_aspm, int, 0444); | |
264 | ||
10ebc0bc DA |
265 | MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); |
266 | module_param_named(runpm, radeon_runtime_pm, int, 0444); | |
267 | ||
363eb0b4 AD |
268 | MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); |
269 | module_param_named(hard_reset, radeon_hard_reset, int, 0444); | |
270 | ||
20b2656d | 271 | MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); |
c1c44132 CK |
272 | module_param_named(vm_size, radeon_vm_size, int, 0444); |
273 | ||
dfc230f9 | 274 | MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); |
4510fb98 CK |
275 | module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); |
276 | ||
a624f429 AD |
277 | MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); |
278 | module_param_named(deep_color, radeon_deep_color, int, 0444); | |
279 | ||
39dc5454 MK |
280 | MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); |
281 | module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); | |
282 | ||
6e909f74 AD |
283 | MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); |
284 | module_param_named(bapm, radeon_bapm, int, 0444); | |
285 | ||
bc13018b AD |
286 | MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); |
287 | module_param_named(backlight, radeon_backlight, int, 0444); | |
288 | ||
875711f0 DA |
289 | MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); |
290 | module_param_named(auxch, radeon_auxch, int, 0444); | |
291 | ||
9843ead0 DA |
292 | MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); |
293 | module_param_named(mst, radeon_mst, int, 0444); | |
294 | ||
f1a0a67a JG |
295 | MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); |
296 | module_param_named(uvd, radeon_uvd, int, 0444); | |
297 | ||
fabb5935 JG |
298 | MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); |
299 | module_param_named(vce, radeon_vce, int, 0444); | |
300 | ||
14adc892 CK |
301 | static struct pci_device_id pciidlist[] = { |
302 | radeon_PCI_IDS | |
303 | }; | |
304 | ||
305 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
306 | ||
771fe6b9 JG |
307 | static struct drm_driver kms_driver; |
308 | ||
a801abe4 AD |
309 | bool radeon_device_is_virtual(void); |
310 | ||
30238151 | 311 | static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) |
a56f7428 BH |
312 | { |
313 | struct apertures_struct *ap; | |
314 | bool primary = false; | |
315 | ||
316 | ap = alloc_apertures(1); | |
30238151 TR |
317 | if (!ap) |
318 | return -ENOMEM; | |
319 | ||
a56f7428 BH |
320 | ap->ranges[0].base = pci_resource_start(pdev, 0); |
321 | ap->ranges[0].size = pci_resource_len(pdev, 0); | |
322 | ||
323 | #ifdef CONFIG_X86 | |
324 | primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
325 | #endif | |
44adece5 | 326 | drm_fb_helper_remove_conflicting_framebuffers(ap, "radeondrmfb", primary); |
a56f7428 | 327 | kfree(ap); |
30238151 TR |
328 | |
329 | return 0; | |
a56f7428 BH |
330 | } |
331 | ||
56550d94 GKH |
332 | static int radeon_pci_probe(struct pci_dev *pdev, |
333 | const struct pci_device_id *ent) | |
771fe6b9 | 334 | { |
30238151 TR |
335 | int ret; |
336 | ||
412c8f7d OG |
337 | /* |
338 | * Initialize amdkfd before starting radeon. If it was not loaded yet, | |
339 | * defer radeon probing | |
340 | */ | |
341 | ret = radeon_kfd_init(); | |
342 | if (ret == -EPROBE_DEFER) | |
343 | return ret; | |
344 | ||
b00e5334 | 345 | if (vga_switcheroo_client_probe_defer(pdev)) |
14d20001 LW |
346 | return -EPROBE_DEFER; |
347 | ||
a56f7428 | 348 | /* Get rid of things like offb */ |
30238151 TR |
349 | ret = radeon_kick_out_firmware_fb(pdev); |
350 | if (ret) | |
351 | return ret; | |
a56f7428 | 352 | |
dcdb1674 | 353 | return drm_get_pci_dev(pdev, ent, &kms_driver); |
771fe6b9 JG |
354 | } |
355 | ||
356 | static void | |
357 | radeon_pci_remove(struct pci_dev *pdev) | |
358 | { | |
359 | struct drm_device *dev = pci_get_drvdata(pdev); | |
360 | ||
361 | drm_put_dev(dev); | |
362 | } | |
363 | ||
a801abe4 AD |
364 | static void |
365 | radeon_pci_shutdown(struct pci_dev *pdev) | |
366 | { | |
367 | /* if we are running in a VM, make sure the device | |
a481daa8 AD |
368 | * torn down properly on reboot/shutdown. |
369 | * unfortunately we can't detect certain | |
370 | * hypervisors so just do this all the time. | |
a801abe4 | 371 | */ |
a481daa8 | 372 | radeon_pci_remove(pdev); |
a801abe4 AD |
373 | } |
374 | ||
7473e830 | 375 | static int radeon_pmops_suspend(struct device *dev) |
771fe6b9 | 376 | { |
7473e830 DA |
377 | struct pci_dev *pdev = to_pci_dev(dev); |
378 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
274ad65c | 379 | return radeon_suspend_kms(drm_dev, true, true, false); |
771fe6b9 JG |
380 | } |
381 | ||
7473e830 | 382 | static int radeon_pmops_resume(struct device *dev) |
771fe6b9 | 383 | { |
7473e830 DA |
384 | struct pci_dev *pdev = to_pci_dev(dev); |
385 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
103917b3 AD |
386 | |
387 | /* GPU comes up enabled by the bios on resume */ | |
388 | if (radeon_is_px(drm_dev)) { | |
389 | pm_runtime_disable(dev); | |
390 | pm_runtime_set_active(dev); | |
391 | pm_runtime_enable(dev); | |
392 | } | |
393 | ||
10ebc0bc | 394 | return radeon_resume_kms(drm_dev, true, true); |
7473e830 DA |
395 | } |
396 | ||
397 | static int radeon_pmops_freeze(struct device *dev) | |
398 | { | |
399 | struct pci_dev *pdev = to_pci_dev(dev); | |
400 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
274ad65c | 401 | return radeon_suspend_kms(drm_dev, false, true, true); |
771fe6b9 JG |
402 | } |
403 | ||
7473e830 DA |
404 | static int radeon_pmops_thaw(struct device *dev) |
405 | { | |
406 | struct pci_dev *pdev = to_pci_dev(dev); | |
407 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
10ebc0bc DA |
408 | return radeon_resume_kms(drm_dev, false, true); |
409 | } | |
410 | ||
411 | static int radeon_pmops_runtime_suspend(struct device *dev) | |
412 | { | |
413 | struct pci_dev *pdev = to_pci_dev(dev); | |
414 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
415 | int ret; | |
416 | ||
90c4cde9 | 417 | if (!radeon_is_px(drm_dev)) { |
1d8eec8b DA |
418 | pm_runtime_forbid(dev); |
419 | return -EBUSY; | |
420 | } | |
9babd35a | 421 | |
10ebc0bc DA |
422 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
423 | drm_kms_helper_poll_disable(drm_dev); | |
424 | vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); | |
425 | ||
274ad65c | 426 | ret = radeon_suspend_kms(drm_dev, false, false, false); |
10ebc0bc DA |
427 | pci_save_state(pdev); |
428 | pci_disable_device(pdev); | |
b440bde7 | 429 | pci_ignore_hotplug(pdev); |
31764c1e AD |
430 | if (radeon_is_atpx_hybrid()) |
431 | pci_set_power_state(pdev, PCI_D3cold); | |
84919992 | 432 | else if (!radeon_has_atpx_dgpu_power_cntl()) |
f7ea4189 | 433 | pci_set_power_state(pdev, PCI_D3hot); |
10ebc0bc DA |
434 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
439 | static int radeon_pmops_runtime_resume(struct device *dev) | |
440 | { | |
441 | struct pci_dev *pdev = to_pci_dev(dev); | |
442 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
443 | int ret; | |
444 | ||
90c4cde9 | 445 | if (!radeon_is_px(drm_dev)) |
9babd35a AD |
446 | return -EINVAL; |
447 | ||
10ebc0bc DA |
448 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
449 | ||
84919992 AD |
450 | if (radeon_is_atpx_hybrid() || |
451 | !radeon_has_atpx_dgpu_power_cntl()) | |
452 | pci_set_power_state(pdev, PCI_D0); | |
10ebc0bc DA |
453 | pci_restore_state(pdev); |
454 | ret = pci_enable_device(pdev); | |
455 | if (ret) | |
456 | return ret; | |
457 | pci_set_master(pdev); | |
458 | ||
459 | ret = radeon_resume_kms(drm_dev, false, false); | |
460 | drm_kms_helper_poll_enable(drm_dev); | |
461 | vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); | |
462 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
463 | return 0; | |
464 | } | |
465 | ||
466 | static int radeon_pmops_runtime_idle(struct device *dev) | |
467 | { | |
468 | struct pci_dev *pdev = to_pci_dev(dev); | |
469 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
470 | struct drm_crtc *crtc; | |
471 | ||
90c4cde9 | 472 | if (!radeon_is_px(drm_dev)) { |
1d8eec8b | 473 | pm_runtime_forbid(dev); |
10ebc0bc DA |
474 | return -EBUSY; |
475 | } | |
476 | ||
477 | list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { | |
478 | if (crtc->enabled) { | |
479 | DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); | |
480 | return -EBUSY; | |
481 | } | |
482 | } | |
483 | ||
484 | pm_runtime_mark_last_busy(dev); | |
485 | pm_runtime_autosuspend(dev); | |
486 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ | |
487 | return 1; | |
488 | } | |
489 | ||
490 | long radeon_drm_ioctl(struct file *filp, | |
491 | unsigned int cmd, unsigned long arg) | |
492 | { | |
493 | struct drm_file *file_priv = filp->private_data; | |
494 | struct drm_device *dev; | |
495 | long ret; | |
496 | dev = file_priv->minor->dev; | |
497 | ret = pm_runtime_get_sync(dev->dev); | |
498 | if (ret < 0) | |
499 | return ret; | |
500 | ||
501 | ret = drm_ioctl(filp, cmd, arg); | |
502 | ||
503 | pm_runtime_mark_last_busy(dev->dev); | |
504 | pm_runtime_put_autosuspend(dev->dev); | |
505 | return ret; | |
7473e830 DA |
506 | } |
507 | ||
508 | static const struct dev_pm_ops radeon_pm_ops = { | |
509 | .suspend = radeon_pmops_suspend, | |
510 | .resume = radeon_pmops_resume, | |
511 | .freeze = radeon_pmops_freeze, | |
512 | .thaw = radeon_pmops_thaw, | |
513 | .poweroff = radeon_pmops_freeze, | |
514 | .restore = radeon_pmops_resume, | |
10ebc0bc DA |
515 | .runtime_suspend = radeon_pmops_runtime_suspend, |
516 | .runtime_resume = radeon_pmops_runtime_resume, | |
517 | .runtime_idle = radeon_pmops_runtime_idle, | |
7473e830 DA |
518 | }; |
519 | ||
e08e96de AV |
520 | static const struct file_operations radeon_driver_kms_fops = { |
521 | .owner = THIS_MODULE, | |
522 | .open = drm_open, | |
523 | .release = drm_release, | |
10ebc0bc | 524 | .unlocked_ioctl = radeon_drm_ioctl, |
e08e96de AV |
525 | .mmap = radeon_mmap, |
526 | .poll = drm_poll, | |
e08e96de AV |
527 | .read = drm_read, |
528 | #ifdef CONFIG_COMPAT | |
529 | .compat_ioctl = radeon_kms_compat_ioctl, | |
530 | #endif | |
531 | }; | |
532 | ||
771fe6b9 JG |
533 | static struct drm_driver kms_driver = { |
534 | .driver_features = | |
28185647 | 535 | DRIVER_USE_AGP | |
81e95697 | 536 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | |
f33bcab9 | 537 | DRIVER_PRIME | DRIVER_RENDER, |
771fe6b9 | 538 | .load = radeon_driver_load_kms, |
771fe6b9 JG |
539 | .open = radeon_driver_open_kms, |
540 | .preclose = radeon_driver_preclose_kms, | |
541 | .postclose = radeon_driver_postclose_kms, | |
542 | .lastclose = radeon_driver_lastclose_kms, | |
915b4d11 | 543 | .set_busid = drm_pci_set_busid, |
771fe6b9 | 544 | .unload = radeon_driver_unload_kms, |
771fe6b9 JG |
545 | .get_vblank_counter = radeon_get_vblank_counter_kms, |
546 | .enable_vblank = radeon_enable_vblank_kms, | |
547 | .disable_vblank = radeon_disable_vblank_kms, | |
f5a80209 MK |
548 | .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, |
549 | .get_scanout_position = radeon_get_crtc_scanoutpos, | |
771fe6b9 JG |
550 | .irq_preinstall = radeon_driver_irq_preinstall_kms, |
551 | .irq_postinstall = radeon_driver_irq_postinstall_kms, | |
552 | .irq_uninstall = radeon_driver_irq_uninstall_kms, | |
553 | .irq_handler = radeon_driver_irq_handler_kms, | |
771fe6b9 | 554 | .ioctls = radeon_ioctls_kms, |
71cbf451 | 555 | .gem_free_object_unlocked = radeon_gem_object_free, |
721604a1 JG |
556 | .gem_open_object = radeon_gem_object_open, |
557 | .gem_close_object = radeon_gem_object_close, | |
ff72145b DA |
558 | .dumb_create = radeon_mode_dumb_create, |
559 | .dumb_map_offset = radeon_mode_dumb_mmap, | |
43387b37 | 560 | .dumb_destroy = drm_gem_dumb_destroy, |
e08e96de | 561 | .fops = &radeon_driver_kms_fops, |
40f5cf99 AD |
562 | |
563 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
564 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
f72a113a | 565 | .gem_prime_export = radeon_gem_prime_export, |
1e6d17a5 AP |
566 | .gem_prime_import = drm_gem_prime_import, |
567 | .gem_prime_pin = radeon_gem_prime_pin, | |
280cf211 | 568 | .gem_prime_unpin = radeon_gem_prime_unpin, |
3aac4502 | 569 | .gem_prime_res_obj = radeon_gem_prime_res_obj, |
1e6d17a5 AP |
570 | .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, |
571 | .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, | |
572 | .gem_prime_vmap = radeon_gem_prime_vmap, | |
573 | .gem_prime_vunmap = radeon_gem_prime_vunmap, | |
40f5cf99 | 574 | |
771fe6b9 JG |
575 | .name = DRIVER_NAME, |
576 | .desc = DRIVER_DESC, | |
577 | .date = DRIVER_DATE, | |
578 | .major = KMS_DRIVER_MAJOR, | |
579 | .minor = KMS_DRIVER_MINOR, | |
580 | .patchlevel = KMS_DRIVER_PATCHLEVEL, | |
581 | }; | |
771fe6b9 JG |
582 | |
583 | static struct drm_driver *driver; | |
8410ea3b DA |
584 | static struct pci_driver *pdriver; |
585 | ||
8410ea3b DA |
586 | static struct pci_driver radeon_kms_pci_driver = { |
587 | .name = DRIVER_NAME, | |
588 | .id_table = pciidlist, | |
589 | .probe = radeon_pci_probe, | |
590 | .remove = radeon_pci_remove, | |
a801abe4 | 591 | .shutdown = radeon_pci_shutdown, |
7473e830 | 592 | .driver.pm = &radeon_pm_ops, |
8410ea3b | 593 | }; |
771fe6b9 | 594 | |
1da177e4 LT |
595 | static int __init radeon_init(void) |
596 | { | |
e9ced8e0 DA |
597 | if (vgacon_text_force() && radeon_modeset == -1) { |
598 | DRM_INFO("VGACON disable radeon kernel modesetting.\n"); | |
599 | radeon_modeset = 0; | |
600 | } | |
e9ced8e0 DA |
601 | /* set to modesetting by default if not nomodeset */ |
602 | if (radeon_modeset == -1) | |
603 | radeon_modeset = 1; | |
604 | ||
771fe6b9 JG |
605 | if (radeon_modeset == 1) { |
606 | DRM_INFO("radeon kernel modesetting enabled.\n"); | |
607 | driver = &kms_driver; | |
8410ea3b | 608 | pdriver = &radeon_kms_pci_driver; |
771fe6b9 JG |
609 | driver->driver_features |= DRIVER_MODESET; |
610 | driver->num_ioctls = radeon_max_kms_ioctl; | |
6a9ee8af | 611 | radeon_register_atpx_handler(); |
14adc892 CK |
612 | |
613 | } else { | |
14adc892 CK |
614 | DRM_ERROR("No UMS support in radeon module!\n"); |
615 | return -EINVAL; | |
771fe6b9 | 616 | } |
14adc892 CK |
617 | |
618 | /* let modprobe override vga console setting */ | |
8410ea3b | 619 | return drm_pci_init(driver, pdriver); |
1da177e4 LT |
620 | } |
621 | ||
622 | static void __exit radeon_exit(void) | |
623 | { | |
e28740ec | 624 | radeon_kfd_fini(); |
8410ea3b | 625 | drm_pci_exit(driver, pdriver); |
6a9ee8af | 626 | radeon_unregister_atpx_handler(); |
1da177e4 LT |
627 | } |
628 | ||
176f613e | 629 | module_init(radeon_init); |
1da177e4 LT |
630 | module_exit(radeon_exit); |
631 | ||
b5e89ed5 DA |
632 | MODULE_AUTHOR(DRIVER_AUTHOR); |
633 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 634 | MODULE_LICENSE("GPL and additional rights"); |