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Merge tag 'v4.0-rc7' into drm-next
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
1da177e4
LT		 1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
1da177e4
LT		 34#include "radeon_drv.h"
35
760285e7 36#include <drm/drm_pciids.h>
771fe6b9 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
10ebc0bc
DA		 39#include <linux/pm_runtime.h>
40#include <linux/vga_switcheroo.h>
d9fc9413
DV		 41#include <drm/drm_gem.h>
42
10ebc0bc 43#include "drm_crtc_helper.h"
e28740ec
OG		 44#include "radeon_kfd.h"
45
771fe6b9
JG		 46/*
47 * KMS wrapper.
0de1a57b
DA		 48 * - 2.0.0 - initial interface
49 * - 2.1.0 - add square tiling interface
fdb43528 50 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 51 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 52 * - 2.4.0 - add crtc id query
148a03bc 53 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 54 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 55 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 56 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 57 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD		 58 * 2.10.0 - fusion 2D tiling
59 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 60 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 61 * 2.13.0 - virtual memory support, streamout
285484e2 62 * 2.14.0 - add evergreen tiling informations
609c1e15 63 * 2.15.0 - add max_pipes query
d2609875 64 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 65 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 66 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 67 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 68 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 69 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 70 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 71 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 72 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 73 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 74 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 75 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 76 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 77 * 2.29.0 - R500 FP16 color clear registers
774c389f 78 * 2.30.0 - fix for FMASK texturing
a0a53aa8 79 * 2.31.0 - Add fastfb support for rs690
902aaef6 80 * 2.32.0 - new info request for rings working
64d7b8be 81 * 2.33.0 - Add SI tiling mode array query
39aee490 82 * 2.34.0 - Add CIK tiling mode array query
32f79a8a 83 * 2.35.0 - Add CIK macrotile mode array query
9482d0d3 84 * 2.36.0 - Fix CIK DCE tiling setup
7c4c62a0 85 * 2.37.0 - allow GS ring setup on r6xx/r7xx
020ff546
MO		 86 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
87 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
65fcf668 88 * 2.39.0 - Add INFO query for number of active CUs
72a9987e 89 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
897eba82 90 * CS to GPU on >= r600
16613743 91 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
771fe6b9
JG		 92 */
93#define KMS_DRIVER_MAJOR 2
16613743 94#define KMS_DRIVER_MINOR 41
771fe6b9
JG		 95#define KMS_DRIVER_PATCHLEVEL 0
96int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
97int radeon_driver_unload_kms(struct drm_device *dev);
771fe6b9
JG		 98void radeon_driver_lastclose_kms(struct drm_device *dev);
99int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
100void radeon_driver_postclose_kms(struct drm_device *dev,
101 struct drm_file *file_priv);
102void radeon_driver_preclose_kms(struct drm_device *dev,
103 struct drm_file *file_priv);
10ebc0bc
DA		 104int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
105int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
771fe6b9
JG		 106u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
107int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
108void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
f5a80209
MK		 109int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
110 int *max_error,
111 struct timeval *vblank_time,
112 unsigned flags);
771fe6b9
JG		 113void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
114int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
115void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
e9f0d76f 116irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
771fe6b9 117void radeon_gem_object_free(struct drm_gem_object *obj);
721604a1
JG		 118int radeon_gem_object_open(struct drm_gem_object *obj,
119 struct drm_file *file_priv);
120void radeon_gem_object_close(struct drm_gem_object *obj,
121 struct drm_file *file_priv);
f72a113a
CK		 122struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
123 struct drm_gem_object *gobj,
124 int flags);
f5a80209 125extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
abca9e45 126 unsigned int flags,
d47abc58
MK		 127 int *vpos, int *hpos, ktime_t *stime,
128 ktime_t *etime);
90c4cde9 129extern bool radeon_is_px(struct drm_device *dev);
baa70943 130extern const struct drm_ioctl_desc radeon_ioctls_kms[];
771fe6b9
JG		 131extern int radeon_max_kms_ioctl;
132int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
ff72145b
DA		 133int radeon_mode_dumb_mmap(struct drm_file *filp,
134 struct drm_device *dev,
135 uint32_t handle, uint64_t *offset_p);
136int radeon_mode_dumb_create(struct drm_file *file_priv,
137 struct drm_device *dev,
138 struct drm_mode_create_dumb *args);
1e6d17a5
AP		 139struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
140struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
b5e9c1a2 141 struct dma_buf_attachment *,
1e6d17a5
AP		 142 struct sg_table *sg);
143int radeon_gem_prime_pin(struct drm_gem_object *obj);
280cf211 144void radeon_gem_prime_unpin(struct drm_gem_object *obj);
3aac4502 145struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
1e6d17a5
AP		 146void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
147void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
14adc892
CK		 148extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
149 unsigned long arg);
ff72145b 150
771fe6b9
JG		 151#if defined(CONFIG_DEBUG_FS)
152int radeon_debugfs_init(struct drm_minor *minor);
153void radeon_debugfs_cleanup(struct drm_minor *minor);
154#endif
771fe6b9 155
14adc892
CK		 156/* atpx handler */
157#if defined(CONFIG_VGA_SWITCHEROO)
158void radeon_register_atpx_handler(void);
159void radeon_unregister_atpx_handler(void);
160#else
161static inline void radeon_register_atpx_handler(void) {}
162static inline void radeon_unregister_atpx_handler(void) {}
163#endif
1da177e4 164
689b9d74 165int radeon_no_wb;
e9ced8e0 166int radeon_modeset = -1;
771fe6b9
JG		 167int radeon_dynclks = -1;
168int radeon_r4xx_atom = 0;
169int radeon_agpmode = 0;
170int radeon_vram_limit = 0;
edcd26e8 171int radeon_gart_size = -1; /* auto */
771fe6b9 172int radeon_benchmarking = 0;
ecc0b326 173int radeon_testing = 0;
771fe6b9 174int radeon_connector_table = 0;
4ce001ab 175int radeon_tv = 1;
108dc8e8 176int radeon_audio = -1;
f46c0120 177int radeon_disp_priority = 0;
e2b0a8e1 178int radeon_hw_i2c = 0;
197bbb3d 179int radeon_pcie_gen2 = -1;
a18cee15 180int radeon_msi = -1;
3368ff0c 181int radeon_lockup_timeout = 10000;
a0a53aa8 182int radeon_fastfb = 0;
da321c8a 183int radeon_dpm = -1;
1294d4a3 184int radeon_aspm = -1;
10ebc0bc 185int radeon_runtime_pm = -1;
363eb0b4 186int radeon_hard_reset = 0;
dfc230f9
CK		 187int radeon_vm_size = 8;
188int radeon_vm_block_size = -1;
a624f429 189int radeon_deep_color = 0;
39dc5454 190int radeon_use_pflipirq = 2;
6e909f74 191int radeon_bapm = -1;
bc13018b 192int radeon_backlight = -1;
875711f0 193int radeon_auxch = -1;
9843ead0 194int radeon_mst = 0;
689b9d74 195
61a2d07d 196MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA		 197module_param_named(no_wb, radeon_no_wb, int, 0444);
198
771fe6b9
JG		 199MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
200module_param_named(modeset, radeon_modeset, int, 0400);
201
202MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
203module_param_named(dynclks, radeon_dynclks, int, 0444);
204
205MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
206module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
207
8902e6f2 208MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
771fe6b9
JG		 209module_param_named(vramlimit, radeon_vram_limit, int, 0600);
210
211MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
212module_param_named(agpmode, radeon_agpmode, int, 0444);
213
edcd26e8 214MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
771fe6b9
JG		 215module_param_named(gartsize, radeon_gart_size, int, 0600);
216
217MODULE_PARM_DESC(benchmark, "Run benchmark");
218module_param_named(benchmark, radeon_benchmarking, int, 0444);
219
ecc0b326
MD		 220MODULE_PARM_DESC(test, "Run tests");
221module_param_named(test, radeon_testing, int, 0444);
222
771fe6b9
JG		 223MODULE_PARM_DESC(connector_table, "Force connector table");
224module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA		 225
226MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
227module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 228
108dc8e8 229MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
dafc3bd5
CK		 230module_param_named(audio, radeon_audio, int, 0444);
231
f46c0120
AD		 232MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
233module_param_named(disp_priority, radeon_disp_priority, int, 0444);
234
e2b0a8e1
AD		 235MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
236module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
237
197bbb3d 238MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD		 239module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
240
a18cee15
AD		 241MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
242module_param_named(msi, radeon_msi, int, 0444);
243
b5c9ecab 244MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
3368ff0c
CK		 245module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
246
a0a53aa8
SL		 247MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
248module_param_named(fastfb, radeon_fastfb, int, 0444);
249
da321c8a
AD		 250MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
251module_param_named(dpm, radeon_dpm, int, 0444);
252
1294d4a3
AD		 253MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
254module_param_named(aspm, radeon_aspm, int, 0444);
255
10ebc0bc
DA		 256MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
257module_param_named(runpm, radeon_runtime_pm, int, 0444);
258
363eb0b4
AD		 259MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
260module_param_named(hard_reset, radeon_hard_reset, int, 0444);
261
20b2656d 262MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
c1c44132
CK		 263module_param_named(vm_size, radeon_vm_size, int, 0444);
264
dfc230f9 265MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
4510fb98
CK		 266module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
267
a624f429
AD		 268MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
269module_param_named(deep_color, radeon_deep_color, int, 0444);
270
39dc5454
MK		 271MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
272module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
273
6e909f74
AD		 274MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
275module_param_named(bapm, radeon_bapm, int, 0444);
276
bc13018b
AD		 277MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
278module_param_named(backlight, radeon_backlight, int, 0444);
279
875711f0
DA		 280MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
281module_param_named(auxch, radeon_auxch, int, 0444);
282
9843ead0
DA		 283MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
284module_param_named(mst, radeon_mst, int, 0444);
285
14adc892
CK		 286static struct pci_device_id pciidlist[] = {
287 radeon_PCI_IDS
288};
289
290MODULE_DEVICE_TABLE(pci, pciidlist);
291
292#ifdef CONFIG_DRM_RADEON_UMS
293
0a3e67a4
JB		 294static int radeon_suspend(struct drm_device *dev, pm_message_t state)
295{
296 drm_radeon_private_t *dev_priv = dev->dev_private;
297
03efb885
DA		 298 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
299 return 0;
300
0a3e67a4 301 /* Disable *all* interrupts */
800b6995 302 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
0a3e67a4
JB		 303 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
304 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
305 return 0;
306}
307
308static int radeon_resume(struct drm_device *dev)
309{
310 drm_radeon_private_t *dev_priv = dev->dev_private;
311
03efb885
DA		 312 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
313 return 0;
314
0a3e67a4 315 /* Restore interrupt registers */
800b6995 316 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
0a3e67a4
JB		 317 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
318 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
319 return 0;
320}
321
10ebc0bc 322
e08e96de
AV		 323static const struct file_operations radeon_driver_old_fops = {
324 .owner = THIS_MODULE,
325 .open = drm_open,
326 .release = drm_release,
327 .unlocked_ioctl = drm_ioctl,
bfbf3c85 328 .mmap = drm_legacy_mmap,
e08e96de 329 .poll = drm_poll,
e08e96de
AV		 330 .read = drm_read,
331#ifdef CONFIG_COMPAT
332 .compat_ioctl = radeon_compat_ioctl,
333#endif
334 .llseek = noop_llseek,
335};
336
771fe6b9 337static struct drm_driver driver_old = {
b5e89ed5 338 .driver_features =
28185647 339 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
0a3e67a4 340 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
1da177e4 341 .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
22eae947
DA		 342 .load = radeon_driver_load,
343 .firstopen = radeon_driver_firstopen,
344 .open = radeon_driver_open,
345 .preclose = radeon_driver_preclose,
346 .postclose = radeon_driver_postclose,
347 .lastclose = radeon_driver_lastclose,
915b4d11 348 .set_busid = drm_pci_set_busid,
22eae947 349 .unload = radeon_driver_unload,
0a3e67a4
JB		 350 .suspend = radeon_suspend,
351 .resume = radeon_resume,
352 .get_vblank_counter = radeon_get_vblank_counter,
353 .enable_vblank = radeon_enable_vblank,
354 .disable_vblank = radeon_disable_vblank,
60f2ee0b
DA		 355 .master_create = radeon_master_create,
356 .master_destroy = radeon_master_destroy,
1da177e4
LT		 357 .irq_preinstall = radeon_driver_irq_preinstall,
358 .irq_postinstall = radeon_driver_irq_postinstall,
359 .irq_uninstall = radeon_driver_irq_uninstall,
360 .irq_handler = radeon_driver_irq_handler,
1da177e4
LT		 361 .ioctls = radeon_ioctls,
362 .dma_ioctl = radeon_cp_buffers,
e08e96de 363 .fops = &radeon_driver_old_fops,
22eae947
DA		 364 .name = DRIVER_NAME,
365 .desc = DRIVER_DESC,
366 .date = DRIVER_DATE,
367 .major = DRIVER_MAJOR,
368 .minor = DRIVER_MINOR,
369 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT		 370};
371
14adc892
CK		 372#endif
373
771fe6b9
JG		 374static struct drm_driver kms_driver;
375
30238151 376static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
a56f7428
BH		 377{
378 struct apertures_struct *ap;
379 bool primary = false;
380
381 ap = alloc_apertures(1);
30238151
TR		 382 if (!ap)
383 return -ENOMEM;
384
a56f7428
BH		 385 ap->ranges[0].base = pci_resource_start(pdev, 0);
386 ap->ranges[0].size = pci_resource_len(pdev, 0);
387
388#ifdef CONFIG_X86
389 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
390#endif
391 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
392 kfree(ap);
30238151
TR		 393
394 return 0;
a56f7428
BH		 395}
396
56550d94
GKH		 397static int radeon_pci_probe(struct pci_dev *pdev,
398 const struct pci_device_id *ent)
771fe6b9 399{
30238151
TR		 400 int ret;
401
a56f7428 402 /* Get rid of things like offb */
30238151
TR		 403 ret = radeon_kick_out_firmware_fb(pdev);
404 if (ret)
405 return ret;
a56f7428 406
dcdb1674 407 return drm_get_pci_dev(pdev, ent, &kms_driver);
771fe6b9
JG		 408}
409
410static void
411radeon_pci_remove(struct pci_dev *pdev)
412{
413 struct drm_device *dev = pci_get_drvdata(pdev);
414
415 drm_put_dev(dev);
416}
417
7473e830 418static int radeon_pmops_suspend(struct device *dev)
771fe6b9 419{
7473e830
DA		 420 struct pci_dev *pdev = to_pci_dev(dev);
421 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 422 return radeon_suspend_kms(drm_dev, true, true);
771fe6b9
JG		 423}
424
7473e830 425static int radeon_pmops_resume(struct device *dev)
771fe6b9 426{
7473e830
DA		 427 struct pci_dev *pdev = to_pci_dev(dev);
428 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 429 return radeon_resume_kms(drm_dev, true, true);
7473e830
DA		 430}
431
432static int radeon_pmops_freeze(struct device *dev)
433{
434 struct pci_dev *pdev = to_pci_dev(dev);
435 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 436 return radeon_suspend_kms(drm_dev, false, true);
771fe6b9
JG		 437}
438
7473e830
DA		 439static int radeon_pmops_thaw(struct device *dev)
440{
441 struct pci_dev *pdev = to_pci_dev(dev);
442 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc
DA		 443 return radeon_resume_kms(drm_dev, false, true);
444}
445
446static int radeon_pmops_runtime_suspend(struct device *dev)
447{
448 struct pci_dev *pdev = to_pci_dev(dev);
449 struct drm_device *drm_dev = pci_get_drvdata(pdev);
450 int ret;
451
90c4cde9 452 if (!radeon_is_px(drm_dev)) {
1d8eec8b
DA		 453 pm_runtime_forbid(dev);
454 return -EBUSY;
455 }
9babd35a 456
10ebc0bc
DA		 457 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
458 drm_kms_helper_poll_disable(drm_dev);
459 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
460
461 ret = radeon_suspend_kms(drm_dev, false, false);
462 pci_save_state(pdev);
463 pci_disable_device(pdev);
b440bde7 464 pci_ignore_hotplug(pdev);
10ebc0bc
DA		 465 pci_set_power_state(pdev, PCI_D3cold);
466 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
467
468 return 0;
469}
470
471static int radeon_pmops_runtime_resume(struct device *dev)
472{
473 struct pci_dev *pdev = to_pci_dev(dev);
474 struct drm_device *drm_dev = pci_get_drvdata(pdev);
475 int ret;
476
90c4cde9 477 if (!radeon_is_px(drm_dev))
9babd35a
AD		 478 return -EINVAL;
479
10ebc0bc
DA		 480 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
481
482 pci_set_power_state(pdev, PCI_D0);
483 pci_restore_state(pdev);
484 ret = pci_enable_device(pdev);
485 if (ret)
486 return ret;
487 pci_set_master(pdev);
488
489 ret = radeon_resume_kms(drm_dev, false, false);
490 drm_kms_helper_poll_enable(drm_dev);
491 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
492 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
493 return 0;
494}
495
496static int radeon_pmops_runtime_idle(struct device *dev)
497{
498 struct pci_dev *pdev = to_pci_dev(dev);
499 struct drm_device *drm_dev = pci_get_drvdata(pdev);
500 struct drm_crtc *crtc;
501
90c4cde9 502 if (!radeon_is_px(drm_dev)) {
1d8eec8b 503 pm_runtime_forbid(dev);
10ebc0bc
DA		 504 return -EBUSY;
505 }
506
507 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
508 if (crtc->enabled) {
509 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
510 return -EBUSY;
511 }
512 }
513
514 pm_runtime_mark_last_busy(dev);
515 pm_runtime_autosuspend(dev);
516 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
517 return 1;
518}
519
520long radeon_drm_ioctl(struct file *filp,
521 unsigned int cmd, unsigned long arg)
522{
523 struct drm_file *file_priv = filp->private_data;
524 struct drm_device *dev;
525 long ret;
526 dev = file_priv->minor->dev;
527 ret = pm_runtime_get_sync(dev->dev);
528 if (ret < 0)
529 return ret;
530
531 ret = drm_ioctl(filp, cmd, arg);
532
533 pm_runtime_mark_last_busy(dev->dev);
534 pm_runtime_put_autosuspend(dev->dev);
535 return ret;
7473e830
DA		 536}
537
538static const struct dev_pm_ops radeon_pm_ops = {
539 .suspend = radeon_pmops_suspend,
540 .resume = radeon_pmops_resume,
541 .freeze = radeon_pmops_freeze,
542 .thaw = radeon_pmops_thaw,
543 .poweroff = radeon_pmops_freeze,
544 .restore = radeon_pmops_resume,
10ebc0bc
DA		 545 .runtime_suspend = radeon_pmops_runtime_suspend,
546 .runtime_resume = radeon_pmops_runtime_resume,
547 .runtime_idle = radeon_pmops_runtime_idle,
7473e830
DA		 548};
549
e08e96de
AV		 550static const struct file_operations radeon_driver_kms_fops = {
551 .owner = THIS_MODULE,
552 .open = drm_open,
553 .release = drm_release,
10ebc0bc 554 .unlocked_ioctl = radeon_drm_ioctl,
e08e96de
AV		 555 .mmap = radeon_mmap,
556 .poll = drm_poll,
e08e96de
AV		 557 .read = drm_read,
558#ifdef CONFIG_COMPAT
559 .compat_ioctl = radeon_kms_compat_ioctl,
560#endif
561};
562
771fe6b9
JG		 563static struct drm_driver kms_driver = {
564 .driver_features =
28185647 565 DRIVER_USE_AGP |
81e95697 566 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
f33bcab9 567 DRIVER_PRIME | DRIVER_RENDER,
771fe6b9 568 .load = radeon_driver_load_kms,
771fe6b9
JG		 569 .open = radeon_driver_open_kms,
570 .preclose = radeon_driver_preclose_kms,
571 .postclose = radeon_driver_postclose_kms,
572 .lastclose = radeon_driver_lastclose_kms,
915b4d11 573 .set_busid = drm_pci_set_busid,
771fe6b9 574 .unload = radeon_driver_unload_kms,
771fe6b9
JG		 575 .get_vblank_counter = radeon_get_vblank_counter_kms,
576 .enable_vblank = radeon_enable_vblank_kms,
577 .disable_vblank = radeon_disable_vblank_kms,
f5a80209
MK		 578 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
579 .get_scanout_position = radeon_get_crtc_scanoutpos,
771fe6b9
JG		 580#if defined(CONFIG_DEBUG_FS)
581 .debugfs_init = radeon_debugfs_init,
582 .debugfs_cleanup = radeon_debugfs_cleanup,
583#endif
584 .irq_preinstall = radeon_driver_irq_preinstall_kms,
585 .irq_postinstall = radeon_driver_irq_postinstall_kms,
586 .irq_uninstall = radeon_driver_irq_uninstall_kms,
587 .irq_handler = radeon_driver_irq_handler_kms,
771fe6b9 588 .ioctls = radeon_ioctls_kms,
771fe6b9 589 .gem_free_object = radeon_gem_object_free,
721604a1
JG		 590 .gem_open_object = radeon_gem_object_open,
591 .gem_close_object = radeon_gem_object_close,
ff72145b
DA		 592 .dumb_create = radeon_mode_dumb_create,
593 .dumb_map_offset = radeon_mode_dumb_mmap,
43387b37 594 .dumb_destroy = drm_gem_dumb_destroy,
e08e96de 595 .fops = &radeon_driver_kms_fops,
40f5cf99
AD		 596
597 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
598 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
f72a113a 599 .gem_prime_export = radeon_gem_prime_export,
1e6d17a5
AP		 600 .gem_prime_import = drm_gem_prime_import,
601 .gem_prime_pin = radeon_gem_prime_pin,
280cf211 602 .gem_prime_unpin = radeon_gem_prime_unpin,
3aac4502 603 .gem_prime_res_obj = radeon_gem_prime_res_obj,
1e6d17a5
AP		 604 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
605 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
606 .gem_prime_vmap = radeon_gem_prime_vmap,
607 .gem_prime_vunmap = radeon_gem_prime_vunmap,
40f5cf99 608
771fe6b9
JG		 609 .name = DRIVER_NAME,
610 .desc = DRIVER_DESC,
611 .date = DRIVER_DATE,
612 .major = KMS_DRIVER_MAJOR,
613 .minor = KMS_DRIVER_MINOR,
614 .patchlevel = KMS_DRIVER_PATCHLEVEL,
615};
771fe6b9
JG		 616
617static struct drm_driver *driver;
8410ea3b
DA		 618static struct pci_driver *pdriver;
619
14adc892 620#ifdef CONFIG_DRM_RADEON_UMS
8410ea3b
DA		 621static struct pci_driver radeon_pci_driver = {
622 .name = DRIVER_NAME,
623 .id_table = pciidlist,
624};
14adc892 625#endif
8410ea3b
DA		 626
627static struct pci_driver radeon_kms_pci_driver = {
628 .name = DRIVER_NAME,
629 .id_table = pciidlist,
630 .probe = radeon_pci_probe,
631 .remove = radeon_pci_remove,
7473e830 632 .driver.pm = &radeon_pm_ops,
8410ea3b 633};
771fe6b9 634
1da177e4
LT		 635static int __init radeon_init(void)
636{
e9ced8e0
DA		 637#ifdef CONFIG_VGA_CONSOLE
638 if (vgacon_text_force() && radeon_modeset == -1) {
639 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
640 radeon_modeset = 0;
641 }
642#endif
643 /* set to modesetting by default if not nomodeset */
644 if (radeon_modeset == -1)
645 radeon_modeset = 1;
646
771fe6b9
JG		 647 if (radeon_modeset == 1) {
648 DRM_INFO("radeon kernel modesetting enabled.\n");
649 driver = &kms_driver;
8410ea3b 650 pdriver = &radeon_kms_pci_driver;
771fe6b9
JG		 651 driver->driver_features |= DRIVER_MODESET;
652 driver->num_ioctls = radeon_max_kms_ioctl;
6a9ee8af 653 radeon_register_atpx_handler();
14adc892
CK		 654
655 } else {
656#ifdef CONFIG_DRM_RADEON_UMS
657 DRM_INFO("radeon userspace modesetting enabled.\n");
658 driver = &driver_old;
659 pdriver = &radeon_pci_driver;
660 driver->driver_features &= ~DRIVER_MODESET;
661 driver->num_ioctls = radeon_max_ioctl;
662#else
663 DRM_ERROR("No UMS support in radeon module!\n");
664 return -EINVAL;
665#endif
771fe6b9 666 }
14adc892 667
e28740ec
OG		 668 radeon_kfd_init();
669
14adc892 670 /* let modprobe override vga console setting */
8410ea3b 671 return drm_pci_init(driver, pdriver);
1da177e4
LT		 672}
673
674static void __exit radeon_exit(void)
675{
e28740ec 676 radeon_kfd_fini();
8410ea3b 677 drm_pci_exit(driver, pdriver);
6a9ee8af 678 radeon_unregister_atpx_handler();
1da177e4
LT		 679}
680
176f613e 681module_init(radeon_init);
1da177e4
LT		 682module_exit(radeon_exit);
683
b5e89ed5
DA		 684MODULE_AUTHOR(DRIVER_AUTHOR);
685MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 686MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)