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drm/radeon: set runtime pm state to active on resume
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
1da177e4
LT		 1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
1da177e4
LT		 34#include "radeon_drv.h"
35
760285e7 36#include <drm/drm_pciids.h>
771fe6b9 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
10ebc0bc
DA		 39#include <linux/pm_runtime.h>
40#include <linux/vga_switcheroo.h>
d9fc9413
DV		 41#include <drm/drm_gem.h>
42
10ebc0bc 43#include "drm_crtc_helper.h"
e28740ec
OG		 44#include "radeon_kfd.h"
45
771fe6b9
JG		 46/*
47 * KMS wrapper.
0de1a57b
DA		 48 * - 2.0.0 - initial interface
49 * - 2.1.0 - add square tiling interface
fdb43528 50 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 51 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 52 * - 2.4.0 - add crtc id query
148a03bc 53 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 54 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 55 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 56 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 57 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD		 58 * 2.10.0 - fusion 2D tiling
59 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 60 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 61 * 2.13.0 - virtual memory support, streamout
285484e2 62 * 2.14.0 - add evergreen tiling informations
609c1e15 63 * 2.15.0 - add max_pipes query
d2609875 64 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 65 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 66 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 67 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 68 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 69 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 70 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 71 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 72 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 73 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 74 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 75 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 76 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 77 * 2.29.0 - R500 FP16 color clear registers
774c389f 78 * 2.30.0 - fix for FMASK texturing
a0a53aa8 79 * 2.31.0 - Add fastfb support for rs690
902aaef6 80 * 2.32.0 - new info request for rings working
64d7b8be 81 * 2.33.0 - Add SI tiling mode array query
39aee490 82 * 2.34.0 - Add CIK tiling mode array query
32f79a8a 83 * 2.35.0 - Add CIK macrotile mode array query
9482d0d3 84 * 2.36.0 - Fix CIK DCE tiling setup
7c4c62a0 85 * 2.37.0 - allow GS ring setup on r6xx/r7xx
020ff546
MO		 86 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
87 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
65fcf668 88 * 2.39.0 - Add INFO query for number of active CUs
72a9987e 89 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
897eba82 90 * CS to GPU on >= r600
16613743 91 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
1957d6be 92 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
72b9076b 93 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
8c4f2bbd 94 * 2.44.0 - SET_APPEND_CNT packet3 support
3d02b7fe 95 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
662ce7bc 96 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
4d6bdbad 97 * 2.47.0 - Add UVD_NO_OP register support
771fe6b9
JG		 98 */
99#define KMS_DRIVER_MAJOR 2
4d6bdbad 100#define KMS_DRIVER_MINOR 47
771fe6b9
JG		 101#define KMS_DRIVER_PATCHLEVEL 0
102int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
103int radeon_driver_unload_kms(struct drm_device *dev);
771fe6b9
JG		 104void radeon_driver_lastclose_kms(struct drm_device *dev);
105int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
106void radeon_driver_postclose_kms(struct drm_device *dev,
107 struct drm_file *file_priv);
108void radeon_driver_preclose_kms(struct drm_device *dev,
109 struct drm_file *file_priv);
274ad65c
JG		 110int radeon_suspend_kms(struct drm_device *dev, bool suspend,
111 bool fbcon, bool freeze);
10ebc0bc 112int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 113u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
114int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
115void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
116int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
f5a80209
MK		 117 int *max_error,
118 struct timeval *vblank_time,
119 unsigned flags);
771fe6b9
JG		 120void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
121int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
122void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
e9f0d76f 123irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
771fe6b9 124void radeon_gem_object_free(struct drm_gem_object *obj);
721604a1
JG		 125int radeon_gem_object_open(struct drm_gem_object *obj,
126 struct drm_file *file_priv);
127void radeon_gem_object_close(struct drm_gem_object *obj,
128 struct drm_file *file_priv);
f72a113a
CK		 129struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
130 struct drm_gem_object *gobj,
131 int flags);
88e72717
TR		 132extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
133 unsigned int flags, int *vpos, int *hpos,
3bb403bf
VS		 134 ktime_t *stime, ktime_t *etime,
135 const struct drm_display_mode *mode);
90c4cde9 136extern bool radeon_is_px(struct drm_device *dev);
baa70943 137extern const struct drm_ioctl_desc radeon_ioctls_kms[];
771fe6b9
JG		 138extern int radeon_max_kms_ioctl;
139int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
ff72145b
DA		 140int radeon_mode_dumb_mmap(struct drm_file *filp,
141 struct drm_device *dev,
142 uint32_t handle, uint64_t *offset_p);
143int radeon_mode_dumb_create(struct drm_file *file_priv,
144 struct drm_device *dev,
145 struct drm_mode_create_dumb *args);
1e6d17a5
AP		 146struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
147struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
b5e9c1a2 148 struct dma_buf_attachment *,
1e6d17a5
AP		 149 struct sg_table *sg);
150int radeon_gem_prime_pin(struct drm_gem_object *obj);
280cf211 151void radeon_gem_prime_unpin(struct drm_gem_object *obj);
3aac4502 152struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
1e6d17a5
AP		 153void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
154void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
14adc892
CK		 155extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
156 unsigned long arg);
ff72145b 157
771fe6b9
JG		 158#if defined(CONFIG_DEBUG_FS)
159int radeon_debugfs_init(struct drm_minor *minor);
160void radeon_debugfs_cleanup(struct drm_minor *minor);
161#endif
771fe6b9 162
14adc892
CK		 163/* atpx handler */
164#if defined(CONFIG_VGA_SWITCHEROO)
165void radeon_register_atpx_handler(void);
166void radeon_unregister_atpx_handler(void);
e1052b35 167bool radeon_has_atpx_dgpu_power_cntl(void);
b8c9fd5a 168bool radeon_is_atpx_hybrid(void);
14adc892
CK		 169#else
170static inline void radeon_register_atpx_handler(void) {}
171static inline void radeon_unregister_atpx_handler(void) {}
e1052b35 172static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
b8c9fd5a 173static inline bool radeon_is_atpx_hybrid(void) { return false; }
14adc892 174#endif
1da177e4 175
689b9d74 176int radeon_no_wb;
e9ced8e0 177int radeon_modeset = -1;
771fe6b9
JG		 178int radeon_dynclks = -1;
179int radeon_r4xx_atom = 0;
180int radeon_agpmode = 0;
181int radeon_vram_limit = 0;
edcd26e8 182int radeon_gart_size = -1; /* auto */
771fe6b9 183int radeon_benchmarking = 0;
ecc0b326 184int radeon_testing = 0;
771fe6b9 185int radeon_connector_table = 0;
4ce001ab 186int radeon_tv = 1;
108dc8e8 187int radeon_audio = -1;
f46c0120 188int radeon_disp_priority = 0;
e2b0a8e1 189int radeon_hw_i2c = 0;
197bbb3d 190int radeon_pcie_gen2 = -1;
a18cee15 191int radeon_msi = -1;
3368ff0c 192int radeon_lockup_timeout = 10000;
a0a53aa8 193int radeon_fastfb = 0;
da321c8a 194int radeon_dpm = -1;
1294d4a3 195int radeon_aspm = -1;
10ebc0bc 196int radeon_runtime_pm = -1;
363eb0b4 197int radeon_hard_reset = 0;
dfc230f9
CK		 198int radeon_vm_size = 8;
199int radeon_vm_block_size = -1;
a624f429 200int radeon_deep_color = 0;
39dc5454 201int radeon_use_pflipirq = 2;
6e909f74 202int radeon_bapm = -1;
bc13018b 203int radeon_backlight = -1;
875711f0 204int radeon_auxch = -1;
9843ead0 205int radeon_mst = 0;
f1a0a67a 206int radeon_uvd = 1;
fabb5935 207int radeon_vce = 1;
689b9d74 208
61a2d07d 209MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA		 210module_param_named(no_wb, radeon_no_wb, int, 0444);
211
771fe6b9
JG		 212MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
213module_param_named(modeset, radeon_modeset, int, 0400);
214
215MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
216module_param_named(dynclks, radeon_dynclks, int, 0444);
217
218MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
219module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
220
8902e6f2 221MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
771fe6b9
JG		 222module_param_named(vramlimit, radeon_vram_limit, int, 0600);
223
224MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
225module_param_named(agpmode, radeon_agpmode, int, 0444);
226
edcd26e8 227MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
771fe6b9
JG		 228module_param_named(gartsize, radeon_gart_size, int, 0600);
229
230MODULE_PARM_DESC(benchmark, "Run benchmark");
231module_param_named(benchmark, radeon_benchmarking, int, 0444);
232
ecc0b326
MD		 233MODULE_PARM_DESC(test, "Run tests");
234module_param_named(test, radeon_testing, int, 0444);
235
771fe6b9
JG		 236MODULE_PARM_DESC(connector_table, "Force connector table");
237module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA		 238
239MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
240module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 241
108dc8e8 242MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
dafc3bd5
CK		 243module_param_named(audio, radeon_audio, int, 0444);
244
f46c0120
AD		 245MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
246module_param_named(disp_priority, radeon_disp_priority, int, 0444);
247
e2b0a8e1
AD		 248MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
249module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
250
197bbb3d 251MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD		 252module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
253
a18cee15
AD		 254MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
255module_param_named(msi, radeon_msi, int, 0444);
256
b5c9ecab 257MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
3368ff0c
CK		 258module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
259
a0a53aa8
SL		 260MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
261module_param_named(fastfb, radeon_fastfb, int, 0444);
262
da321c8a
AD		 263MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
264module_param_named(dpm, radeon_dpm, int, 0444);
265
1294d4a3
AD		 266MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
267module_param_named(aspm, radeon_aspm, int, 0444);
268
10ebc0bc
DA		 269MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
270module_param_named(runpm, radeon_runtime_pm, int, 0444);
271
363eb0b4
AD		 272MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
273module_param_named(hard_reset, radeon_hard_reset, int, 0444);
274
20b2656d 275MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
c1c44132
CK		 276module_param_named(vm_size, radeon_vm_size, int, 0444);
277
dfc230f9 278MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
4510fb98
CK		 279module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
280
a624f429
AD		 281MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
282module_param_named(deep_color, radeon_deep_color, int, 0444);
283
39dc5454
MK		 284MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
285module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
286
6e909f74
AD		 287MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
288module_param_named(bapm, radeon_bapm, int, 0444);
289
bc13018b
AD		 290MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
291module_param_named(backlight, radeon_backlight, int, 0444);
292
875711f0
DA		 293MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
294module_param_named(auxch, radeon_auxch, int, 0444);
295
9843ead0
DA		 296MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
297module_param_named(mst, radeon_mst, int, 0444);
298
f1a0a67a
JG		 299MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
300module_param_named(uvd, radeon_uvd, int, 0444);
301
fabb5935
JG		 302MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
303module_param_named(vce, radeon_vce, int, 0444);
304
14adc892
CK		 305static struct pci_device_id pciidlist[] = {
306 radeon_PCI_IDS
307};
308
309MODULE_DEVICE_TABLE(pci, pciidlist);
310
771fe6b9
JG		 311static struct drm_driver kms_driver;
312
30238151 313static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
a56f7428
BH		 314{
315 struct apertures_struct *ap;
316 bool primary = false;
317
318 ap = alloc_apertures(1);
30238151
TR		 319 if (!ap)
320 return -ENOMEM;
321
a56f7428
BH		 322 ap->ranges[0].base = pci_resource_start(pdev, 0);
323 ap->ranges[0].size = pci_resource_len(pdev, 0);
324
325#ifdef CONFIG_X86
326 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
327#endif
328 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
329 kfree(ap);
30238151
TR		 330
331 return 0;
a56f7428
BH		 332}
333
56550d94
GKH		 334static int radeon_pci_probe(struct pci_dev *pdev,
335 const struct pci_device_id *ent)
771fe6b9 336{
30238151
TR		 337 int ret;
338
412c8f7d
OG		 339 /*
340 * Initialize amdkfd before starting radeon. If it was not loaded yet,
341 * defer radeon probing
342 */
343 ret = radeon_kfd_init();
344 if (ret == -EPROBE_DEFER)
345 return ret;
346
b00e5334 347 if (vga_switcheroo_client_probe_defer(pdev))
14d20001
LW		 348 return -EPROBE_DEFER;
349
a56f7428 350 /* Get rid of things like offb */
30238151
TR		 351 ret = radeon_kick_out_firmware_fb(pdev);
352 if (ret)
353 return ret;
a56f7428 354
dcdb1674 355 return drm_get_pci_dev(pdev, ent, &kms_driver);
771fe6b9
JG		 356}
357
358static void
359radeon_pci_remove(struct pci_dev *pdev)
360{
361 struct drm_device *dev = pci_get_drvdata(pdev);
362
363 drm_put_dev(dev);
364}
365
7473e830 366static int radeon_pmops_suspend(struct device *dev)
771fe6b9 367{
7473e830
DA		 368 struct pci_dev *pdev = to_pci_dev(dev);
369 struct drm_device *drm_dev = pci_get_drvdata(pdev);
274ad65c 370 return radeon_suspend_kms(drm_dev, true, true, false);
771fe6b9
JG		 371}
372
7473e830 373static int radeon_pmops_resume(struct device *dev)
771fe6b9 374{
7473e830
DA		 375 struct pci_dev *pdev = to_pci_dev(dev);
376 struct drm_device *drm_dev = pci_get_drvdata(pdev);
103917b3
AD		 377
378 /* GPU comes up enabled by the bios on resume */
379 if (radeon_is_px(drm_dev)) {
380 pm_runtime_disable(dev);
381 pm_runtime_set_active(dev);
382 pm_runtime_enable(dev);
383 }
384
10ebc0bc 385 return radeon_resume_kms(drm_dev, true, true);
7473e830
DA		 386}
387
388static int radeon_pmops_freeze(struct device *dev)
389{
390 struct pci_dev *pdev = to_pci_dev(dev);
391 struct drm_device *drm_dev = pci_get_drvdata(pdev);
274ad65c 392 return radeon_suspend_kms(drm_dev, false, true, true);
771fe6b9
JG		 393}
394
7473e830
DA		 395static int radeon_pmops_thaw(struct device *dev)
396{
397 struct pci_dev *pdev = to_pci_dev(dev);
398 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc
DA		 399 return radeon_resume_kms(drm_dev, false, true);
400}
401
402static int radeon_pmops_runtime_suspend(struct device *dev)
403{
404 struct pci_dev *pdev = to_pci_dev(dev);
405 struct drm_device *drm_dev = pci_get_drvdata(pdev);
406 int ret;
407
90c4cde9 408 if (!radeon_is_px(drm_dev)) {
1d8eec8b
DA		 409 pm_runtime_forbid(dev);
410 return -EBUSY;
411 }
9babd35a 412
10ebc0bc
DA		 413 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
414 drm_kms_helper_poll_disable(drm_dev);
415 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
416
274ad65c 417 ret = radeon_suspend_kms(drm_dev, false, false, false);
10ebc0bc
DA		 418 pci_save_state(pdev);
419 pci_disable_device(pdev);
b440bde7 420 pci_ignore_hotplug(pdev);
31764c1e
AD		 421 if (radeon_is_atpx_hybrid())
422 pci_set_power_state(pdev, PCI_D3cold);
84919992 423 else if (!radeon_has_atpx_dgpu_power_cntl())
f7ea4189 424 pci_set_power_state(pdev, PCI_D3hot);
10ebc0bc
DA		 425 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
426
427 return 0;
428}
429
430static int radeon_pmops_runtime_resume(struct device *dev)
431{
432 struct pci_dev *pdev = to_pci_dev(dev);
433 struct drm_device *drm_dev = pci_get_drvdata(pdev);
434 int ret;
435
90c4cde9 436 if (!radeon_is_px(drm_dev))
9babd35a
AD		 437 return -EINVAL;
438
10ebc0bc
DA		 439 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
440
84919992
AD		 441 if (radeon_is_atpx_hybrid() ||
442 !radeon_has_atpx_dgpu_power_cntl())
443 pci_set_power_state(pdev, PCI_D0);
10ebc0bc
DA		 444 pci_restore_state(pdev);
445 ret = pci_enable_device(pdev);
446 if (ret)
447 return ret;
448 pci_set_master(pdev);
449
450 ret = radeon_resume_kms(drm_dev, false, false);
451 drm_kms_helper_poll_enable(drm_dev);
452 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
453 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
454 return 0;
455}
456
457static int radeon_pmops_runtime_idle(struct device *dev)
458{
459 struct pci_dev *pdev = to_pci_dev(dev);
460 struct drm_device *drm_dev = pci_get_drvdata(pdev);
461 struct drm_crtc *crtc;
462
90c4cde9 463 if (!radeon_is_px(drm_dev)) {
1d8eec8b 464 pm_runtime_forbid(dev);
10ebc0bc
DA		 465 return -EBUSY;
466 }
467
468 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
469 if (crtc->enabled) {
470 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
471 return -EBUSY;
472 }
473 }
474
475 pm_runtime_mark_last_busy(dev);
476 pm_runtime_autosuspend(dev);
477 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
478 return 1;
479}
480
481long radeon_drm_ioctl(struct file *filp,
482 unsigned int cmd, unsigned long arg)
483{
484 struct drm_file *file_priv = filp->private_data;
485 struct drm_device *dev;
486 long ret;
487 dev = file_priv->minor->dev;
488 ret = pm_runtime_get_sync(dev->dev);
489 if (ret < 0)
490 return ret;
491
492 ret = drm_ioctl(filp, cmd, arg);
493
494 pm_runtime_mark_last_busy(dev->dev);
495 pm_runtime_put_autosuspend(dev->dev);
496 return ret;
7473e830
DA		 497}
498
499static const struct dev_pm_ops radeon_pm_ops = {
500 .suspend = radeon_pmops_suspend,
501 .resume = radeon_pmops_resume,
502 .freeze = radeon_pmops_freeze,
503 .thaw = radeon_pmops_thaw,
504 .poweroff = radeon_pmops_freeze,
505 .restore = radeon_pmops_resume,
10ebc0bc
DA		 506 .runtime_suspend = radeon_pmops_runtime_suspend,
507 .runtime_resume = radeon_pmops_runtime_resume,
508 .runtime_idle = radeon_pmops_runtime_idle,
7473e830
DA		 509};
510
e08e96de
AV		 511static const struct file_operations radeon_driver_kms_fops = {
512 .owner = THIS_MODULE,
513 .open = drm_open,
514 .release = drm_release,
10ebc0bc 515 .unlocked_ioctl = radeon_drm_ioctl,
e08e96de
AV		 516 .mmap = radeon_mmap,
517 .poll = drm_poll,
e08e96de
AV		 518 .read = drm_read,
519#ifdef CONFIG_COMPAT
520 .compat_ioctl = radeon_kms_compat_ioctl,
521#endif
522};
523
771fe6b9
JG		 524static struct drm_driver kms_driver = {
525 .driver_features =
28185647 526 DRIVER_USE_AGP |
81e95697 527 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
f33bcab9 528 DRIVER_PRIME | DRIVER_RENDER,
771fe6b9 529 .load = radeon_driver_load_kms,
771fe6b9
JG		 530 .open = radeon_driver_open_kms,
531 .preclose = radeon_driver_preclose_kms,
532 .postclose = radeon_driver_postclose_kms,
533 .lastclose = radeon_driver_lastclose_kms,
915b4d11 534 .set_busid = drm_pci_set_busid,
771fe6b9 535 .unload = radeon_driver_unload_kms,
771fe6b9
JG		 536 .get_vblank_counter = radeon_get_vblank_counter_kms,
537 .enable_vblank = radeon_enable_vblank_kms,
538 .disable_vblank = radeon_disable_vblank_kms,
f5a80209
MK		 539 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
540 .get_scanout_position = radeon_get_crtc_scanoutpos,
771fe6b9
JG		 541#if defined(CONFIG_DEBUG_FS)
542 .debugfs_init = radeon_debugfs_init,
543 .debugfs_cleanup = radeon_debugfs_cleanup,
544#endif
545 .irq_preinstall = radeon_driver_irq_preinstall_kms,
546 .irq_postinstall = radeon_driver_irq_postinstall_kms,
547 .irq_uninstall = radeon_driver_irq_uninstall_kms,
548 .irq_handler = radeon_driver_irq_handler_kms,
771fe6b9 549 .ioctls = radeon_ioctls_kms,
71cbf451 550 .gem_free_object_unlocked = radeon_gem_object_free,
721604a1
JG		 551 .gem_open_object = radeon_gem_object_open,
552 .gem_close_object = radeon_gem_object_close,
ff72145b
DA		 553 .dumb_create = radeon_mode_dumb_create,
554 .dumb_map_offset = radeon_mode_dumb_mmap,
43387b37 555 .dumb_destroy = drm_gem_dumb_destroy,
e08e96de 556 .fops = &radeon_driver_kms_fops,
40f5cf99
AD		 557
558 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
559 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
f72a113a 560 .gem_prime_export = radeon_gem_prime_export,
1e6d17a5
AP		 561 .gem_prime_import = drm_gem_prime_import,
562 .gem_prime_pin = radeon_gem_prime_pin,
280cf211 563 .gem_prime_unpin = radeon_gem_prime_unpin,
3aac4502 564 .gem_prime_res_obj = radeon_gem_prime_res_obj,
1e6d17a5
AP		 565 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
566 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
567 .gem_prime_vmap = radeon_gem_prime_vmap,
568 .gem_prime_vunmap = radeon_gem_prime_vunmap,
40f5cf99 569
771fe6b9
JG		 570 .name = DRIVER_NAME,
571 .desc = DRIVER_DESC,
572 .date = DRIVER_DATE,
573 .major = KMS_DRIVER_MAJOR,
574 .minor = KMS_DRIVER_MINOR,
575 .patchlevel = KMS_DRIVER_PATCHLEVEL,
576};
771fe6b9
JG		 577
578static struct drm_driver *driver;
8410ea3b
DA		 579static struct pci_driver *pdriver;
580
8410ea3b
DA		 581static struct pci_driver radeon_kms_pci_driver = {
582 .name = DRIVER_NAME,
583 .id_table = pciidlist,
584 .probe = radeon_pci_probe,
585 .remove = radeon_pci_remove,
7473e830 586 .driver.pm = &radeon_pm_ops,
8410ea3b 587};
771fe6b9 588
1da177e4
LT		 589static int __init radeon_init(void)
590{
e9ced8e0
DA		 591 if (vgacon_text_force() && radeon_modeset == -1) {
592 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
593 radeon_modeset = 0;
594 }
e9ced8e0
DA		 595 /* set to modesetting by default if not nomodeset */
596 if (radeon_modeset == -1)
597 radeon_modeset = 1;
598
771fe6b9
JG		 599 if (radeon_modeset == 1) {
600 DRM_INFO("radeon kernel modesetting enabled.\n");
601 driver = &kms_driver;
8410ea3b 602 pdriver = &radeon_kms_pci_driver;
771fe6b9
JG		 603 driver->driver_features |= DRIVER_MODESET;
604 driver->num_ioctls = radeon_max_kms_ioctl;
6a9ee8af 605 radeon_register_atpx_handler();
14adc892
CK		 606
607 } else {
14adc892
CK		 608 DRM_ERROR("No UMS support in radeon module!\n");
609 return -EINVAL;
771fe6b9 610 }
14adc892
CK		 611
612 /* let modprobe override vga console setting */
8410ea3b 613 return drm_pci_init(driver, pdriver);
1da177e4
LT		 614}
615
616static void __exit radeon_exit(void)
617{
e28740ec 618 radeon_kfd_fini();
8410ea3b 619 drm_pci_exit(driver, pdriver);
6a9ee8af 620 radeon_unregister_atpx_handler();
1da177e4
LT		 621}
622
176f613e 623module_init(radeon_init);
1da177e4
LT		 624module_exit(radeon_exit);
625
b5e89ed5
DA		 626MODULE_AUTHOR(DRIVER_AUTHOR);
627MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 628MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)