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drm/radeon: use pflip irq on R600+ v2
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_display.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/radeon_drm.h>
771fe6b9
JG		 28#include "radeon.h"
29
30#include "atom.h"
31#include <asm/div64.h>
32
10ebc0bc 33#include <linux/pm_runtime.h>
760285e7
DH		 34#include <drm/drm_crtc_helper.h>
35#include <drm/drm_edid.h>
771fe6b9 36
32167016
CK		 37#include <linux/gcd.h>
38
771fe6b9
JG		 39static void avivo_crtc_load_lut(struct drm_crtc *crtc)
40{
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 struct drm_device *dev = crtc->dev;
43 struct radeon_device *rdev = dev->dev_private;
44 int i;
45
d9fdaafb 46 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
771fe6b9
JG		 47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
48
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
52
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
56
57 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
58 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
59 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
60
61 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
62 for (i = 0; i < 256; i++) {
63 WREG32(AVIVO_DC_LUT_30_COLOR,
64 (radeon_crtc->lut_r[i] << 20) |
65 (radeon_crtc->lut_g[i] << 10) |
66 (radeon_crtc->lut_b[i] << 0));
67 }
68
69 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
70}
71
fee298fd 72static void dce4_crtc_load_lut(struct drm_crtc *crtc)
bcc1c2a1
AD		 73{
74 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
75 struct drm_device *dev = crtc->dev;
76 struct radeon_device *rdev = dev->dev_private;
77 int i;
78
d9fdaafb 79 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
bcc1c2a1
AD		 80 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
81
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
85
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
89
677d0768
AD		 90 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
91 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
bcc1c2a1 92
677d0768 93 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
bcc1c2a1 94 for (i = 0; i < 256; i++) {
677d0768 95 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
bcc1c2a1
AD		 96 (radeon_crtc->lut_r[i] << 20) |
97 (radeon_crtc->lut_g[i] << 10) |
98 (radeon_crtc->lut_b[i] << 0));
99 }
100}
101
fee298fd
AD		 102static void dce5_crtc_load_lut(struct drm_crtc *crtc)
103{
104 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
105 struct drm_device *dev = crtc->dev;
106 struct radeon_device *rdev = dev->dev_private;
107 int i;
108
109 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
110
111 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
112 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
113 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
114 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
115 NI_GRPH_PRESCALE_BYPASS);
116 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
117 NI_OVL_PRESCALE_BYPASS);
118 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
119 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
120 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
121
122 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
123
124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
127
128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
131
132 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
133 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
134
135 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
136 for (i = 0; i < 256; i++) {
137 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
138 (radeon_crtc->lut_r[i] << 20) |
139 (radeon_crtc->lut_g[i] << 10) |
140 (radeon_crtc->lut_b[i] << 0));
141 }
142
143 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
144 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
145 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
147 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
148 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
149 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
150 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
151 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
152 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
153 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
154 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
155 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
156 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
157 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
158 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
9e05fa1d
AD		 159 if (ASIC_IS_DCE8(rdev)) {
160 /* XXX this only needs to be programmed once per crtc at startup,
161 * not sure where the best place for it is
162 */
163 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
164 CIK_CURSOR_ALPHA_BLND_ENA);
165 }
fee298fd
AD		 166}
167
771fe6b9
JG		 168static void legacy_crtc_load_lut(struct drm_crtc *crtc)
169{
170 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
171 struct drm_device *dev = crtc->dev;
172 struct radeon_device *rdev = dev->dev_private;
173 int i;
174 uint32_t dac2_cntl;
175
176 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
177 if (radeon_crtc->crtc_id == 0)
178 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
179 else
180 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
181 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
182
183 WREG8(RADEON_PALETTE_INDEX, 0);
184 for (i = 0; i < 256; i++) {
185 WREG32(RADEON_PALETTE_30_DATA,
186 (radeon_crtc->lut_r[i] << 20) |
187 (radeon_crtc->lut_g[i] << 10) |
188 (radeon_crtc->lut_b[i] << 0));
189 }
190}
191
192void radeon_crtc_load_lut(struct drm_crtc *crtc)
193{
194 struct drm_device *dev = crtc->dev;
195 struct radeon_device *rdev = dev->dev_private;
196
197 if (!crtc->enabled)
198 return;
199
fee298fd
AD		 200 if (ASIC_IS_DCE5(rdev))
201 dce5_crtc_load_lut(crtc);
202 else if (ASIC_IS_DCE4(rdev))
203 dce4_crtc_load_lut(crtc);
bcc1c2a1 204 else if (ASIC_IS_AVIVO(rdev))
771fe6b9
JG		 205 avivo_crtc_load_lut(crtc);
206 else
207 legacy_crtc_load_lut(crtc);
208}
209
b8c00ac5 210/** Sets the color ramps on behalf of fbcon */
771fe6b9
JG		 211void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
212 u16 blue, int regno)
213{
214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
215
771fe6b9
JG		 216 radeon_crtc->lut_r[regno] = red >> 6;
217 radeon_crtc->lut_g[regno] = green >> 6;
218 radeon_crtc->lut_b[regno] = blue >> 6;
219}
220
b8c00ac5
DA		 221/** Gets the color ramps on behalf of fbcon */
222void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
223 u16 *blue, int regno)
224{
225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
226
227 *red = radeon_crtc->lut_r[regno] << 6;
228 *green = radeon_crtc->lut_g[regno] << 6;
229 *blue = radeon_crtc->lut_b[regno] << 6;
230}
231
771fe6b9 232static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 233 u16 *blue, uint32_t start, uint32_t size)
771fe6b9
JG		 234{
235 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
7203425a 236 int end = (start + size > 256) ? 256 : start + size, i;
771fe6b9 237
b8c00ac5 238 /* userspace palettes are always correct as is */
7203425a 239 for (i = start; i < end; i++) {
b8c00ac5
DA		 240 radeon_crtc->lut_r[i] = red[i] >> 6;
241 radeon_crtc->lut_g[i] = green[i] >> 6;
242 radeon_crtc->lut_b[i] = blue[i] >> 6;
771fe6b9 243 }
771fe6b9
JG		 244 radeon_crtc_load_lut(crtc);
245}
246
247static void radeon_crtc_destroy(struct drm_crtc *crtc)
248{
249 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
250
771fe6b9
JG		 251 drm_crtc_cleanup(crtc);
252 kfree(radeon_crtc);
253}
254
6f34be50
AD		 255/*
256 * Handle unpin events outside the interrupt handler proper.
257 */
258static void radeon_unpin_work_func(struct work_struct *__work)
259{
260 struct radeon_unpin_work *work =
261 container_of(__work, struct radeon_unpin_work, work);
262 int r;
263
264 /* unpin of the old buffer */
265 r = radeon_bo_reserve(work->old_rbo, false);
266 if (likely(r == 0)) {
267 r = radeon_bo_unpin(work->old_rbo);
268 if (unlikely(r != 0)) {
269 DRM_ERROR("failed to unpin buffer after flip\n");
270 }
271 radeon_bo_unreserve(work->old_rbo);
272 } else
273 DRM_ERROR("failed to reserve buffer after flip\n");
498c555f
DA		 274
275 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
6f34be50
AD		 276 kfree(work);
277}
278
279void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
280{
281 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
282 struct radeon_unpin_work *work;
6f34be50
AD		 283 unsigned long flags;
284 u32 update_pending;
285 int vpos, hpos;
f5d636d2
CK		 286
287 /* can happen during initialization */
288 if (radeon_crtc == NULL)
289 return;
6f34be50
AD		 290
291 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
292 work = radeon_crtc->unpin_work;
293 if (work == NULL ||
fcc485d6 294 (work->fence && !radeon_fence_signaled(work->fence))) {
6f34be50
AD		 295 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
296 return;
297 }
298 /* New pageflip, or just completion of a previous one? */
299 if (!radeon_crtc->deferred_flip_completion) {
300 /* do the flip (mmio) */
301 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
302 } else {
303 /* This is just a completion of a flip queued in crtc
304 * at last invocation. Make sure we go directly to
305 * completion routine.
306 */
307 update_pending = 0;
308 radeon_crtc->deferred_flip_completion = 0;
309 }
310
311 /* Has the pageflip already completed in crtc, or is it certain
312 * to complete in this vblank?
313 */
314 if (update_pending &&
abca9e45 315 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
d47abc58 316 &vpos, &hpos, NULL, NULL)) &&
81ffbbed
FK		 317 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
318 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
319 /* crtc didn't flip in this target vblank interval,
320 * but flip is pending in crtc. Based on the current
321 * scanout position we know that the current frame is
322 * (nearly) complete and the flip will (likely)
323 * complete before the start of the next frame.
324 */
325 update_pending = 0;
326 }
327 if (update_pending) {
6f34be50
AD		 328 /* crtc didn't flip in this target vblank interval,
329 * but flip is pending in crtc. It will complete it
330 * in next vblank interval, so complete the flip at
331 * next vblank irq.
332 */
333 radeon_crtc->deferred_flip_completion = 1;
334 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
335 return;
336 }
337
338 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
339 radeon_crtc->unpin_work = NULL;
340
341 /* wakeup userspace */
26ae4667
RC		 342 if (work->event)
343 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
344
6f34be50
AD		 345 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
346
347 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
348 radeon_fence_unref(&work->fence);
349 radeon_post_page_flip(work->rdev, work->crtc_id);
350 schedule_work(&work->work);
351}
352
353static int radeon_crtc_page_flip(struct drm_crtc *crtc,
354 struct drm_framebuffer *fb,
ed8d1975
KP		 355 struct drm_pending_vblank_event *event,
356 uint32_t page_flip_flags)
6f34be50
AD		 357{
358 struct drm_device *dev = crtc->dev;
359 struct radeon_device *rdev = dev->dev_private;
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct radeon_framebuffer *old_radeon_fb;
362 struct radeon_framebuffer *new_radeon_fb;
363 struct drm_gem_object *obj;
364 struct radeon_bo *rbo;
6f34be50
AD		 365 struct radeon_unpin_work *work;
366 unsigned long flags;
367 u32 tiling_flags, pitch_pixels;
368 u64 base;
369 int r;
370
371 work = kzalloc(sizeof *work, GFP_KERNEL);
372 if (work == NULL)
373 return -ENOMEM;
374
6f34be50
AD		 375 work->event = event;
376 work->rdev = rdev;
377 work->crtc_id = radeon_crtc->crtc_id;
f4510a27 378 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
6f34be50
AD		 379 new_radeon_fb = to_radeon_framebuffer(fb);
380 /* schedule unpin of the old buffer */
381 obj = old_radeon_fb->obj;
498c555f
DA		 382 /* take a reference to the old object */
383 drm_gem_object_reference(obj);
7e4d15d9 384 rbo = gem_to_radeon_bo(obj);
6f34be50 385 work->old_rbo = rbo;
fcc485d6
MD		 386 obj = new_radeon_fb->obj;
387 rbo = gem_to_radeon_bo(obj);
9af20792
DV		 388
389 spin_lock(&rbo->tbo.bdev->fence_lock);
fcc485d6
MD		 390 if (rbo->tbo.sync_obj)
391 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
9af20792
DV		 392 spin_unlock(&rbo->tbo.bdev->fence_lock);
393
6f34be50
AD		 394 INIT_WORK(&work->work, radeon_unpin_work_func);
395
396 /* We borrow the event spin lock for protecting unpin_work */
397 spin_lock_irqsave(&dev->event_lock, flags);
398 if (radeon_crtc->unpin_work) {
6f34be50 399 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
498c555f
DA		 400 r = -EBUSY;
401 goto unlock_free;
6f34be50
AD		 402 }
403 radeon_crtc->unpin_work = work;
404 radeon_crtc->deferred_flip_completion = 0;
405 spin_unlock_irqrestore(&dev->event_lock, flags);
406
407 /* pin the new buffer */
6f34be50
AD		 408 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
409 work->old_rbo, rbo);
410
411 r = radeon_bo_reserve(rbo, false);
412 if (unlikely(r != 0)) {
413 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
414 goto pflip_cleanup;
415 }
0349af70
MD		 416 /* Only 27 bit offset for legacy CRTC */
417 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
418 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
6f34be50
AD		 419 if (unlikely(r != 0)) {
420 radeon_bo_unreserve(rbo);
421 r = -EINVAL;
422 DRM_ERROR("failed to pin new rbo buffer before flip\n");
423 goto pflip_cleanup;
424 }
425 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
426 radeon_bo_unreserve(rbo);
427
428 if (!ASIC_IS_AVIVO(rdev)) {
429 /* crtc offset is from display base addr not FB location */
430 base -= radeon_crtc->legacy_display_base_addr;
01f2c773 431 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
6f34be50
AD		 432
433 if (tiling_flags & RADEON_TILING_MACRO) {
434 if (ASIC_IS_R300(rdev)) {
435 base &= ~0x7ff;
436 } else {
437 int byteshift = fb->bits_per_pixel >> 4;
438 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
439 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
440 }
441 } else {
442 int offset = crtc->y * pitch_pixels + crtc->x;
443 switch (fb->bits_per_pixel) {
444 case 8:
445 default:
446 offset *= 1;
447 break;
448 case 15:
449 case 16:
450 offset *= 2;
451 break;
452 case 24:
453 offset *= 3;
454 break;
455 case 32:
456 offset *= 4;
457 break;
458 }
459 base += offset;
460 }
461 base &= ~7;
462 }
463
464 spin_lock_irqsave(&dev->event_lock, flags);
465 work->new_crtc_base = base;
466 spin_unlock_irqrestore(&dev->event_lock, flags);
467
468 /* update crtc fb */
f4510a27 469 crtc->primary->fb = fb;
6f34be50
AD		 470
471 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
472 if (r) {
473 DRM_ERROR("failed to get vblank before flip\n");
474 goto pflip_cleanup1;
475 }
476
6f34be50
AD		 477 /* set the proper interrupt */
478 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
6f34be50
AD		 479
480 return 0;
481
6f34be50 482pflip_cleanup1:
d0254d56 483 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
6f34be50
AD		 484 DRM_ERROR("failed to reserve new rbo in error path\n");
485 goto pflip_cleanup;
486 }
d0254d56 487 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
6f34be50 488 DRM_ERROR("failed to unpin new rbo in error path\n");
6f34be50
AD		 489 }
490 radeon_bo_unreserve(rbo);
491
492pflip_cleanup:
493 spin_lock_irqsave(&dev->event_lock, flags);
494 radeon_crtc->unpin_work = NULL;
498c555f 495unlock_free:
6f34be50 496 spin_unlock_irqrestore(&dev->event_lock, flags);
db318d7a 497 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
fcc485d6 498 radeon_fence_unref(&work->fence);
6f34be50
AD		 499 kfree(work);
500
501 return r;
502}
503
10ebc0bc
DA		 504static int
505radeon_crtc_set_config(struct drm_mode_set *set)
506{
507 struct drm_device *dev;
508 struct radeon_device *rdev;
509 struct drm_crtc *crtc;
510 bool active = false;
511 int ret;
512
513 if (!set || !set->crtc)
514 return -EINVAL;
515
516 dev = set->crtc->dev;
517
518 ret = pm_runtime_get_sync(dev->dev);
519 if (ret < 0)
520 return ret;
521
522 ret = drm_crtc_helper_set_config(set);
523
524 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
525 if (crtc->enabled)
526 active = true;
527
528 pm_runtime_mark_last_busy(dev->dev);
529
530 rdev = dev->dev_private;
531 /* if we have active crtcs and we don't have a power ref,
532 take the current one */
533 if (active && !rdev->have_disp_power_ref) {
534 rdev->have_disp_power_ref = true;
535 return ret;
536 }
537 /* if we have no active crtcs, then drop the power ref
538 we got before */
539 if (!active && rdev->have_disp_power_ref) {
540 pm_runtime_put_autosuspend(dev->dev);
541 rdev->have_disp_power_ref = false;
542 }
543
544 /* drop the power reference we got coming in here */
545 pm_runtime_put_autosuspend(dev->dev);
546 return ret;
547}
771fe6b9
JG		 548static const struct drm_crtc_funcs radeon_crtc_funcs = {
549 .cursor_set = radeon_crtc_cursor_set,
550 .cursor_move = radeon_crtc_cursor_move,
551 .gamma_set = radeon_crtc_gamma_set,
10ebc0bc 552 .set_config = radeon_crtc_set_config,
771fe6b9 553 .destroy = radeon_crtc_destroy,
6f34be50 554 .page_flip = radeon_crtc_page_flip,
771fe6b9
JG		 555};
556
557static void radeon_crtc_init(struct drm_device *dev, int index)
558{
559 struct radeon_device *rdev = dev->dev_private;
560 struct radeon_crtc *radeon_crtc;
561 int i;
562
563 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
564 if (radeon_crtc == NULL)
565 return;
566
567 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
568
569 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
570 radeon_crtc->crtc_id = index;
c93bb85b 571 rdev->mode_info.crtcs[index] = radeon_crtc;
771fe6b9 572
9e05fa1d
AD		 573 if (rdev->family >= CHIP_BONAIRE) {
574 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
575 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
576 } else {
577 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
578 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
579 }
bea61c59
AD		 580 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
581 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
9e05fa1d 582
785b93ef 583#if 0
771fe6b9
JG		 584 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
585 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
586 radeon_crtc->mode_set.num_connectors = 0;
785b93ef 587#endif
771fe6b9
JG		 588
589 for (i = 0; i < 256; i++) {
590 radeon_crtc->lut_r[i] = i << 2;
591 radeon_crtc->lut_g[i] = i << 2;
592 radeon_crtc->lut_b[i] = i << 2;
593 }
594
595 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
596 radeon_atombios_init_crtc(dev, radeon_crtc);
597 else
598 radeon_legacy_init_crtc(dev, radeon_crtc);
599}
600
e68adef8 601static const char *encoder_names[38] = {
771fe6b9
JG		 602 "NONE",
603 "INTERNAL_LVDS",
604 "INTERNAL_TMDS1",
605 "INTERNAL_TMDS2",
606 "INTERNAL_DAC1",
607 "INTERNAL_DAC2",
608 "INTERNAL_SDVOA",
609 "INTERNAL_SDVOB",
610 "SI170B",
611 "CH7303",
612 "CH7301",
613 "INTERNAL_DVO1",
614 "EXTERNAL_SDVOA",
615 "EXTERNAL_SDVOB",
616 "TITFP513",
617 "INTERNAL_LVTM1",
618 "VT1623",
619 "HDMI_SI1930",
620 "HDMI_INTERNAL",
621 "INTERNAL_KLDSCP_TMDS1",
622 "INTERNAL_KLDSCP_DVO1",
623 "INTERNAL_KLDSCP_DAC1",
624 "INTERNAL_KLDSCP_DAC2",
625 "SI178",
626 "MVPU_FPGA",
627 "INTERNAL_DDI",
628 "VT1625",
629 "HDMI_SI1932",
630 "DP_AN9801",
631 "DP_DP501",
632 "INTERNAL_UNIPHY",
633 "INTERNAL_KLDSCP_LVTMA",
634 "INTERNAL_UNIPHY1",
635 "INTERNAL_UNIPHY2",
bf982ebf
AD		 636 "NUTMEG",
637 "TRAVIS",
e68adef8
AD		 638 "INTERNAL_VCE",
639 "INTERNAL_UNIPHY3",
771fe6b9
JG		 640};
641
cbd4623d 642static const char *hpd_names[6] = {
eed45b30
AD		 643 "HPD1",
644 "HPD2",
645 "HPD3",
646 "HPD4",
647 "HPD5",
648 "HPD6",
649};
650
771fe6b9
JG		 651static void radeon_print_display_setup(struct drm_device *dev)
652{
653 struct drm_connector *connector;
654 struct radeon_connector *radeon_connector;
655 struct drm_encoder *encoder;
656 struct radeon_encoder *radeon_encoder;
657 uint32_t devices;
658 int i = 0;
659
660 DRM_INFO("Radeon Display Connectors\n");
661 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
662 radeon_connector = to_radeon_connector(connector);
663 DRM_INFO("Connector %d:\n", i);
c1d2dbd2 664 DRM_INFO(" %s\n", drm_get_connector_name(connector));
eed45b30
AD		 665 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
666 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
4b9d2a21 667 if (radeon_connector->ddc_bus) {
771fe6b9
JG		 668 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
669 radeon_connector->ddc_bus->rec.mask_clk_reg,
670 radeon_connector->ddc_bus->rec.mask_data_reg,
671 radeon_connector->ddc_bus->rec.a_clk_reg,
672 radeon_connector->ddc_bus->rec.a_data_reg,
9b9fe724
AD		 673 radeon_connector->ddc_bus->rec.en_clk_reg,
674 radeon_connector->ddc_bus->rec.en_data_reg,
675 radeon_connector->ddc_bus->rec.y_clk_reg,
676 radeon_connector->ddc_bus->rec.y_data_reg);
fb939dfc 677 if (radeon_connector->router.ddc_valid)
26b5bc98 678 DRM_INFO(" DDC Router 0x%x/0x%x\n",
fb939dfc
AD		 679 radeon_connector->router.ddc_mux_control_pin,
680 radeon_connector->router.ddc_mux_state);
681 if (radeon_connector->router.cd_valid)
682 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
683 radeon_connector->router.cd_mux_control_pin,
684 radeon_connector->router.cd_mux_state);
4b9d2a21
DA		 685 } else {
686 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
687 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
688 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
689 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
690 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
691 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
692 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
693 }
771fe6b9
JG		 694 DRM_INFO(" Encoders:\n");
695 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
696 radeon_encoder = to_radeon_encoder(encoder);
697 devices = radeon_encoder->devices & radeon_connector->devices;
698 if (devices) {
699 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
700 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
701 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
702 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
703 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
704 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
705 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
706 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
707 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
708 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
709 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
710 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
711 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
712 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
713 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
714 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
73758a5d
AD		 715 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
716 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
771fe6b9
JG		 717 if (devices & ATOM_DEVICE_TV1_SUPPORT)
718 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
719 if (devices & ATOM_DEVICE_CV_SUPPORT)
720 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
721 }
722 }
723 i++;
724 }
725}
726
4ce001ab 727static bool radeon_setup_enc_conn(struct drm_device *dev)
771fe6b9
JG		 728{
729 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 730 bool ret = false;
731
732 if (rdev->bios) {
733 if (rdev->is_atom_bios) {
a084e6ee
AD		 734 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
735 if (ret == false)
771fe6b9 736 ret = radeon_get_atom_connector_info_from_object_table(dev);
b9597a1c 737 } else {
771fe6b9 738 ret = radeon_get_legacy_connector_info_from_bios(dev);
b9597a1c
AD		 739 if (ret == false)
740 ret = radeon_get_legacy_connector_info_from_table(dev);
741 }
771fe6b9
JG		 742 } else {
743 if (!ASIC_IS_AVIVO(rdev))
744 ret = radeon_get_legacy_connector_info_from_table(dev);
745 }
746 if (ret) {
1f3b6a45 747 radeon_setup_encoder_clones(dev);
771fe6b9 748 radeon_print_display_setup(dev);
771fe6b9
JG		 749 }
750
751 return ret;
752}
753
754int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
755{
3c537889
AD		 756 struct drm_device *dev = radeon_connector->base.dev;
757 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 758 int ret = 0;
759
26b5bc98 760 /* on hw with routers, select right port */
fb939dfc
AD		 761 if (radeon_connector->router.ddc_valid)
762 radeon_router_select_ddc_port(radeon_connector);
26b5bc98 763
0a9069d3
NOS		 764 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
765 ENCODER_OBJECT_ID_NONE) {
379dfc25 766 if (radeon_connector->ddc_bus->has_aux)
0a9069d3 767 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
379dfc25 768 &radeon_connector->ddc_bus->aux.ddc);
0a9069d3
NOS		 769 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
770 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
746c1aa4 771 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
b06947b5 772
7a15cbd4 773 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
379dfc25
AD		 774 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
775 radeon_connector->ddc_bus->has_aux)
b06947b5 776 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
379dfc25 777 &radeon_connector->ddc_bus->aux.ddc);
b06947b5
AD		 778 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
779 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
780 &radeon_connector->ddc_bus->adapter);
781 } else {
782 if (radeon_connector->ddc_bus && !radeon_connector->edid)
783 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
784 &radeon_connector->ddc_bus->adapter);
0294cf4f 785 }
c324acd5
AD		 786
787 if (!radeon_connector->edid) {
788 if (rdev->is_atom_bios) {
789 /* some laptops provide a hardcoded edid in rom for LCDs */
790 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
791 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
792 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
793 } else
794 /* some servers provide a hardcoded edid in rom for KVMs */
795 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
796 }
0294cf4f
AD		 797 if (radeon_connector->edid) {
798 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
799 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
16086279 800 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
771fe6b9
JG		 801 return ret;
802 }
803 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
42dea5dd 804 return 0;
771fe6b9
JG		 805}
806
f523f74e 807/* avivo */
f523f74e 808
32167016
CK		 809/**
810 * avivo_reduce_ratio - fractional number reduction
811 *
812 * @nom: nominator
813 * @den: denominator
814 * @nom_min: minimum value for nominator
815 * @den_min: minimum value for denominator
816 *
817 * Find the greatest common divisor and apply it on both nominator and
818 * denominator, but make nominator and denominator are at least as large
819 * as their minimum values.
820 */
821static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
822 unsigned nom_min, unsigned den_min)
f523f74e 823{
32167016
CK		 824 unsigned tmp;
825
826 /* reduce the numbers to a simpler ratio */
827 tmp = gcd(*nom, *den);
828 *nom /= tmp;
829 *den /= tmp;
830
831 /* make sure nominator is large enough */
832 if (*nom < nom_min) {
833 tmp = (nom_min + *nom - 1) / *nom;
834 *nom *= tmp;
835 *den *= tmp;
f523f74e
AD		 836 }
837
32167016
CK		 838 /* make sure the denominator is large enough */
839 if (*den < den_min) {
840 tmp = (den_min + *den - 1) / *den;
841 *nom *= tmp;
842 *den *= tmp;
f523f74e 843 }
f523f74e
AD		 844}
845
c2fb3094
CK		 846/**
847 * avivo_get_fb_ref_div - feedback and ref divider calculation
848 *
849 * @nom: nominator
850 * @den: denominator
851 * @post_div: post divider
852 * @fb_div_max: feedback divider maximum
853 * @ref_div_max: reference divider maximum
854 * @fb_div: resulting feedback divider
855 * @ref_div: resulting reference divider
856 *
857 * Calculate feedback and reference divider for a given post divider. Makes
858 * sure we stay within the limits.
859 */
860static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
861 unsigned fb_div_max, unsigned ref_div_max,
862 unsigned *fb_div, unsigned *ref_div)
863{
864 /* limit reference * post divider to a maximum */
865 ref_div_max = min(210 / post_div, ref_div_max);
866
867 /* get matching reference and feedback divider */
868 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
869 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
870
871 /* limit fb divider to its maximum */
872 if (*fb_div > fb_div_max) {
873 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
874 *fb_div = fb_div_max;
875 }
876}
877
32167016
CK		 878/**
879 * radeon_compute_pll_avivo - compute PLL paramaters
880 *
881 * @pll: information about the PLL
882 * @dot_clock_p: resulting pixel clock
883 * fb_div_p: resulting feedback divider
884 * frac_fb_div_p: fractional part of the feedback divider
885 * ref_div_p: resulting reference divider
886 * post_div_p: resulting reference divider
887 *
888 * Try to calculate the PLL parameters to generate the given frequency:
889 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
890 */
f523f74e
AD		 891void radeon_compute_pll_avivo(struct radeon_pll *pll,
892 u32 freq,
893 u32 *dot_clock_p,
894 u32 *fb_div_p,
895 u32 *frac_fb_div_p,
896 u32 *ref_div_p,
897 u32 *post_div_p)
898{
c2fb3094
CK		 899 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
900 freq : freq / 10;
901
32167016
CK		 902 unsigned fb_div_min, fb_div_max, fb_div;
903 unsigned post_div_min, post_div_max, post_div;
904 unsigned ref_div_min, ref_div_max, ref_div;
905 unsigned post_div_best, diff_best;
f8a2645e 906 unsigned nom, den;
f523f74e 907
32167016
CK		 908 /* determine allowed feedback divider range */
909 fb_div_min = pll->min_feedback_div;
910 fb_div_max = pll->max_feedback_div;
f523f74e
AD		 911
912 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
32167016
CK		 913 fb_div_min *= 10;
914 fb_div_max *= 10;
915 }
916
917 /* determine allowed ref divider range */
918 if (pll->flags & RADEON_PLL_USE_REF_DIV)
919 ref_div_min = pll->reference_div;
920 else
921 ref_div_min = pll->min_ref_div;
24315814
CK		 922
923 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
924 pll->flags & RADEON_PLL_USE_REF_DIV)
925 ref_div_max = pll->reference_div;
926 else
927 ref_div_max = pll->max_ref_div;
32167016
CK		 928
929 /* determine allowed post divider range */
930 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
931 post_div_min = pll->post_div;
932 post_div_max = pll->post_div;
933 } else {
32167016
CK		 934 unsigned vco_min, vco_max;
935
936 if (pll->flags & RADEON_PLL_IS_LCD) {
937 vco_min = pll->lcd_pll_out_min;
938 vco_max = pll->lcd_pll_out_max;
939 } else {
940 vco_min = pll->pll_out_min;
941 vco_max = pll->pll_out_max;
f523f74e 942 }
32167016 943
c2fb3094
CK		 944 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
945 vco_min *= 10;
946 vco_max *= 10;
947 }
948
32167016
CK		 949 post_div_min = vco_min / target_clock;
950 if ((target_clock * post_div_min) < vco_min)
951 ++post_div_min;
952 if (post_div_min < pll->min_post_div)
953 post_div_min = pll->min_post_div;
954
955 post_div_max = vco_max / target_clock;
956 if ((target_clock * post_div_max) > vco_max)
957 --post_div_max;
958 if (post_div_max > pll->max_post_div)
959 post_div_max = pll->max_post_div;
960 }
961
962 /* represent the searched ratio as fractional number */
c2fb3094 963 nom = target_clock;
32167016
CK		 964 den = pll->reference_freq;
965
966 /* reduce the numbers to a simpler ratio */
967 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
968
969 /* now search for a post divider */
970 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
971 post_div_best = post_div_min;
972 else
973 post_div_best = post_div_max;
974 diff_best = ~0;
975
976 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
c2fb3094
CK		 977 unsigned diff;
978 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
979 ref_div_max, &fb_div, &ref_div);
980 diff = abs(target_clock - (pll->reference_freq * fb_div) /
981 (ref_div * post_div));
982
32167016
CK		 983 if (diff < diff_best || (diff == diff_best &&
984 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
985
986 post_div_best = post_div;
987 diff_best = diff;
f523f74e 988 }
32167016
CK		 989 }
990 post_div = post_div_best;
991
c2fb3094
CK		 992 /* get the feedback and reference divider for the optimal value */
993 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
994 &fb_div, &ref_div);
32167016
CK		 995
996 /* reduce the numbers to a simpler ratio once more */
997 /* this also makes sure that the reference divider is large enough */
998 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
999
1000 /* and finally save the result */
1001 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1002 *fb_div_p = fb_div / 10;
1003 *frac_fb_div_p = fb_div % 10;
f523f74e 1004 } else {
32167016
CK		 1005 *fb_div_p = fb_div;
1006 *frac_fb_div_p = 0;
f523f74e
AD		 1007 }
1008
32167016
CK		 1009 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1010 (pll->reference_freq * *frac_fb_div_p)) /
1011 (ref_div * post_div * 10);
f523f74e
AD		 1012 *ref_div_p = ref_div;
1013 *post_div_p = post_div;
32167016
CK		 1014
1015 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
c2fb3094 1016 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
32167016 1017 ref_div, post_div);
f523f74e
AD		 1018}
1019
1020/* pre-avivo */
771fe6b9
JG		 1021static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1022{
1023 uint64_t mod;
1024
1025 n += d / 2;
1026
1027 mod = do_div(n, d);
1028 return n;
1029}
1030
f523f74e
AD		 1031void radeon_compute_pll_legacy(struct radeon_pll *pll,
1032 uint64_t freq,
1033 uint32_t *dot_clock_p,
1034 uint32_t *fb_div_p,
1035 uint32_t *frac_fb_div_p,
1036 uint32_t *ref_div_p,
1037 uint32_t *post_div_p)
771fe6b9
JG		 1038{
1039 uint32_t min_ref_div = pll->min_ref_div;
1040 uint32_t max_ref_div = pll->max_ref_div;
fc10332b
AD		 1041 uint32_t min_post_div = pll->min_post_div;
1042 uint32_t max_post_div = pll->max_post_div;
771fe6b9
JG		 1043 uint32_t min_fractional_feed_div = 0;
1044 uint32_t max_fractional_feed_div = 0;
1045 uint32_t best_vco = pll->best_vco;
1046 uint32_t best_post_div = 1;
1047 uint32_t best_ref_div = 1;
1048 uint32_t best_feedback_div = 1;
1049 uint32_t best_frac_feedback_div = 0;
1050 uint32_t best_freq = -1;
1051 uint32_t best_error = 0xffffffff;
1052 uint32_t best_vco_diff = 1;
1053 uint32_t post_div;
86cb2bbf 1054 u32 pll_out_min, pll_out_max;
771fe6b9 1055
d9fdaafb 1056 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
771fe6b9
JG		 1057 freq = freq * 1000;
1058
86cb2bbf
AD		 1059 if (pll->flags & RADEON_PLL_IS_LCD) {
1060 pll_out_min = pll->lcd_pll_out_min;
1061 pll_out_max = pll->lcd_pll_out_max;
1062 } else {
1063 pll_out_min = pll->pll_out_min;
1064 pll_out_max = pll->pll_out_max;
1065 }
1066
619efb10
AD		 1067 if (pll_out_min > 64800)
1068 pll_out_min = 64800;
1069
fc10332b 1070 if (pll->flags & RADEON_PLL_USE_REF_DIV)
771fe6b9
JG		 1071 min_ref_div = max_ref_div = pll->reference_div;
1072 else {
1073 while (min_ref_div < max_ref_div-1) {
1074 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1075 uint32_t pll_in = pll->reference_freq / mid;
1076 if (pll_in < pll->pll_in_min)
1077 max_ref_div = mid;
1078 else if (pll_in > pll->pll_in_max)
1079 min_ref_div = mid;
1080 else
1081 break;
1082 }
1083 }
1084
fc10332b
AD		 1085 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1086 min_post_div = max_post_div = pll->post_div;
1087
1088 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
771fe6b9
JG		 1089 min_fractional_feed_div = pll->min_frac_feedback_div;
1090 max_fractional_feed_div = pll->max_frac_feedback_div;
1091 }
1092
bd6a60af 1093 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
771fe6b9
JG		 1094 uint32_t ref_div;
1095
fc10332b 1096 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
771fe6b9
JG		 1097 continue;
1098
1099 /* legacy radeons only have a few post_divs */
fc10332b 1100 if (pll->flags & RADEON_PLL_LEGACY) {
771fe6b9
JG		 1101 if ((post_div == 5) ||
1102 (post_div == 7) ||
1103 (post_div == 9) ||
1104 (post_div == 10) ||
1105 (post_div == 11) ||
1106 (post_div == 13) ||
1107 (post_div == 14) ||
1108 (post_div == 15))
1109 continue;
1110 }
1111
1112 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1113 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1114 uint32_t pll_in = pll->reference_freq / ref_div;
1115 uint32_t min_feed_div = pll->min_feedback_div;
1116 uint32_t max_feed_div = pll->max_feedback_div + 1;
1117
1118 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1119 continue;
1120
1121 while (min_feed_div < max_feed_div) {
1122 uint32_t vco;
1123 uint32_t min_frac_feed_div = min_fractional_feed_div;
1124 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1125 uint32_t frac_feedback_div;
1126 uint64_t tmp;
1127
1128 feedback_div = (min_feed_div + max_feed_div) / 2;
1129
1130 tmp = (uint64_t)pll->reference_freq * feedback_div;
1131 vco = radeon_div(tmp, ref_div);
1132
86cb2bbf 1133 if (vco < pll_out_min) {
771fe6b9
JG		 1134 min_feed_div = feedback_div + 1;
1135 continue;
86cb2bbf 1136 } else if (vco > pll_out_max) {
771fe6b9
JG		 1137 max_feed_div = feedback_div;
1138 continue;
1139 }
1140
1141 while (min_frac_feed_div < max_frac_feed_div) {
1142 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1143 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1144 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1145 current_freq = radeon_div(tmp, ref_div * post_div);
1146
fc10332b 1147 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
167ffc44
DC		 1148 if (freq < current_freq)
1149 error = 0xffffffff;
1150 else
1151 error = freq - current_freq;
d0e275a9
AD		 1152 } else
1153 error = abs(current_freq - freq);
771fe6b9
JG		 1154 vco_diff = abs(vco - best_vco);
1155
1156 if ((best_vco == 0 && error < best_error) ||
1157 (best_vco != 0 &&
167ffc44 1158 ((best_error > 100 && error < best_error - 100) ||
5480f727 1159 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
771fe6b9
JG		 1160 best_post_div = post_div;
1161 best_ref_div = ref_div;
1162 best_feedback_div = feedback_div;
1163 best_frac_feedback_div = frac_feedback_div;
1164 best_freq = current_freq;
1165 best_error = error;
1166 best_vco_diff = vco_diff;
5480f727
DA		 1167 } else if (current_freq == freq) {
1168 if (best_freq == -1) {
1169 best_post_div = post_div;
1170 best_ref_div = ref_div;
1171 best_feedback_div = feedback_div;
1172 best_frac_feedback_div = frac_feedback_div;
1173 best_freq = current_freq;
1174 best_error = error;
1175 best_vco_diff = vco_diff;
1176 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1177 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1178 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1179 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1180 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1181 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1182 best_post_div = post_div;
1183 best_ref_div = ref_div;
1184 best_feedback_div = feedback_div;
1185 best_frac_feedback_div = frac_feedback_div;
1186 best_freq = current_freq;
1187 best_error = error;
1188 best_vco_diff = vco_diff;
1189 }
771fe6b9
JG		 1190 }
1191 if (current_freq < freq)
1192 min_frac_feed_div = frac_feedback_div + 1;
1193 else
1194 max_frac_feed_div = frac_feedback_div;
1195 }
1196 if (current_freq < freq)
1197 min_feed_div = feedback_div + 1;
1198 else
1199 max_feed_div = feedback_div;
1200 }
1201 }
1202 }
1203
1204 *dot_clock_p = best_freq / 10000;
1205 *fb_div_p = best_feedback_div;
1206 *frac_fb_div_p = best_frac_feedback_div;
1207 *ref_div_p = best_ref_div;
1208 *post_div_p = best_post_div;
bbb0aef5
JP		 1209 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1210 (long long)freq,
1211 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
51d4bf84
AD		 1212 best_ref_div, best_post_div);
1213
771fe6b9
JG		 1214}
1215
1216static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1217{
1218 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
771fe6b9 1219
29d08b3e 1220 if (radeon_fb->obj) {
bc9025bd 1221 drm_gem_object_unreference_unlocked(radeon_fb->obj);
29d08b3e 1222 }
771fe6b9
JG		 1223 drm_framebuffer_cleanup(fb);
1224 kfree(radeon_fb);
1225}
1226
1227static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1228 struct drm_file *file_priv,
1229 unsigned int *handle)
1230{
1231 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1232
1233 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1234}
1235
1236static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1237 .destroy = radeon_user_framebuffer_destroy,
1238 .create_handle = radeon_user_framebuffer_create_handle,
1239};
1240
aaefcd42 1241int
38651674
DA		 1242radeon_framebuffer_init(struct drm_device *dev,
1243 struct radeon_framebuffer *rfb,
308e5bcb 1244 struct drm_mode_fb_cmd2 *mode_cmd,
38651674 1245 struct drm_gem_object *obj)
771fe6b9 1246{
aaefcd42 1247 int ret;
38651674 1248 rfb->obj = obj;
c7d73f6a 1249 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
aaefcd42
DA		 1250 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1251 if (ret) {
1252 rfb->obj = NULL;
1253 return ret;
1254 }
aaefcd42 1255 return 0;
771fe6b9
JG		 1256}
1257
1258static struct drm_framebuffer *
1259radeon_user_framebuffer_create(struct drm_device *dev,
1260 struct drm_file *file_priv,
308e5bcb 1261 struct drm_mode_fb_cmd2 *mode_cmd)
771fe6b9
JG		 1262{
1263 struct drm_gem_object *obj;
38651674 1264 struct radeon_framebuffer *radeon_fb;
aaefcd42 1265 int ret;
771fe6b9 1266
308e5bcb 1267 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
7e71c9e2
JG		 1268 if (obj == NULL) {
1269 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
308e5bcb 1270 "can't create framebuffer\n", mode_cmd->handles[0]);
cce13ff7 1271 return ERR_PTR(-ENOENT);
7e71c9e2 1272 }
38651674
DA		 1273
1274 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
f2d68cf4 1275 if (radeon_fb == NULL) {
1276 drm_gem_object_unreference_unlocked(obj);
cce13ff7 1277 return ERR_PTR(-ENOMEM);
f2d68cf4 1278 }
38651674 1279
aaefcd42
DA		 1280 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1281 if (ret) {
1282 kfree(radeon_fb);
1283 drm_gem_object_unreference_unlocked(obj);
b2f4b03f 1284 return ERR_PTR(ret);
aaefcd42 1285 }
38651674
DA		 1286
1287 return &radeon_fb->base;
771fe6b9
JG		 1288}
1289
eb1f8e4f
DA		 1290static void radeon_output_poll_changed(struct drm_device *dev)
1291{
1292 struct radeon_device *rdev = dev->dev_private;
1293 radeon_fb_output_poll_changed(rdev);
1294}
1295
771fe6b9
JG		 1296static const struct drm_mode_config_funcs radeon_mode_funcs = {
1297 .fb_create = radeon_user_framebuffer_create,
eb1f8e4f 1298 .output_poll_changed = radeon_output_poll_changed
771fe6b9
JG		 1299};
1300
445282db
DA		 1301static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1302{ { 0, "driver" },
1303 { 1, "bios" },
1304};
1305
1306static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1307{ { TV_STD_NTSC, "ntsc" },
1308 { TV_STD_PAL, "pal" },
1309 { TV_STD_PAL_M, "pal-m" },
1310 { TV_STD_PAL_60, "pal-60" },
1311 { TV_STD_NTSC_J, "ntsc-j" },
1312 { TV_STD_SCART_PAL, "scart-pal" },
1313 { TV_STD_PAL_CN, "pal-cn" },
1314 { TV_STD_SECAM, "secam" },
1315};
1316
5b1714d3
AD		 1317static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1318{ { UNDERSCAN_OFF, "off" },
1319 { UNDERSCAN_ON, "on" },
1320 { UNDERSCAN_AUTO, "auto" },
1321};
1322
8666c076
AD		 1323static struct drm_prop_enum_list radeon_audio_enum_list[] =
1324{ { RADEON_AUDIO_DISABLE, "off" },
1325 { RADEON_AUDIO_ENABLE, "on" },
1326 { RADEON_AUDIO_AUTO, "auto" },
1327};
1328
6214bb74
AD		 1329/* XXX support different dither options? spatial, temporal, both, etc. */
1330static struct drm_prop_enum_list radeon_dither_enum_list[] =
1331{ { RADEON_FMT_DITHER_DISABLE, "off" },
1332 { RADEON_FMT_DITHER_ENABLE, "on" },
1333};
1334
d79766fa 1335static int radeon_modeset_create_props(struct radeon_device *rdev)
445282db 1336{
4a67d391 1337 int sz;
445282db
DA		 1338
1339 if (rdev->is_atom_bios) {
1340 rdev->mode_info.coherent_mode_property =
d9bc3c02 1341 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
445282db
DA		 1342 if (!rdev->mode_info.coherent_mode_property)
1343 return -ENOMEM;
445282db
DA		 1344 }
1345
1346 if (!ASIC_IS_AVIVO(rdev)) {
1347 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1348 rdev->mode_info.tmds_pll_property =
4a67d391
SH		 1349 drm_property_create_enum(rdev->ddev, 0,
1350 "tmds_pll",
1351 radeon_tmds_pll_enum_list, sz);
445282db
DA		 1352 }
1353
1354 rdev->mode_info.load_detect_property =
d9bc3c02 1355 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
445282db
DA		 1356 if (!rdev->mode_info.load_detect_property)
1357 return -ENOMEM;
445282db
DA		 1358
1359 drm_mode_create_scaling_mode_property(rdev->ddev);
1360
1361 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1362 rdev->mode_info.tv_std_property =
4a67d391
SH		 1363 drm_property_create_enum(rdev->ddev, 0,
1364 "tv standard",
1365 radeon_tv_std_enum_list, sz);
445282db 1366
5b1714d3
AD		 1367 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1368 rdev->mode_info.underscan_property =
4a67d391
SH		 1369 drm_property_create_enum(rdev->ddev, 0,
1370 "underscan",
1371 radeon_underscan_enum_list, sz);
5b1714d3 1372
5bccf5e3 1373 rdev->mode_info.underscan_hborder_property =
d9bc3c02
SH		 1374 drm_property_create_range(rdev->ddev, 0,
1375 "underscan hborder", 0, 128);
5bccf5e3
MG		 1376 if (!rdev->mode_info.underscan_hborder_property)
1377 return -ENOMEM;
5bccf5e3
MG		 1378
1379 rdev->mode_info.underscan_vborder_property =
d9bc3c02
SH		 1380 drm_property_create_range(rdev->ddev, 0,
1381 "underscan vborder", 0, 128);
5bccf5e3
MG		 1382 if (!rdev->mode_info.underscan_vborder_property)
1383 return -ENOMEM;
5bccf5e3 1384
8666c076
AD		 1385 sz = ARRAY_SIZE(radeon_audio_enum_list);
1386 rdev->mode_info.audio_property =
1387 drm_property_create_enum(rdev->ddev, 0,
1388 "audio",
1389 radeon_audio_enum_list, sz);
1390
6214bb74
AD		 1391 sz = ARRAY_SIZE(radeon_dither_enum_list);
1392 rdev->mode_info.dither_property =
1393 drm_property_create_enum(rdev->ddev, 0,
1394 "dither",
1395 radeon_dither_enum_list, sz);
1396
445282db
DA		 1397 return 0;
1398}
1399
f46c0120
AD		 1400void radeon_update_display_priority(struct radeon_device *rdev)
1401{
1402 /* adjustment options for the display watermarks */
1403 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1404 /* set display priority to high for r3xx, rv515 chips
1405 * this avoids flickering due to underflow to the
1406 * display controllers during heavy acceleration.
45737447
AD		 1407 * Don't force high on rs4xx igp chips as it seems to
1408 * affect the sound card. See kernel bug 15982.
f46c0120 1409 */
45737447
AD		 1410 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1411 !(rdev->flags & RADEON_IS_IGP))
f46c0120
AD		 1412 rdev->disp_priority = 2;
1413 else
1414 rdev->disp_priority = 0;
1415 } else
1416 rdev->disp_priority = radeon_disp_priority;
1417
1418}
1419
0783986a
AD		 1420/*
1421 * Allocate hdmi structs and determine register offsets
1422 */
1423static void radeon_afmt_init(struct radeon_device *rdev)
1424{
1425 int i;
1426
1427 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1428 rdev->mode_info.afmt[i] = NULL;
1429
b530602f
AD		 1430 if (ASIC_IS_NODCE(rdev)) {
1431 /* nothing to do */
0783986a 1432 } else if (ASIC_IS_DCE4(rdev)) {
a4d39e68
RM		 1433 static uint32_t eg_offsets[] = {
1434 EVERGREEN_CRTC0_REGISTER_OFFSET,
1435 EVERGREEN_CRTC1_REGISTER_OFFSET,
1436 EVERGREEN_CRTC2_REGISTER_OFFSET,
1437 EVERGREEN_CRTC3_REGISTER_OFFSET,
1438 EVERGREEN_CRTC4_REGISTER_OFFSET,
1439 EVERGREEN_CRTC5_REGISTER_OFFSET,
b530602f 1440 0x13830 - 0x7030,
a4d39e68
RM		 1441 };
1442 int num_afmt;
1443
b530602f
AD		 1444 /* DCE8 has 7 audio blocks tied to DIG encoders */
1445 /* DCE6 has 6 audio blocks tied to DIG encoders */
0783986a
AD		 1446 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1447 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
b530602f
AD		 1448 if (ASIC_IS_DCE8(rdev))
1449 num_afmt = 7;
1450 else if (ASIC_IS_DCE6(rdev))
1451 num_afmt = 6;
1452 else if (ASIC_IS_DCE5(rdev))
a4d39e68
RM		 1453 num_afmt = 6;
1454 else if (ASIC_IS_DCE41(rdev))
1455 num_afmt = 2;
1456 else /* DCE4 */
1457 num_afmt = 6;
1458
1459 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1460 for (i = 0; i < num_afmt; i++) {
1461 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1462 if (rdev->mode_info.afmt[i]) {
1463 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1464 rdev->mode_info.afmt[i]->id = i;
0783986a
AD		 1465 }
1466 }
1467 } else if (ASIC_IS_DCE3(rdev)) {
1468 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1469 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1470 if (rdev->mode_info.afmt[0]) {
1471 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1472 rdev->mode_info.afmt[0]->id = 0;
1473 }
1474 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1475 if (rdev->mode_info.afmt[1]) {
1476 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1477 rdev->mode_info.afmt[1]->id = 1;
1478 }
1479 } else if (ASIC_IS_DCE2(rdev)) {
1480 /* DCE2 has at least 1 routable audio block */
1481 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1482 if (rdev->mode_info.afmt[0]) {
1483 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1484 rdev->mode_info.afmt[0]->id = 0;
1485 }
1486 /* r6xx has 2 routable audio blocks */
1487 if (rdev->family >= CHIP_R600) {
1488 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1489 if (rdev->mode_info.afmt[1]) {
1490 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1491 rdev->mode_info.afmt[1]->id = 1;
1492 }
1493 }
1494 }
1495}
1496
1497static void radeon_afmt_fini(struct radeon_device *rdev)
1498{
1499 int i;
1500
1501 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1502 kfree(rdev->mode_info.afmt[i]);
1503 rdev->mode_info.afmt[i] = NULL;
1504 }
1505}
1506
771fe6b9
JG		 1507int radeon_modeset_init(struct radeon_device *rdev)
1508{
18917b60 1509 int i;
771fe6b9
JG		 1510 int ret;
1511
1512 drm_mode_config_init(rdev->ddev);
1513 rdev->mode_info.mode_config_initialized = true;
1514
e6ecefaa 1515 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
771fe6b9 1516
881dd74e
AD		 1517 if (ASIC_IS_DCE5(rdev)) {
1518 rdev->ddev->mode_config.max_width = 16384;
1519 rdev->ddev->mode_config.max_height = 16384;
1520 } else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9
JG		 1521 rdev->ddev->mode_config.max_width = 8192;
1522 rdev->ddev->mode_config.max_height = 8192;
1523 } else {
1524 rdev->ddev->mode_config.max_width = 4096;
1525 rdev->ddev->mode_config.max_height = 4096;
1526 }
1527
019d96cb
DA		 1528 rdev->ddev->mode_config.preferred_depth = 24;
1529 rdev->ddev->mode_config.prefer_shadow = 1;
1530
771fe6b9
JG		 1531 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1532
445282db
DA		 1533 ret = radeon_modeset_create_props(rdev);
1534 if (ret) {
1535 return ret;
1536 }
dfee5614 1537
f376b94f
AD		 1538 /* init i2c buses */
1539 radeon_i2c_init(rdev);
1540
3c537889
AD		 1541 /* check combios for a valid hardcoded EDID - Sun servers */
1542 if (!rdev->is_atom_bios) {
1543 /* check for hardcoded EDID in BIOS */
1544 radeon_combios_check_hardcoded_edid(rdev);
1545 }
1546
dfee5614 1547 /* allocate crtcs */
18917b60 1548 for (i = 0; i < rdev->num_crtc; i++) {
771fe6b9
JG		 1549 radeon_crtc_init(rdev->ddev, i);
1550 }
1551
1552 /* okay we should have all the bios connectors */
1553 ret = radeon_setup_enc_conn(rdev->ddev);
1554 if (!ret) {
1555 return ret;
1556 }
ac89af1e 1557
3fa47d9e
AD		 1558 /* init dig PHYs, disp eng pll */
1559 if (rdev->is_atom_bios) {
ac89af1e 1560 radeon_atom_encoder_init(rdev);
f3f1f03e 1561 radeon_atom_disp_eng_pll_init(rdev);
3fa47d9e 1562 }
ac89af1e 1563
d4877cf2
AD		 1564 /* initialize hpd */
1565 radeon_hpd_init(rdev);
38651674 1566
0783986a
AD		 1567 /* setup afmt */
1568 radeon_afmt_init(rdev);
1569
38651674 1570 radeon_fbdev_init(rdev);
eb1f8e4f
DA		 1571 drm_kms_helper_poll_init(rdev->ddev);
1572
6c7bccea
AD		 1573 if (rdev->pm.dpm_enabled) {
1574 /* do dpm late init */
1575 ret = radeon_pm_late_init(rdev);
1576 if (ret) {
1577 rdev->pm.dpm_enabled = false;
1578 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1579 }
1580 /* set the dpm state for PX since there won't be
1581 * a modeset to call this.
1582 */
1583 radeon_pm_compute_clocks(rdev);
1584 }
1585
771fe6b9
JG		 1586 return 0;
1587}
1588
1589void radeon_modeset_fini(struct radeon_device *rdev)
1590{
38651674 1591 radeon_fbdev_fini(rdev);
3c537889
AD		 1592 kfree(rdev->mode_info.bios_hardcoded_edid);
1593
771fe6b9 1594 if (rdev->mode_info.mode_config_initialized) {
0783986a 1595 radeon_afmt_fini(rdev);
eb1f8e4f 1596 drm_kms_helper_poll_fini(rdev->ddev);
d4877cf2 1597 radeon_hpd_fini(rdev);
771fe6b9
JG		 1598 drm_mode_config_cleanup(rdev->ddev);
1599 rdev->mode_info.mode_config_initialized = false;
1600 }
f376b94f
AD		 1601 /* free i2c buses */
1602 radeon_i2c_fini(rdev);
771fe6b9
JG		 1603}
1604
e811f5ae 1605static bool is_hdtv_mode(const struct drm_display_mode *mode)
039ed2d9
AD		 1606{
1607 /* try and guess if this is a tv or a monitor */
1608 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1609 (mode->vdisplay == 576) || /* 576p */
1610 (mode->vdisplay == 720) || /* 720p */
1611 (mode->vdisplay == 1080)) /* 1080p */
1612 return true;
1613 else
1614 return false;
1615}
1616
c93bb85b 1617bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
e811f5ae 1618 const struct drm_display_mode *mode,
c93bb85b 1619 struct drm_display_mode *adjusted_mode)
771fe6b9 1620{
c93bb85b 1621 struct drm_device *dev = crtc->dev;
5b1714d3 1622 struct radeon_device *rdev = dev->dev_private;
c93bb85b
JG		 1623 struct drm_encoder *encoder;
1624 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1625 struct radeon_encoder *radeon_encoder;
5b1714d3
AD		 1626 struct drm_connector *connector;
1627 struct radeon_connector *radeon_connector;
c93bb85b 1628 bool first = true;
d65d65b1
AD		 1629 u32 src_v = 1, dst_v = 1;
1630 u32 src_h = 1, dst_h = 1;
771fe6b9 1631
5b1714d3
AD		 1632 radeon_crtc->h_border = 0;
1633 radeon_crtc->v_border = 0;
1634
c93bb85b 1635 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
c93bb85b
JG		 1636 if (encoder->crtc != crtc)
1637 continue;
d65d65b1 1638 radeon_encoder = to_radeon_encoder(encoder);
5b1714d3
AD		 1639 connector = radeon_get_connector_for_encoder(encoder);
1640 radeon_connector = to_radeon_connector(connector);
1641
c93bb85b 1642 if (first) {
80297e87
AD		 1643 /* set scaling */
1644 if (radeon_encoder->rmx_type == RMX_OFF)
1645 radeon_crtc->rmx_type = RMX_OFF;
1646 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1647 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1648 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1649 else
1650 radeon_crtc->rmx_type = RMX_OFF;
1651 /* copy native mode */
c93bb85b 1652 memcpy(&radeon_crtc->native_mode,
80297e87 1653 &radeon_encoder->native_mode,
de2103e4 1654 sizeof(struct drm_display_mode));
ff32a59d
AD		 1655 src_v = crtc->mode.vdisplay;
1656 dst_v = radeon_crtc->native_mode.vdisplay;
1657 src_h = crtc->mode.hdisplay;
1658 dst_h = radeon_crtc->native_mode.hdisplay;
5b1714d3
AD		 1659
1660 /* fix up for overscan on hdmi */
1661 if (ASIC_IS_AVIVO(rdev) &&
e6db0da0 1662 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
5b1714d3
AD		 1663 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1664 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
039ed2d9
AD		 1665 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1666 is_hdtv_mode(mode)))) {
5bccf5e3
MG		 1667 if (radeon_encoder->underscan_hborder != 0)
1668 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1669 else
1670 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1671 if (radeon_encoder->underscan_vborder != 0)
1672 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1673 else
1674 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
5b1714d3
AD		 1675 radeon_crtc->rmx_type = RMX_FULL;
1676 src_v = crtc->mode.vdisplay;
1677 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1678 src_h = crtc->mode.hdisplay;
1679 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1680 }
c93bb85b
JG		 1681 first = false;
1682 } else {
1683 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1684 /* WARNING: Right now this can't happen but
1685 * in the future we need to check that scaling
d65d65b1 1686 * are consistent across different encoder
c93bb85b
JG		 1687 * (ie all encoder can work with the same
1688 * scaling).
1689 */
d65d65b1 1690 DRM_ERROR("Scaling not consistent across encoder.\n");
c93bb85b
JG		 1691 return false;
1692 }
771fe6b9
JG		 1693 }
1694 }
c93bb85b
JG		 1695 if (radeon_crtc->rmx_type != RMX_OFF) {
1696 fixed20_12 a, b;
d65d65b1
AD		 1697 a.full = dfixed_const(src_v);
1698 b.full = dfixed_const(dst_v);
68adac5e 1699 radeon_crtc->vsc.full = dfixed_div(a, b);
d65d65b1
AD		 1700 a.full = dfixed_const(src_h);
1701 b.full = dfixed_const(dst_h);
68adac5e 1702 radeon_crtc->hsc.full = dfixed_div(a, b);
771fe6b9 1703 } else {
68adac5e
BS		 1704 radeon_crtc->vsc.full = dfixed_const(1);
1705 radeon_crtc->hsc.full = dfixed_const(1);
771fe6b9 1706 }
c93bb85b 1707 return true;
771fe6b9 1708}
6383cf7d
MK		 1709
1710/*
d47abc58
MK		 1711 * Retrieve current video scanout position of crtc on a given gpu, and
1712 * an optional accurate timestamp of when query happened.
6383cf7d 1713 *
f5a80209 1714 * \param dev Device to query.
6383cf7d 1715 * \param crtc Crtc to query.
abca9e45 1716 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
6383cf7d
MK		 1717 * \param *vpos Location where vertical scanout position should be stored.
1718 * \param *hpos Location where horizontal scanout position should go.
d47abc58
MK		 1719 * \param *stime Target location for timestamp taken immediately before
1720 * scanout position query. Can be NULL to skip timestamp.
1721 * \param *etime Target location for timestamp taken immediately after
1722 * scanout position query. Can be NULL to skip timestamp.
6383cf7d
MK		 1723 *
1724 * Returns vpos as a positive number while in active scanout area.
1725 * Returns vpos as a negative number inside vblank, counting the number
1726 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1727 * until start of active scanout / end of vblank."
1728 *
1729 * \return Flags, or'ed together as follows:
1730 *
25985edc 1731 * DRM_SCANOUTPOS_VALID = Query successful.
f5a80209
MK		 1732 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1733 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
6383cf7d
MK		 1734 * this flag means that returned position may be offset by a constant but
1735 * unknown small number of scanlines wrt. real scanout position.
1736 *
1737 */
abca9e45
VS		 1738int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1739 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
6383cf7d
MK		 1740{
1741 u32 stat_crtc = 0, vbl = 0, position = 0;
1742 int vbl_start, vbl_end, vtotal, ret = 0;
1743 bool in_vbl = true;
1744
f5a80209
MK		 1745 struct radeon_device *rdev = dev->dev_private;
1746
d47abc58
MK		 1747 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1748
1749 /* Get optional system timestamp before query. */
1750 if (stime)
1751 *stime = ktime_get();
1752
6383cf7d
MK		 1753 if (ASIC_IS_DCE4(rdev)) {
1754 if (crtc == 0) {
1755 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1756 EVERGREEN_CRTC0_REGISTER_OFFSET);
1757 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1758 EVERGREEN_CRTC0_REGISTER_OFFSET);
f5a80209 1759 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1760 }
1761 if (crtc == 1) {
1762 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1763 EVERGREEN_CRTC1_REGISTER_OFFSET);
1764 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1765 EVERGREEN_CRTC1_REGISTER_OFFSET);
f5a80209 1766 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1767 }
1768 if (crtc == 2) {
1769 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1770 EVERGREEN_CRTC2_REGISTER_OFFSET);
1771 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1772 EVERGREEN_CRTC2_REGISTER_OFFSET);
f5a80209 1773 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1774 }
1775 if (crtc == 3) {
1776 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1777 EVERGREEN_CRTC3_REGISTER_OFFSET);
1778 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1779 EVERGREEN_CRTC3_REGISTER_OFFSET);
f5a80209 1780 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1781 }
1782 if (crtc == 4) {
1783 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1784 EVERGREEN_CRTC4_REGISTER_OFFSET);
1785 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1786 EVERGREEN_CRTC4_REGISTER_OFFSET);
f5a80209 1787 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1788 }
1789 if (crtc == 5) {
1790 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1791 EVERGREEN_CRTC5_REGISTER_OFFSET);
1792 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1793 EVERGREEN_CRTC5_REGISTER_OFFSET);
f5a80209 1794 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1795 }
1796 } else if (ASIC_IS_AVIVO(rdev)) {
1797 if (crtc == 0) {
1798 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1799 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
f5a80209 1800 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1801 }
1802 if (crtc == 1) {
1803 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1804 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
f5a80209 1805 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1806 }
1807 } else {
1808 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1809 if (crtc == 0) {
1810 /* Assume vbl_end == 0, get vbl_start from
1811 * upper 16 bits.
1812 */
1813 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1814 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1815 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1816 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1817 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1818 if (!(stat_crtc & 1))
1819 in_vbl = false;
1820
f5a80209 1821 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1822 }
1823 if (crtc == 1) {
1824 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1825 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1826 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1827 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1828 if (!(stat_crtc & 1))
1829 in_vbl = false;
1830
f5a80209 1831 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1832 }
1833 }
1834
d47abc58
MK		 1835 /* Get optional system timestamp after query. */
1836 if (etime)
1837 *etime = ktime_get();
1838
1839 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1840
6383cf7d
MK		 1841 /* Decode into vertical and horizontal scanout position. */
1842 *vpos = position & 0x1fff;
1843 *hpos = (position >> 16) & 0x1fff;
1844
1845 /* Valid vblank area boundaries from gpu retrieved? */
1846 if (vbl > 0) {
1847 /* Yes: Decode. */
f5a80209 1848 ret |= DRM_SCANOUTPOS_ACCURATE;
6383cf7d
MK		 1849 vbl_start = vbl & 0x1fff;
1850 vbl_end = (vbl >> 16) & 0x1fff;
1851 }
1852 else {
1853 /* No: Fake something reasonable which gives at least ok results. */
f5a80209 1854 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
6383cf7d
MK		 1855 vbl_end = 0;
1856 }
1857
1858 /* Test scanout position against vblank region. */
1859 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1860 in_vbl = false;
1861
1862 /* Check if inside vblank area and apply corrective offsets:
1863 * vpos will then be >=0 in video scanout area, but negative
1864 * within vblank area, counting down the number of lines until
1865 * start of scanout.
1866 */
1867
1868 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1869 if (in_vbl && (*vpos >= vbl_start)) {
f5a80209 1870 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
6383cf7d
MK		 1871 *vpos = *vpos - vtotal;
1872 }
1873
1874 /* Correct for shifted end of vbl at vbl_end. */
1875 *vpos = *vpos - vbl_end;
1876
1877 /* In vblank? */
1878 if (in_vbl)
f5a80209 1879 ret |= DRM_SCANOUTPOS_INVBL;
6383cf7d 1880
8072bfa6
VS		 1881 /* Is vpos outside nominal vblank area, but less than
1882 * 1/100 of a frame height away from start of vblank?
1883 * If so, assume this isn't a massively delayed vblank
1884 * interrupt, but a vblank interrupt that fired a few
1885 * microseconds before true start of vblank. Compensate
1886 * by adding a full frame duration to the final timestamp.
1887 * Happens, e.g., on ATI R500, R600.
1888 *
1889 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1890 */
1891 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1892 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1893 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1894
1895 if (vbl_start - *vpos < vtotal / 100) {
1896 *vpos -= vtotal;
1897
1898 /* Signal this correction as "applied". */
1899 ret |= 0x8;
1900 }
1901 }
1902
6383cf7d
MK		 1903 return ret;
1904}
Linux 6.x block layer and io_uring tree(s)