Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/console.h> | |
29 | #include <drm/drmP.h> | |
30 | #include <drm/drm_crtc_helper.h> | |
31 | #include <drm/radeon_drm.h> | |
28d52043 | 32 | #include <linux/vgaarb.h> |
6a9ee8af | 33 | #include <linux/vga_switcheroo.h> |
771fe6b9 JG |
34 | #include "radeon_reg.h" |
35 | #include "radeon.h" | |
771fe6b9 JG |
36 | #include "atom.h" |
37 | ||
b1e3a6d1 MD |
38 | /* |
39 | * Clear GPU surface registers. | |
40 | */ | |
3ce0a23d | 41 | void radeon_surface_init(struct radeon_device *rdev) |
b1e3a6d1 MD |
42 | { |
43 | /* FIXME: check this out */ | |
44 | if (rdev->family < CHIP_R600) { | |
45 | int i; | |
46 | ||
550e2d92 DA |
47 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
48 | if (rdev->surface_regs[i].bo) | |
49 | radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); | |
50 | else | |
51 | radeon_clear_surface_reg(rdev, i); | |
b1e3a6d1 | 52 | } |
e024e110 DA |
53 | /* enable surfaces */ |
54 | WREG32(RADEON_SURFACE_CNTL, 0); | |
b1e3a6d1 MD |
55 | } |
56 | } | |
57 | ||
771fe6b9 JG |
58 | /* |
59 | * GPU scratch registers helpers function. | |
60 | */ | |
3ce0a23d | 61 | void radeon_scratch_init(struct radeon_device *rdev) |
771fe6b9 JG |
62 | { |
63 | int i; | |
64 | ||
65 | /* FIXME: check this out */ | |
66 | if (rdev->family < CHIP_R300) { | |
67 | rdev->scratch.num_reg = 5; | |
68 | } else { | |
69 | rdev->scratch.num_reg = 7; | |
70 | } | |
71 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
72 | rdev->scratch.free[i] = true; | |
73 | rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); | |
74 | } | |
75 | } | |
76 | ||
77 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) | |
78 | { | |
79 | int i; | |
80 | ||
81 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
82 | if (rdev->scratch.free[i]) { | |
83 | rdev->scratch.free[i] = false; | |
84 | *reg = rdev->scratch.reg[i]; | |
85 | return 0; | |
86 | } | |
87 | } | |
88 | return -EINVAL; | |
89 | } | |
90 | ||
91 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) | |
92 | { | |
93 | int i; | |
94 | ||
95 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
96 | if (rdev->scratch.reg[i] == reg) { | |
97 | rdev->scratch.free[i] = true; | |
98 | return; | |
99 | } | |
100 | } | |
101 | } | |
102 | ||
d594e46a JG |
103 | /** |
104 | * radeon_vram_location - try to find VRAM location | |
105 | * @rdev: radeon device structure holding all necessary informations | |
106 | * @mc: memory controller structure holding memory informations | |
107 | * @base: base address at which to put VRAM | |
108 | * | |
109 | * Function will place try to place VRAM at base address provided | |
110 | * as parameter (which is so far either PCI aperture address or | |
111 | * for IGP TOM base address). | |
112 | * | |
113 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
114 | * address space then we limit the VRAM size to the aperture. | |
115 | * | |
116 | * If we are using AGP and if the AGP aperture doesn't allow us to have | |
117 | * room for all the VRAM than we restrict the VRAM to the PCI aperture | |
118 | * size and print a warning. | |
119 | * | |
120 | * This function will never fails, worst case are limiting VRAM. | |
121 | * | |
122 | * Note: GTT start, end, size should be initialized before calling this | |
123 | * function on AGP platform. | |
124 | * | |
125 | * Note: We don't explictly enforce VRAM start to be aligned on VRAM size, | |
126 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
127 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
128 | * not IGP. | |
129 | * | |
130 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
131 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
132 | * Novell bug 204882 + along with lots of ubuntu ones | |
133 | * | |
134 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
135 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
136 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
137 | * ones) | |
138 | * | |
139 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
140 | * explicitly check for that thought. | |
141 | * | |
142 | * FIXME: when reducing VRAM size align new size on power of 2. | |
771fe6b9 | 143 | */ |
d594e46a | 144 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
771fe6b9 | 145 | { |
d594e46a JG |
146 | mc->vram_start = base; |
147 | if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { | |
148 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); | |
149 | mc->real_vram_size = mc->aper_size; | |
150 | mc->mc_vram_size = mc->aper_size; | |
151 | } | |
152 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
153 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) { | |
154 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); | |
155 | mc->real_vram_size = mc->aper_size; | |
156 | mc->mc_vram_size = mc->aper_size; | |
157 | } | |
158 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
159 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", | |
160 | mc->mc_vram_size >> 20, mc->vram_start, | |
161 | mc->vram_end, mc->real_vram_size >> 20); | |
162 | } | |
771fe6b9 | 163 | |
d594e46a JG |
164 | /** |
165 | * radeon_gtt_location - try to find GTT location | |
166 | * @rdev: radeon device structure holding all necessary informations | |
167 | * @mc: memory controller structure holding memory informations | |
168 | * | |
169 | * Function will place try to place GTT before or after VRAM. | |
170 | * | |
171 | * If GTT size is bigger than space left then we ajust GTT size. | |
172 | * Thus function will never fails. | |
173 | * | |
174 | * FIXME: when reducing GTT size align new size on power of 2. | |
175 | */ | |
176 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) | |
177 | { | |
178 | u64 size_af, size_bf; | |
179 | ||
180 | size_af = 0xFFFFFFFF - mc->vram_end; | |
181 | size_bf = mc->vram_start; | |
182 | if (size_bf > size_af) { | |
183 | if (mc->gtt_size > size_bf) { | |
184 | dev_warn(rdev->dev, "limiting GTT\n"); | |
185 | mc->gtt_size = size_bf; | |
771fe6b9 | 186 | } |
d594e46a | 187 | mc->gtt_start = mc->vram_start - mc->gtt_size; |
771fe6b9 | 188 | } else { |
d594e46a JG |
189 | if (mc->gtt_size > size_af) { |
190 | dev_warn(rdev->dev, "limiting GTT\n"); | |
191 | mc->gtt_size = size_af; | |
192 | } | |
193 | mc->gtt_start = mc->vram_end + 1; | |
771fe6b9 | 194 | } |
d594e46a JG |
195 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
196 | dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", | |
197 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); | |
771fe6b9 JG |
198 | } |
199 | ||
771fe6b9 JG |
200 | /* |
201 | * GPU helpers function. | |
202 | */ | |
9f022ddf | 203 | bool radeon_card_posted(struct radeon_device *rdev) |
771fe6b9 JG |
204 | { |
205 | uint32_t reg; | |
206 | ||
207 | /* first check CRTCs */ | |
bcc1c2a1 AD |
208 | if (ASIC_IS_DCE4(rdev)) { |
209 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | | |
210 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | | |
211 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | | |
212 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | | |
213 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | | |
214 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
215 | if (reg & EVERGREEN_CRTC_MASTER_EN) | |
216 | return true; | |
217 | } else if (ASIC_IS_AVIVO(rdev)) { | |
771fe6b9 JG |
218 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
219 | RREG32(AVIVO_D2CRTC_CONTROL); | |
220 | if (reg & AVIVO_CRTC_EN) { | |
221 | return true; | |
222 | } | |
223 | } else { | |
224 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | | |
225 | RREG32(RADEON_CRTC2_GEN_CNTL); | |
226 | if (reg & RADEON_CRTC_EN) { | |
227 | return true; | |
228 | } | |
229 | } | |
230 | ||
231 | /* then check MEM_SIZE, in case the crtcs are off */ | |
232 | if (rdev->family >= CHIP_R600) | |
233 | reg = RREG32(R600_CONFIG_MEMSIZE); | |
234 | else | |
235 | reg = RREG32(RADEON_CONFIG_MEMSIZE); | |
236 | ||
237 | if (reg) | |
238 | return true; | |
239 | ||
240 | return false; | |
241 | ||
242 | } | |
243 | ||
f47299c5 AD |
244 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
245 | { | |
246 | fixed20_12 a; | |
247 | u32 sclk, mclk; | |
248 | ||
249 | if (rdev->flags & RADEON_IS_IGP) { | |
250 | sclk = radeon_get_engine_clock(rdev); | |
251 | mclk = rdev->clock.default_mclk; | |
252 | ||
253 | a.full = rfixed_const(100); | |
254 | rdev->pm.sclk.full = rfixed_const(sclk); | |
255 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | |
256 | rdev->pm.mclk.full = rfixed_const(mclk); | |
257 | rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a); | |
258 | ||
259 | a.full = rfixed_const(16); | |
260 | /* core_bandwidth = sclk(Mhz) * 16 */ | |
261 | rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a); | |
262 | } else { | |
263 | sclk = radeon_get_engine_clock(rdev); | |
264 | mclk = radeon_get_memory_clock(rdev); | |
265 | ||
266 | a.full = rfixed_const(100); | |
267 | rdev->pm.sclk.full = rfixed_const(sclk); | |
268 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | |
269 | rdev->pm.mclk.full = rfixed_const(mclk); | |
270 | rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a); | |
271 | } | |
272 | } | |
273 | ||
72542d77 DA |
274 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
275 | { | |
276 | if (radeon_card_posted(rdev)) | |
277 | return true; | |
278 | ||
279 | if (rdev->bios) { | |
280 | DRM_INFO("GPU not posted. posting now...\n"); | |
281 | if (rdev->is_atom_bios) | |
282 | atom_asic_init(rdev->mode_info.atom_context); | |
283 | else | |
284 | radeon_combios_asic_init(rdev->ddev); | |
285 | return true; | |
286 | } else { | |
287 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
288 | return false; | |
289 | } | |
290 | } | |
291 | ||
3ce0a23d JG |
292 | int radeon_dummy_page_init(struct radeon_device *rdev) |
293 | { | |
82568565 DA |
294 | if (rdev->dummy_page.page) |
295 | return 0; | |
3ce0a23d JG |
296 | rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); |
297 | if (rdev->dummy_page.page == NULL) | |
298 | return -ENOMEM; | |
299 | rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, | |
300 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
301 | if (!rdev->dummy_page.addr) { | |
302 | __free_page(rdev->dummy_page.page); | |
303 | rdev->dummy_page.page = NULL; | |
304 | return -ENOMEM; | |
305 | } | |
306 | return 0; | |
307 | } | |
308 | ||
309 | void radeon_dummy_page_fini(struct radeon_device *rdev) | |
310 | { | |
311 | if (rdev->dummy_page.page == NULL) | |
312 | return; | |
313 | pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, | |
314 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
315 | __free_page(rdev->dummy_page.page); | |
316 | rdev->dummy_page.page = NULL; | |
317 | } | |
318 | ||
771fe6b9 | 319 | |
771fe6b9 JG |
320 | /* ATOM accessor methods */ |
321 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
322 | { | |
323 | struct radeon_device *rdev = info->dev->dev_private; | |
324 | uint32_t r; | |
325 | ||
326 | r = rdev->pll_rreg(rdev, reg); | |
327 | return r; | |
328 | } | |
329 | ||
330 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
331 | { | |
332 | struct radeon_device *rdev = info->dev->dev_private; | |
333 | ||
334 | rdev->pll_wreg(rdev, reg, val); | |
335 | } | |
336 | ||
337 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
338 | { | |
339 | struct radeon_device *rdev = info->dev->dev_private; | |
340 | uint32_t r; | |
341 | ||
342 | r = rdev->mc_rreg(rdev, reg); | |
343 | return r; | |
344 | } | |
345 | ||
346 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
347 | { | |
348 | struct radeon_device *rdev = info->dev->dev_private; | |
349 | ||
350 | rdev->mc_wreg(rdev, reg, val); | |
351 | } | |
352 | ||
353 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
354 | { | |
355 | struct radeon_device *rdev = info->dev->dev_private; | |
356 | ||
357 | WREG32(reg*4, val); | |
358 | } | |
359 | ||
360 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
361 | { | |
362 | struct radeon_device *rdev = info->dev->dev_private; | |
363 | uint32_t r; | |
364 | ||
365 | r = RREG32(reg*4); | |
366 | return r; | |
367 | } | |
368 | ||
771fe6b9 JG |
369 | int radeon_atombios_init(struct radeon_device *rdev) |
370 | { | |
61c4b24b MF |
371 | struct card_info *atom_card_info = |
372 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
373 | ||
374 | if (!atom_card_info) | |
375 | return -ENOMEM; | |
376 | ||
377 | rdev->mode_info.atom_card_info = atom_card_info; | |
378 | atom_card_info->dev = rdev->ddev; | |
379 | atom_card_info->reg_read = cail_reg_read; | |
380 | atom_card_info->reg_write = cail_reg_write; | |
381 | atom_card_info->mc_read = cail_mc_read; | |
382 | atom_card_info->mc_write = cail_mc_write; | |
383 | atom_card_info->pll_read = cail_pll_read; | |
384 | atom_card_info->pll_write = cail_pll_write; | |
385 | ||
386 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); | |
c31ad97f | 387 | mutex_init(&rdev->mode_info.atom_context->mutex); |
771fe6b9 | 388 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
d904ef9b | 389 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
771fe6b9 JG |
390 | return 0; |
391 | } | |
392 | ||
393 | void radeon_atombios_fini(struct radeon_device *rdev) | |
394 | { | |
4a04a844 JG |
395 | if (rdev->mode_info.atom_context) { |
396 | kfree(rdev->mode_info.atom_context->scratch); | |
397 | kfree(rdev->mode_info.atom_context); | |
398 | } | |
61c4b24b | 399 | kfree(rdev->mode_info.atom_card_info); |
771fe6b9 JG |
400 | } |
401 | ||
402 | int radeon_combios_init(struct radeon_device *rdev) | |
403 | { | |
404 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); | |
405 | return 0; | |
406 | } | |
407 | ||
408 | void radeon_combios_fini(struct radeon_device *rdev) | |
409 | { | |
410 | } | |
411 | ||
28d52043 DA |
412 | /* if we get transitioned to only one device, tak VGA back */ |
413 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) | |
414 | { | |
415 | struct radeon_device *rdev = cookie; | |
28d52043 DA |
416 | radeon_vga_set_state(rdev, state); |
417 | if (state) | |
418 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
419 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
420 | else | |
421 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
422 | } | |
c1176d6f | 423 | |
36421338 JG |
424 | void radeon_check_arguments(struct radeon_device *rdev) |
425 | { | |
426 | /* vramlimit must be a power of two */ | |
427 | switch (radeon_vram_limit) { | |
428 | case 0: | |
429 | case 4: | |
430 | case 8: | |
431 | case 16: | |
432 | case 32: | |
433 | case 64: | |
434 | case 128: | |
435 | case 256: | |
436 | case 512: | |
437 | case 1024: | |
438 | case 2048: | |
439 | case 4096: | |
440 | break; | |
441 | default: | |
442 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", | |
443 | radeon_vram_limit); | |
444 | radeon_vram_limit = 0; | |
445 | break; | |
446 | } | |
447 | radeon_vram_limit = radeon_vram_limit << 20; | |
448 | /* gtt size must be power of two and greater or equal to 32M */ | |
449 | switch (radeon_gart_size) { | |
450 | case 4: | |
451 | case 8: | |
452 | case 16: | |
453 | dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", | |
454 | radeon_gart_size); | |
455 | radeon_gart_size = 512; | |
456 | break; | |
457 | case 32: | |
458 | case 64: | |
459 | case 128: | |
460 | case 256: | |
461 | case 512: | |
462 | case 1024: | |
463 | case 2048: | |
464 | case 4096: | |
465 | break; | |
466 | default: | |
467 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", | |
468 | radeon_gart_size); | |
469 | radeon_gart_size = 512; | |
470 | break; | |
471 | } | |
472 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
473 | /* AGP mode can only be -1, 1, 2, 4, 8 */ | |
474 | switch (radeon_agpmode) { | |
475 | case -1: | |
476 | case 0: | |
477 | case 1: | |
478 | case 2: | |
479 | case 4: | |
480 | case 8: | |
481 | break; | |
482 | default: | |
483 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " | |
484 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); | |
485 | radeon_agpmode = 0; | |
486 | break; | |
487 | } | |
488 | } | |
489 | ||
6a9ee8af DA |
490 | static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
491 | { | |
492 | struct drm_device *dev = pci_get_drvdata(pdev); | |
493 | struct radeon_device *rdev = dev->dev_private; | |
494 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
495 | if (state == VGA_SWITCHEROO_ON) { | |
496 | printk(KERN_INFO "radeon: switched on\n"); | |
497 | /* don't suspend or resume card normally */ | |
498 | rdev->powered_down = false; | |
499 | radeon_resume_kms(dev); | |
500 | } else { | |
501 | printk(KERN_INFO "radeon: switched off\n"); | |
502 | radeon_suspend_kms(dev, pmm); | |
503 | /* don't suspend or resume card normally */ | |
504 | rdev->powered_down = true; | |
505 | } | |
506 | } | |
507 | ||
508 | static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) | |
509 | { | |
510 | struct drm_device *dev = pci_get_drvdata(pdev); | |
511 | bool can_switch; | |
512 | ||
513 | spin_lock(&dev->count_lock); | |
514 | can_switch = (dev->open_count == 0); | |
515 | spin_unlock(&dev->count_lock); | |
516 | return can_switch; | |
517 | } | |
518 | ||
519 | ||
771fe6b9 JG |
520 | int radeon_device_init(struct radeon_device *rdev, |
521 | struct drm_device *ddev, | |
522 | struct pci_dev *pdev, | |
523 | uint32_t flags) | |
524 | { | |
6cf8a3f5 | 525 | int r; |
ad49f501 | 526 | int dma_bits; |
771fe6b9 JG |
527 | |
528 | DRM_INFO("radeon: Initializing kernel modesetting.\n"); | |
529 | rdev->shutdown = false; | |
9f022ddf | 530 | rdev->dev = &pdev->dev; |
771fe6b9 JG |
531 | rdev->ddev = ddev; |
532 | rdev->pdev = pdev; | |
533 | rdev->flags = flags; | |
534 | rdev->family = flags & RADEON_FAMILY_MASK; | |
535 | rdev->is_atom_bios = false; | |
536 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; | |
537 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
538 | rdev->gpu_lockup = false; | |
733289c2 | 539 | rdev->accel_working = false; |
771fe6b9 JG |
540 | /* mutex initialization are all done here so we |
541 | * can recall function without having locking issues */ | |
542 | mutex_init(&rdev->cs_mutex); | |
543 | mutex_init(&rdev->ib_pool.mutex); | |
544 | mutex_init(&rdev->cp.mutex); | |
40bacf16 | 545 | mutex_init(&rdev->dc_hw_i2c_mutex); |
d8f60cfc AD |
546 | if (rdev->family >= CHIP_R600) |
547 | spin_lock_init(&rdev->ih.lock); | |
4c788679 | 548 | mutex_init(&rdev->gem.mutex); |
c913e23a | 549 | mutex_init(&rdev->pm.mutex); |
771fe6b9 | 550 | rwlock_init(&rdev->fence_drv.lock); |
9f022ddf | 551 | INIT_LIST_HEAD(&rdev->gem.objects); |
73a6d3fc | 552 | init_waitqueue_head(&rdev->irq.vblank_queue); |
771fe6b9 | 553 | |
d4877cf2 AD |
554 | /* setup workqueue */ |
555 | rdev->wq = create_workqueue("radeon"); | |
556 | if (rdev->wq == NULL) | |
557 | return -ENOMEM; | |
558 | ||
4aac0473 JG |
559 | /* Set asic functions */ |
560 | r = radeon_asic_init(rdev); | |
36421338 | 561 | if (r) |
4aac0473 | 562 | return r; |
36421338 | 563 | radeon_check_arguments(rdev); |
4aac0473 | 564 | |
f95df9ca AD |
565 | /* all of the newer IGP chips have an internal gart |
566 | * However some rs4xx report as AGP, so remove that here. | |
567 | */ | |
568 | if ((rdev->family >= CHIP_RS400) && | |
569 | (rdev->flags & RADEON_IS_IGP)) { | |
570 | rdev->flags &= ~RADEON_IS_AGP; | |
571 | } | |
572 | ||
30256a3f | 573 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
b574f251 | 574 | radeon_agp_disable(rdev); |
771fe6b9 JG |
575 | } |
576 | ||
ad49f501 DA |
577 | /* set DMA mask + need_dma32 flags. |
578 | * PCIE - can handle 40-bits. | |
579 | * IGP - can handle 40-bits (in theory) | |
580 | * AGP - generally dma32 is safest | |
581 | * PCI - only dma32 | |
582 | */ | |
583 | rdev->need_dma32 = false; | |
584 | if (rdev->flags & RADEON_IS_AGP) | |
585 | rdev->need_dma32 = true; | |
586 | if (rdev->flags & RADEON_IS_PCI) | |
587 | rdev->need_dma32 = true; | |
588 | ||
589 | dma_bits = rdev->need_dma32 ? 32 : 40; | |
590 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); | |
771fe6b9 JG |
591 | if (r) { |
592 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); | |
593 | } | |
594 | ||
595 | /* Registers mapping */ | |
596 | /* TODO: block userspace mapping of io register */ | |
597 | rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2); | |
598 | rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2); | |
599 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); | |
600 | if (rdev->rmmio == NULL) { | |
601 | return -ENOMEM; | |
602 | } | |
603 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); | |
604 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); | |
605 | ||
28d52043 | 606 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
93239ea1 DA |
607 | /* this will fail for cards that aren't VGA class devices, just |
608 | * ignore it */ | |
609 | vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); | |
6a9ee8af DA |
610 | vga_switcheroo_register_client(rdev->pdev, |
611 | radeon_switcheroo_set_state, | |
612 | radeon_switcheroo_can_switch); | |
28d52043 | 613 | |
3ce0a23d | 614 | r = radeon_init(rdev); |
b574f251 | 615 | if (r) |
3ce0a23d | 616 | return r; |
3ce0a23d | 617 | |
b574f251 JG |
618 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
619 | /* Acceleration not working on AGP card try again | |
620 | * with fallback to PCI or PCIE GART | |
621 | */ | |
1a029b76 | 622 | radeon_gpu_reset(rdev); |
b574f251 JG |
623 | radeon_fini(rdev); |
624 | radeon_agp_disable(rdev); | |
625 | r = radeon_init(rdev); | |
4aac0473 JG |
626 | if (r) |
627 | return r; | |
771fe6b9 | 628 | } |
ecc0b326 MD |
629 | if (radeon_testing) { |
630 | radeon_test_moves(rdev); | |
631 | } | |
771fe6b9 JG |
632 | if (radeon_benchmarking) { |
633 | radeon_benchmark(rdev); | |
634 | } | |
6cf8a3f5 | 635 | return 0; |
771fe6b9 JG |
636 | } |
637 | ||
638 | void radeon_device_fini(struct radeon_device *rdev) | |
639 | { | |
771fe6b9 JG |
640 | DRM_INFO("radeon: finishing device.\n"); |
641 | rdev->shutdown = true; | |
62a8ea3f | 642 | radeon_fini(rdev); |
d4877cf2 | 643 | destroy_workqueue(rdev->wq); |
6a9ee8af | 644 | vga_switcheroo_unregister_client(rdev->pdev); |
c1176d6f | 645 | vga_client_register(rdev->pdev, NULL, NULL, NULL); |
771fe6b9 JG |
646 | iounmap(rdev->rmmio); |
647 | rdev->rmmio = NULL; | |
648 | } | |
649 | ||
650 | ||
651 | /* | |
652 | * Suspend & resume. | |
653 | */ | |
654 | int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) | |
655 | { | |
875c1866 | 656 | struct radeon_device *rdev; |
771fe6b9 | 657 | struct drm_crtc *crtc; |
4c788679 | 658 | int r; |
771fe6b9 | 659 | |
875c1866 | 660 | if (dev == NULL || dev->dev_private == NULL) { |
771fe6b9 JG |
661 | return -ENODEV; |
662 | } | |
663 | if (state.event == PM_EVENT_PRETHAW) { | |
664 | return 0; | |
665 | } | |
875c1866 DJ |
666 | rdev = dev->dev_private; |
667 | ||
6a9ee8af DA |
668 | if (rdev->powered_down) |
669 | return 0; | |
771fe6b9 JG |
670 | /* unpin the front buffers */ |
671 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
672 | struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); | |
4c788679 | 673 | struct radeon_bo *robj; |
771fe6b9 JG |
674 | |
675 | if (rfb == NULL || rfb->obj == NULL) { | |
676 | continue; | |
677 | } | |
678 | robj = rfb->obj->driver_private; | |
4c788679 JG |
679 | if (robj != rdev->fbdev_rbo) { |
680 | r = radeon_bo_reserve(robj, false); | |
681 | if (unlikely(r == 0)) { | |
682 | radeon_bo_unpin(robj); | |
683 | radeon_bo_unreserve(robj); | |
684 | } | |
771fe6b9 JG |
685 | } |
686 | } | |
687 | /* evict vram memory */ | |
4c788679 | 688 | radeon_bo_evict_vram(rdev); |
771fe6b9 JG |
689 | /* wait for gpu to finish processing current batch */ |
690 | radeon_fence_wait_last(rdev); | |
691 | ||
f657c2a7 YZ |
692 | radeon_save_bios_scratch_regs(rdev); |
693 | ||
62a8ea3f | 694 | radeon_suspend(rdev); |
d4877cf2 | 695 | radeon_hpd_fini(rdev); |
771fe6b9 | 696 | /* evict remaining vram memory */ |
4c788679 | 697 | radeon_bo_evict_vram(rdev); |
771fe6b9 | 698 | |
771fe6b9 JG |
699 | pci_save_state(dev->pdev); |
700 | if (state.event == PM_EVENT_SUSPEND) { | |
701 | /* Shut down the device */ | |
702 | pci_disable_device(dev->pdev); | |
703 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
704 | } | |
705 | acquire_console_sem(); | |
706 | fb_set_suspend(rdev->fbdev_info, 1); | |
707 | release_console_sem(); | |
708 | return 0; | |
709 | } | |
710 | ||
711 | int radeon_resume_kms(struct drm_device *dev) | |
712 | { | |
713 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 | 714 | |
6a9ee8af DA |
715 | if (rdev->powered_down) |
716 | return 0; | |
717 | ||
771fe6b9 JG |
718 | acquire_console_sem(); |
719 | pci_set_power_state(dev->pdev, PCI_D0); | |
720 | pci_restore_state(dev->pdev); | |
721 | if (pci_enable_device(dev->pdev)) { | |
722 | release_console_sem(); | |
723 | return -1; | |
724 | } | |
725 | pci_set_master(dev->pdev); | |
0ebf1717 DA |
726 | /* resume AGP if in use */ |
727 | radeon_agp_resume(rdev); | |
62a8ea3f | 728 | radeon_resume(rdev); |
f657c2a7 | 729 | radeon_restore_bios_scratch_regs(rdev); |
771fe6b9 JG |
730 | fb_set_suspend(rdev->fbdev_info, 0); |
731 | release_console_sem(); | |
732 | ||
d4877cf2 AD |
733 | /* reset hpd state */ |
734 | radeon_hpd_init(rdev); | |
771fe6b9 JG |
735 | /* blat the mode back in */ |
736 | drm_helper_resume_force_mode(dev); | |
737 | return 0; | |
738 | } | |
739 | ||
740 | ||
741 | /* | |
742 | * Debugfs | |
743 | */ | |
744 | struct radeon_debugfs { | |
745 | struct drm_info_list *files; | |
746 | unsigned num_files; | |
747 | }; | |
748 | static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; | |
749 | static unsigned _radeon_debugfs_count = 0; | |
750 | ||
751 | int radeon_debugfs_add_files(struct radeon_device *rdev, | |
752 | struct drm_info_list *files, | |
753 | unsigned nfiles) | |
754 | { | |
755 | unsigned i; | |
756 | ||
757 | for (i = 0; i < _radeon_debugfs_count; i++) { | |
758 | if (_radeon_debugfs[i].files == files) { | |
759 | /* Already registered */ | |
760 | return 0; | |
761 | } | |
762 | } | |
763 | if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { | |
764 | DRM_ERROR("Reached maximum number of debugfs files.\n"); | |
765 | DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); | |
766 | return -EINVAL; | |
767 | } | |
768 | _radeon_debugfs[_radeon_debugfs_count].files = files; | |
769 | _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; | |
770 | _radeon_debugfs_count++; | |
771 | #if defined(CONFIG_DEBUG_FS) | |
772 | drm_debugfs_create_files(files, nfiles, | |
773 | rdev->ddev->control->debugfs_root, | |
774 | rdev->ddev->control); | |
775 | drm_debugfs_create_files(files, nfiles, | |
776 | rdev->ddev->primary->debugfs_root, | |
777 | rdev->ddev->primary); | |
778 | #endif | |
779 | return 0; | |
780 | } | |
781 | ||
782 | #if defined(CONFIG_DEBUG_FS) | |
783 | int radeon_debugfs_init(struct drm_minor *minor) | |
784 | { | |
785 | return 0; | |
786 | } | |
787 | ||
788 | void radeon_debugfs_cleanup(struct drm_minor *minor) | |
789 | { | |
790 | unsigned i; | |
791 | ||
792 | for (i = 0; i < _radeon_debugfs_count; i++) { | |
793 | drm_debugfs_remove_files(_radeon_debugfs[i].files, | |
794 | _radeon_debugfs[i].num_files, minor); | |
795 | } | |
796 | } | |
797 | #endif |