Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
4330441a | 27 | #include <linux/list_sort.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
30 | #include "radeon_reg.h" |
31 | #include "radeon.h" | |
860024e5 | 32 | #include "radeon_trace.h" |
771fe6b9 | 33 | |
c9b76548 MO |
34 | #define RADEON_CS_MAX_PRIORITY 32u |
35 | #define RADEON_CS_NUM_BUCKETS (RADEON_CS_MAX_PRIORITY + 1) | |
36 | ||
37 | /* This is based on the bucket sort with O(n) time complexity. | |
38 | * An item with priority "i" is added to bucket[i]. The lists are then | |
39 | * concatenated in descending order. | |
40 | */ | |
41 | struct radeon_cs_buckets { | |
42 | struct list_head bucket[RADEON_CS_NUM_BUCKETS]; | |
43 | }; | |
44 | ||
45 | static void radeon_cs_buckets_init(struct radeon_cs_buckets *b) | |
46 | { | |
47 | unsigned i; | |
48 | ||
49 | for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) | |
50 | INIT_LIST_HEAD(&b->bucket[i]); | |
51 | } | |
52 | ||
53 | static void radeon_cs_buckets_add(struct radeon_cs_buckets *b, | |
54 | struct list_head *item, unsigned priority) | |
55 | { | |
56 | /* Since buffers which appear sooner in the relocation list are | |
57 | * likely to be used more often than buffers which appear later | |
58 | * in the list, the sort mustn't change the ordering of buffers | |
59 | * with the same priority, i.e. it must be stable. | |
60 | */ | |
61 | list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]); | |
62 | } | |
63 | ||
64 | static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b, | |
65 | struct list_head *out_list) | |
66 | { | |
67 | unsigned i; | |
68 | ||
69 | /* Connect the sorted buckets in the output list. */ | |
70 | for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) { | |
71 | list_splice(&b->bucket[i], out_list); | |
72 | } | |
73 | } | |
74 | ||
1109ca09 | 75 | static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) |
771fe6b9 JG |
76 | { |
77 | struct drm_device *ddev = p->rdev->ddev; | |
78 | struct radeon_cs_chunk *chunk; | |
c9b76548 | 79 | struct radeon_cs_buckets buckets; |
466be338 CK |
80 | unsigned i; |
81 | bool need_mmap_lock = false; | |
f72a113a | 82 | int r; |
771fe6b9 | 83 | |
6d2d13dd | 84 | if (p->chunk_relocs == NULL) { |
771fe6b9 JG |
85 | return 0; |
86 | } | |
6d2d13dd | 87 | chunk = p->chunk_relocs; |
cf4ccd01 | 88 | p->dma_reloc_idx = 0; |
771fe6b9 JG |
89 | /* FIXME: we assume that each relocs use 4 dwords */ |
90 | p->nrelocs = chunk->length_dw / 4; | |
1d0c0942 | 91 | p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_bo_list), GFP_KERNEL); |
771fe6b9 JG |
92 | if (p->relocs == NULL) { |
93 | return -ENOMEM; | |
94 | } | |
c9b76548 MO |
95 | |
96 | radeon_cs_buckets_init(&buckets); | |
97 | ||
771fe6b9 JG |
98 | for (i = 0; i < p->nrelocs; i++) { |
99 | struct drm_radeon_cs_reloc *r; | |
d33a8fc7 | 100 | struct drm_gem_object *gobj; |
c9b76548 | 101 | unsigned priority; |
771fe6b9 | 102 | |
771fe6b9 | 103 | r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; |
d33a8fc7 CK |
104 | gobj = drm_gem_object_lookup(ddev, p->filp, r->handle); |
105 | if (gobj == NULL) { | |
4474f3a9 CK |
106 | DRM_ERROR("gem object lookup failed 0x%x\n", |
107 | r->handle); | |
108 | return -ENOENT; | |
109 | } | |
d33a8fc7 | 110 | p->relocs[i].robj = gem_to_radeon_bo(gobj); |
c9b76548 MO |
111 | |
112 | /* The userspace buffer priorities are from 0 to 15. A higher | |
113 | * number means the buffer is more important. | |
114 | * Also, the buffers used for write have a higher priority than | |
115 | * the buffers used for read only, which doubles the range | |
116 | * to 0 to 31. 32 is reserved for the kernel driver. | |
117 | */ | |
701e1e78 CK |
118 | priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2 |
119 | + !!r->write_domain; | |
4474f3a9 | 120 | |
4f66c599 | 121 | /* the first reloc of an UVD job is the msg and that must be in |
b6a7eeea CK |
122 | VRAM, also but everything into VRAM on AGP cards and older |
123 | IGP chips to avoid image corruptions */ | |
4f66c599 | 124 | if (p->ring == R600_RING_TYPE_UVD_INDEX && |
b6a7eeea CK |
125 | (i == 0 || drm_pci_device_is_agp(p->rdev->ddev) || |
126 | p->rdev->family == CHIP_RS780 || | |
127 | p->rdev->family == CHIP_RS880)) { | |
128 | ||
bcf6f1e9 | 129 | /* TODO: is this still needed for NI+ ? */ |
ce6758c8 | 130 | p->relocs[i].prefered_domains = |
f2ba57b5 CK |
131 | RADEON_GEM_DOMAIN_VRAM; |
132 | ||
ce6758c8 | 133 | p->relocs[i].allowed_domains = |
f2ba57b5 CK |
134 | RADEON_GEM_DOMAIN_VRAM; |
135 | ||
c9b76548 MO |
136 | /* prioritize this over any other relocation */ |
137 | priority = RADEON_CS_MAX_PRIORITY; | |
f2ba57b5 CK |
138 | } else { |
139 | uint32_t domain = r->write_domain ? | |
140 | r->write_domain : r->read_domains; | |
141 | ||
ec65da38 MO |
142 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
143 | DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid " | |
144 | "for command submission\n"); | |
145 | return -EINVAL; | |
146 | } | |
147 | ||
ce6758c8 | 148 | p->relocs[i].prefered_domains = domain; |
f2ba57b5 CK |
149 | if (domain == RADEON_GEM_DOMAIN_VRAM) |
150 | domain |= RADEON_GEM_DOMAIN_GTT; | |
ce6758c8 | 151 | p->relocs[i].allowed_domains = domain; |
f2ba57b5 | 152 | } |
4474f3a9 | 153 | |
f72a113a CK |
154 | if (radeon_ttm_tt_has_userptr(p->relocs[i].robj->tbo.ttm)) { |
155 | uint32_t domain = p->relocs[i].prefered_domains; | |
156 | if (!(domain & RADEON_GEM_DOMAIN_GTT)) { | |
157 | DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is " | |
158 | "allowed for userptr BOs\n"); | |
159 | return -EINVAL; | |
160 | } | |
161 | need_mmap_lock = true; | |
162 | domain = RADEON_GEM_DOMAIN_GTT; | |
163 | p->relocs[i].prefered_domains = domain; | |
164 | p->relocs[i].allowed_domains = domain; | |
165 | } | |
166 | ||
df0af440 | 167 | p->relocs[i].tv.bo = &p->relocs[i].robj->tbo; |
298593b6 | 168 | p->relocs[i].tv.shared = !r->write_domain; |
4474f3a9 | 169 | |
df0af440 | 170 | radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head, |
c9b76548 | 171 | priority); |
771fe6b9 | 172 | } |
c9b76548 MO |
173 | |
174 | radeon_cs_buckets_get_list(&buckets, &p->validated); | |
175 | ||
6d2f2944 CK |
176 | if (p->cs_flags & RADEON_CS_USE_VM) |
177 | p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm, | |
178 | &p->validated); | |
f72a113a CK |
179 | if (need_mmap_lock) |
180 | down_read(¤t->mm->mmap_sem); | |
181 | ||
182 | r = radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring); | |
183 | ||
184 | if (need_mmap_lock) | |
185 | up_read(¤t->mm->mmap_sem); | |
6d2f2944 | 186 | |
f72a113a | 187 | return r; |
771fe6b9 JG |
188 | } |
189 | ||
721604a1 JG |
190 | static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) |
191 | { | |
192 | p->priority = priority; | |
193 | ||
194 | switch (ring) { | |
195 | default: | |
196 | DRM_ERROR("unknown ring id: %d\n", ring); | |
197 | return -EINVAL; | |
198 | case RADEON_CS_RING_GFX: | |
199 | p->ring = RADEON_RING_TYPE_GFX_INDEX; | |
200 | break; | |
201 | case RADEON_CS_RING_COMPUTE: | |
963e81f9 | 202 | if (p->rdev->family >= CHIP_TAHITI) { |
8d5ef7b1 AD |
203 | if (p->priority > 0) |
204 | p->ring = CAYMAN_RING_TYPE_CP1_INDEX; | |
205 | else | |
206 | p->ring = CAYMAN_RING_TYPE_CP2_INDEX; | |
207 | } else | |
208 | p->ring = RADEON_RING_TYPE_GFX_INDEX; | |
721604a1 | 209 | break; |
278a334c AD |
210 | case RADEON_CS_RING_DMA: |
211 | if (p->rdev->family >= CHIP_CAYMAN) { | |
212 | if (p->priority > 0) | |
213 | p->ring = R600_RING_TYPE_DMA_INDEX; | |
214 | else | |
215 | p->ring = CAYMAN_RING_TYPE_DMA1_INDEX; | |
b9ace36f | 216 | } else if (p->rdev->family >= CHIP_RV770) { |
278a334c AD |
217 | p->ring = R600_RING_TYPE_DMA_INDEX; |
218 | } else { | |
219 | return -EINVAL; | |
220 | } | |
221 | break; | |
f2ba57b5 CK |
222 | case RADEON_CS_RING_UVD: |
223 | p->ring = R600_RING_TYPE_UVD_INDEX; | |
224 | break; | |
d93f7937 CK |
225 | case RADEON_CS_RING_VCE: |
226 | /* TODO: only use the low priority ring for now */ | |
227 | p->ring = TN_RING_TYPE_VCE1_INDEX; | |
228 | break; | |
721604a1 JG |
229 | } |
230 | return 0; | |
231 | } | |
232 | ||
392a250b | 233 | static int radeon_cs_sync_rings(struct radeon_cs_parser *p) |
93504fce | 234 | { |
1d0c0942 | 235 | struct radeon_bo_list *reloc; |
c1f0a9c2 | 236 | int r; |
93504fce | 237 | |
c1f0a9c2 | 238 | list_for_each_entry(reloc, &p->validated, tv.head) { |
f2c24b83 | 239 | struct reservation_object *resv; |
f2c24b83 | 240 | |
c1f0a9c2 | 241 | resv = reloc->robj->tbo.resv; |
975700d2 | 242 | r = radeon_sync_resv(p->rdev, &p->ib.sync, resv, |
c1f0a9c2 | 243 | reloc->tv.shared); |
392a250b | 244 | if (r) |
c1f0a9c2 | 245 | return r; |
8f676c4c | 246 | } |
c1f0a9c2 | 247 | return 0; |
93504fce CK |
248 | } |
249 | ||
9b00147d | 250 | /* XXX: note that this is called from the legacy UMS CS ioctl as well */ |
771fe6b9 JG |
251 | int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) |
252 | { | |
253 | struct drm_radeon_cs *cs = data; | |
254 | uint64_t *chunk_array_ptr; | |
721604a1 JG |
255 | unsigned size, i; |
256 | u32 ring = RADEON_CS_RING_GFX; | |
257 | s32 priority = 0; | |
771fe6b9 JG |
258 | |
259 | if (!cs->num_chunks) { | |
260 | return 0; | |
261 | } | |
262 | /* get chunks */ | |
263 | INIT_LIST_HEAD(&p->validated); | |
264 | p->idx = 0; | |
f2e39221 | 265 | p->ib.sa_bo = NULL; |
f2e39221 | 266 | p->const_ib.sa_bo = NULL; |
6d2d13dd CK |
267 | p->chunk_ib = NULL; |
268 | p->chunk_relocs = NULL; | |
269 | p->chunk_flags = NULL; | |
270 | p->chunk_const_ib = NULL; | |
771fe6b9 JG |
271 | p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL); |
272 | if (p->chunks_array == NULL) { | |
273 | return -ENOMEM; | |
274 | } | |
275 | chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); | |
1d6ac185 | 276 | if (copy_from_user(p->chunks_array, chunk_array_ptr, |
771fe6b9 JG |
277 | sizeof(uint64_t)*cs->num_chunks)) { |
278 | return -EFAULT; | |
279 | } | |
721604a1 | 280 | p->cs_flags = 0; |
771fe6b9 JG |
281 | p->nchunks = cs->num_chunks; |
282 | p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL); | |
283 | if (p->chunks == NULL) { | |
284 | return -ENOMEM; | |
285 | } | |
286 | for (i = 0; i < p->nchunks; i++) { | |
287 | struct drm_radeon_cs_chunk __user **chunk_ptr = NULL; | |
288 | struct drm_radeon_cs_chunk user_chunk; | |
289 | uint32_t __user *cdata; | |
290 | ||
291 | chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; | |
1d6ac185 | 292 | if (copy_from_user(&user_chunk, chunk_ptr, |
771fe6b9 JG |
293 | sizeof(struct drm_radeon_cs_chunk))) { |
294 | return -EFAULT; | |
295 | } | |
5176fdc4 | 296 | p->chunks[i].length_dw = user_chunk.length_dw; |
6d2d13dd CK |
297 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_RELOCS) { |
298 | p->chunk_relocs = &p->chunks[i]; | |
771fe6b9 | 299 | } |
6d2d13dd CK |
300 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) { |
301 | p->chunk_ib = &p->chunks[i]; | |
5176fdc4 DA |
302 | /* zero length IB isn't useful */ |
303 | if (p->chunks[i].length_dw == 0) | |
304 | return -EINVAL; | |
771fe6b9 | 305 | } |
6d2d13dd CK |
306 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB) { |
307 | p->chunk_const_ib = &p->chunks[i]; | |
dfcf5f36 AD |
308 | /* zero length CONST IB isn't useful */ |
309 | if (p->chunks[i].length_dw == 0) | |
310 | return -EINVAL; | |
311 | } | |
6d2d13dd CK |
312 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) { |
313 | p->chunk_flags = &p->chunks[i]; | |
721604a1 JG |
314 | /* zero length flags aren't useful */ |
315 | if (p->chunks[i].length_dw == 0) | |
316 | return -EINVAL; | |
e70f224c | 317 | } |
5176fdc4 | 318 | |
28a326c5 ML |
319 | size = p->chunks[i].length_dw; |
320 | cdata = (void __user *)(unsigned long)user_chunk.chunk_data; | |
321 | p->chunks[i].user_ptr = cdata; | |
6d2d13dd | 322 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB) |
28a326c5 ML |
323 | continue; |
324 | ||
6d2d13dd | 325 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) { |
28a326c5 ML |
326 | if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP)) |
327 | continue; | |
328 | } | |
329 | ||
330 | p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); | |
331 | size *= sizeof(uint32_t); | |
332 | if (p->chunks[i].kdata == NULL) { | |
333 | return -ENOMEM; | |
334 | } | |
1d6ac185 | 335 | if (copy_from_user(p->chunks[i].kdata, cdata, size)) { |
28a326c5 ML |
336 | return -EFAULT; |
337 | } | |
6d2d13dd | 338 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) { |
28a326c5 ML |
339 | p->cs_flags = p->chunks[i].kdata[0]; |
340 | if (p->chunks[i].length_dw > 1) | |
341 | ring = p->chunks[i].kdata[1]; | |
342 | if (p->chunks[i].length_dw > 2) | |
343 | priority = (s32)p->chunks[i].kdata[2]; | |
771fe6b9 JG |
344 | } |
345 | } | |
721604a1 | 346 | |
9b00147d AD |
347 | /* these are KMS only */ |
348 | if (p->rdev) { | |
349 | if ((p->cs_flags & RADEON_CS_USE_VM) && | |
350 | !p->rdev->vm_manager.enabled) { | |
351 | DRM_ERROR("VM not active on asic!\n"); | |
352 | return -EINVAL; | |
353 | } | |
1b5475db | 354 | |
57449040 | 355 | if (radeon_cs_get_ring(p, ring, priority)) |
9b00147d | 356 | return -EINVAL; |
721604a1 | 357 | |
57449040 | 358 | /* we only support VM on some SI+ rings */ |
60a44540 CK |
359 | if ((p->cs_flags & RADEON_CS_USE_VM) == 0) { |
360 | if (p->rdev->asic->ring[p->ring]->cs_parse == NULL) { | |
361 | DRM_ERROR("Ring %d requires VM!\n", p->ring); | |
362 | return -EINVAL; | |
363 | } | |
364 | } else { | |
365 | if (p->rdev->asic->ring[p->ring]->ib_parse == NULL) { | |
366 | DRM_ERROR("VM not supported on ring %d!\n", | |
367 | p->ring); | |
368 | return -EINVAL; | |
369 | } | |
57449040 | 370 | } |
9b00147d | 371 | } |
721604a1 | 372 | |
771fe6b9 JG |
373 | return 0; |
374 | } | |
375 | ||
4330441a MO |
376 | static int cmp_size_smaller_first(void *priv, struct list_head *a, |
377 | struct list_head *b) | |
378 | { | |
1d0c0942 CK |
379 | struct radeon_bo_list *la = list_entry(a, struct radeon_bo_list, tv.head); |
380 | struct radeon_bo_list *lb = list_entry(b, struct radeon_bo_list, tv.head); | |
4330441a MO |
381 | |
382 | /* Sort A before B if A is smaller. */ | |
df0af440 | 383 | return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; |
4330441a MO |
384 | } |
385 | ||
771fe6b9 JG |
386 | /** |
387 | * cs_parser_fini() - clean parser states | |
388 | * @parser: parser structure holding parsing context. | |
389 | * @error: error number | |
390 | * | |
391 | * If error is set than unvalidate buffer, otherwise just free memory | |
392 | * used by parsing context. | |
393 | **/ | |
ecff665f | 394 | static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff) |
771fe6b9 JG |
395 | { |
396 | unsigned i; | |
397 | ||
e43b5ec0 | 398 | if (!error) { |
4330441a MO |
399 | /* Sort the buffer list from the smallest to largest buffer, |
400 | * which affects the order of buffers in the LRU list. | |
401 | * This assures that the smallest buffers are added first | |
402 | * to the LRU list, so they are likely to be later evicted | |
403 | * first, instead of large buffers whose eviction is more | |
404 | * expensive. | |
405 | * | |
406 | * This slightly lowers the number of bytes moved by TTM | |
407 | * per frame under memory pressure. | |
408 | */ | |
409 | list_sort(NULL, &parser->validated, cmp_size_smaller_first); | |
410 | ||
ecff665f ML |
411 | ttm_eu_fence_buffer_objects(&parser->ticket, |
412 | &parser->validated, | |
f2c24b83 | 413 | &parser->ib.fence->base); |
ecff665f ML |
414 | } else if (backoff) { |
415 | ttm_eu_backoff_reservation(&parser->ticket, | |
416 | &parser->validated); | |
e43b5ec0 | 417 | } |
147666fb | 418 | |
fcbc451b PN |
419 | if (parser->relocs != NULL) { |
420 | for (i = 0; i < parser->nrelocs; i++) { | |
d33a8fc7 CK |
421 | struct radeon_bo *bo = parser->relocs[i].robj; |
422 | if (bo == NULL) | |
423 | continue; | |
424 | ||
425 | drm_gem_object_unreference_unlocked(&bo->gem_base); | |
fcbc451b | 426 | } |
771fe6b9 | 427 | } |
48e113e5 | 428 | kfree(parser->track); |
771fe6b9 | 429 | kfree(parser->relocs); |
e5a5fd4d | 430 | drm_free_large(parser->vm_bos); |
28a326c5 ML |
431 | for (i = 0; i < parser->nchunks; i++) |
432 | drm_free_large(parser->chunks[i].kdata); | |
771fe6b9 JG |
433 | kfree(parser->chunks); |
434 | kfree(parser->chunks_array); | |
435 | radeon_ib_free(parser->rdev, &parser->ib); | |
f2e39221 | 436 | radeon_ib_free(parser->rdev, &parser->const_ib); |
771fe6b9 JG |
437 | } |
438 | ||
721604a1 JG |
439 | static int radeon_cs_ib_chunk(struct radeon_device *rdev, |
440 | struct radeon_cs_parser *parser) | |
441 | { | |
721604a1 JG |
442 | int r; |
443 | ||
6d2d13dd | 444 | if (parser->chunk_ib == NULL) |
721604a1 JG |
445 | return 0; |
446 | ||
447 | if (parser->cs_flags & RADEON_CS_USE_VM) | |
448 | return 0; | |
449 | ||
eb0c19c5 | 450 | r = radeon_cs_parse(rdev, parser->ring, parser); |
721604a1 JG |
451 | if (r || parser->parser_error) { |
452 | DRM_ERROR("Invalid command stream !\n"); | |
453 | return r; | |
454 | } | |
ce3537d5 | 455 | |
392a250b ML |
456 | r = radeon_cs_sync_rings(parser); |
457 | if (r) { | |
458 | if (r != -ERESTARTSYS) | |
459 | DRM_ERROR("Failed to sync rings: %i\n", r); | |
460 | return r; | |
461 | } | |
462 | ||
ce3537d5 AD |
463 | if (parser->ring == R600_RING_TYPE_UVD_INDEX) |
464 | radeon_uvd_note_usage(rdev); | |
03afe6f6 AD |
465 | else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) || |
466 | (parser->ring == TN_RING_TYPE_VCE2_INDEX)) | |
467 | radeon_vce_note_usage(rdev); | |
ce3537d5 | 468 | |
1538a9e0 | 469 | r = radeon_ib_schedule(rdev, &parser->ib, NULL, true); |
721604a1 JG |
470 | if (r) { |
471 | DRM_ERROR("Failed to schedule IB !\n"); | |
472 | } | |
93bf888c | 473 | return r; |
721604a1 JG |
474 | } |
475 | ||
6d2f2944 | 476 | static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p, |
721604a1 JG |
477 | struct radeon_vm *vm) |
478 | { | |
6d2f2944 | 479 | struct radeon_device *rdev = p->rdev; |
036bf46a | 480 | struct radeon_bo_va *bo_va; |
6d2f2944 | 481 | int i, r; |
721604a1 | 482 | |
6d2f2944 CK |
483 | r = radeon_vm_update_page_directory(rdev, vm); |
484 | if (r) | |
3e8970f9 | 485 | return r; |
6d2f2944 | 486 | |
036bf46a CK |
487 | r = radeon_vm_clear_freed(rdev, vm); |
488 | if (r) | |
489 | return r; | |
490 | ||
cc9e67e3 | 491 | if (vm->ib_bo_va == NULL) { |
036bf46a CK |
492 | DRM_ERROR("Tmp BO not in VM!\n"); |
493 | return -EINVAL; | |
494 | } | |
495 | ||
cc9e67e3 CK |
496 | r = radeon_vm_bo_update(rdev, vm->ib_bo_va, |
497 | &rdev->ring_tmp_bo.bo->tbo.mem); | |
6d2f2944 CK |
498 | if (r) |
499 | return r; | |
500 | ||
501 | for (i = 0; i < p->nrelocs; i++) { | |
502 | struct radeon_bo *bo; | |
503 | ||
6d2f2944 | 504 | bo = p->relocs[i].robj; |
036bf46a CK |
505 | bo_va = radeon_vm_bo_find(vm, bo); |
506 | if (bo_va == NULL) { | |
507 | dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm); | |
508 | return -EINVAL; | |
509 | } | |
510 | ||
511 | r = radeon_vm_bo_update(rdev, bo_va, &bo->tbo.mem); | |
6d2f2944 | 512 | if (r) |
721604a1 | 513 | return r; |
94214635 CK |
514 | |
515 | radeon_sync_fence(&p->ib.sync, bo_va->last_pt_update); | |
721604a1 | 516 | } |
e31ad969 CK |
517 | |
518 | return radeon_vm_clear_invalids(rdev, vm); | |
721604a1 JG |
519 | } |
520 | ||
521 | static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, | |
522 | struct radeon_cs_parser *parser) | |
523 | { | |
721604a1 JG |
524 | struct radeon_fpriv *fpriv = parser->filp->driver_priv; |
525 | struct radeon_vm *vm = &fpriv->vm; | |
526 | int r; | |
527 | ||
6d2d13dd | 528 | if (parser->chunk_ib == NULL) |
721604a1 | 529 | return 0; |
721604a1 JG |
530 | if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) |
531 | return 0; | |
532 | ||
28a326c5 | 533 | if (parser->const_ib.length_dw) { |
f2e39221 | 534 | r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib); |
dfcf5f36 AD |
535 | if (r) { |
536 | return r; | |
537 | } | |
538 | } | |
539 | ||
f2e39221 | 540 | r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib); |
721604a1 JG |
541 | if (r) { |
542 | return r; | |
543 | } | |
544 | ||
ce3537d5 AD |
545 | if (parser->ring == R600_RING_TYPE_UVD_INDEX) |
546 | radeon_uvd_note_usage(rdev); | |
547 | ||
721604a1 | 548 | mutex_lock(&vm->mutex); |
721604a1 JG |
549 | r = radeon_bo_vm_update_pte(parser, vm); |
550 | if (r) { | |
551 | goto out; | |
552 | } | |
392a250b ML |
553 | |
554 | r = radeon_cs_sync_rings(parser); | |
555 | if (r) { | |
556 | if (r != -ERESTARTSYS) | |
557 | DRM_ERROR("Failed to sync rings: %i\n", r); | |
558 | goto out; | |
559 | } | |
4ef72566 | 560 | |
dfcf5f36 | 561 | if ((rdev->family >= CHIP_TAHITI) && |
6d2d13dd | 562 | (parser->chunk_const_ib != NULL)) { |
1538a9e0 | 563 | r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true); |
4ef72566 | 564 | } else { |
1538a9e0 | 565 | r = radeon_ib_schedule(rdev, &parser->ib, NULL, true); |
dfcf5f36 AD |
566 | } |
567 | ||
ee60e29f | 568 | out: |
36ff39c4 | 569 | mutex_unlock(&vm->mutex); |
721604a1 JG |
570 | return r; |
571 | } | |
572 | ||
6c6f4783 CK |
573 | static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r) |
574 | { | |
575 | if (r == -EDEADLK) { | |
576 | r = radeon_gpu_reset(rdev); | |
577 | if (!r) | |
578 | r = -EAGAIN; | |
579 | } | |
580 | return r; | |
581 | } | |
582 | ||
28a326c5 ML |
583 | static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser) |
584 | { | |
585 | struct radeon_cs_chunk *ib_chunk; | |
586 | struct radeon_vm *vm = NULL; | |
587 | int r; | |
588 | ||
6d2d13dd | 589 | if (parser->chunk_ib == NULL) |
28a326c5 ML |
590 | return 0; |
591 | ||
592 | if (parser->cs_flags & RADEON_CS_USE_VM) { | |
593 | struct radeon_fpriv *fpriv = parser->filp->driver_priv; | |
594 | vm = &fpriv->vm; | |
595 | ||
596 | if ((rdev->family >= CHIP_TAHITI) && | |
6d2d13dd CK |
597 | (parser->chunk_const_ib != NULL)) { |
598 | ib_chunk = parser->chunk_const_ib; | |
28a326c5 ML |
599 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { |
600 | DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw); | |
601 | return -EINVAL; | |
602 | } | |
603 | r = radeon_ib_get(rdev, parser->ring, &parser->const_ib, | |
604 | vm, ib_chunk->length_dw * 4); | |
605 | if (r) { | |
606 | DRM_ERROR("Failed to get const ib !\n"); | |
607 | return r; | |
608 | } | |
609 | parser->const_ib.is_const_ib = true; | |
610 | parser->const_ib.length_dw = ib_chunk->length_dw; | |
1d6ac185 | 611 | if (copy_from_user(parser->const_ib.ptr, |
28a326c5 ML |
612 | ib_chunk->user_ptr, |
613 | ib_chunk->length_dw * 4)) | |
614 | return -EFAULT; | |
615 | } | |
616 | ||
6d2d13dd | 617 | ib_chunk = parser->chunk_ib; |
28a326c5 ML |
618 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { |
619 | DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw); | |
620 | return -EINVAL; | |
621 | } | |
622 | } | |
6d2d13dd | 623 | ib_chunk = parser->chunk_ib; |
28a326c5 ML |
624 | |
625 | r = radeon_ib_get(rdev, parser->ring, &parser->ib, | |
626 | vm, ib_chunk->length_dw * 4); | |
627 | if (r) { | |
628 | DRM_ERROR("Failed to get ib !\n"); | |
629 | return r; | |
630 | } | |
631 | parser->ib.length_dw = ib_chunk->length_dw; | |
632 | if (ib_chunk->kdata) | |
633 | memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4); | |
1d6ac185 | 634 | else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4)) |
28a326c5 ML |
635 | return -EFAULT; |
636 | return 0; | |
637 | } | |
638 | ||
771fe6b9 JG |
639 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
640 | { | |
641 | struct radeon_device *rdev = dev->dev_private; | |
642 | struct radeon_cs_parser parser; | |
771fe6b9 JG |
643 | int r; |
644 | ||
dee53e7f | 645 | down_read(&rdev->exclusive_lock); |
6b7746e8 | 646 | if (!rdev->accel_working) { |
dee53e7f | 647 | up_read(&rdev->exclusive_lock); |
6b7746e8 JG |
648 | return -EBUSY; |
649 | } | |
9bb39ff4 ML |
650 | if (rdev->in_reset) { |
651 | up_read(&rdev->exclusive_lock); | |
652 | r = radeon_gpu_reset(rdev); | |
653 | if (!r) | |
654 | r = -EAGAIN; | |
655 | return r; | |
656 | } | |
771fe6b9 JG |
657 | /* initialize parser */ |
658 | memset(&parser, 0, sizeof(struct radeon_cs_parser)); | |
659 | parser.filp = filp; | |
660 | parser.rdev = rdev; | |
c8c15ff1 | 661 | parser.dev = rdev->dev; |
428c6e36 | 662 | parser.family = rdev->family; |
771fe6b9 JG |
663 | r = radeon_cs_parser_init(&parser, data); |
664 | if (r) { | |
665 | DRM_ERROR("Failed to initialize parser !\n"); | |
ecff665f | 666 | radeon_cs_parser_fini(&parser, r, false); |
dee53e7f | 667 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 668 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
669 | return r; |
670 | } | |
28a326c5 ML |
671 | |
672 | r = radeon_cs_ib_fill(rdev, &parser); | |
673 | if (!r) { | |
674 | r = radeon_cs_parser_relocs(&parser); | |
675 | if (r && r != -ERESTARTSYS) | |
97f23b3d | 676 | DRM_ERROR("Failed to parse relocation %d!\n", r); |
28a326c5 ML |
677 | } |
678 | ||
679 | if (r) { | |
ecff665f | 680 | radeon_cs_parser_fini(&parser, r, false); |
dee53e7f | 681 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 682 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
683 | return r; |
684 | } | |
55b51c88 | 685 | |
860024e5 CK |
686 | trace_radeon_cs(&parser); |
687 | ||
721604a1 | 688 | r = radeon_cs_ib_chunk(rdev, &parser); |
771fe6b9 | 689 | if (r) { |
721604a1 | 690 | goto out; |
771fe6b9 | 691 | } |
721604a1 | 692 | r = radeon_cs_ib_vm_chunk(rdev, &parser); |
771fe6b9 | 693 | if (r) { |
721604a1 | 694 | goto out; |
771fe6b9 | 695 | } |
721604a1 | 696 | out: |
ecff665f | 697 | radeon_cs_parser_fini(&parser, r, true); |
dee53e7f | 698 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 699 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
700 | return r; |
701 | } | |
513bcb46 | 702 | |
4db01311 IH |
703 | /** |
704 | * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet | |
705 | * @parser: parser structure holding parsing context. | |
706 | * @pkt: where to store packet information | |
707 | * | |
708 | * Assume that chunk_ib_index is properly set. Will return -EINVAL | |
709 | * if packet is bigger than remaining ib size. or if packets is unknown. | |
710 | **/ | |
711 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, | |
712 | struct radeon_cs_packet *pkt, | |
713 | unsigned idx) | |
714 | { | |
6d2d13dd | 715 | struct radeon_cs_chunk *ib_chunk = p->chunk_ib; |
4db01311 IH |
716 | struct radeon_device *rdev = p->rdev; |
717 | uint32_t header; | |
e1b4e722 | 718 | int ret = 0, i; |
4db01311 IH |
719 | |
720 | if (idx >= ib_chunk->length_dw) { | |
721 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", | |
722 | idx, ib_chunk->length_dw); | |
723 | return -EINVAL; | |
724 | } | |
725 | header = radeon_get_ib_value(p, idx); | |
726 | pkt->idx = idx; | |
727 | pkt->type = RADEON_CP_PACKET_GET_TYPE(header); | |
728 | pkt->count = RADEON_CP_PACKET_GET_COUNT(header); | |
729 | pkt->one_reg_wr = 0; | |
730 | switch (pkt->type) { | |
731 | case RADEON_PACKET_TYPE0: | |
732 | if (rdev->family < CHIP_R600) { | |
733 | pkt->reg = R100_CP_PACKET0_GET_REG(header); | |
734 | pkt->one_reg_wr = | |
735 | RADEON_CP_PACKET0_GET_ONE_REG_WR(header); | |
736 | } else | |
737 | pkt->reg = R600_CP_PACKET0_GET_REG(header); | |
738 | break; | |
739 | case RADEON_PACKET_TYPE3: | |
740 | pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header); | |
741 | break; | |
742 | case RADEON_PACKET_TYPE2: | |
743 | pkt->count = -1; | |
744 | break; | |
745 | default: | |
746 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); | |
e1b4e722 AD |
747 | ret = -EINVAL; |
748 | goto dump_ib; | |
4db01311 IH |
749 | } |
750 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { | |
751 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", | |
752 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); | |
e1b4e722 AD |
753 | ret = -EINVAL; |
754 | goto dump_ib; | |
4db01311 IH |
755 | } |
756 | return 0; | |
e1b4e722 AD |
757 | |
758 | dump_ib: | |
759 | for (i = 0; i < ib_chunk->length_dw; i++) { | |
760 | if (i == idx) | |
761 | printk("\t0x%08x <---\n", radeon_get_ib_value(p, i)); | |
762 | else | |
763 | printk("\t0x%08x\n", radeon_get_ib_value(p, i)); | |
764 | } | |
765 | return ret; | |
4db01311 | 766 | } |
9ffb7a6d IH |
767 | |
768 | /** | |
769 | * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP | |
770 | * @p: structure holding the parser context. | |
771 | * | |
772 | * Check if the next packet is NOP relocation packet3. | |
773 | **/ | |
774 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) | |
775 | { | |
776 | struct radeon_cs_packet p3reloc; | |
777 | int r; | |
778 | ||
779 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx); | |
780 | if (r) | |
781 | return false; | |
782 | if (p3reloc.type != RADEON_PACKET_TYPE3) | |
783 | return false; | |
784 | if (p3reloc.opcode != RADEON_PACKET3_NOP) | |
785 | return false; | |
786 | return true; | |
787 | } | |
c3ad63af IH |
788 | |
789 | /** | |
790 | * radeon_cs_dump_packet() - dump raw packet context | |
791 | * @p: structure holding the parser context. | |
792 | * @pkt: structure holding the packet. | |
793 | * | |
794 | * Used mostly for debugging and error reporting. | |
795 | **/ | |
796 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, | |
797 | struct radeon_cs_packet *pkt) | |
798 | { | |
799 | volatile uint32_t *ib; | |
800 | unsigned i; | |
801 | unsigned idx; | |
802 | ||
803 | ib = p->ib.ptr; | |
804 | idx = pkt->idx; | |
805 | for (i = 0; i <= (pkt->count + 1); i++, idx++) | |
806 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); | |
807 | } | |
808 | ||
e9716993 IH |
809 | /** |
810 | * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet | |
811 | * @parser: parser structure holding parsing context. | |
812 | * @data: pointer to relocation data | |
813 | * @offset_start: starting offset | |
814 | * @offset_mask: offset mask (to align start offset on) | |
815 | * @reloc: reloc informations | |
816 | * | |
817 | * Check if next packet is relocation packet3, do bo validation and compute | |
818 | * GPU offset using the provided start. | |
819 | **/ | |
820 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, | |
1d0c0942 | 821 | struct radeon_bo_list **cs_reloc, |
e9716993 IH |
822 | int nomm) |
823 | { | |
824 | struct radeon_cs_chunk *relocs_chunk; | |
825 | struct radeon_cs_packet p3reloc; | |
826 | unsigned idx; | |
827 | int r; | |
828 | ||
6d2d13dd | 829 | if (p->chunk_relocs == NULL) { |
e9716993 IH |
830 | DRM_ERROR("No relocation chunk !\n"); |
831 | return -EINVAL; | |
832 | } | |
833 | *cs_reloc = NULL; | |
6d2d13dd | 834 | relocs_chunk = p->chunk_relocs; |
e9716993 IH |
835 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx); |
836 | if (r) | |
837 | return r; | |
838 | p->idx += p3reloc.count + 2; | |
839 | if (p3reloc.type != RADEON_PACKET_TYPE3 || | |
840 | p3reloc.opcode != RADEON_PACKET3_NOP) { | |
841 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", | |
842 | p3reloc.idx); | |
843 | radeon_cs_dump_packet(p, &p3reloc); | |
844 | return -EINVAL; | |
845 | } | |
846 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); | |
847 | if (idx >= relocs_chunk->length_dw) { | |
848 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", | |
849 | idx, relocs_chunk->length_dw); | |
850 | radeon_cs_dump_packet(p, &p3reloc); | |
851 | return -EINVAL; | |
852 | } | |
853 | /* FIXME: we assume reloc size is 4 dwords */ | |
854 | if (nomm) { | |
855 | *cs_reloc = p->relocs; | |
df0af440 | 856 | (*cs_reloc)->gpu_offset = |
e9716993 | 857 | (u64)relocs_chunk->kdata[idx + 3] << 32; |
df0af440 | 858 | (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0]; |
e9716993 | 859 | } else |
466be338 | 860 | *cs_reloc = &p->relocs[(idx / 4)]; |
e9716993 IH |
861 | return 0; |
862 | } |